2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
38 #include "instr-a3xx.h"
40 #include "ir3_context.h"
43 static struct ir3_instruction
*
44 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
45 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
47 struct ir3_block
*block
= ctx
->block
;
48 struct ir3_instruction
*mov
;
49 struct ir3_register
*src
;
51 mov
= ir3_instr_create(block
, OPC_MOV
);
52 mov
->cat1
.src_type
= TYPE_U32
;
53 mov
->cat1
.dst_type
= TYPE_U32
;
54 ir3_reg_create(mov
, 0, 0);
55 src
= ir3_reg_create(mov
, 0, IR3_REG_SSA
| IR3_REG_RELATIV
);
58 src
->array
.offset
= n
;
60 ir3_instr_set_address(mov
, address
);
65 static struct ir3_instruction
*
66 create_input_compmask(struct ir3_context
*ctx
, unsigned n
, unsigned compmask
)
68 struct ir3_instruction
*in
;
70 in
= ir3_instr_create(ctx
->in_block
, OPC_META_INPUT
);
71 in
->inout
.block
= ctx
->in_block
;
72 ir3_reg_create(in
, n
, 0);
74 in
->regs
[0]->wrmask
= compmask
;
79 static struct ir3_instruction
*
80 create_input(struct ir3_context
*ctx
, unsigned n
)
82 return create_input_compmask(ctx
, n
, 0x1);
85 static struct ir3_instruction
*
86 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
, unsigned n
)
88 struct ir3_block
*block
= ctx
->block
;
89 struct ir3_instruction
*instr
;
90 /* packed inloc is fixed up later: */
91 struct ir3_instruction
*inloc
= create_immed(block
, n
);
94 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
95 instr
->cat6
.type
= TYPE_U32
;
96 instr
->cat6
.iim_val
= 1;
98 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->ij_pixel
, 0);
99 instr
->regs
[2]->wrmask
= 0x3;
105 static struct ir3_instruction
*
106 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
108 /* first four vec4 sysval's reserved for UBOs: */
109 /* NOTE: dp is in scalar, but there can be >4 dp components: */
110 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
111 unsigned n
= const_state
->offsets
.driver_param
;
112 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
113 return create_uniform(ctx
->block
, r
);
117 * Adreno uses uint rather than having dedicated bool type,
118 * which (potentially) requires some conversion, in particular
119 * when using output of an bool instr to int input, or visa
123 * -------+---------+-------+-
127 * To convert from an adreno bool (uint) to nir, use:
129 * absneg.s dst, (neg)src
131 * To convert back in the other direction:
133 * absneg.s dst, (abs)arc
135 * The CP step can clean up the absneg.s that cancel each other
136 * out, and with a slight bit of extra cleverness (to recognize
137 * the instructions which produce either a 0 or 1) can eliminate
138 * the absneg.s's completely when an instruction that wants
139 * 0/1 consumes the result. For example, when a nir 'bcsel'
140 * consumes the result of 'feq'. So we should be able to get by
141 * without a boolean resolve step, and without incuring any
142 * extra penalty in instruction count.
145 /* NIR bool -> native (adreno): */
146 static struct ir3_instruction
*
147 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
149 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
152 /* native (adreno) -> NIR bool: */
153 static struct ir3_instruction
*
154 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
156 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
160 * alu/sfu instructions:
163 static struct ir3_instruction
*
164 create_cov(struct ir3_context
*ctx
, struct ir3_instruction
*src
,
165 unsigned src_bitsize
, nir_op op
)
167 type_t src_type
, dst_type
;
171 case nir_op_f2f16_rtne
:
172 case nir_op_f2f16_rtz
:
180 switch (src_bitsize
) {
188 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
197 switch (src_bitsize
) {
208 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
217 switch (src_bitsize
) {
228 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
233 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
243 case nir_op_f2f16_rtne
:
244 case nir_op_f2f16_rtz
:
246 /* TODO how to handle rounding mode? */
283 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
286 return ir3_COV(ctx
->block
, src
, src_type
, dst_type
);
290 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
292 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
293 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
294 unsigned bs
[info
->num_inputs
]; /* bit size */
295 struct ir3_block
*b
= ctx
->block
;
296 unsigned dst_sz
, wrmask
;
297 type_t dst_type
= nir_dest_bit_size(alu
->dest
.dest
) < 32 ?
300 if (alu
->dest
.dest
.is_ssa
) {
301 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
302 wrmask
= (1 << dst_sz
) - 1;
304 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
305 wrmask
= alu
->dest
.write_mask
;
308 dst
= ir3_get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
310 /* Vectors are special in that they have non-scalarized writemasks,
311 * and just take the first swizzle channel for each argument in
312 * order into each writemask channel.
314 if ((alu
->op
== nir_op_vec2
) ||
315 (alu
->op
== nir_op_vec3
) ||
316 (alu
->op
== nir_op_vec4
)) {
318 for (int i
= 0; i
< info
->num_inputs
; i
++) {
319 nir_alu_src
*asrc
= &alu
->src
[i
];
321 compile_assert(ctx
, !asrc
->abs
);
322 compile_assert(ctx
, !asrc
->negate
);
324 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
326 src
[i
] = create_immed_typed(ctx
->block
, 0, dst_type
);
327 dst
[i
] = ir3_MOV(b
, src
[i
], dst_type
);
330 ir3_put_dst(ctx
, &alu
->dest
.dest
);
334 /* We also get mov's with more than one component for mov's so
335 * handle those specially:
337 if (alu
->op
== nir_op_mov
) {
338 nir_alu_src
*asrc
= &alu
->src
[0];
339 struct ir3_instruction
*const *src0
= ir3_get_src(ctx
, &asrc
->src
);
341 for (unsigned i
= 0; i
< dst_sz
; i
++) {
342 if (wrmask
& (1 << i
)) {
343 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], dst_type
);
349 ir3_put_dst(ctx
, &alu
->dest
.dest
);
353 /* General case: We can just grab the one used channel per src. */
354 for (int i
= 0; i
< info
->num_inputs
; i
++) {
355 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
356 nir_alu_src
*asrc
= &alu
->src
[i
];
358 compile_assert(ctx
, !asrc
->abs
);
359 compile_assert(ctx
, !asrc
->negate
);
361 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
362 bs
[i
] = nir_src_bit_size(asrc
->src
);
364 compile_assert(ctx
, src
[i
]);
369 case nir_op_f2f16_rtne
:
370 case nir_op_f2f16_rtz
:
388 dst
[0] = create_cov(ctx
, src
[0], bs
[0], alu
->op
);
390 case nir_op_fquantize2f16
:
391 dst
[0] = create_cov(ctx
,
392 create_cov(ctx
, src
[0], 32, nir_op_f2f16
),
396 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
397 dst
[0]->cat2
.condition
= IR3_COND_NE
;
398 dst
[0] = ir3_n2b(b
, dst
[0]);
401 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F16
);
404 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
409 dst
[0] = ir3_b2n(b
, src
[0]);
412 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
413 dst
[0]->cat2
.condition
= IR3_COND_NE
;
414 dst
[0] = ir3_n2b(b
, dst
[0]);
418 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
421 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
424 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
427 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
430 /* if there is just a single use of the src, and it supports
431 * (sat) bit, we can just fold the (sat) flag back to the
432 * src instruction and create a mov. This is easier for cp
435 * TODO probably opc_cat==4 is ok too
437 if (alu
->src
[0].src
.is_ssa
&&
438 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
439 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
440 src
[0]->flags
|= IR3_INSTR_SAT
;
441 dst
[0] = ir3_MOV(b
, src
[0], dst_type
);
443 /* otherwise generate a max.f that saturates.. blob does
444 * similar (generating a cat2 mov using max.f)
446 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
447 dst
[0]->flags
|= IR3_INSTR_SAT
;
451 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
454 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
457 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
460 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
463 case nir_op_fddx_coarse
:
464 dst
[0] = ir3_DSX(b
, src
[0], 0);
465 dst
[0]->cat5
.type
= TYPE_F32
;
468 case nir_op_fddy_coarse
:
469 dst
[0] = ir3_DSY(b
, src
[0], 0);
470 dst
[0]->cat5
.type
= TYPE_F32
;
474 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
475 dst
[0]->cat2
.condition
= IR3_COND_LT
;
476 dst
[0] = ir3_n2b(b
, dst
[0]);
479 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
480 dst
[0]->cat2
.condition
= IR3_COND_GE
;
481 dst
[0] = ir3_n2b(b
, dst
[0]);
484 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
485 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
486 dst
[0] = ir3_n2b(b
, dst
[0]);
489 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
490 dst
[0]->cat2
.condition
= IR3_COND_NE
;
491 dst
[0] = ir3_n2b(b
, dst
[0]);
494 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
497 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
500 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
502 case nir_op_fround_even
:
503 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
506 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
510 dst
[0] = ir3_SIN(b
, src
[0], 0);
513 dst
[0] = ir3_COS(b
, src
[0], 0);
516 dst
[0] = ir3_RSQ(b
, src
[0], 0);
519 dst
[0] = ir3_RCP(b
, src
[0], 0);
522 dst
[0] = ir3_LOG2(b
, src
[0], 0);
525 dst
[0] = ir3_EXP2(b
, src
[0], 0);
528 dst
[0] = ir3_SQRT(b
, src
[0], 0);
532 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
535 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
538 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
541 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
544 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
547 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
550 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
552 case nir_op_umul_low
:
553 dst
[0] = ir3_MULL_U(b
, src
[0], 0, src
[1], 0);
555 case nir_op_imadsh_mix16
:
556 dst
[0] = ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0, src
[2], 0);
559 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
562 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
565 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
568 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
571 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
574 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
577 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
580 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
583 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
584 dst
[0]->cat2
.condition
= IR3_COND_LT
;
585 dst
[0] = ir3_n2b(b
, dst
[0]);
588 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
589 dst
[0]->cat2
.condition
= IR3_COND_GE
;
590 dst
[0] = ir3_n2b(b
, dst
[0]);
593 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
594 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
595 dst
[0] = ir3_n2b(b
, dst
[0]);
598 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
599 dst
[0]->cat2
.condition
= IR3_COND_NE
;
600 dst
[0] = ir3_n2b(b
, dst
[0]);
603 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
604 dst
[0]->cat2
.condition
= IR3_COND_LT
;
605 dst
[0] = ir3_n2b(b
, dst
[0]);
608 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
609 dst
[0]->cat2
.condition
= IR3_COND_GE
;
610 dst
[0] = ir3_n2b(b
, dst
[0]);
613 case nir_op_b32csel
: {
614 struct ir3_instruction
*cond
= ir3_b2n(b
, src
[0]);
615 compile_assert(ctx
, bs
[1] == bs
[2]);
616 /* the boolean condition is 32b even if src[1] and src[2] are
617 * half-precision, but sel.b16 wants all three src's to be the
621 cond
= ir3_COV(b
, cond
, TYPE_U32
, TYPE_U16
);
622 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, cond
, 0, src
[2], 0);
625 case nir_op_bit_count
: {
626 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
627 // double check on earlier gen's. Once half-precision support is
628 // in place, this should probably move to a NIR lowering pass:
629 struct ir3_instruction
*hi
, *lo
;
631 hi
= ir3_COV(b
, ir3_SHR_B(b
, src
[0], 0, create_immed(b
, 16), 0),
633 lo
= ir3_COV(b
, src
[0], TYPE_U32
, TYPE_U16
);
635 hi
= ir3_CBITS_B(b
, hi
, 0);
636 lo
= ir3_CBITS_B(b
, lo
, 0);
638 // TODO maybe the builders should default to making dst half-precision
639 // if the src's were half precision, to make this less awkward.. otoh
640 // we should probably just do this lowering in NIR.
641 hi
->regs
[0]->flags
|= IR3_REG_HALF
;
642 lo
->regs
[0]->flags
|= IR3_REG_HALF
;
644 dst
[0] = ir3_ADD_S(b
, hi
, 0, lo
, 0);
645 dst
[0]->regs
[0]->flags
|= IR3_REG_HALF
;
646 dst
[0] = ir3_COV(b
, dst
[0], TYPE_U16
, TYPE_U32
);
649 case nir_op_ifind_msb
: {
650 struct ir3_instruction
*cmp
;
651 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
652 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
653 cmp
->cat2
.condition
= IR3_COND_GE
;
654 dst
[0] = ir3_SEL_B32(b
,
655 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
659 case nir_op_ufind_msb
:
660 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
661 dst
[0] = ir3_SEL_B32(b
,
662 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
663 src
[0], 0, dst
[0], 0);
665 case nir_op_find_lsb
:
666 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
667 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
669 case nir_op_bitfield_reverse
:
670 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
674 ir3_context_error(ctx
, "Unhandled ALU op: %s\n",
675 nir_op_infos
[alu
->op
].name
);
679 ir3_put_dst(ctx
, &alu
->dest
.dest
);
682 /* handles direct/indirect UBO reads: */
684 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
685 struct ir3_instruction
**dst
)
687 struct ir3_block
*b
= ctx
->block
;
688 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
689 /* UBO addresses are the first driver params, but subtract 2 here to
690 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
691 * is the uniforms: */
692 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
693 unsigned ubo
= regid(const_state
->offsets
.ubo
, 0) - 2;
694 const unsigned ptrsz
= ir3_pointer_size(ctx
->compiler
);
698 /* First src is ubo index, which could either be an immed or not: */
699 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0];
700 if (is_same_type_mov(src0
) &&
701 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
702 base_lo
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
703 base_hi
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
705 base_lo
= create_uniform_indirect(b
, ubo
, ir3_get_addr(ctx
, src0
, ptrsz
));
706 base_hi
= create_uniform_indirect(b
, ubo
+ 1, ir3_get_addr(ctx
, src0
, ptrsz
));
708 /* NOTE: since relative addressing is used, make sure constlen is
709 * at least big enough to cover all the UBO addresses, since the
710 * assembler won't know what the max address reg is.
712 ctx
->so
->constlen
= MAX2(ctx
->so
->constlen
,
713 const_state
->offsets
.ubo
+ (ctx
->s
->info
.num_ubos
* ptrsz
));
716 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
719 if (nir_src_is_const(intr
->src
[1])) {
720 off
+= nir_src_as_uint(intr
->src
[1]);
722 /* For load_ubo_indirect, second src is indirect offset: */
723 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0];
725 /* and add offset to addr: */
726 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
729 /* if offset is to large to encode in the ldg, split it out: */
730 if ((off
+ (intr
->num_components
* 4)) > 1024) {
731 /* split out the minimal amount to improve the odds that
732 * cp can fit the immediate in the add.s instruction:
734 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
735 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
740 struct ir3_instruction
*carry
;
742 /* handle 32b rollover, ie:
743 * if (addr < base_lo)
746 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
747 carry
->cat2
.condition
= IR3_COND_LT
;
748 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
750 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
753 for (int i
= 0; i
< intr
->num_components
; i
++) {
754 struct ir3_instruction
*load
=
755 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0, /* num components */
756 create_immed(b
, off
+ i
* 4), 0);
757 load
->cat6
.type
= TYPE_U32
;
762 /* src[] = { block_index } */
764 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
765 struct ir3_instruction
**dst
)
767 /* SSBO size stored as a const starting at ssbo_sizes: */
768 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
769 unsigned blk_idx
= nir_src_as_uint(intr
->src
[0]);
770 unsigned idx
= regid(const_state
->offsets
.ssbo_sizes
, 0) +
771 const_state
->ssbo_size
.off
[blk_idx
];
773 debug_assert(const_state
->ssbo_size
.mask
& (1 << blk_idx
));
775 dst
[0] = create_uniform(ctx
->block
, idx
);
778 /* src[] = { offset }. const_index[] = { base } */
780 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
781 struct ir3_instruction
**dst
)
783 struct ir3_block
*b
= ctx
->block
;
784 struct ir3_instruction
*ldl
, *offset
;
787 offset
= ir3_get_src(ctx
, &intr
->src
[0])[0];
788 base
= nir_intrinsic_base(intr
);
790 ldl
= ir3_LDL(b
, offset
, 0,
791 create_immed(b
, intr
->num_components
), 0,
792 create_immed(b
, base
), 0);
794 ldl
->cat6
.type
= utype_dst(intr
->dest
);
795 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
797 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
798 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
800 ir3_split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
803 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
805 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
807 struct ir3_block
*b
= ctx
->block
;
808 struct ir3_instruction
*stl
, *offset
;
809 struct ir3_instruction
* const *value
;
810 unsigned base
, wrmask
;
812 value
= ir3_get_src(ctx
, &intr
->src
[0]);
813 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
815 base
= nir_intrinsic_base(intr
);
816 wrmask
= nir_intrinsic_write_mask(intr
);
818 /* Combine groups of consecutive enabled channels in one write
819 * message. We use ffs to find the first enabled channel and then ffs on
820 * the bit-inverse, down-shifted writemask to determine the length of
821 * the block of enabled bits.
823 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
826 unsigned first_component
= ffs(wrmask
) - 1;
827 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
829 stl
= ir3_STL(b
, offset
, 0,
830 ir3_create_collect(ctx
, &value
[first_component
], length
), 0,
831 create_immed(b
, length
), 0);
832 stl
->cat6
.dst_offset
= first_component
+ base
;
833 stl
->cat6
.type
= utype_src(intr
->src
[0]);
834 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
835 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
837 array_insert(b
, b
->keeps
, stl
);
839 /* Clear the bits in the writemask that we just wrote, then try
840 * again to see if more channels are left.
842 wrmask
&= (15 << (first_component
+ length
));
846 /* src[] = { offset }. const_index[] = { base } */
848 emit_intrinsic_load_shared_ir3(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
849 struct ir3_instruction
**dst
)
851 struct ir3_block
*b
= ctx
->block
;
852 struct ir3_instruction
*load
, *offset
;
855 offset
= ir3_get_src(ctx
, &intr
->src
[0])[0];
856 base
= nir_intrinsic_base(intr
);
858 load
= ir3_LDLW(b
, offset
, 0,
859 create_immed(b
, intr
->num_components
), 0,
860 create_immed(b
, base
), 0);
862 load
->cat6
.type
= utype_dst(intr
->dest
);
863 load
->regs
[0]->wrmask
= MASK(intr
->num_components
);
865 load
->barrier_class
= IR3_BARRIER_SHARED_R
;
866 load
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
868 ir3_split_dest(b
, dst
, load
, 0, intr
->num_components
);
871 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
873 emit_intrinsic_store_shared_ir3(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
875 struct ir3_block
*b
= ctx
->block
;
876 struct ir3_instruction
*store
, *offset
;
877 struct ir3_instruction
* const *value
;
878 unsigned base
, wrmask
;
880 value
= ir3_get_src(ctx
, &intr
->src
[0]);
881 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
883 base
= nir_intrinsic_base(intr
);
884 wrmask
= nir_intrinsic_write_mask(intr
);
886 /* Combine groups of consecutive enabled channels in one write
887 * message. We use ffs to find the first enabled channel and then ffs on
888 * the bit-inverse, down-shifted writemask to determine the length of
889 * the block of enabled bits.
891 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
894 unsigned first_component
= ffs(wrmask
) - 1;
895 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
897 store
= ir3_STLW(b
, offset
, 0,
898 ir3_create_collect(ctx
, &value
[first_component
], length
), 0,
899 create_immed(b
, length
), 0);
901 store
->cat6
.dst_offset
= first_component
+ base
;
902 store
->cat6
.type
= utype_src(intr
->src
[0]);
903 store
->barrier_class
= IR3_BARRIER_SHARED_W
;
904 store
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
906 array_insert(b
, b
->keeps
, store
);
908 /* Clear the bits in the writemask that we just wrote, then try
909 * again to see if more channels are left.
911 wrmask
&= (15 << (first_component
+ length
));
916 * CS shared variable atomic intrinsics
918 * All of the shared variable atomic memory operations read a value from
919 * memory, compute a new value using one of the operations below, write the
920 * new value to memory, and return the original value read.
922 * All operations take 2 sources except CompSwap that takes 3. These
925 * 0: The offset into the shared variable storage region that the atomic
926 * operation will operate on.
927 * 1: The data parameter to the atomic function (i.e. the value to add
928 * in shared_atomic_add, etc).
929 * 2: For CompSwap only: the second data parameter.
931 static struct ir3_instruction
*
932 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
934 struct ir3_block
*b
= ctx
->block
;
935 struct ir3_instruction
*atomic
, *src0
, *src1
;
936 type_t type
= TYPE_U32
;
938 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0]; /* offset */
939 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0]; /* value */
941 switch (intr
->intrinsic
) {
942 case nir_intrinsic_shared_atomic_add
:
943 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
945 case nir_intrinsic_shared_atomic_imin
:
946 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
949 case nir_intrinsic_shared_atomic_umin
:
950 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
952 case nir_intrinsic_shared_atomic_imax
:
953 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
956 case nir_intrinsic_shared_atomic_umax
:
957 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
959 case nir_intrinsic_shared_atomic_and
:
960 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
962 case nir_intrinsic_shared_atomic_or
:
963 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
965 case nir_intrinsic_shared_atomic_xor
:
966 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
968 case nir_intrinsic_shared_atomic_exchange
:
969 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
971 case nir_intrinsic_shared_atomic_comp_swap
:
972 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
973 src1
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
974 ir3_get_src(ctx
, &intr
->src
[2])[0],
977 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
983 atomic
->cat6
.iim_val
= 1;
985 atomic
->cat6
.type
= type
;
986 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
987 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
989 /* even if nothing consume the result, we can't DCE the instruction: */
990 array_insert(b
, b
->keeps
, atomic
);
995 /* TODO handle actual indirect/dynamic case.. which is going to be weird
996 * to handle with the image_mapping table..
998 static struct ir3_instruction
*
999 get_image_samp_tex_src(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1001 unsigned slot
= ir3_get_image_slot(nir_src_as_deref(intr
->src
[0]));
1002 unsigned tex_idx
= ir3_image_to_tex(&ctx
->so
->image_mapping
, slot
);
1003 struct ir3_instruction
*texture
, *sampler
;
1005 texture
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
1006 sampler
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
1008 return ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1014 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1016 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1017 struct ir3_instruction
**dst
)
1019 struct ir3_block
*b
= ctx
->block
;
1020 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
1021 struct ir3_instruction
*samp_tex
= get_image_samp_tex_src(ctx
, intr
);
1022 struct ir3_instruction
*sam
;
1023 struct ir3_instruction
* const *src0
= ir3_get_src(ctx
, &intr
->src
[1]);
1024 struct ir3_instruction
*coords
[4];
1025 unsigned flags
, ncoords
= ir3_get_image_coords(var
, &flags
);
1026 type_t type
= ir3_get_image_type(var
);
1028 /* hmm, this seems a bit odd, but it is what blob does and (at least
1029 * a5xx) just faults on bogus addresses otherwise:
1031 if (flags
& IR3_INSTR_3D
) {
1032 flags
&= ~IR3_INSTR_3D
;
1033 flags
|= IR3_INSTR_A
;
1036 for (unsigned i
= 0; i
< ncoords
; i
++)
1037 coords
[i
] = src0
[i
];
1040 coords
[ncoords
++] = create_immed(b
, 0);
1042 sam
= ir3_SAM(b
, OPC_ISAM
, type
, 0b1111, flags
,
1043 samp_tex
, ir3_create_collect(ctx
, coords
, ncoords
), NULL
);
1045 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
1046 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
1048 ir3_split_dest(b
, dst
, sam
, 0, 4);
1052 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1053 struct ir3_instruction
**dst
)
1055 struct ir3_block
*b
= ctx
->block
;
1056 const nir_variable
*var
= nir_intrinsic_get_var(intr
, 0);
1057 struct ir3_instruction
*samp_tex
= get_image_samp_tex_src(ctx
, intr
);
1058 struct ir3_instruction
*sam
, *lod
;
1059 unsigned flags
, ncoords
= ir3_get_image_coords(var
, &flags
);
1061 lod
= create_immed(b
, 0);
1062 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, 0b1111, flags
,
1063 samp_tex
, lod
, NULL
);
1065 /* Array size actually ends up in .w rather than .z. This doesn't
1066 * matter for miplevel 0, but for higher mips the value in z is
1067 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1068 * returned, which means that we have to add 1 to it for arrays for
1071 * Note use a temporary dst and then copy, since the size of the dst
1072 * array that is passed in is based on nir's understanding of the
1073 * result size, not the hardware's
1075 struct ir3_instruction
*tmp
[4];
1077 ir3_split_dest(b
, tmp
, sam
, 0, 4);
1079 /* get_size instruction returns size in bytes instead of texels
1080 * for imageBuffer, so we need to divide it by the pixel size
1081 * of the image format.
1083 * TODO: This is at least true on a5xx. Check other gens.
1085 enum glsl_sampler_dim dim
=
1086 glsl_get_sampler_dim(glsl_without_array(var
->type
));
1087 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
1088 /* Since all the possible values the divisor can take are
1089 * power-of-two (4, 8, or 16), the division is implemented
1091 * During shader setup, the log2 of the image format's
1092 * bytes-per-pixel should have been emitted in 2nd slot of
1093 * image_dims. See ir3_shader::emit_image_dims().
1095 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
1096 unsigned cb
= regid(const_state
->offsets
.image_dims
, 0) +
1097 const_state
->image_dims
.off
[var
->data
.driver_location
];
1098 struct ir3_instruction
*aux
= create_uniform(b
, cb
+ 1);
1100 tmp
[0] = ir3_SHR_B(b
, tmp
[0], 0, aux
, 0);
1103 for (unsigned i
= 0; i
< ncoords
; i
++)
1106 if (flags
& IR3_INSTR_A
) {
1107 if (ctx
->compiler
->levels_add_one
) {
1108 dst
[ncoords
-1] = ir3_ADD_U(b
, tmp
[3], 0, create_immed(b
, 1), 0);
1110 dst
[ncoords
-1] = ir3_MOV(b
, tmp
[3], TYPE_U32
);
1116 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1118 struct ir3_block
*b
= ctx
->block
;
1119 struct ir3_instruction
*barrier
;
1121 switch (intr
->intrinsic
) {
1122 case nir_intrinsic_barrier
:
1123 barrier
= ir3_BAR(b
);
1124 barrier
->cat7
.g
= true;
1125 barrier
->cat7
.l
= true;
1126 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
1127 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1129 case nir_intrinsic_memory_barrier
:
1130 barrier
= ir3_FENCE(b
);
1131 barrier
->cat7
.g
= true;
1132 barrier
->cat7
.r
= true;
1133 barrier
->cat7
.w
= true;
1134 barrier
->cat7
.l
= true;
1135 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
1136 IR3_BARRIER_BUFFER_W
;
1137 barrier
->barrier_conflict
=
1138 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1139 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1141 case nir_intrinsic_memory_barrier_atomic_counter
:
1142 case nir_intrinsic_memory_barrier_buffer
:
1143 barrier
= ir3_FENCE(b
);
1144 barrier
->cat7
.g
= true;
1145 barrier
->cat7
.r
= true;
1146 barrier
->cat7
.w
= true;
1147 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1148 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
1149 IR3_BARRIER_BUFFER_W
;
1151 case nir_intrinsic_memory_barrier_image
:
1152 // TODO double check if this should have .g set
1153 barrier
= ir3_FENCE(b
);
1154 barrier
->cat7
.g
= true;
1155 barrier
->cat7
.r
= true;
1156 barrier
->cat7
.w
= true;
1157 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1158 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
1159 IR3_BARRIER_IMAGE_W
;
1161 case nir_intrinsic_memory_barrier_shared
:
1162 barrier
= ir3_FENCE(b
);
1163 barrier
->cat7
.g
= true;
1164 barrier
->cat7
.l
= true;
1165 barrier
->cat7
.r
= true;
1166 barrier
->cat7
.w
= true;
1167 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
1168 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
1169 IR3_BARRIER_SHARED_W
;
1171 case nir_intrinsic_group_memory_barrier
:
1172 barrier
= ir3_FENCE(b
);
1173 barrier
->cat7
.g
= true;
1174 barrier
->cat7
.l
= true;
1175 barrier
->cat7
.r
= true;
1176 barrier
->cat7
.w
= true;
1177 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
1178 IR3_BARRIER_IMAGE_W
|
1179 IR3_BARRIER_BUFFER_W
;
1180 barrier
->barrier_conflict
=
1181 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
1182 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1183 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1189 /* make sure barrier doesn't get DCE'd */
1190 array_insert(b
, b
->keeps
, barrier
);
1193 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
1194 gl_system_value slot
, unsigned compmask
,
1195 struct ir3_instruction
*instr
)
1197 struct ir3_shader_variant
*so
= ctx
->so
;
1198 unsigned r
= regid(so
->inputs_count
, 0);
1199 unsigned n
= so
->inputs_count
++;
1201 so
->inputs
[n
].sysval
= true;
1202 so
->inputs
[n
].slot
= slot
;
1203 so
->inputs
[n
].compmask
= compmask
;
1204 so
->inputs
[n
].regid
= r
;
1205 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1208 ctx
->ir
->ninputs
= MAX2(ctx
->ir
->ninputs
, r
+ 1);
1209 ctx
->ir
->inputs
[r
] = instr
;
1212 static void add_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
1213 struct ir3_instruction
*instr
)
1215 add_sysval_input_compmask(ctx
, slot
, 0x1, instr
);
1218 static struct ir3_instruction
*
1219 get_barycentric_centroid(struct ir3_context
*ctx
)
1221 if (!ctx
->ij_centroid
) {
1222 struct ir3_instruction
*xy
[2];
1223 struct ir3_instruction
*ij
;
1225 ij
= create_input_compmask(ctx
, 0, 0x3);
1226 ir3_split_dest(ctx
->block
, xy
, ij
, 0, 2);
1228 ctx
->ij_centroid
= ir3_create_collect(ctx
, xy
, 2);
1230 add_sysval_input_compmask(ctx
,
1231 SYSTEM_VALUE_BARYCENTRIC_CENTROID
,
1235 return ctx
->ij_centroid
;
1238 static struct ir3_instruction
*
1239 get_barycentric_sample(struct ir3_context
*ctx
)
1241 if (!ctx
->ij_sample
) {
1242 struct ir3_instruction
*xy
[2];
1243 struct ir3_instruction
*ij
;
1245 ij
= create_input_compmask(ctx
, 0, 0x3);
1246 ir3_split_dest(ctx
->block
, xy
, ij
, 0, 2);
1248 ctx
->ij_sample
= ir3_create_collect(ctx
, xy
, 2);
1250 add_sysval_input_compmask(ctx
,
1251 SYSTEM_VALUE_BARYCENTRIC_SAMPLE
,
1255 return ctx
->ij_sample
;
1258 static struct ir3_instruction
*
1259 get_barycentric_pixel(struct ir3_context
*ctx
)
1261 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1262 * this to create ij_pixel only on demand:
1264 return ctx
->ij_pixel
;
1267 static struct ir3_instruction
*
1268 get_frag_coord(struct ir3_context
*ctx
)
1270 if (!ctx
->frag_coord
) {
1271 struct ir3_block
*b
= ctx
->block
;
1272 struct ir3_instruction
*xyzw
[4];
1273 struct ir3_instruction
*hw_frag_coord
;
1275 hw_frag_coord
= create_input_compmask(ctx
, 0, 0xf);
1276 ir3_split_dest(ctx
->block
, xyzw
, hw_frag_coord
, 0, 4);
1278 /* for frag_coord.xy, we get unsigned values.. we need
1279 * to subtract (integer) 8 and divide by 16 (right-
1280 * shift by 4) then convert to float:
1284 * mov.u32f32 dst, tmp
1287 for (int i
= 0; i
< 2; i
++) {
1288 xyzw
[i
] = ir3_SUB_S(b
, xyzw
[i
], 0,
1289 create_immed(b
, 8), 0);
1290 xyzw
[i
] = ir3_SHR_B(b
, xyzw
[i
], 0,
1291 create_immed(b
, 4), 0);
1292 xyzw
[i
] = ir3_COV(b
, xyzw
[i
], TYPE_U32
, TYPE_F32
);
1295 ctx
->frag_coord
= ir3_create_collect(ctx
, xyzw
, 4);
1297 add_sysval_input_compmask(ctx
,
1298 SYSTEM_VALUE_FRAG_COORD
,
1299 0xf, hw_frag_coord
);
1301 ctx
->so
->frag_coord
= true;
1304 return ctx
->frag_coord
;
1308 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1310 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1311 struct ir3_instruction
**dst
;
1312 struct ir3_instruction
* const *src
;
1313 struct ir3_block
*b
= ctx
->block
;
1316 if (info
->has_dest
) {
1317 unsigned n
= nir_intrinsic_dest_components(intr
);
1318 dst
= ir3_get_dst(ctx
, &intr
->dest
, n
);
1323 const unsigned primitive_param
= ctx
->so
->shader
->const_state
.offsets
.primitive_param
* 4;
1324 const unsigned primitive_map
= ctx
->so
->shader
->const_state
.offsets
.primitive_map
* 4;
1326 switch (intr
->intrinsic
) {
1327 case nir_intrinsic_load_uniform
:
1328 idx
= nir_intrinsic_base(intr
);
1329 if (nir_src_is_const(intr
->src
[0])) {
1330 idx
+= nir_src_as_uint(intr
->src
[0]);
1331 for (int i
= 0; i
< intr
->num_components
; i
++) {
1332 dst
[i
] = create_uniform_typed(b
, idx
+ i
,
1333 nir_dest_bit_size(intr
->dest
) < 32 ? TYPE_F16
: TYPE_F32
);
1336 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1337 for (int i
= 0; i
< intr
->num_components
; i
++) {
1338 dst
[i
] = create_uniform_indirect(b
, idx
+ i
,
1339 ir3_get_addr(ctx
, src
[0], 1));
1341 /* NOTE: if relative addressing is used, we set
1342 * constlen in the compiler (to worst-case value)
1343 * since we don't know in the assembler what the max
1344 * addr reg value can be:
1346 ctx
->so
->constlen
= MAX2(ctx
->so
->constlen
,
1347 ctx
->so
->shader
->ubo_state
.size
/ 16);
1351 case nir_intrinsic_load_vs_primitive_stride_ir3
:
1352 dst
[0] = create_uniform(b
, primitive_param
+ 0);
1354 case nir_intrinsic_load_vs_vertex_stride_ir3
:
1355 dst
[0] = create_uniform(b
, primitive_param
+ 1);
1357 case nir_intrinsic_load_primitive_location_ir3
:
1358 idx
= nir_intrinsic_driver_location(intr
);
1359 dst
[0] = create_uniform(b
, primitive_map
+ idx
);
1362 case nir_intrinsic_load_ubo
:
1363 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1365 case nir_intrinsic_load_frag_coord
:
1366 ir3_split_dest(b
, dst
, get_frag_coord(ctx
), 0, 4);
1368 case nir_intrinsic_load_sample_pos_from_id
: {
1369 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1370 * but that doesn't seem necessary.
1372 struct ir3_instruction
*offset
=
1373 ir3_RGETPOS(b
, ir3_get_src(ctx
, &intr
->src
[0])[0], 0);
1374 offset
->regs
[0]->wrmask
= 0x3;
1375 offset
->cat5
.type
= TYPE_F32
;
1377 ir3_split_dest(b
, dst
, offset
, 0, 2);
1381 case nir_intrinsic_load_size_ir3
:
1382 if (!ctx
->ij_size
) {
1383 ctx
->ij_size
= create_input(ctx
, 0);
1385 add_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_SIZE
,
1388 dst
[0] = ctx
->ij_size
;
1390 case nir_intrinsic_load_barycentric_centroid
:
1391 ir3_split_dest(b
, dst
, get_barycentric_centroid(ctx
), 0, 2);
1393 case nir_intrinsic_load_barycentric_sample
:
1394 if (ctx
->so
->key
.msaa
) {
1395 ir3_split_dest(b
, dst
, get_barycentric_sample(ctx
), 0, 2);
1397 ir3_split_dest(b
, dst
, get_barycentric_pixel(ctx
), 0, 2);
1400 case nir_intrinsic_load_barycentric_pixel
:
1401 ir3_split_dest(b
, dst
, get_barycentric_pixel(ctx
), 0, 2);
1403 case nir_intrinsic_load_interpolated_input
:
1404 idx
= nir_intrinsic_base(intr
);
1405 comp
= nir_intrinsic_component(intr
);
1406 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1407 if (nir_src_is_const(intr
->src
[1])) {
1408 struct ir3_instruction
*coord
= ir3_create_collect(ctx
, src
, 2);
1409 idx
+= nir_src_as_uint(intr
->src
[1]);
1410 for (int i
= 0; i
< intr
->num_components
; i
++) {
1411 unsigned inloc
= idx
* 4 + i
+ comp
;
1412 if (ctx
->so
->inputs
[idx
].bary
&&
1413 !ctx
->so
->inputs
[idx
].use_ldlv
) {
1414 dst
[i
] = ir3_BARY_F(b
, create_immed(b
, inloc
), 0, coord
, 0);
1416 /* for non-varyings use the pre-setup input, since
1417 * that is easier than mapping things back to a
1418 * nir_variable to figure out what it is.
1420 dst
[i
] = ctx
->ir
->inputs
[inloc
];
1424 ir3_context_error(ctx
, "unhandled");
1427 case nir_intrinsic_load_input
:
1428 idx
= nir_intrinsic_base(intr
);
1429 comp
= nir_intrinsic_component(intr
);
1430 if (nir_src_is_const(intr
->src
[0])) {
1431 idx
+= nir_src_as_uint(intr
->src
[0]);
1432 for (int i
= 0; i
< intr
->num_components
; i
++) {
1433 unsigned n
= idx
* 4 + i
+ comp
;
1434 dst
[i
] = ctx
->ir
->inputs
[n
];
1435 compile_assert(ctx
, ctx
->ir
->inputs
[n
]);
1438 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1439 struct ir3_instruction
*collect
=
1440 ir3_create_collect(ctx
, ctx
->ir
->inputs
, ctx
->ir
->ninputs
);
1441 struct ir3_instruction
*addr
= ir3_get_addr(ctx
, src
[0], 4);
1442 for (int i
= 0; i
< intr
->num_components
; i
++) {
1443 unsigned n
= idx
* 4 + i
+ comp
;
1444 dst
[i
] = create_indirect_load(ctx
, ctx
->ir
->ninputs
,
1449 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1450 * pass and replaced by an ir3-specifc version that adds the
1451 * dword-offset in the last source.
1453 case nir_intrinsic_load_ssbo_ir3
:
1454 ctx
->funcs
->emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
1456 case nir_intrinsic_store_ssbo_ir3
:
1457 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1458 !ctx
->s
->info
.fs
.early_fragment_tests
)
1459 ctx
->so
->no_earlyz
= true;
1460 ctx
->funcs
->emit_intrinsic_store_ssbo(ctx
, intr
);
1462 case nir_intrinsic_get_buffer_size
:
1463 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
1465 case nir_intrinsic_ssbo_atomic_add_ir3
:
1466 case nir_intrinsic_ssbo_atomic_imin_ir3
:
1467 case nir_intrinsic_ssbo_atomic_umin_ir3
:
1468 case nir_intrinsic_ssbo_atomic_imax_ir3
:
1469 case nir_intrinsic_ssbo_atomic_umax_ir3
:
1470 case nir_intrinsic_ssbo_atomic_and_ir3
:
1471 case nir_intrinsic_ssbo_atomic_or_ir3
:
1472 case nir_intrinsic_ssbo_atomic_xor_ir3
:
1473 case nir_intrinsic_ssbo_atomic_exchange_ir3
:
1474 case nir_intrinsic_ssbo_atomic_comp_swap_ir3
:
1475 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1476 !ctx
->s
->info
.fs
.early_fragment_tests
)
1477 ctx
->so
->no_earlyz
= true;
1478 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_ssbo(ctx
, intr
);
1480 case nir_intrinsic_load_shared
:
1481 emit_intrinsic_load_shared(ctx
, intr
, dst
);
1483 case nir_intrinsic_store_shared
:
1484 emit_intrinsic_store_shared(ctx
, intr
);
1486 case nir_intrinsic_shared_atomic_add
:
1487 case nir_intrinsic_shared_atomic_imin
:
1488 case nir_intrinsic_shared_atomic_umin
:
1489 case nir_intrinsic_shared_atomic_imax
:
1490 case nir_intrinsic_shared_atomic_umax
:
1491 case nir_intrinsic_shared_atomic_and
:
1492 case nir_intrinsic_shared_atomic_or
:
1493 case nir_intrinsic_shared_atomic_xor
:
1494 case nir_intrinsic_shared_atomic_exchange
:
1495 case nir_intrinsic_shared_atomic_comp_swap
:
1496 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
1498 case nir_intrinsic_image_deref_load
:
1499 emit_intrinsic_load_image(ctx
, intr
, dst
);
1501 case nir_intrinsic_image_deref_store
:
1502 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1503 !ctx
->s
->info
.fs
.early_fragment_tests
)
1504 ctx
->so
->no_earlyz
= true;
1505 ctx
->funcs
->emit_intrinsic_store_image(ctx
, intr
);
1507 case nir_intrinsic_image_deref_size
:
1508 emit_intrinsic_image_size(ctx
, intr
, dst
);
1510 case nir_intrinsic_image_deref_atomic_add
:
1511 case nir_intrinsic_image_deref_atomic_imin
:
1512 case nir_intrinsic_image_deref_atomic_umin
:
1513 case nir_intrinsic_image_deref_atomic_imax
:
1514 case nir_intrinsic_image_deref_atomic_umax
:
1515 case nir_intrinsic_image_deref_atomic_and
:
1516 case nir_intrinsic_image_deref_atomic_or
:
1517 case nir_intrinsic_image_deref_atomic_xor
:
1518 case nir_intrinsic_image_deref_atomic_exchange
:
1519 case nir_intrinsic_image_deref_atomic_comp_swap
:
1520 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1521 !ctx
->s
->info
.fs
.early_fragment_tests
)
1522 ctx
->so
->no_earlyz
= true;
1523 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_image(ctx
, intr
);
1525 case nir_intrinsic_barrier
:
1526 case nir_intrinsic_memory_barrier
:
1527 case nir_intrinsic_group_memory_barrier
:
1528 case nir_intrinsic_memory_barrier_atomic_counter
:
1529 case nir_intrinsic_memory_barrier_buffer
:
1530 case nir_intrinsic_memory_barrier_image
:
1531 case nir_intrinsic_memory_barrier_shared
:
1532 emit_intrinsic_barrier(ctx
, intr
);
1533 /* note that blk ptr no longer valid, make that obvious: */
1536 case nir_intrinsic_store_output
:
1537 idx
= nir_intrinsic_base(intr
);
1538 comp
= nir_intrinsic_component(intr
);
1539 compile_assert(ctx
, nir_src_is_const(intr
->src
[1]));
1540 idx
+= nir_src_as_uint(intr
->src
[1]);
1542 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1543 for (int i
= 0; i
< intr
->num_components
; i
++) {
1544 unsigned n
= idx
* 4 + i
+ comp
;
1545 ctx
->ir
->outputs
[n
] = src
[i
];
1548 case nir_intrinsic_load_base_vertex
:
1549 case nir_intrinsic_load_first_vertex
:
1550 if (!ctx
->basevertex
) {
1551 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1552 add_sysval_input(ctx
, SYSTEM_VALUE_FIRST_VERTEX
, ctx
->basevertex
);
1554 dst
[0] = ctx
->basevertex
;
1556 case nir_intrinsic_load_vertex_id_zero_base
:
1557 case nir_intrinsic_load_vertex_id
:
1558 if (!ctx
->vertex_id
) {
1559 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
1560 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
1561 ctx
->vertex_id
= create_input(ctx
, 0);
1562 add_sysval_input(ctx
, sv
, ctx
->vertex_id
);
1564 dst
[0] = ctx
->vertex_id
;
1566 case nir_intrinsic_load_instance_id
:
1567 if (!ctx
->instance_id
) {
1568 ctx
->instance_id
= create_input(ctx
, 0);
1569 add_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
,
1572 dst
[0] = ctx
->instance_id
;
1574 case nir_intrinsic_load_sample_id
:
1575 ctx
->so
->per_samp
= true;
1577 case nir_intrinsic_load_sample_id_no_per_sample
:
1578 if (!ctx
->samp_id
) {
1579 ctx
->samp_id
= create_input(ctx
, 0);
1580 ctx
->samp_id
->regs
[0]->flags
|= IR3_REG_HALF
;
1581 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_ID
,
1584 dst
[0] = ir3_COV(b
, ctx
->samp_id
, TYPE_U16
, TYPE_U32
);
1586 case nir_intrinsic_load_sample_mask_in
:
1587 if (!ctx
->samp_mask_in
) {
1588 ctx
->samp_mask_in
= create_input(ctx
, 0);
1589 add_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_MASK_IN
,
1592 dst
[0] = ctx
->samp_mask_in
;
1594 case nir_intrinsic_load_user_clip_plane
:
1595 idx
= nir_intrinsic_ucp_id(intr
);
1596 for (int i
= 0; i
< intr
->num_components
; i
++) {
1597 unsigned n
= idx
* 4 + i
;
1598 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1601 case nir_intrinsic_load_front_face
:
1602 if (!ctx
->frag_face
) {
1603 ctx
->so
->frag_face
= true;
1604 ctx
->frag_face
= create_input(ctx
, 0);
1605 add_sysval_input(ctx
, SYSTEM_VALUE_FRONT_FACE
, ctx
->frag_face
);
1606 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
1608 /* for fragface, we get -1 for back and 0 for front. However this is
1609 * the inverse of what nir expects (where ~0 is true).
1611 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
1612 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
1614 case nir_intrinsic_load_local_invocation_id
:
1615 if (!ctx
->local_invocation_id
) {
1616 ctx
->local_invocation_id
= create_input_compmask(ctx
, 0, 0x7);
1617 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
,
1618 0x7, ctx
->local_invocation_id
);
1620 ir3_split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
1622 case nir_intrinsic_load_work_group_id
:
1623 if (!ctx
->work_group_id
) {
1624 ctx
->work_group_id
= create_input_compmask(ctx
, 0, 0x7);
1625 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
,
1626 0x7, ctx
->work_group_id
);
1627 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
1629 ir3_split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
1631 case nir_intrinsic_load_num_work_groups
:
1632 for (int i
= 0; i
< intr
->num_components
; i
++) {
1633 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
1636 case nir_intrinsic_load_local_group_size
:
1637 for (int i
= 0; i
< intr
->num_components
; i
++) {
1638 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
1641 case nir_intrinsic_discard_if
:
1642 case nir_intrinsic_discard
: {
1643 struct ir3_instruction
*cond
, *kill
;
1645 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1646 /* conditional discard: */
1647 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1648 cond
= ir3_b2n(b
, src
[0]);
1650 /* unconditional discard: */
1651 cond
= create_immed(b
, 1);
1654 /* NOTE: only cmps.*.* can write p0.x: */
1655 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1656 cond
->cat2
.condition
= IR3_COND_NE
;
1658 /* condition always goes in predicate register: */
1659 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1661 kill
= ir3_KILL(b
, cond
, 0);
1662 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1664 array_insert(b
, b
->keeps
, kill
);
1665 ctx
->so
->no_earlyz
= true;
1669 case nir_intrinsic_load_shared_ir3
:
1670 emit_intrinsic_load_shared_ir3(ctx
, intr
, dst
);
1672 case nir_intrinsic_store_shared_ir3
:
1673 emit_intrinsic_store_shared_ir3(ctx
, intr
);
1676 ir3_context_error(ctx
, "Unhandled intrinsic type: %s\n",
1677 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1682 ir3_put_dst(ctx
, &intr
->dest
);
1686 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
1688 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &instr
->def
,
1689 instr
->def
.num_components
);
1691 if (instr
->def
.bit_size
< 32) {
1692 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1693 dst
[i
] = create_immed_typed(ctx
->block
,
1694 instr
->value
[i
].u16
,
1697 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1698 dst
[i
] = create_immed_typed(ctx
->block
,
1699 instr
->value
[i
].u32
,
1706 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
1708 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &undef
->def
,
1709 undef
->def
.num_components
);
1710 type_t type
= (undef
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
1712 /* backend doesn't want undefined instructions, so just plug
1715 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1716 dst
[i
] = create_immed_typed(ctx
->block
, fui(0.0), type
);
1720 * texture fetch/sample instructions:
1724 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
1726 unsigned coords
, flags
= 0;
1728 /* note: would use tex->coord_components.. except txs.. also,
1729 * since array index goes after shadow ref, we don't want to
1732 switch (tex
->sampler_dim
) {
1733 case GLSL_SAMPLER_DIM_1D
:
1734 case GLSL_SAMPLER_DIM_BUF
:
1737 case GLSL_SAMPLER_DIM_2D
:
1738 case GLSL_SAMPLER_DIM_RECT
:
1739 case GLSL_SAMPLER_DIM_EXTERNAL
:
1740 case GLSL_SAMPLER_DIM_MS
:
1743 case GLSL_SAMPLER_DIM_3D
:
1744 case GLSL_SAMPLER_DIM_CUBE
:
1746 flags
|= IR3_INSTR_3D
;
1749 unreachable("bad sampler_dim");
1752 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1753 flags
|= IR3_INSTR_S
;
1755 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
1756 flags
|= IR3_INSTR_A
;
1762 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1763 * or immediate (in which case it will get lowered later to a non .s2en
1764 * version of the tex instruction which encode tex/samp as immediates:
1766 static struct ir3_instruction
*
1767 get_tex_samp_tex_src(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
1769 int texture_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_texture_offset
);
1770 int sampler_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_sampler_offset
);
1771 struct ir3_instruction
*texture
, *sampler
;
1773 if (texture_idx
>= 0) {
1774 texture
= ir3_get_src(ctx
, &tex
->src
[texture_idx
].src
)[0];
1775 texture
= ir3_COV(ctx
->block
, texture
, TYPE_U32
, TYPE_U16
);
1777 /* TODO what to do for dynamic case? I guess we only need the
1778 * max index for astc srgb workaround so maybe not a problem
1779 * to worry about if we don't enable indirect samplers for
1782 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex
->texture_index
);
1783 texture
= create_immed_typed(ctx
->block
, tex
->texture_index
, TYPE_U16
);
1786 if (sampler_idx
>= 0) {
1787 sampler
= ir3_get_src(ctx
, &tex
->src
[sampler_idx
].src
)[0];
1788 sampler
= ir3_COV(ctx
->block
, sampler
, TYPE_U32
, TYPE_U16
);
1790 sampler
= create_immed_typed(ctx
->block
, tex
->sampler_index
, TYPE_U16
);
1793 return ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1800 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
1802 struct ir3_block
*b
= ctx
->block
;
1803 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
1804 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
1805 struct ir3_instruction
*lod
, *compare
, *proj
, *sample_index
;
1806 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
1807 unsigned i
, coords
, flags
, ncomp
;
1808 unsigned nsrc0
= 0, nsrc1
= 0;
1812 ncomp
= nir_dest_num_components(tex
->dest
);
1814 coord
= off
= ddx
= ddy
= NULL
;
1815 lod
= proj
= compare
= sample_index
= NULL
;
1817 dst
= ir3_get_dst(ctx
, &tex
->dest
, ncomp
);
1819 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1820 switch (tex
->src
[i
].src_type
) {
1821 case nir_tex_src_coord
:
1822 coord
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
1824 case nir_tex_src_bias
:
1825 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1828 case nir_tex_src_lod
:
1829 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1832 case nir_tex_src_comparator
: /* shadow comparator */
1833 compare
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1835 case nir_tex_src_projector
:
1836 proj
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1839 case nir_tex_src_offset
:
1840 off
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
1843 case nir_tex_src_ddx
:
1844 ddx
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
1846 case nir_tex_src_ddy
:
1847 ddy
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
1849 case nir_tex_src_ms_index
:
1850 sample_index
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
1852 case nir_tex_src_texture_offset
:
1853 case nir_tex_src_sampler_offset
:
1854 /* handled in get_tex_samp_src() */
1857 ir3_context_error(ctx
, "Unhandled NIR tex src type: %d\n",
1858 tex
->src
[i
].src_type
);
1864 case nir_texop_tex
: opc
= has_lod
? OPC_SAML
: OPC_SAM
; break;
1865 case nir_texop_txb
: opc
= OPC_SAMB
; break;
1866 case nir_texop_txl
: opc
= OPC_SAML
; break;
1867 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
1868 case nir_texop_txf
: opc
= OPC_ISAML
; break;
1869 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
1871 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1872 * what blob does, seems gather is broken?), and a3xx did
1873 * not support it (but probably could also emulate).
1875 switch (tex
->component
) {
1876 case 0: opc
= OPC_GATHER4R
; break;
1877 case 1: opc
= OPC_GATHER4G
; break;
1878 case 2: opc
= OPC_GATHER4B
; break;
1879 case 3: opc
= OPC_GATHER4A
; break;
1882 case nir_texop_txf_ms_fb
:
1883 case nir_texop_txf_ms
: opc
= OPC_ISAMM
; break;
1885 ir3_context_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
1889 tex_info(tex
, &flags
, &coords
);
1892 * lay out the first argument in the proper order:
1893 * - actual coordinates first
1894 * - shadow reference
1897 * - starting at offset 4, dpdx.xy, dpdy.xy
1899 * bias/lod go into the second arg
1902 /* insert tex coords: */
1903 for (i
= 0; i
< coords
; i
++)
1908 /* scale up integer coords for TXF based on the LOD */
1909 if (ctx
->compiler
->unminify_coords
&& (opc
== OPC_ISAML
)) {
1911 for (i
= 0; i
< coords
; i
++)
1912 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
1916 /* hw doesn't do 1d, so we treat it as 2d with
1917 * height of 1, and patch up the y coord.
1920 src0
[nsrc0
++] = create_immed(b
, 0);
1922 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
1926 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
1927 src0
[nsrc0
++] = compare
;
1929 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
1930 struct ir3_instruction
*idx
= coord
[coords
];
1932 /* the array coord for cube arrays needs 0.5 added to it */
1933 if (ctx
->compiler
->array_index_add_half
&& !is_isam(opc
))
1934 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
1936 src0
[nsrc0
++] = idx
;
1940 src0
[nsrc0
++] = proj
;
1941 flags
|= IR3_INSTR_P
;
1944 /* pad to 4, then ddx/ddy: */
1945 if (tex
->op
== nir_texop_txd
) {
1947 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1948 for (i
= 0; i
< coords
; i
++)
1949 src0
[nsrc0
++] = ddx
[i
];
1951 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1952 for (i
= 0; i
< coords
; i
++)
1953 src0
[nsrc0
++] = ddy
[i
];
1955 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
1958 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
1959 * with scaled x coord according to requested sample:
1961 if (opc
== OPC_ISAMM
) {
1962 if (ctx
->compiler
->txf_ms_with_isaml
) {
1963 /* the samples are laid out in x dimension as
1965 * x_ms = (x << ms) + sample_index;
1967 struct ir3_instruction
*ms
;
1968 ms
= create_immed(b
, (ctx
->samples
>> (2 * tex
->texture_index
)) & 3);
1970 src0
[0] = ir3_SHL_B(b
, src0
[0], 0, ms
, 0);
1971 src0
[0] = ir3_ADD_U(b
, src0
[0], 0, sample_index
, 0);
1975 src0
[nsrc0
++] = sample_index
;
1980 * second argument (if applicable):
1985 if (has_off
| has_lod
| has_bias
) {
1987 unsigned off_coords
= coords
;
1988 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
1990 for (i
= 0; i
< off_coords
; i
++)
1991 src1
[nsrc1
++] = off
[i
];
1993 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
1994 flags
|= IR3_INSTR_O
;
1997 if (has_lod
| has_bias
)
1998 src1
[nsrc1
++] = lod
;
2001 switch (tex
->dest_type
) {
2002 case nir_type_invalid
:
2003 case nir_type_float
:
2014 unreachable("bad dest_type");
2017 if (opc
== OPC_GETLOD
)
2020 struct ir3_instruction
*samp_tex
;
2022 if (tex
->op
== nir_texop_txf_ms_fb
) {
2023 /* only expect a single txf_ms_fb per shader: */
2024 compile_assert(ctx
, !ctx
->so
->fb_read
);
2025 compile_assert(ctx
, ctx
->so
->type
== MESA_SHADER_FRAGMENT
);
2027 ctx
->so
->fb_read
= true;
2028 samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2029 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
2030 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
2033 ctx
->so
->num_samp
++;
2035 samp_tex
= get_tex_samp_tex_src(ctx
, tex
);
2038 struct ir3_instruction
*col0
= ir3_create_collect(ctx
, src0
, nsrc0
);
2039 struct ir3_instruction
*col1
= ir3_create_collect(ctx
, src1
, nsrc1
);
2041 sam
= ir3_SAM(b
, opc
, type
, MASK(ncomp
), flags
,
2042 samp_tex
, col0
, col1
);
2044 if ((ctx
->astc_srgb
& (1 << tex
->texture_index
)) && !nir_tex_instr_is_query(tex
)) {
2045 /* only need first 3 components: */
2046 sam
->regs
[0]->wrmask
= 0x7;
2047 ir3_split_dest(b
, dst
, sam
, 0, 3);
2049 /* we need to sample the alpha separately with a non-ASTC
2052 sam
= ir3_SAM(b
, opc
, type
, 0b1000, flags
,
2053 samp_tex
, col0
, col1
);
2055 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2057 /* fixup .w component: */
2058 ir3_split_dest(b
, &dst
[3], sam
, 3, 1);
2060 /* normal (non-workaround) case: */
2061 ir3_split_dest(b
, dst
, sam
, 0, ncomp
);
2064 /* GETLOD returns results in 4.8 fixed point */
2065 if (opc
== OPC_GETLOD
) {
2066 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2068 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2069 for (i
= 0; i
< 2; i
++) {
2070 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_S32
, TYPE_F32
), 0,
2075 ir3_put_dst(ctx
, &tex
->dest
);
2079 emit_tex_info(struct ir3_context
*ctx
, nir_tex_instr
*tex
, unsigned idx
)
2081 struct ir3_block
*b
= ctx
->block
;
2082 struct ir3_instruction
**dst
, *sam
;
2084 dst
= ir3_get_dst(ctx
, &tex
->dest
, 1);
2086 sam
= ir3_SAM(b
, OPC_GETINFO
, TYPE_U32
, 1 << idx
, 0,
2087 get_tex_samp_tex_src(ctx
, tex
), NULL
, NULL
);
2089 /* even though there is only one component, since it ends
2090 * up in .y/.z/.w rather than .x, we need a split_dest()
2093 ir3_split_dest(b
, dst
, sam
, 0, idx
+ 1);
2095 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2096 * the value in TEX_CONST_0 is zero-based.
2098 if (ctx
->compiler
->levels_add_one
)
2099 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2101 ir3_put_dst(ctx
, &tex
->dest
);
2105 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2107 struct ir3_block
*b
= ctx
->block
;
2108 struct ir3_instruction
**dst
, *sam
;
2109 struct ir3_instruction
*lod
;
2110 unsigned flags
, coords
;
2112 tex_info(tex
, &flags
, &coords
);
2114 /* Actually we want the number of dimensions, not coordinates. This
2115 * distinction only matters for cubes.
2117 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2120 dst
= ir3_get_dst(ctx
, &tex
->dest
, 4);
2122 compile_assert(ctx
, tex
->num_srcs
== 1);
2123 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2125 lod
= ir3_get_src(ctx
, &tex
->src
[0].src
)[0];
2127 sam
= ir3_SAM(b
, OPC_GETSIZE
, TYPE_U32
, 0b1111, flags
,
2128 get_tex_samp_tex_src(ctx
, tex
), lod
, NULL
);
2130 ir3_split_dest(b
, dst
, sam
, 0, 4);
2132 /* Array size actually ends up in .w rather than .z. This doesn't
2133 * matter for miplevel 0, but for higher mips the value in z is
2134 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2135 * returned, which means that we have to add 1 to it for arrays.
2137 if (tex
->is_array
) {
2138 if (ctx
->compiler
->levels_add_one
) {
2139 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2141 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2145 ir3_put_dst(ctx
, &tex
->dest
);
2149 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2151 switch (jump
->type
) {
2152 case nir_jump_break
:
2153 case nir_jump_continue
:
2154 case nir_jump_return
:
2155 /* I *think* we can simply just ignore this, and use the
2156 * successor block link to figure out where we need to
2157 * jump to for break/continue
2161 ir3_context_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2167 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2169 switch (instr
->type
) {
2170 case nir_instr_type_alu
:
2171 emit_alu(ctx
, nir_instr_as_alu(instr
));
2173 case nir_instr_type_deref
:
2174 /* ignored, handled as part of the intrinsic they are src to */
2176 case nir_instr_type_intrinsic
:
2177 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2179 case nir_instr_type_load_const
:
2180 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2182 case nir_instr_type_ssa_undef
:
2183 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2185 case nir_instr_type_tex
: {
2186 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2187 /* couple tex instructions get special-cased:
2191 emit_tex_txs(ctx
, tex
);
2193 case nir_texop_query_levels
:
2194 emit_tex_info(ctx
, tex
, 2);
2196 case nir_texop_texture_samples
:
2197 emit_tex_info(ctx
, tex
, 3);
2205 case nir_instr_type_jump
:
2206 emit_jump(ctx
, nir_instr_as_jump(instr
));
2208 case nir_instr_type_phi
:
2209 /* we have converted phi webs to regs in NIR by now */
2210 ir3_context_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
2212 case nir_instr_type_call
:
2213 case nir_instr_type_parallel_copy
:
2214 ir3_context_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2219 static struct ir3_block
*
2220 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
2222 struct ir3_block
*block
;
2223 struct hash_entry
*hentry
;
2225 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2227 return hentry
->data
;
2229 block
= ir3_block_create(ctx
->ir
);
2230 block
->nblock
= nblock
;
2231 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2233 block
->predecessors
= _mesa_pointer_set_create(block
);
2234 set_foreach(nblock
->predecessors
, sentry
) {
2235 _mesa_set_add(block
->predecessors
, get_block(ctx
, sentry
->key
));
2242 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2244 struct ir3_block
*block
= get_block(ctx
, nblock
);
2246 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2247 if (nblock
->successors
[i
]) {
2248 block
->successors
[i
] =
2249 get_block(ctx
, nblock
->successors
[i
]);
2254 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2256 /* re-emit addr register in each block if needed: */
2257 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr_ht
); i
++) {
2258 _mesa_hash_table_destroy(ctx
->addr_ht
[i
], NULL
);
2259 ctx
->addr_ht
[i
] = NULL
;
2262 nir_foreach_instr(instr
, nblock
) {
2263 ctx
->cur_instr
= instr
;
2264 emit_instr(ctx
, instr
);
2265 ctx
->cur_instr
= NULL
;
2271 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
2274 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
2276 struct ir3_instruction
*condition
= ir3_get_src(ctx
, &nif
->condition
)[0];
2278 ctx
->block
->condition
=
2279 ir3_get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
2281 emit_cf_list(ctx
, &nif
->then_list
);
2282 emit_cf_list(ctx
, &nif
->else_list
);
2286 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
2288 emit_cf_list(ctx
, &nloop
->body
);
2293 stack_push(struct ir3_context
*ctx
)
2296 ctx
->max_stack
= MAX2(ctx
->max_stack
, ctx
->stack
);
2300 stack_pop(struct ir3_context
*ctx
)
2302 compile_assert(ctx
, ctx
->stack
> 0);
2307 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
2309 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2310 switch (node
->type
) {
2311 case nir_cf_node_block
:
2312 emit_block(ctx
, nir_cf_node_as_block(node
));
2314 case nir_cf_node_if
:
2316 emit_if(ctx
, nir_cf_node_as_if(node
));
2319 case nir_cf_node_loop
:
2321 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2324 case nir_cf_node_function
:
2325 ir3_context_error(ctx
, "TODO\n");
2331 /* emit stream-out code. At this point, the current block is the original
2332 * (nir) end block, and nir ensures that all flow control paths terminate
2333 * into the end block. We re-purpose the original end block to generate
2334 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2335 * block holding stream-out write instructions, followed by the new end
2339 * p0.x = (vtxcnt < maxvtxcnt)
2340 * // succs: blockStreamOut, blockNewEnd
2343 * ... stream-out instructions ...
2344 * // succs: blockNewEnd
2350 emit_stream_out(struct ir3_context
*ctx
)
2352 struct ir3
*ir
= ctx
->ir
;
2353 struct ir3_stream_output_info
*strmout
=
2354 &ctx
->so
->shader
->stream_output
;
2355 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2356 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2357 struct ir3_instruction
*bases
[IR3_MAX_SO_BUFFERS
];
2359 /* create vtxcnt input in input block at top of shader,
2360 * so that it is seen as live over the entire duration
2363 vtxcnt
= create_input(ctx
, 0);
2364 add_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, vtxcnt
);
2366 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2368 /* at this point, we are at the original 'end' block,
2369 * re-purpose this block to stream-out condition, then
2370 * append stream-out block and new-end block
2372 orig_end_block
= ctx
->block
;
2374 // TODO these blocks need to update predecessors..
2375 // maybe w/ store_global intrinsic, we could do this
2376 // stuff in nir->nir pass
2378 stream_out_block
= ir3_block_create(ir
);
2379 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2381 new_end_block
= ir3_block_create(ir
);
2382 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2384 orig_end_block
->successors
[0] = stream_out_block
;
2385 orig_end_block
->successors
[1] = new_end_block
;
2386 stream_out_block
->successors
[0] = new_end_block
;
2388 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2389 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2390 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2391 cond
->cat2
.condition
= IR3_COND_LT
;
2393 /* condition goes on previous block to the conditional,
2394 * since it is used to pick which of the two successor
2397 orig_end_block
->condition
= cond
;
2399 /* switch to stream_out_block to generate the stream-out
2402 ctx
->block
= stream_out_block
;
2404 /* Calculate base addresses based on vtxcnt. Instructions
2405 * generated for bases not used in following loop will be
2406 * stripped out in the backend.
2408 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
2409 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
2410 unsigned stride
= strmout
->stride
[i
];
2411 struct ir3_instruction
*base
, *off
;
2413 base
= create_uniform(ctx
->block
, regid(const_state
->offsets
.tfbo
, i
));
2415 /* 24-bit should be enough: */
2416 off
= ir3_MUL_U(ctx
->block
, vtxcnt
, 0,
2417 create_immed(ctx
->block
, stride
* 4), 0);
2419 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2422 /* Generate the per-output store instructions: */
2423 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2424 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2425 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2426 struct ir3_instruction
*base
, *out
, *stg
;
2428 base
= bases
[strmout
->output
[i
].output_buffer
];
2429 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2431 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2432 create_immed(ctx
->block
, 1), 0);
2433 stg
->cat6
.type
= TYPE_U32
;
2434 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2436 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2440 /* and finally switch to the new_end_block: */
2441 ctx
->block
= new_end_block
;
2445 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
2447 nir_metadata_require(impl
, nir_metadata_block_index
);
2449 compile_assert(ctx
, ctx
->stack
== 0);
2451 emit_cf_list(ctx
, &impl
->body
);
2452 emit_block(ctx
, impl
->end_block
);
2454 compile_assert(ctx
, ctx
->stack
== 0);
2456 /* at this point, we should have a single empty block,
2457 * into which we emit the 'end' instruction.
2459 compile_assert(ctx
, list_empty(&ctx
->block
->instr_list
));
2461 /* If stream-out (aka transform-feedback) enabled, emit the
2462 * stream-out instructions, followed by a new empty block (into
2463 * which the 'end' instruction lands).
2465 * NOTE: it is done in this order, rather than inserting before
2466 * we emit end_block, because NIR guarantees that all blocks
2467 * flow into end_block, and that end_block has no successors.
2468 * So by re-purposing end_block as the first block of stream-
2469 * out, we guarantee that all exit paths flow into the stream-
2472 if ((ctx
->compiler
->gpu_id
< 500) &&
2473 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2474 !ctx
->so
->binning_pass
) {
2475 debug_assert(ctx
->so
->type
== MESA_SHADER_VERTEX
);
2476 emit_stream_out(ctx
);
2479 ir3_END(ctx
->block
);
2483 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
2485 struct ir3_shader_variant
*so
= ctx
->so
;
2486 unsigned ncomp
= glsl_get_components(in
->type
);
2487 unsigned n
= in
->data
.driver_location
;
2488 unsigned frac
= in
->data
.location_frac
;
2489 unsigned slot
= in
->data
.location
;
2491 /* skip unread inputs, we could end up with (for example), unsplit
2492 * matrix/etc inputs in the case they are not read, so just silently
2498 so
->inputs
[n
].slot
= slot
;
2499 so
->inputs
[n
].compmask
= (1 << (ncomp
+ frac
)) - 1;
2500 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2501 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2503 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
2505 /* if any varyings have 'sample' qualifer, that triggers us
2506 * to run in per-sample mode:
2508 so
->per_samp
|= in
->data
.sample
;
2510 for (int i
= 0; i
< ncomp
; i
++) {
2511 struct ir3_instruction
*instr
= NULL
;
2512 unsigned idx
= (n
* 4) + i
+ frac
;
2514 if (slot
== VARYING_SLOT_POS
) {
2515 ir3_context_error(ctx
, "fragcoord should be a sysval!\n");
2516 } else if (slot
== VARYING_SLOT_PNTC
) {
2517 /* see for example st_nir_fixup_varying_slots().. this is
2518 * maybe a bit mesa/st specific. But we need things to line
2519 * up for this in fdN_program:
2520 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2521 * if (emit->sprite_coord_enable & texmask) {
2525 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
2526 so
->inputs
[n
].bary
= true;
2527 instr
= create_frag_input(ctx
, false, idx
);
2529 /* detect the special case for front/back colors where
2530 * we need to do flat vs smooth shading depending on
2533 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
2535 case VARYING_SLOT_COL0
:
2536 case VARYING_SLOT_COL1
:
2537 case VARYING_SLOT_BFC0
:
2538 case VARYING_SLOT_BFC1
:
2539 so
->inputs
[n
].rasterflat
= true;
2546 if (ctx
->compiler
->flat_bypass
) {
2547 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
2548 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2549 so
->inputs
[n
].use_ldlv
= true;
2552 so
->inputs
[n
].bary
= true;
2554 instr
= create_frag_input(ctx
, so
->inputs
[n
].use_ldlv
, idx
);
2557 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2559 ctx
->ir
->inputs
[idx
] = instr
;
2561 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
) {
2562 for (int i
= 0; i
< ncomp
; i
++) {
2563 unsigned idx
= (n
* 4) + i
+ frac
;
2564 compile_assert(ctx
, idx
< ctx
->ir
->ninputs
);
2565 ctx
->ir
->inputs
[idx
] = create_input(ctx
, idx
);
2568 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2571 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== MESA_SHADER_VERTEX
)) {
2572 so
->total_in
+= ncomp
;
2576 /* Initially we assign non-packed inloc's for varyings, as we don't really
2577 * know up-front which components will be unused. After all the compilation
2578 * stages we scan the shader to see which components are actually used, and
2579 * re-pack the inlocs to eliminate unneeded varyings.
2582 pack_inlocs(struct ir3_context
*ctx
)
2584 struct ir3_shader_variant
*so
= ctx
->so
;
2585 uint8_t used_components
[so
->inputs_count
];
2587 memset(used_components
, 0, sizeof(used_components
));
2590 * First Step: scan shader to find which bary.f/ldlv remain:
2593 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2594 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
2595 if (is_input(instr
)) {
2596 unsigned inloc
= instr
->regs
[1]->iim_val
;
2597 unsigned i
= inloc
/ 4;
2598 unsigned j
= inloc
% 4;
2600 compile_assert(ctx
, instr
->regs
[1]->flags
& IR3_REG_IMMED
);
2601 compile_assert(ctx
, i
< so
->inputs_count
);
2603 used_components
[i
] |= 1 << j
;
2609 * Second Step: reassign varying inloc/slots:
2612 unsigned actual_in
= 0;
2615 for (unsigned i
= 0; i
< so
->inputs_count
; i
++) {
2616 unsigned compmask
= 0, maxcomp
= 0;
2618 so
->inputs
[i
].inloc
= inloc
;
2619 so
->inputs
[i
].bary
= false;
2621 for (unsigned j
= 0; j
< 4; j
++) {
2622 if (!(used_components
[i
] & (1 << j
)))
2625 compmask
|= (1 << j
);
2629 /* at this point, since used_components[i] mask is only
2630 * considering varyings (ie. not sysvals) we know this
2633 so
->inputs
[i
].bary
= true;
2636 if (so
->inputs
[i
].bary
) {
2638 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
2644 * Third Step: reassign packed inloc's:
2647 list_for_each_entry (struct ir3_block
, block
, &ctx
->ir
->block_list
, node
) {
2648 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
2649 if (is_input(instr
)) {
2650 unsigned inloc
= instr
->regs
[1]->iim_val
;
2651 unsigned i
= inloc
/ 4;
2652 unsigned j
= inloc
% 4;
2654 instr
->regs
[1]->iim_val
= so
->inputs
[i
].inloc
+ j
;
2661 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
2663 struct ir3_shader_variant
*so
= ctx
->so
;
2664 unsigned ncomp
= glsl_get_components(out
->type
);
2665 unsigned n
= out
->data
.driver_location
;
2666 unsigned frac
= out
->data
.location_frac
;
2667 unsigned slot
= out
->data
.location
;
2670 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
2672 case FRAG_RESULT_DEPTH
:
2673 comp
= 2; /* tgsi will write to .z component */
2674 so
->writes_pos
= true;
2676 case FRAG_RESULT_COLOR
:
2679 case FRAG_RESULT_SAMPLE_MASK
:
2680 so
->writes_smask
= true;
2683 if (slot
>= FRAG_RESULT_DATA0
)
2685 ir3_context_error(ctx
, "unknown FS output name: %s\n",
2686 gl_frag_result_name(slot
));
2688 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
) {
2690 case VARYING_SLOT_POS
:
2691 so
->writes_pos
= true;
2693 case VARYING_SLOT_PSIZ
:
2694 so
->writes_psize
= true;
2696 case VARYING_SLOT_COL0
:
2697 case VARYING_SLOT_COL1
:
2698 case VARYING_SLOT_BFC0
:
2699 case VARYING_SLOT_BFC1
:
2700 case VARYING_SLOT_FOGC
:
2701 case VARYING_SLOT_CLIP_DIST0
:
2702 case VARYING_SLOT_CLIP_DIST1
:
2703 case VARYING_SLOT_CLIP_VERTEX
:
2706 if (slot
>= VARYING_SLOT_VAR0
)
2708 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
2710 ir3_context_error(ctx
, "unknown VS output name: %s\n",
2711 gl_varying_slot_name(slot
));
2714 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
2717 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
2719 so
->outputs
[n
].slot
= slot
;
2720 so
->outputs
[n
].regid
= regid(n
, comp
);
2721 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
2723 for (int i
= 0; i
< ncomp
; i
++) {
2724 unsigned idx
= (n
* 4) + i
+ frac
;
2725 compile_assert(ctx
, idx
< ctx
->ir
->noutputs
);
2726 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2729 /* if varying packing doesn't happen, we could end up in a situation
2730 * with "holes" in the output, and since the per-generation code that
2731 * sets up varying linkage registers doesn't expect to have more than
2732 * one varying per vec4 slot, pad the holes.
2734 * Note that this should probably generate a performance warning of
2737 for (int i
= 0; i
< frac
; i
++) {
2738 unsigned idx
= (n
* 4) + i
;
2739 if (!ctx
->ir
->outputs
[idx
]) {
2740 ctx
->ir
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
2746 max_drvloc(struct exec_list
*vars
)
2749 nir_foreach_variable(var
, vars
) {
2750 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
2755 static const unsigned max_sysvals
[] = {
2756 [MESA_SHADER_FRAGMENT
] = 24, // TODO
2757 [MESA_SHADER_VERTEX
] = 16,
2758 [MESA_SHADER_COMPUTE
] = 16, // TODO how many do we actually need?
2759 [MESA_SHADER_KERNEL
] = 16, // TODO how many do we actually need?
2763 emit_instructions(struct ir3_context
*ctx
)
2765 unsigned ninputs
, noutputs
;
2766 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
2768 ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
2769 noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
2771 /* we need to leave room for sysvals:
2773 ninputs
+= max_sysvals
[ctx
->so
->type
];
2775 ctx
->ir
= ir3_create(ctx
->compiler
, ctx
->so
->type
, ninputs
, noutputs
);
2777 /* Create inputs in first block: */
2778 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
2779 ctx
->in_block
= ctx
->block
;
2780 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
2782 ninputs
-= max_sysvals
[ctx
->so
->type
];
2784 /* for fragment shader, the vcoord input register is used as the
2785 * base for bary.f varying fetch instrs:
2787 * TODO defer creating ctx->ij_pixel and corresponding sysvals
2788 * until emit_intrinsic when we know they are actually needed.
2789 * For now, we defer creating ctx->ij_centroid, etc, since we
2790 * only need ij_pixel for "old style" varying inputs (ie.
2793 struct ir3_instruction
*vcoord
= NULL
;
2794 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
2795 struct ir3_instruction
*xy
[2];
2797 vcoord
= create_input_compmask(ctx
, 0, 0x3);
2798 ir3_split_dest(ctx
->block
, xy
, vcoord
, 0, 2);
2800 ctx
->ij_pixel
= ir3_create_collect(ctx
, xy
, 2);
2804 nir_foreach_variable(var
, &ctx
->s
->inputs
) {
2805 setup_input(ctx
, var
);
2808 /* Defer add_sysval_input() stuff until after setup_inputs(),
2809 * because sysvals need to be appended after varyings:
2812 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_BARYCENTRIC_PIXEL
,
2816 /* Setup outputs: */
2817 nir_foreach_variable(var
, &ctx
->s
->outputs
) {
2818 setup_output(ctx
, var
);
2821 /* Find # of samplers: */
2822 nir_foreach_variable(var
, &ctx
->s
->uniforms
) {
2823 ctx
->so
->num_samp
+= glsl_type_get_sampler_count(var
->type
);
2824 /* just assume that we'll be reading from images.. if it
2825 * is write-only we don't have to count it, but not sure
2826 * if there is a good way to know?
2828 ctx
->so
->num_samp
+= glsl_type_get_image_count(var
->type
);
2831 /* NOTE: need to do something more clever when we support >1 fxn */
2832 nir_foreach_register(reg
, &fxn
->registers
) {
2833 ir3_declare_array(ctx
, reg
);
2835 /* And emit the body: */
2837 emit_function(ctx
, fxn
);
2840 /* from NIR perspective, we actually have varying inputs. But the varying
2841 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
2842 * only actual inputs are the sysvals.
2845 fixup_frag_inputs(struct ir3_context
*ctx
)
2847 struct ir3_shader_variant
*so
= ctx
->so
;
2848 struct ir3
*ir
= ctx
->ir
;
2851 /* sysvals should appear at the end of the inputs, drop everything else: */
2852 while ((i
< so
->inputs_count
) && !so
->inputs
[i
].sysval
)
2855 /* at IR level, inputs are always blocks of 4 scalars: */
2858 ir
->inputs
= &ir
->inputs
[i
];
2862 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2863 * need to assign the tex state indexes for these after we know the
2867 fixup_astc_srgb(struct ir3_context
*ctx
)
2869 struct ir3_shader_variant
*so
= ctx
->so
;
2870 /* indexed by original tex idx, value is newly assigned alpha sampler
2871 * state tex idx. Zero is invalid since there is at least one sampler
2874 unsigned alt_tex_state
[16] = {0};
2875 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
2878 so
->astc_srgb
.base
= tex_idx
;
2880 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
2881 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
2883 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
2885 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
2886 /* assign new alternate/alpha tex state slot: */
2887 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
2888 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
2889 so
->astc_srgb
.count
++;
2892 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
2897 fixup_binning_pass(struct ir3_context
*ctx
)
2899 struct ir3_shader_variant
*so
= ctx
->so
;
2900 struct ir3
*ir
= ctx
->ir
;
2903 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
2904 unsigned slot
= so
->outputs
[i
].slot
;
2906 /* throw away everything but first position/psize */
2907 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
2909 so
->outputs
[j
] = so
->outputs
[i
];
2910 ir
->outputs
[(j
*4)+0] = ir
->outputs
[(i
*4)+0];
2911 ir
->outputs
[(j
*4)+1] = ir
->outputs
[(i
*4)+1];
2912 ir
->outputs
[(j
*4)+2] = ir
->outputs
[(i
*4)+2];
2913 ir
->outputs
[(j
*4)+3] = ir
->outputs
[(i
*4)+3];
2918 so
->outputs_count
= j
;
2919 ir
->noutputs
= j
* 4;
2923 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
2924 struct ir3_shader_variant
*so
)
2926 struct ir3_context
*ctx
;
2928 struct ir3_instruction
**inputs
;
2930 int ret
= 0, max_bary
;
2934 ctx
= ir3_context_init(compiler
, so
);
2936 DBG("INIT failed!");
2941 emit_instructions(ctx
);
2944 DBG("EMIT failed!");
2949 ir
= so
->ir
= ctx
->ir
;
2951 /* keep track of the inputs from TGSI perspective.. */
2952 inputs
= ir
->inputs
;
2954 /* but fixup actual inputs for frag shader: */
2955 if (so
->type
== MESA_SHADER_FRAGMENT
)
2956 fixup_frag_inputs(ctx
);
2958 /* at this point, for binning pass, throw away unneeded outputs: */
2959 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
< 600))
2960 fixup_binning_pass(ctx
);
2962 /* if we want half-precision outputs, mark the output registers
2965 if (so
->key
.half_precision
) {
2966 for (i
= 0; i
< ir
->noutputs
; i
++) {
2967 struct ir3_instruction
*out
= ir
->outputs
[i
];
2972 /* if frag shader writes z, that needs to be full precision: */
2973 if (so
->outputs
[i
/4].slot
== FRAG_RESULT_DEPTH
)
2976 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2977 /* output could be a fanout (ie. texture fetch output)
2978 * in which case we need to propagate the half-reg flag
2979 * up to the definer so that RA sees it:
2981 if (out
->opc
== OPC_META_FO
) {
2982 out
= out
->regs
[1]->instr
;
2983 out
->regs
[0]->flags
|= IR3_REG_HALF
;
2986 if (out
->opc
== OPC_MOV
) {
2987 out
->cat1
.dst_type
= half_type(out
->cat1
.dst_type
);
2992 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
2993 printf("BEFORE CP:\n");
2999 /* at this point, for binning pass, throw away unneeded outputs:
3000 * Note that for a6xx and later, we do this after ir3_cp to ensure
3001 * that the uniform/constant layout for BS and VS matches, so that
3002 * we can re-use same VS_CONST state group.
3004 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
>= 600))
3005 fixup_binning_pass(ctx
);
3007 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3008 * need to make sure not to remove any inputs that are used by
3009 * the nonbinning VS.
3011 if (ctx
->compiler
->gpu_id
>= 600 && so
->binning_pass
) {
3012 debug_assert(so
->type
== MESA_SHADER_VERTEX
);
3013 for (int i
= 0; i
< ir
->ninputs
; i
++) {
3014 struct ir3_instruction
*in
= ir
->inputs
[i
];
3022 debug_assert(n
< so
->nonbinning
->inputs_count
);
3024 if (so
->nonbinning
->inputs
[n
].sysval
)
3027 /* be sure to keep inputs, even if only used in VS */
3028 if (so
->nonbinning
->inputs
[n
].compmask
& (1 << c
))
3029 array_insert(in
->block
, in
->block
->keeps
, in
);
3033 /* Insert mov if there's same instruction for each output.
3034 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
3036 for (int i
= ir
->noutputs
- 1; i
>= 0; i
--) {
3037 if (!ir
->outputs
[i
])
3039 for (unsigned j
= 0; j
< i
; j
++) {
3040 if (ir
->outputs
[i
] == ir
->outputs
[j
]) {
3042 ir3_MOV(ir
->outputs
[i
]->block
, ir
->outputs
[i
], TYPE_F32
);
3047 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
3048 printf("BEFORE GROUPING:\n");
3052 ir3_sched_add_deps(ir
);
3054 /* Group left/right neighbors, inserting mov's where needed to
3059 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
3060 printf("AFTER GROUPING:\n");
3066 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
3067 printf("AFTER DEPTH:\n");
3071 /* do Sethi–Ullman numbering before scheduling: */
3074 ret
= ir3_sched(ir
);
3076 DBG("SCHED failed!");
3080 if (compiler
->gpu_id
>= 600) {
3081 ir3_a6xx_fixup_atomic_dests(ir
, so
);
3084 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
3085 printf("AFTER SCHED:\n");
3089 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3090 * with draw pass VS, so binning and draw pass can both use the
3093 * Note that VS inputs are expected to be full precision.
3095 bool pre_assign_inputs
= (ir
->compiler
->gpu_id
>= 600) &&
3096 (ir
->type
== MESA_SHADER_VERTEX
) &&
3099 if (pre_assign_inputs
) {
3100 for (unsigned i
= 0; i
< ir
->ninputs
; i
++) {
3101 struct ir3_instruction
*instr
= ir
->inputs
[i
];
3108 unsigned regid
= so
->nonbinning
->inputs
[n
].regid
+ c
;
3110 instr
->regs
[0]->num
= regid
;
3113 ret
= ir3_ra(so
, ir
->inputs
, ir
->ninputs
);
3115 ret
= ir3_ra(so
, NULL
, 0);
3123 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
3124 printf("AFTER RA:\n");
3128 if (so
->type
== MESA_SHADER_FRAGMENT
)
3131 /* fixup input/outputs: */
3132 for (i
= 0; i
< so
->outputs_count
; i
++) {
3133 /* sometimes we get outputs that don't write the .x coord, like:
3135 * decl_var shader_out INTERP_MODE_NONE float Color (VARYING_SLOT_VAR9.z, 1, 0)
3137 * Presumably the result of varying packing and then eliminating
3138 * some unneeded varyings? Just skip head to the first valid
3139 * component of the output.
3141 for (unsigned j
= 0; j
< 4; j
++) {
3142 struct ir3_instruction
*instr
= ir
->outputs
[(i
*4) + j
];
3144 so
->outputs
[i
].regid
= instr
->regs
[0]->num
;
3145 so
->outputs
[i
].half
= !!(instr
->regs
[0]->flags
& IR3_REG_HALF
);
3151 /* Note that some or all channels of an input may be unused: */
3152 for (i
= 0; i
< so
->inputs_count
; i
++) {
3153 unsigned j
, reg
= regid(63,0);
3155 for (j
= 0; j
< 4; j
++) {
3156 struct ir3_instruction
*in
= inputs
[(i
*4) + j
];
3161 if (in
->flags
& IR3_INSTR_UNUSED
)
3164 reg
= in
->regs
[0]->num
- j
;
3166 compile_assert(ctx
, in
->regs
[0]->flags
& IR3_REG_HALF
);
3168 half
= !!(in
->regs
[0]->flags
& IR3_REG_HALF
);
3171 so
->inputs
[i
].regid
= reg
;
3172 so
->inputs
[i
].half
= half
;
3176 fixup_astc_srgb(ctx
);
3178 /* We need to do legalize after (for frag shader's) the "bary.f"
3179 * offsets (inloc) have been assigned.
3181 ir3_legalize(ir
, &so
->has_ssbo
, &so
->need_pixlod
, &max_bary
);
3183 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
3184 printf("AFTER LEGALIZE:\n");
3188 so
->branchstack
= ctx
->max_stack
;
3190 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3191 if (so
->type
== MESA_SHADER_FRAGMENT
)
3192 so
->total_in
= max_bary
+ 1;
3194 so
->max_sun
= ir
->max_sun
;
3199 ir3_destroy(so
->ir
);
3202 ir3_context_free(ctx
);