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freedreno,tu: Don't request fragcoord components not being read.
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 __ssa_dst(mov);
55 src = __ssa_src(mov, collect, IR3_REG_RELATIV);
56 src->size = arrsz;
57 src->array.offset = n;
58
59 ir3_instr_set_address(mov, address);
60
61 return mov;
62 }
63
64 static struct ir3_instruction *
65 create_input(struct ir3_context *ctx, unsigned compmask)
66 {
67 struct ir3_instruction *in;
68
69 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
70 in->input.sysval = ~0;
71 __ssa_dst(in)->wrmask = compmask;
72
73 array_insert(ctx->ir, ctx->ir->inputs, in);
74
75 return in;
76 }
77
78 static struct ir3_instruction *
79 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
80 {
81 struct ir3_block *block = ctx->block;
82 struct ir3_instruction *instr;
83 /* packed inloc is fixed up later: */
84 struct ir3_instruction *inloc = create_immed(block, n);
85
86 if (use_ldlv) {
87 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
88 instr->cat6.type = TYPE_U32;
89 instr->cat6.iim_val = 1;
90 } else {
91 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
92 instr->regs[2]->wrmask = 0x3;
93 }
94
95 return instr;
96 }
97
98 static struct ir3_instruction *
99 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
100 {
101 /* first four vec4 sysval's reserved for UBOs: */
102 /* NOTE: dp is in scalar, but there can be >4 dp components: */
103 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
104 unsigned n = const_state->offsets.driver_param;
105 unsigned r = regid(n + dp / 4, dp % 4);
106 return create_uniform(ctx->block, r);
107 }
108
109 /*
110 * Adreno's comparisons produce a 1 for true and 0 for false, in either 16 or
111 * 32-bit registers. We use NIR's 1-bit integers to represent bools, and
112 * trust that we will only see and/or/xor on those 1-bit values, so we can
113 * safely store NIR i1s in a 32-bit reg while always containing either a 1 or
114 * 0.
115 */
116
117 /*
118 * alu/sfu instructions:
119 */
120
121 static struct ir3_instruction *
122 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
123 unsigned src_bitsize, nir_op op)
124 {
125 type_t src_type, dst_type;
126
127 switch (op) {
128 case nir_op_f2f32:
129 case nir_op_f2f16_rtne:
130 case nir_op_f2f16_rtz:
131 case nir_op_f2f16:
132 case nir_op_f2i32:
133 case nir_op_f2i16:
134 case nir_op_f2i8:
135 case nir_op_f2u32:
136 case nir_op_f2u16:
137 case nir_op_f2u8:
138 switch (src_bitsize) {
139 case 32:
140 src_type = TYPE_F32;
141 break;
142 case 16:
143 src_type = TYPE_F16;
144 break;
145 default:
146 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
147 }
148 break;
149
150 case nir_op_i2f32:
151 case nir_op_i2f16:
152 case nir_op_i2i32:
153 case nir_op_i2i16:
154 case nir_op_i2i8:
155 switch (src_bitsize) {
156 case 32:
157 src_type = TYPE_S32;
158 break;
159 case 16:
160 src_type = TYPE_S16;
161 break;
162 case 8:
163 src_type = TYPE_S8;
164 break;
165 default:
166 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
167 }
168 break;
169
170 case nir_op_u2f32:
171 case nir_op_u2f16:
172 case nir_op_u2u32:
173 case nir_op_u2u16:
174 case nir_op_u2u8:
175 switch (src_bitsize) {
176 case 32:
177 src_type = TYPE_U32;
178 break;
179 case 16:
180 src_type = TYPE_U16;
181 break;
182 case 8:
183 src_type = TYPE_U8;
184 break;
185 default:
186 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
187 }
188 break;
189
190 case nir_op_b2f16:
191 case nir_op_b2f32:
192 case nir_op_b2i8:
193 case nir_op_b2i16:
194 case nir_op_b2i32:
195 src_type = TYPE_U32;
196 break;
197
198 default:
199 ir3_context_error(ctx, "invalid conversion op: %u", op);
200 }
201
202 switch (op) {
203 case nir_op_f2f32:
204 case nir_op_i2f32:
205 case nir_op_u2f32:
206 case nir_op_b2f32:
207 dst_type = TYPE_F32;
208 break;
209
210 case nir_op_f2f16_rtne:
211 case nir_op_f2f16_rtz:
212 case nir_op_f2f16:
213 case nir_op_i2f16:
214 case nir_op_u2f16:
215 case nir_op_b2f16:
216 dst_type = TYPE_F16;
217 break;
218
219 case nir_op_f2i32:
220 case nir_op_i2i32:
221 case nir_op_b2i32:
222 dst_type = TYPE_S32;
223 break;
224
225 case nir_op_f2i16:
226 case nir_op_i2i16:
227 case nir_op_b2i16:
228 dst_type = TYPE_S16;
229 break;
230
231 case nir_op_f2i8:
232 case nir_op_i2i8:
233 case nir_op_b2i8:
234 dst_type = TYPE_S8;
235 break;
236
237 case nir_op_f2u32:
238 case nir_op_u2u32:
239 dst_type = TYPE_U32;
240 break;
241
242 case nir_op_f2u16:
243 case nir_op_u2u16:
244 dst_type = TYPE_U16;
245 break;
246
247 case nir_op_f2u8:
248 case nir_op_u2u8:
249 dst_type = TYPE_U8;
250 break;
251
252 default:
253 ir3_context_error(ctx, "invalid conversion op: %u", op);
254 }
255
256 if (src_type == dst_type)
257 return src;
258
259 struct ir3_instruction *cov =
260 ir3_COV(ctx->block, src, src_type, dst_type);
261
262 if (op == nir_op_f2f16_rtne)
263 cov->regs[0]->flags |= IR3_REG_EVEN;
264
265 return cov;
266 }
267
268 static void
269 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
270 {
271 const nir_op_info *info = &nir_op_infos[alu->op];
272 struct ir3_instruction **dst, *src[info->num_inputs];
273 unsigned bs[info->num_inputs]; /* bit size */
274 struct ir3_block *b = ctx->block;
275 unsigned dst_sz, wrmask;
276 type_t dst_type = nir_dest_bit_size(alu->dest.dest) == 16 ?
277 TYPE_U16 : TYPE_U32;
278
279 if (alu->dest.dest.is_ssa) {
280 dst_sz = alu->dest.dest.ssa.num_components;
281 wrmask = (1 << dst_sz) - 1;
282 } else {
283 dst_sz = alu->dest.dest.reg.reg->num_components;
284 wrmask = alu->dest.write_mask;
285 }
286
287 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
288
289 /* Vectors are special in that they have non-scalarized writemasks,
290 * and just take the first swizzle channel for each argument in
291 * order into each writemask channel.
292 */
293 if ((alu->op == nir_op_vec2) ||
294 (alu->op == nir_op_vec3) ||
295 (alu->op == nir_op_vec4)) {
296
297 for (int i = 0; i < info->num_inputs; i++) {
298 nir_alu_src *asrc = &alu->src[i];
299
300 compile_assert(ctx, !asrc->abs);
301 compile_assert(ctx, !asrc->negate);
302
303 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
304 if (!src[i])
305 src[i] = create_immed_typed(ctx->block, 0, dst_type);
306 dst[i] = ir3_MOV(b, src[i], dst_type);
307 }
308
309 ir3_put_dst(ctx, &alu->dest.dest);
310 return;
311 }
312
313 /* We also get mov's with more than one component for mov's so
314 * handle those specially:
315 */
316 if (alu->op == nir_op_mov) {
317 nir_alu_src *asrc = &alu->src[0];
318 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
319
320 for (unsigned i = 0; i < dst_sz; i++) {
321 if (wrmask & (1 << i)) {
322 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
323 } else {
324 dst[i] = NULL;
325 }
326 }
327
328 ir3_put_dst(ctx, &alu->dest.dest);
329 return;
330 }
331
332 /* General case: We can just grab the one used channel per src. */
333 for (int i = 0; i < info->num_inputs; i++) {
334 unsigned chan = ffs(alu->dest.write_mask) - 1;
335 nir_alu_src *asrc = &alu->src[i];
336
337 compile_assert(ctx, !asrc->abs);
338 compile_assert(ctx, !asrc->negate);
339
340 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
341 bs[i] = nir_src_bit_size(asrc->src);
342
343 compile_assert(ctx, src[i]);
344 }
345
346 switch (alu->op) {
347 case nir_op_f2f32:
348 case nir_op_f2f16_rtne:
349 case nir_op_f2f16_rtz:
350 case nir_op_f2f16:
351 case nir_op_f2i32:
352 case nir_op_f2i16:
353 case nir_op_f2i8:
354 case nir_op_f2u32:
355 case nir_op_f2u16:
356 case nir_op_f2u8:
357 case nir_op_i2f32:
358 case nir_op_i2f16:
359 case nir_op_i2i32:
360 case nir_op_i2i16:
361 case nir_op_i2i8:
362 case nir_op_u2f32:
363 case nir_op_u2f16:
364 case nir_op_u2u32:
365 case nir_op_u2u16:
366 case nir_op_u2u8:
367 case nir_op_b2f16:
368 case nir_op_b2f32:
369 case nir_op_b2i8:
370 case nir_op_b2i16:
371 case nir_op_b2i32:
372 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
373 break;
374
375 case nir_op_fquantize2f16:
376 dst[0] = create_cov(ctx,
377 create_cov(ctx, src[0], 32, nir_op_f2f16),
378 16, nir_op_f2f32);
379 break;
380 case nir_op_f2b1:
381 dst[0] = ir3_CMPS_F(b,
382 src[0], 0,
383 create_immed_typed(b, 0, bs[0] == 16 ? TYPE_F16 : TYPE_F32), 0);
384 dst[0]->cat2.condition = IR3_COND_NE;
385 break;
386
387 case nir_op_i2b1:
388 /* i2b1 will appear when translating from nir_load_ubo or
389 * nir_intrinsic_load_ssbo, where any non-zero value is true.
390 */
391 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
392 dst[0]->cat2.condition = IR3_COND_NE;
393 break;
394
395 case nir_op_b2b1:
396 /* b2b1 will appear when translating from
397 *
398 * - nir_intrinsic_load_shared of a 32-bit 0/~0 value.
399 * - nir_intrinsic_load_constant of a 32-bit 0/~0 value
400 *
401 * A negate can turn those into a 1 or 0 for us.
402 */
403 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
404 break;
405
406 case nir_op_b2b32:
407 /* b2b32 will appear when converting our 1-bit bools to a store_shared
408 * argument.
409 *
410 * A negate can turn those into a ~0 for us.
411 */
412 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
413 break;
414
415 case nir_op_fneg:
416 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
417 break;
418 case nir_op_fabs:
419 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
420 break;
421 case nir_op_fmax:
422 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
423 break;
424 case nir_op_fmin:
425 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
426 break;
427 case nir_op_fsat:
428 /* if there is just a single use of the src, and it supports
429 * (sat) bit, we can just fold the (sat) flag back to the
430 * src instruction and create a mov. This is easier for cp
431 * to eliminate.
432 *
433 * TODO probably opc_cat==4 is ok too
434 */
435 if (alu->src[0].src.is_ssa &&
436 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
437 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
438 src[0]->flags |= IR3_INSTR_SAT;
439 dst[0] = ir3_MOV(b, src[0], dst_type);
440 } else {
441 /* otherwise generate a max.f that saturates.. blob does
442 * similar (generating a cat2 mov using max.f)
443 */
444 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
445 dst[0]->flags |= IR3_INSTR_SAT;
446 }
447 break;
448 case nir_op_fmul:
449 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
450 break;
451 case nir_op_fadd:
452 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
453 break;
454 case nir_op_fsub:
455 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
456 break;
457 case nir_op_ffma:
458 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
459 break;
460 case nir_op_fddx:
461 case nir_op_fddx_coarse:
462 dst[0] = ir3_DSX(b, src[0], 0);
463 dst[0]->cat5.type = TYPE_F32;
464 break;
465 case nir_op_fddx_fine:
466 dst[0] = ir3_DSXPP_1(b, src[0], 0);
467 dst[0]->cat5.type = TYPE_F32;
468 break;
469 case nir_op_fddy:
470 case nir_op_fddy_coarse:
471 dst[0] = ir3_DSY(b, src[0], 0);
472 dst[0]->cat5.type = TYPE_F32;
473 break;
474 break;
475 case nir_op_fddy_fine:
476 dst[0] = ir3_DSYPP_1(b, src[0], 0);
477 dst[0]->cat5.type = TYPE_F32;
478 break;
479 case nir_op_flt:
480 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
481 dst[0]->cat2.condition = IR3_COND_LT;
482 break;
483 case nir_op_fge:
484 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
485 dst[0]->cat2.condition = IR3_COND_GE;
486 break;
487 case nir_op_feq:
488 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
489 dst[0]->cat2.condition = IR3_COND_EQ;
490 break;
491 case nir_op_fne:
492 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
493 dst[0]->cat2.condition = IR3_COND_NE;
494 break;
495 case nir_op_fceil:
496 dst[0] = ir3_CEIL_F(b, src[0], 0);
497 break;
498 case nir_op_ffloor:
499 dst[0] = ir3_FLOOR_F(b, src[0], 0);
500 break;
501 case nir_op_ftrunc:
502 dst[0] = ir3_TRUNC_F(b, src[0], 0);
503 break;
504 case nir_op_fround_even:
505 dst[0] = ir3_RNDNE_F(b, src[0], 0);
506 break;
507 case nir_op_fsign:
508 dst[0] = ir3_SIGN_F(b, src[0], 0);
509 break;
510
511 case nir_op_fsin:
512 dst[0] = ir3_SIN(b, src[0], 0);
513 break;
514 case nir_op_fcos:
515 dst[0] = ir3_COS(b, src[0], 0);
516 break;
517 case nir_op_frsq:
518 dst[0] = ir3_RSQ(b, src[0], 0);
519 break;
520 case nir_op_frcp:
521 dst[0] = ir3_RCP(b, src[0], 0);
522 break;
523 case nir_op_flog2:
524 dst[0] = ir3_LOG2(b, src[0], 0);
525 break;
526 case nir_op_fexp2:
527 dst[0] = ir3_EXP2(b, src[0], 0);
528 break;
529 case nir_op_fsqrt:
530 dst[0] = ir3_SQRT(b, src[0], 0);
531 break;
532
533 case nir_op_iabs:
534 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
535 break;
536 case nir_op_iadd:
537 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
538 break;
539 case nir_op_iand:
540 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
541 break;
542 case nir_op_imax:
543 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
544 break;
545 case nir_op_umax:
546 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
547 break;
548 case nir_op_imin:
549 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
550 break;
551 case nir_op_umin:
552 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
553 break;
554 case nir_op_umul_low:
555 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
556 break;
557 case nir_op_imadsh_mix16:
558 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
559 break;
560 case nir_op_imad24_ir3:
561 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
562 break;
563 case nir_op_imul24:
564 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
565 break;
566 case nir_op_ineg:
567 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
568 break;
569 case nir_op_inot:
570 if (bs[0] == 1) {
571 dst[0] = ir3_SUB_U(b, create_immed(ctx->block, 1), 0, src[0], 0);
572 } else {
573 dst[0] = ir3_NOT_B(b, src[0], 0);
574 }
575 break;
576 case nir_op_ior:
577 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
578 break;
579 case nir_op_ishl:
580 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
581 break;
582 case nir_op_ishr:
583 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
584 break;
585 case nir_op_isub:
586 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
587 break;
588 case nir_op_ixor:
589 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
590 break;
591 case nir_op_ushr:
592 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
593 break;
594 case nir_op_ilt:
595 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
596 dst[0]->cat2.condition = IR3_COND_LT;
597 break;
598 case nir_op_ige:
599 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
600 dst[0]->cat2.condition = IR3_COND_GE;
601 break;
602 case nir_op_ieq:
603 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
604 dst[0]->cat2.condition = IR3_COND_EQ;
605 break;
606 case nir_op_ine:
607 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
608 dst[0]->cat2.condition = IR3_COND_NE;
609 break;
610 case nir_op_ult:
611 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
612 dst[0]->cat2.condition = IR3_COND_LT;
613 break;
614 case nir_op_uge:
615 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
616 dst[0]->cat2.condition = IR3_COND_GE;
617 break;
618
619 case nir_op_bcsel: {
620 struct ir3_instruction *cond = src[0];
621
622 /* If src[0] is a negation (likely as a result of an ir3_b2n(cond)),
623 * we can ignore that and use original cond, since the nonzero-ness of
624 * cond stays the same.
625 */
626 if (cond->opc == OPC_ABSNEG_S &&
627 cond->flags == 0 &&
628 (cond->regs[1]->flags & (IR3_REG_SNEG | IR3_REG_SABS)) == IR3_REG_SNEG) {
629 cond = cond->regs[1]->instr;
630 }
631
632 compile_assert(ctx, bs[1] == bs[2]);
633 /* The condition's size has to match the other two arguments' size, so
634 * convert down if necessary.
635 */
636 if (bs[1] == 16) {
637 struct hash_entry *prev_entry =
638 _mesa_hash_table_search(ctx->sel_cond_conversions, src[0]);
639 if (prev_entry) {
640 cond = prev_entry->data;
641 } else {
642 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
643 _mesa_hash_table_insert(ctx->sel_cond_conversions, src[0], cond);
644 }
645 }
646
647 if (bs[1] != 16)
648 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
649 else
650 dst[0] = ir3_SEL_B16(b, src[1], 0, cond, 0, src[2], 0);
651 break;
652 }
653 case nir_op_bit_count: {
654 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
655 // double check on earlier gen's. Once half-precision support is
656 // in place, this should probably move to a NIR lowering pass:
657 struct ir3_instruction *hi, *lo;
658
659 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
660 TYPE_U32, TYPE_U16);
661 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
662
663 hi = ir3_CBITS_B(b, hi, 0);
664 lo = ir3_CBITS_B(b, lo, 0);
665
666 // TODO maybe the builders should default to making dst half-precision
667 // if the src's were half precision, to make this less awkward.. otoh
668 // we should probably just do this lowering in NIR.
669 hi->regs[0]->flags |= IR3_REG_HALF;
670 lo->regs[0]->flags |= IR3_REG_HALF;
671
672 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
673 dst[0]->regs[0]->flags |= IR3_REG_HALF;
674 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
675 break;
676 }
677 case nir_op_ifind_msb: {
678 struct ir3_instruction *cmp;
679 dst[0] = ir3_CLZ_S(b, src[0], 0);
680 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
681 cmp->cat2.condition = IR3_COND_GE;
682 dst[0] = ir3_SEL_B32(b,
683 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
684 cmp, 0, dst[0], 0);
685 break;
686 }
687 case nir_op_ufind_msb:
688 dst[0] = ir3_CLZ_B(b, src[0], 0);
689 dst[0] = ir3_SEL_B32(b,
690 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
691 src[0], 0, dst[0], 0);
692 break;
693 case nir_op_find_lsb:
694 dst[0] = ir3_BFREV_B(b, src[0], 0);
695 dst[0] = ir3_CLZ_B(b, dst[0], 0);
696 break;
697 case nir_op_bitfield_reverse:
698 dst[0] = ir3_BFREV_B(b, src[0], 0);
699 break;
700
701 default:
702 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
703 nir_op_infos[alu->op].name);
704 break;
705 }
706
707 if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) {
708 assert(nir_dest_bit_size(alu->dest.dest) == 1 ||
709 alu->op == nir_op_b2b32);
710 assert(dst_sz == 1);
711 } else {
712 /* 1-bit values stored in 32-bit registers are only valid for certain
713 * ALU ops.
714 */
715 switch (alu->op) {
716 case nir_op_iand:
717 case nir_op_ior:
718 case nir_op_ixor:
719 case nir_op_inot:
720 case nir_op_bcsel:
721 break;
722 default:
723 compile_assert(ctx, nir_dest_bit_size(alu->dest.dest) != 1);
724 }
725 }
726
727 ir3_put_dst(ctx, &alu->dest.dest);
728 }
729
730 static void
731 emit_intrinsic_load_ubo_ldc(struct ir3_context *ctx, nir_intrinsic_instr *intr,
732 struct ir3_instruction **dst)
733 {
734 struct ir3_block *b = ctx->block;
735
736 unsigned ncomp = intr->num_components;
737 struct ir3_instruction *offset = ir3_get_src(ctx, &intr->src[1])[0];
738 struct ir3_instruction *idx = ir3_get_src(ctx, &intr->src[0])[0];
739 struct ir3_instruction *ldc = ir3_LDC(b, idx, 0, offset, 0);
740 ldc->regs[0]->wrmask = MASK(ncomp);
741 ldc->cat6.iim_val = ncomp;
742 ldc->cat6.d = nir_intrinsic_base(intr);
743 ldc->cat6.type = TYPE_U32;
744
745 nir_intrinsic_instr *bindless = ir3_bindless_resource(intr->src[0]);
746 if (bindless) {
747 ldc->flags |= IR3_INSTR_B;
748 ldc->cat6.base = nir_intrinsic_desc_set(bindless);
749 ctx->so->bindless_ubo = true;
750 }
751
752 ir3_split_dest(b, dst, ldc, 0, ncomp);
753 }
754
755
756 /* handles direct/indirect UBO reads: */
757 static void
758 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
759 struct ir3_instruction **dst)
760 {
761 struct ir3_block *b = ctx->block;
762 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
763 /* UBO addresses are the first driver params, but subtract 2 here to
764 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
765 * is the uniforms: */
766 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
767 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
768 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
769
770 int off = 0;
771
772 /* First src is ubo index, which could either be an immed or not: */
773 src0 = ir3_get_src(ctx, &intr->src[0])[0];
774 if (is_same_type_mov(src0) &&
775 (src0->regs[1]->flags & IR3_REG_IMMED)) {
776 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
777 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
778 } else {
779 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr0(ctx, src0, ptrsz));
780 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr0(ctx, src0, ptrsz));
781
782 /* NOTE: since relative addressing is used, make sure constlen is
783 * at least big enough to cover all the UBO addresses, since the
784 * assembler won't know what the max address reg is.
785 */
786 ctx->so->constlen = MAX2(ctx->so->constlen,
787 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
788 }
789
790 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
791 addr = base_lo;
792
793 if (nir_src_is_const(intr->src[1])) {
794 off += nir_src_as_uint(intr->src[1]);
795 } else {
796 /* For load_ubo_indirect, second src is indirect offset: */
797 src1 = ir3_get_src(ctx, &intr->src[1])[0];
798
799 /* and add offset to addr: */
800 addr = ir3_ADD_S(b, addr, 0, src1, 0);
801 }
802
803 /* if offset is to large to encode in the ldg, split it out: */
804 if ((off + (intr->num_components * 4)) > 1024) {
805 /* split out the minimal amount to improve the odds that
806 * cp can fit the immediate in the add.s instruction:
807 */
808 unsigned off2 = off + (intr->num_components * 4) - 1024;
809 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
810 off -= off2;
811 }
812
813 if (ptrsz == 2) {
814 struct ir3_instruction *carry;
815
816 /* handle 32b rollover, ie:
817 * if (addr < base_lo)
818 * base_hi++
819 */
820 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
821 carry->cat2.condition = IR3_COND_LT;
822 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
823
824 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
825 }
826
827 for (int i = 0; i < intr->num_components; i++) {
828 struct ir3_instruction *load =
829 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
830 create_immed(b, off + i * 4), 0);
831 load->cat6.type = TYPE_U32;
832 dst[i] = load;
833 }
834 }
835
836 /* src[] = { block_index } */
837 static void
838 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
839 struct ir3_instruction **dst)
840 {
841 /* SSBO size stored as a const starting at ssbo_sizes: */
842 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
843 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
844 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
845 const_state->ssbo_size.off[blk_idx];
846
847 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
848
849 dst[0] = create_uniform(ctx->block, idx);
850 }
851
852 /* src[] = { offset }. const_index[] = { base } */
853 static void
854 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
855 struct ir3_instruction **dst)
856 {
857 struct ir3_block *b = ctx->block;
858 struct ir3_instruction *ldl, *offset;
859 unsigned base;
860
861 offset = ir3_get_src(ctx, &intr->src[0])[0];
862 base = nir_intrinsic_base(intr);
863
864 ldl = ir3_LDL(b, offset, 0,
865 create_immed(b, intr->num_components), 0,
866 create_immed(b, base), 0);
867
868 ldl->cat6.type = utype_dst(intr->dest);
869 ldl->regs[0]->wrmask = MASK(intr->num_components);
870
871 ldl->barrier_class = IR3_BARRIER_SHARED_R;
872 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
873
874 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
875 }
876
877 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
878 static void
879 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
880 {
881 struct ir3_block *b = ctx->block;
882 struct ir3_instruction *stl, *offset;
883 struct ir3_instruction * const *value;
884 unsigned base, wrmask;
885
886 value = ir3_get_src(ctx, &intr->src[0]);
887 offset = ir3_get_src(ctx, &intr->src[1])[0];
888
889 base = nir_intrinsic_base(intr);
890 wrmask = nir_intrinsic_write_mask(intr);
891
892 /* Combine groups of consecutive enabled channels in one write
893 * message. We use ffs to find the first enabled channel and then ffs on
894 * the bit-inverse, down-shifted writemask to determine the length of
895 * the block of enabled bits.
896 *
897 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
898 */
899 while (wrmask) {
900 unsigned first_component = ffs(wrmask) - 1;
901 unsigned length = ffs(~(wrmask >> first_component)) - 1;
902
903 stl = ir3_STL(b, offset, 0,
904 ir3_create_collect(ctx, &value[first_component], length), 0,
905 create_immed(b, length), 0);
906 stl->cat6.dst_offset = first_component + base;
907 stl->cat6.type = utype_src(intr->src[0]);
908 stl->barrier_class = IR3_BARRIER_SHARED_W;
909 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
910
911 array_insert(b, b->keeps, stl);
912
913 /* Clear the bits in the writemask that we just wrote, then try
914 * again to see if more channels are left.
915 */
916 wrmask &= (15 << (first_component + length));
917 }
918 }
919
920 /* src[] = { offset }. const_index[] = { base } */
921 static void
922 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
923 struct ir3_instruction **dst)
924 {
925 struct ir3_block *b = ctx->block;
926 struct ir3_instruction *load, *offset;
927 unsigned base;
928
929 offset = ir3_get_src(ctx, &intr->src[0])[0];
930 base = nir_intrinsic_base(intr);
931
932 load = ir3_LDLW(b, offset, 0,
933 create_immed(b, intr->num_components), 0,
934 create_immed(b, base), 0);
935
936 load->cat6.type = utype_dst(intr->dest);
937 load->regs[0]->wrmask = MASK(intr->num_components);
938
939 load->barrier_class = IR3_BARRIER_SHARED_R;
940 load->barrier_conflict = IR3_BARRIER_SHARED_W;
941
942 ir3_split_dest(b, dst, load, 0, intr->num_components);
943 }
944
945 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
946 static void
947 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
948 {
949 struct ir3_block *b = ctx->block;
950 struct ir3_instruction *store, *offset;
951 struct ir3_instruction * const *value;
952 unsigned base, wrmask;
953
954 value = ir3_get_src(ctx, &intr->src[0]);
955 offset = ir3_get_src(ctx, &intr->src[1])[0];
956
957 base = nir_intrinsic_base(intr);
958 wrmask = nir_intrinsic_write_mask(intr);
959
960 /* Combine groups of consecutive enabled channels in one write
961 * message. We use ffs to find the first enabled channel and then ffs on
962 * the bit-inverse, down-shifted writemask to determine the length of
963 * the block of enabled bits.
964 *
965 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
966 */
967 while (wrmask) {
968 unsigned first_component = ffs(wrmask) - 1;
969 unsigned length = ffs(~(wrmask >> first_component)) - 1;
970
971 store = ir3_STLW(b, offset, 0,
972 ir3_create_collect(ctx, &value[first_component], length), 0,
973 create_immed(b, length), 0);
974
975 store->cat6.dst_offset = first_component + base;
976 store->cat6.type = utype_src(intr->src[0]);
977 store->barrier_class = IR3_BARRIER_SHARED_W;
978 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
979
980 array_insert(b, b->keeps, store);
981
982 /* Clear the bits in the writemask that we just wrote, then try
983 * again to see if more channels are left.
984 */
985 wrmask &= (15 << (first_component + length));
986 }
987 }
988
989 /*
990 * CS shared variable atomic intrinsics
991 *
992 * All of the shared variable atomic memory operations read a value from
993 * memory, compute a new value using one of the operations below, write the
994 * new value to memory, and return the original value read.
995 *
996 * All operations take 2 sources except CompSwap that takes 3. These
997 * sources represent:
998 *
999 * 0: The offset into the shared variable storage region that the atomic
1000 * operation will operate on.
1001 * 1: The data parameter to the atomic function (i.e. the value to add
1002 * in shared_atomic_add, etc).
1003 * 2: For CompSwap only: the second data parameter.
1004 */
1005 static struct ir3_instruction *
1006 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1007 {
1008 struct ir3_block *b = ctx->block;
1009 struct ir3_instruction *atomic, *src0, *src1;
1010 type_t type = TYPE_U32;
1011
1012 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
1013 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
1014
1015 switch (intr->intrinsic) {
1016 case nir_intrinsic_shared_atomic_add:
1017 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
1018 break;
1019 case nir_intrinsic_shared_atomic_imin:
1020 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1021 type = TYPE_S32;
1022 break;
1023 case nir_intrinsic_shared_atomic_umin:
1024 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1025 break;
1026 case nir_intrinsic_shared_atomic_imax:
1027 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1028 type = TYPE_S32;
1029 break;
1030 case nir_intrinsic_shared_atomic_umax:
1031 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1032 break;
1033 case nir_intrinsic_shared_atomic_and:
1034 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
1035 break;
1036 case nir_intrinsic_shared_atomic_or:
1037 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
1038 break;
1039 case nir_intrinsic_shared_atomic_xor:
1040 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
1041 break;
1042 case nir_intrinsic_shared_atomic_exchange:
1043 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
1044 break;
1045 case nir_intrinsic_shared_atomic_comp_swap:
1046 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1047 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1048 ir3_get_src(ctx, &intr->src[2])[0],
1049 src1,
1050 }, 2);
1051 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
1052 break;
1053 default:
1054 unreachable("boo");
1055 }
1056
1057 atomic->cat6.iim_val = 1;
1058 atomic->cat6.d = 1;
1059 atomic->cat6.type = type;
1060 atomic->barrier_class = IR3_BARRIER_SHARED_W;
1061 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1062
1063 /* even if nothing consume the result, we can't DCE the instruction: */
1064 array_insert(b, b->keeps, atomic);
1065
1066 return atomic;
1067 }
1068
1069 struct tex_src_info {
1070 /* For prefetch */
1071 unsigned tex_base, samp_base, tex_idx, samp_idx;
1072 /* For normal tex instructions */
1073 unsigned base, combined_idx, a1_val, flags;
1074 struct ir3_instruction *samp_tex;
1075 };
1076
1077 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1078 * to handle with the image_mapping table..
1079 */
1080 static struct tex_src_info
1081 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1082 {
1083 struct ir3_block *b = ctx->block;
1084 struct tex_src_info info = { 0 };
1085 nir_intrinsic_instr *bindless_tex = ir3_bindless_resource(intr->src[0]);
1086 ctx->so->bindless_tex = true;
1087
1088 if (bindless_tex) {
1089 /* Bindless case */
1090 info.flags |= IR3_INSTR_B;
1091
1092 /* Gather information required to determine which encoding to
1093 * choose as well as for prefetch.
1094 */
1095 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
1096 bool tex_const = nir_src_is_const(bindless_tex->src[0]);
1097 if (tex_const)
1098 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
1099 info.samp_idx = 0;
1100
1101 /* Choose encoding. */
1102 if (tex_const && info.tex_idx < 256) {
1103 if (info.tex_idx < 16) {
1104 /* Everything fits within the instruction */
1105 info.base = info.tex_base;
1106 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
1107 } else {
1108 info.base = info.tex_base;
1109 info.a1_val = info.tex_idx << 3;
1110 info.combined_idx = 0;
1111 info.flags |= IR3_INSTR_A1EN;
1112 }
1113 info.samp_tex = NULL;
1114 } else {
1115 info.flags |= IR3_INSTR_S2EN;
1116 info.base = info.tex_base;
1117
1118 /* Note: the indirect source is now a vec2 instead of hvec2 */
1119 struct ir3_instruction *texture, *sampler;
1120
1121 texture = ir3_get_src(ctx, &intr->src[0])[0];
1122 sampler = create_immed(b, 0);
1123 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1124 texture,
1125 sampler,
1126 }, 2);
1127 }
1128 } else {
1129 info.flags |= IR3_INSTR_S2EN;
1130 unsigned slot = nir_src_as_uint(intr->src[0]);
1131 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1132 struct ir3_instruction *texture, *sampler;
1133
1134 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1135 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1136
1137 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1138 sampler,
1139 texture,
1140 }, 2);
1141 }
1142
1143 return info;
1144 }
1145
1146 static struct ir3_instruction *
1147 emit_sam(struct ir3_context *ctx, opc_t opc, struct tex_src_info info,
1148 type_t type, unsigned wrmask, struct ir3_instruction *src0,
1149 struct ir3_instruction *src1)
1150 {
1151 struct ir3_instruction *sam, *addr;
1152 if (info.flags & IR3_INSTR_A1EN) {
1153 addr = ir3_get_addr1(ctx, info.a1_val);
1154 }
1155 sam = ir3_SAM(ctx->block, opc, type, 0b1111, info.flags,
1156 info.samp_tex, src0, src1);
1157 if (info.flags & IR3_INSTR_A1EN) {
1158 ir3_instr_set_address(sam, addr);
1159 }
1160 if (info.flags & IR3_INSTR_B) {
1161 sam->cat5.tex_base = info.base;
1162 sam->cat5.samp = info.combined_idx;
1163 }
1164 return sam;
1165 }
1166
1167 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1168 static void
1169 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1170 struct ir3_instruction **dst)
1171 {
1172 struct ir3_block *b = ctx->block;
1173 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1174 struct ir3_instruction *sam;
1175 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1176 struct ir3_instruction *coords[4];
1177 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1178 type_t type = ir3_get_type_for_image_intrinsic(intr);
1179
1180 /* hmm, this seems a bit odd, but it is what blob does and (at least
1181 * a5xx) just faults on bogus addresses otherwise:
1182 */
1183 if (flags & IR3_INSTR_3D) {
1184 flags &= ~IR3_INSTR_3D;
1185 flags |= IR3_INSTR_A;
1186 }
1187 info.flags |= flags;
1188
1189 for (unsigned i = 0; i < ncoords; i++)
1190 coords[i] = src0[i];
1191
1192 if (ncoords == 1)
1193 coords[ncoords++] = create_immed(b, 0);
1194
1195 sam = emit_sam(ctx, OPC_ISAM, info, type, 0b1111,
1196 ir3_create_collect(ctx, coords, ncoords), NULL);
1197
1198 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1199 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1200
1201 ir3_split_dest(b, dst, sam, 0, 4);
1202 }
1203
1204 static void
1205 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1206 struct ir3_instruction **dst)
1207 {
1208 struct ir3_block *b = ctx->block;
1209 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1210 struct ir3_instruction *sam, *lod;
1211 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1212 type_t dst_type = nir_dest_bit_size(intr->dest) == 16 ?
1213 TYPE_U16 : TYPE_U32;
1214
1215 info.flags |= flags;
1216 lod = create_immed(b, 0);
1217 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
1218
1219 /* Array size actually ends up in .w rather than .z. This doesn't
1220 * matter for miplevel 0, but for higher mips the value in z is
1221 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1222 * returned, which means that we have to add 1 to it for arrays for
1223 * a3xx.
1224 *
1225 * Note use a temporary dst and then copy, since the size of the dst
1226 * array that is passed in is based on nir's understanding of the
1227 * result size, not the hardware's
1228 */
1229 struct ir3_instruction *tmp[4];
1230
1231 ir3_split_dest(b, tmp, sam, 0, 4);
1232
1233 /* get_size instruction returns size in bytes instead of texels
1234 * for imageBuffer, so we need to divide it by the pixel size
1235 * of the image format.
1236 *
1237 * TODO: This is at least true on a5xx. Check other gens.
1238 */
1239 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF) {
1240 /* Since all the possible values the divisor can take are
1241 * power-of-two (4, 8, or 16), the division is implemented
1242 * as a shift-right.
1243 * During shader setup, the log2 of the image format's
1244 * bytes-per-pixel should have been emitted in 2nd slot of
1245 * image_dims. See ir3_shader::emit_image_dims().
1246 */
1247 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1248 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1249 const_state->image_dims.off[nir_src_as_uint(intr->src[0])];
1250 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1251
1252 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1253 }
1254
1255 for (unsigned i = 0; i < ncoords; i++)
1256 dst[i] = tmp[i];
1257
1258 if (flags & IR3_INSTR_A) {
1259 if (ctx->compiler->levels_add_one) {
1260 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1261 } else {
1262 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1263 }
1264 }
1265 }
1266
1267 static void
1268 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1269 {
1270 struct ir3_block *b = ctx->block;
1271 struct ir3_instruction *barrier;
1272
1273 switch (intr->intrinsic) {
1274 case nir_intrinsic_control_barrier:
1275 barrier = ir3_BAR(b);
1276 barrier->cat7.g = true;
1277 barrier->cat7.l = true;
1278 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1279 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1280 break;
1281 case nir_intrinsic_memory_barrier:
1282 barrier = ir3_FENCE(b);
1283 barrier->cat7.g = true;
1284 barrier->cat7.r = true;
1285 barrier->cat7.w = true;
1286 barrier->cat7.l = true;
1287 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1288 IR3_BARRIER_BUFFER_W;
1289 barrier->barrier_conflict =
1290 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1291 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1292 break;
1293 case nir_intrinsic_memory_barrier_buffer:
1294 barrier = ir3_FENCE(b);
1295 barrier->cat7.g = true;
1296 barrier->cat7.r = true;
1297 barrier->cat7.w = true;
1298 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1299 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1300 IR3_BARRIER_BUFFER_W;
1301 break;
1302 case nir_intrinsic_memory_barrier_image:
1303 // TODO double check if this should have .g set
1304 barrier = ir3_FENCE(b);
1305 barrier->cat7.g = true;
1306 barrier->cat7.r = true;
1307 barrier->cat7.w = true;
1308 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1309 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1310 IR3_BARRIER_IMAGE_W;
1311 break;
1312 case nir_intrinsic_memory_barrier_shared:
1313 barrier = ir3_FENCE(b);
1314 barrier->cat7.g = true;
1315 barrier->cat7.l = true;
1316 barrier->cat7.r = true;
1317 barrier->cat7.w = true;
1318 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1319 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1320 IR3_BARRIER_SHARED_W;
1321 break;
1322 case nir_intrinsic_group_memory_barrier:
1323 barrier = ir3_FENCE(b);
1324 barrier->cat7.g = true;
1325 barrier->cat7.l = true;
1326 barrier->cat7.r = true;
1327 barrier->cat7.w = true;
1328 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1329 IR3_BARRIER_IMAGE_W |
1330 IR3_BARRIER_BUFFER_W;
1331 barrier->barrier_conflict =
1332 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1333 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1334 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1335 break;
1336 default:
1337 unreachable("boo");
1338 }
1339
1340 /* make sure barrier doesn't get DCE'd */
1341 array_insert(b, b->keeps, barrier);
1342 }
1343
1344 static void add_sysval_input_compmask(struct ir3_context *ctx,
1345 gl_system_value slot, unsigned compmask,
1346 struct ir3_instruction *instr)
1347 {
1348 struct ir3_shader_variant *so = ctx->so;
1349 unsigned n = so->inputs_count++;
1350
1351 assert(instr->opc == OPC_META_INPUT);
1352 instr->input.inidx = n;
1353 instr->input.sysval = slot;
1354
1355 so->inputs[n].sysval = true;
1356 so->inputs[n].slot = slot;
1357 so->inputs[n].compmask = compmask;
1358 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1359 so->total_in++;
1360 }
1361
1362 static struct ir3_instruction *
1363 create_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1364 unsigned compmask)
1365 {
1366 assert(compmask);
1367 struct ir3_instruction *sysval = create_input(ctx, compmask);
1368 add_sysval_input_compmask(ctx, slot, compmask, sysval);
1369 return sysval;
1370 }
1371
1372 static struct ir3_instruction *
1373 get_barycentric_centroid(struct ir3_context *ctx)
1374 {
1375 if (!ctx->ij_centroid) {
1376 struct ir3_instruction *xy[2];
1377 struct ir3_instruction *ij;
1378
1379 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID, 0x3);
1380 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1381
1382 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1383 }
1384
1385 return ctx->ij_centroid;
1386 }
1387
1388 static struct ir3_instruction *
1389 get_barycentric_sample(struct ir3_context *ctx)
1390 {
1391 if (!ctx->ij_sample) {
1392 struct ir3_instruction *xy[2];
1393 struct ir3_instruction *ij;
1394
1395 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE, 0x3);
1396 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1397
1398 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1399 }
1400
1401 return ctx->ij_sample;
1402 }
1403
1404 static struct ir3_instruction *
1405 get_barycentric_pixel(struct ir3_context *ctx)
1406 {
1407 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1408 * this to create ij_pixel only on demand:
1409 */
1410 return ctx->ij_pixel;
1411 }
1412
1413 static struct ir3_instruction *
1414 get_frag_coord(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1415 {
1416 if (!ctx->frag_coord) {
1417 struct ir3_block *b = ctx->in_block;
1418 struct ir3_instruction *xyzw[4];
1419 struct ir3_instruction *hw_frag_coord;
1420
1421 hw_frag_coord = create_sysval_input(ctx, SYSTEM_VALUE_FRAG_COORD, 0xf);
1422 ir3_split_dest(b, xyzw, hw_frag_coord, 0, 4);
1423
1424 /* for frag_coord.xy, we get unsigned values.. we need
1425 * to subtract (integer) 8 and divide by 16 (right-
1426 * shift by 4) then convert to float:
1427 *
1428 * sub.s tmp, src, 8
1429 * shr.b tmp, tmp, 4
1430 * mov.u32f32 dst, tmp
1431 *
1432 */
1433 for (int i = 0; i < 2; i++) {
1434 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1435 xyzw[i] = ir3_MUL_F(b, xyzw[i], 0, create_immed(b, fui(1.0 / 16.0)), 0);
1436 }
1437
1438 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1439 }
1440
1441 ctx->so->fragcoord_compmask |=
1442 nir_ssa_def_components_read(&intr->dest.ssa);
1443
1444 return ctx->frag_coord;
1445 }
1446
1447 static void
1448 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1449 {
1450 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1451 struct ir3_instruction **dst;
1452 struct ir3_instruction * const *src;
1453 struct ir3_block *b = ctx->block;
1454 int idx, comp;
1455
1456 if (info->has_dest) {
1457 unsigned n = nir_intrinsic_dest_components(intr);
1458 dst = ir3_get_dst(ctx, &intr->dest, n);
1459 } else {
1460 dst = NULL;
1461 }
1462
1463 const unsigned primitive_param = ctx->so->shader->const_state.offsets.primitive_param * 4;
1464 const unsigned primitive_map = ctx->so->shader->const_state.offsets.primitive_map * 4;
1465
1466 switch (intr->intrinsic) {
1467 case nir_intrinsic_load_uniform:
1468 idx = nir_intrinsic_base(intr);
1469 if (nir_src_is_const(intr->src[0])) {
1470 idx += nir_src_as_uint(intr->src[0]);
1471 for (int i = 0; i < intr->num_components; i++) {
1472 dst[i] = create_uniform_typed(b, idx + i,
1473 nir_dest_bit_size(intr->dest) == 16 ? TYPE_F16 : TYPE_F32);
1474 }
1475 } else {
1476 src = ir3_get_src(ctx, &intr->src[0]);
1477 for (int i = 0; i < intr->num_components; i++) {
1478 dst[i] = create_uniform_indirect(b, idx + i,
1479 ir3_get_addr0(ctx, src[0], 1));
1480 }
1481 /* NOTE: if relative addressing is used, we set
1482 * constlen in the compiler (to worst-case value)
1483 * since we don't know in the assembler what the max
1484 * addr reg value can be:
1485 */
1486 ctx->so->constlen = MAX2(ctx->so->constlen,
1487 ctx->so->shader->ubo_state.size / 16);
1488 }
1489 break;
1490
1491 case nir_intrinsic_load_vs_primitive_stride_ir3:
1492 dst[0] = create_uniform(b, primitive_param + 0);
1493 break;
1494 case nir_intrinsic_load_vs_vertex_stride_ir3:
1495 dst[0] = create_uniform(b, primitive_param + 1);
1496 break;
1497 case nir_intrinsic_load_hs_patch_stride_ir3:
1498 dst[0] = create_uniform(b, primitive_param + 2);
1499 break;
1500 case nir_intrinsic_load_patch_vertices_in:
1501 dst[0] = create_uniform(b, primitive_param + 3);
1502 break;
1503 case nir_intrinsic_load_tess_param_base_ir3:
1504 dst[0] = create_uniform(b, primitive_param + 4);
1505 dst[1] = create_uniform(b, primitive_param + 5);
1506 break;
1507 case nir_intrinsic_load_tess_factor_base_ir3:
1508 dst[0] = create_uniform(b, primitive_param + 6);
1509 dst[1] = create_uniform(b, primitive_param + 7);
1510 break;
1511
1512 case nir_intrinsic_load_primitive_location_ir3:
1513 idx = nir_intrinsic_driver_location(intr);
1514 dst[0] = create_uniform(b, primitive_map + idx);
1515 break;
1516
1517 case nir_intrinsic_load_gs_header_ir3:
1518 dst[0] = ctx->gs_header;
1519 break;
1520 case nir_intrinsic_load_tcs_header_ir3:
1521 dst[0] = ctx->tcs_header;
1522 break;
1523
1524 case nir_intrinsic_load_primitive_id:
1525 dst[0] = ctx->primitive_id;
1526 break;
1527
1528 case nir_intrinsic_load_tess_coord:
1529 if (!ctx->tess_coord) {
1530 ctx->tess_coord =
1531 create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
1532 }
1533 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1534
1535 /* Unused, but ir3_put_dst() below wants to free something */
1536 dst[2] = create_immed(b, 0);
1537 break;
1538
1539 case nir_intrinsic_end_patch_ir3:
1540 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1541 struct ir3_instruction *end = ir3_PREDE(b);
1542 array_insert(b, b->keeps, end);
1543
1544 end->barrier_class = IR3_BARRIER_EVERYTHING;
1545 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1546 break;
1547
1548 case nir_intrinsic_store_global_ir3: {
1549 struct ir3_instruction *value, *addr, *offset;
1550
1551 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1552 ir3_get_src(ctx, &intr->src[1])[0],
1553 ir3_get_src(ctx, &intr->src[1])[1]
1554 }, 2);
1555
1556 offset = ir3_get_src(ctx, &intr->src[2])[0];
1557
1558 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]),
1559 intr->num_components);
1560
1561 struct ir3_instruction *stg =
1562 ir3_STG_G(ctx->block, addr, 0, value, 0,
1563 create_immed(ctx->block, intr->num_components), 0, offset, 0);
1564 stg->cat6.type = TYPE_U32;
1565 stg->cat6.iim_val = 1;
1566
1567 array_insert(b, b->keeps, stg);
1568
1569 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1570 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1571 break;
1572 }
1573
1574 case nir_intrinsic_load_global_ir3: {
1575 struct ir3_instruction *addr, *offset;
1576
1577 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1578 ir3_get_src(ctx, &intr->src[0])[0],
1579 ir3_get_src(ctx, &intr->src[0])[1]
1580 }, 2);
1581
1582 offset = ir3_get_src(ctx, &intr->src[1])[0];
1583
1584 struct ir3_instruction *load =
1585 ir3_LDG(b, addr, 0, create_immed(ctx->block, intr->num_components),
1586 0, offset, 0);
1587 load->cat6.type = TYPE_U32;
1588 load->regs[0]->wrmask = MASK(intr->num_components);
1589
1590 load->barrier_class = IR3_BARRIER_BUFFER_R;
1591 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1592
1593 ir3_split_dest(b, dst, load, 0, intr->num_components);
1594 break;
1595 }
1596
1597 case nir_intrinsic_load_ubo:
1598 emit_intrinsic_load_ubo(ctx, intr, dst);
1599 break;
1600 case nir_intrinsic_load_ubo_ir3:
1601 emit_intrinsic_load_ubo_ldc(ctx, intr, dst);
1602 break;
1603 case nir_intrinsic_load_frag_coord:
1604 ir3_split_dest(b, dst, get_frag_coord(ctx, intr), 0, 4);
1605 break;
1606 case nir_intrinsic_load_sample_pos_from_id: {
1607 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1608 * but that doesn't seem necessary.
1609 */
1610 struct ir3_instruction *offset =
1611 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1612 offset->regs[0]->wrmask = 0x3;
1613 offset->cat5.type = TYPE_F32;
1614
1615 ir3_split_dest(b, dst, offset, 0, 2);
1616
1617 break;
1618 }
1619 case nir_intrinsic_load_size_ir3:
1620 if (!ctx->ij_size) {
1621 ctx->ij_size =
1622 create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE, 0x1);
1623 }
1624 dst[0] = ctx->ij_size;
1625 break;
1626 case nir_intrinsic_load_barycentric_centroid:
1627 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1628 break;
1629 case nir_intrinsic_load_barycentric_sample:
1630 if (ctx->so->key.msaa) {
1631 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1632 } else {
1633 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1634 }
1635 break;
1636 case nir_intrinsic_load_barycentric_pixel:
1637 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1638 break;
1639 case nir_intrinsic_load_interpolated_input:
1640 idx = nir_intrinsic_base(intr);
1641 comp = nir_intrinsic_component(intr);
1642 src = ir3_get_src(ctx, &intr->src[0]);
1643 if (nir_src_is_const(intr->src[1])) {
1644 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1645 idx += nir_src_as_uint(intr->src[1]);
1646 for (int i = 0; i < intr->num_components; i++) {
1647 unsigned inloc = idx * 4 + i + comp;
1648 if (ctx->so->inputs[idx].bary &&
1649 !ctx->so->inputs[idx].use_ldlv) {
1650 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1651 } else {
1652 /* for non-varyings use the pre-setup input, since
1653 * that is easier than mapping things back to a
1654 * nir_variable to figure out what it is.
1655 */
1656 dst[i] = ctx->inputs[inloc];
1657 compile_assert(ctx, dst[i]);
1658 }
1659 }
1660 } else {
1661 ir3_context_error(ctx, "unhandled");
1662 }
1663 break;
1664 case nir_intrinsic_load_input:
1665 idx = nir_intrinsic_base(intr);
1666 comp = nir_intrinsic_component(intr);
1667 if (nir_src_is_const(intr->src[0])) {
1668 idx += nir_src_as_uint(intr->src[0]);
1669 for (int i = 0; i < intr->num_components; i++) {
1670 unsigned n = idx * 4 + i + comp;
1671 dst[i] = ctx->inputs[n];
1672 compile_assert(ctx, ctx->inputs[n]);
1673 }
1674 } else {
1675 src = ir3_get_src(ctx, &intr->src[0]);
1676 struct ir3_instruction *collect =
1677 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ninputs);
1678 struct ir3_instruction *addr = ir3_get_addr0(ctx, src[0], 4);
1679 for (int i = 0; i < intr->num_components; i++) {
1680 unsigned n = idx * 4 + i + comp;
1681 dst[i] = create_indirect_load(ctx, ctx->ninputs,
1682 n, addr, collect);
1683 }
1684 }
1685 break;
1686 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1687 * pass and replaced by an ir3-specifc version that adds the
1688 * dword-offset in the last source.
1689 */
1690 case nir_intrinsic_load_ssbo_ir3:
1691 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1692 break;
1693 case nir_intrinsic_store_ssbo_ir3:
1694 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1695 !ctx->s->info.fs.early_fragment_tests)
1696 ctx->so->no_earlyz = true;
1697 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1698 break;
1699 case nir_intrinsic_get_buffer_size:
1700 emit_intrinsic_ssbo_size(ctx, intr, dst);
1701 break;
1702 case nir_intrinsic_ssbo_atomic_add_ir3:
1703 case nir_intrinsic_ssbo_atomic_imin_ir3:
1704 case nir_intrinsic_ssbo_atomic_umin_ir3:
1705 case nir_intrinsic_ssbo_atomic_imax_ir3:
1706 case nir_intrinsic_ssbo_atomic_umax_ir3:
1707 case nir_intrinsic_ssbo_atomic_and_ir3:
1708 case nir_intrinsic_ssbo_atomic_or_ir3:
1709 case nir_intrinsic_ssbo_atomic_xor_ir3:
1710 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1711 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1712 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1713 !ctx->s->info.fs.early_fragment_tests)
1714 ctx->so->no_earlyz = true;
1715 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1716 break;
1717 case nir_intrinsic_load_shared:
1718 emit_intrinsic_load_shared(ctx, intr, dst);
1719 break;
1720 case nir_intrinsic_store_shared:
1721 emit_intrinsic_store_shared(ctx, intr);
1722 break;
1723 case nir_intrinsic_shared_atomic_add:
1724 case nir_intrinsic_shared_atomic_imin:
1725 case nir_intrinsic_shared_atomic_umin:
1726 case nir_intrinsic_shared_atomic_imax:
1727 case nir_intrinsic_shared_atomic_umax:
1728 case nir_intrinsic_shared_atomic_and:
1729 case nir_intrinsic_shared_atomic_or:
1730 case nir_intrinsic_shared_atomic_xor:
1731 case nir_intrinsic_shared_atomic_exchange:
1732 case nir_intrinsic_shared_atomic_comp_swap:
1733 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1734 break;
1735 case nir_intrinsic_image_load:
1736 emit_intrinsic_load_image(ctx, intr, dst);
1737 break;
1738 case nir_intrinsic_bindless_image_load:
1739 /* Bindless uses the IBO state, which doesn't have swizzle filled out,
1740 * so using isam doesn't work.
1741 *
1742 * TODO: can we use isam if we fill out more fields?
1743 */
1744 ctx->funcs->emit_intrinsic_load_image(ctx, intr, dst);
1745 break;
1746 case nir_intrinsic_image_store:
1747 case nir_intrinsic_bindless_image_store:
1748 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1749 !ctx->s->info.fs.early_fragment_tests)
1750 ctx->so->no_earlyz = true;
1751 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1752 break;
1753 case nir_intrinsic_image_size:
1754 case nir_intrinsic_bindless_image_size:
1755 emit_intrinsic_image_size(ctx, intr, dst);
1756 break;
1757 case nir_intrinsic_image_atomic_add:
1758 case nir_intrinsic_bindless_image_atomic_add:
1759 case nir_intrinsic_image_atomic_imin:
1760 case nir_intrinsic_bindless_image_atomic_imin:
1761 case nir_intrinsic_image_atomic_umin:
1762 case nir_intrinsic_bindless_image_atomic_umin:
1763 case nir_intrinsic_image_atomic_imax:
1764 case nir_intrinsic_bindless_image_atomic_imax:
1765 case nir_intrinsic_image_atomic_umax:
1766 case nir_intrinsic_bindless_image_atomic_umax:
1767 case nir_intrinsic_image_atomic_and:
1768 case nir_intrinsic_bindless_image_atomic_and:
1769 case nir_intrinsic_image_atomic_or:
1770 case nir_intrinsic_bindless_image_atomic_or:
1771 case nir_intrinsic_image_atomic_xor:
1772 case nir_intrinsic_bindless_image_atomic_xor:
1773 case nir_intrinsic_image_atomic_exchange:
1774 case nir_intrinsic_bindless_image_atomic_exchange:
1775 case nir_intrinsic_image_atomic_comp_swap:
1776 case nir_intrinsic_bindless_image_atomic_comp_swap:
1777 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1778 !ctx->s->info.fs.early_fragment_tests)
1779 ctx->so->no_earlyz = true;
1780 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1781 break;
1782 case nir_intrinsic_control_barrier:
1783 case nir_intrinsic_memory_barrier:
1784 case nir_intrinsic_group_memory_barrier:
1785 case nir_intrinsic_memory_barrier_buffer:
1786 case nir_intrinsic_memory_barrier_image:
1787 case nir_intrinsic_memory_barrier_shared:
1788 emit_intrinsic_barrier(ctx, intr);
1789 /* note that blk ptr no longer valid, make that obvious: */
1790 b = NULL;
1791 break;
1792 case nir_intrinsic_store_output:
1793 idx = nir_intrinsic_base(intr);
1794 comp = nir_intrinsic_component(intr);
1795 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1796 idx += nir_src_as_uint(intr->src[1]);
1797
1798 src = ir3_get_src(ctx, &intr->src[0]);
1799 for (int i = 0; i < intr->num_components; i++) {
1800 unsigned n = idx * 4 + i + comp;
1801 ctx->outputs[n] = src[i];
1802 }
1803 break;
1804 case nir_intrinsic_load_base_vertex:
1805 case nir_intrinsic_load_first_vertex:
1806 if (!ctx->basevertex) {
1807 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1808 }
1809 dst[0] = ctx->basevertex;
1810 break;
1811 case nir_intrinsic_load_base_instance:
1812 if (!ctx->base_instance) {
1813 ctx->base_instance = create_driver_param(ctx, IR3_DP_INSTID_BASE);
1814 }
1815 dst[0] = ctx->base_instance;
1816 break;
1817 case nir_intrinsic_load_vertex_id_zero_base:
1818 case nir_intrinsic_load_vertex_id:
1819 if (!ctx->vertex_id) {
1820 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1821 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1822 ctx->vertex_id = create_sysval_input(ctx, sv, 0x1);
1823 }
1824 dst[0] = ctx->vertex_id;
1825 break;
1826 case nir_intrinsic_load_instance_id:
1827 if (!ctx->instance_id) {
1828 ctx->instance_id = create_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 0x1);
1829 }
1830 dst[0] = ctx->instance_id;
1831 break;
1832 case nir_intrinsic_load_sample_id:
1833 ctx->so->per_samp = true;
1834 /* fall-thru */
1835 case nir_intrinsic_load_sample_id_no_per_sample:
1836 if (!ctx->samp_id) {
1837 ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1);
1838 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1839 }
1840 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1841 break;
1842 case nir_intrinsic_load_sample_mask_in:
1843 if (!ctx->samp_mask_in) {
1844 ctx->samp_mask_in = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
1845 }
1846 dst[0] = ctx->samp_mask_in;
1847 break;
1848 case nir_intrinsic_load_user_clip_plane:
1849 idx = nir_intrinsic_ucp_id(intr);
1850 for (int i = 0; i < intr->num_components; i++) {
1851 unsigned n = idx * 4 + i;
1852 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1853 }
1854 break;
1855 case nir_intrinsic_load_front_face:
1856 if (!ctx->frag_face) {
1857 ctx->so->frag_face = true;
1858 ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1);
1859 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1860 }
1861 /* for fragface, we get -1 for back and 0 for front. However this is
1862 * the inverse of what nir expects (where ~0 is true).
1863 */
1864 dst[0] = ir3_CMPS_S(b,
1865 ctx->frag_face, 0,
1866 create_immed_typed(b, 0, TYPE_U16), 0);
1867 dst[0]->cat2.condition = IR3_COND_EQ;
1868 break;
1869 case nir_intrinsic_load_local_invocation_id:
1870 if (!ctx->local_invocation_id) {
1871 ctx->local_invocation_id =
1872 create_sysval_input(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 0x7);
1873 }
1874 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1875 break;
1876 case nir_intrinsic_load_work_group_id:
1877 if (!ctx->work_group_id) {
1878 ctx->work_group_id =
1879 create_sysval_input(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 0x7);
1880 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1881 }
1882 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1883 break;
1884 case nir_intrinsic_load_num_work_groups:
1885 for (int i = 0; i < intr->num_components; i++) {
1886 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1887 }
1888 break;
1889 case nir_intrinsic_load_local_group_size:
1890 for (int i = 0; i < intr->num_components; i++) {
1891 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1892 }
1893 break;
1894 case nir_intrinsic_discard_if:
1895 case nir_intrinsic_discard: {
1896 struct ir3_instruction *cond, *kill;
1897
1898 if (intr->intrinsic == nir_intrinsic_discard_if) {
1899 /* conditional discard: */
1900 src = ir3_get_src(ctx, &intr->src[0]);
1901 cond = src[0];
1902 } else {
1903 /* unconditional discard: */
1904 cond = create_immed(b, 1);
1905 }
1906
1907 /* NOTE: only cmps.*.* can write p0.x: */
1908 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1909 cond->cat2.condition = IR3_COND_NE;
1910
1911 /* condition always goes in predicate register: */
1912 cond->regs[0]->num = regid(REG_P0, 0);
1913 cond->regs[0]->flags &= ~IR3_REG_SSA;
1914
1915 kill = ir3_KILL(b, cond, 0);
1916 kill->regs[1]->num = regid(REG_P0, 0);
1917 array_insert(ctx->ir, ctx->ir->predicates, kill);
1918
1919 array_insert(b, b->keeps, kill);
1920 ctx->so->no_earlyz = true;
1921
1922 break;
1923 }
1924
1925 case nir_intrinsic_cond_end_ir3: {
1926 struct ir3_instruction *cond, *kill;
1927
1928 src = ir3_get_src(ctx, &intr->src[0]);
1929 cond = src[0];
1930
1931 /* NOTE: only cmps.*.* can write p0.x: */
1932 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1933 cond->cat2.condition = IR3_COND_NE;
1934
1935 /* condition always goes in predicate register: */
1936 cond->regs[0]->num = regid(REG_P0, 0);
1937
1938 kill = ir3_PREDT(b, cond, 0);
1939
1940 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1941 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1942
1943 array_insert(ctx->ir, ctx->ir->predicates, kill);
1944 array_insert(b, b->keeps, kill);
1945 break;
1946 }
1947
1948 case nir_intrinsic_load_shared_ir3:
1949 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1950 break;
1951 case nir_intrinsic_store_shared_ir3:
1952 emit_intrinsic_store_shared_ir3(ctx, intr);
1953 break;
1954 case nir_intrinsic_bindless_resource_ir3:
1955 dst[0] = ir3_get_src(ctx, &intr->src[0])[0];
1956 break;
1957 default:
1958 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1959 nir_intrinsic_infos[intr->intrinsic].name);
1960 break;
1961 }
1962
1963 if (info->has_dest)
1964 ir3_put_dst(ctx, &intr->dest);
1965 }
1966
1967 static void
1968 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1969 {
1970 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1971 instr->def.num_components);
1972
1973 if (instr->def.bit_size == 16) {
1974 for (int i = 0; i < instr->def.num_components; i++)
1975 dst[i] = create_immed_typed(ctx->block,
1976 instr->value[i].u16,
1977 TYPE_U16);
1978 } else {
1979 for (int i = 0; i < instr->def.num_components; i++)
1980 dst[i] = create_immed_typed(ctx->block,
1981 instr->value[i].u32,
1982 TYPE_U32);
1983 }
1984
1985 }
1986
1987 static void
1988 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1989 {
1990 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1991 undef->def.num_components);
1992 type_t type = (undef->def.bit_size == 16) ? TYPE_U16 : TYPE_U32;
1993
1994 /* backend doesn't want undefined instructions, so just plug
1995 * in 0.0..
1996 */
1997 for (int i = 0; i < undef->def.num_components; i++)
1998 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1999 }
2000
2001 /*
2002 * texture fetch/sample instructions:
2003 */
2004
2005 static type_t
2006 get_tex_dest_type(nir_tex_instr *tex)
2007 {
2008 type_t type;
2009
2010 switch (nir_alu_type_get_base_type(tex->dest_type)) {
2011 case nir_type_invalid:
2012 case nir_type_float:
2013 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_F16 : TYPE_F32;
2014 break;
2015 case nir_type_int:
2016 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_S16 : TYPE_S32;
2017 break;
2018 case nir_type_uint:
2019 case nir_type_bool:
2020 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_U16 : TYPE_U32;
2021 break;
2022 default:
2023 unreachable("bad dest_type");
2024 }
2025
2026 return type;
2027 }
2028
2029 static void
2030 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
2031 {
2032 unsigned coords = glsl_get_sampler_dim_coordinate_components(tex->sampler_dim);
2033 unsigned flags = 0;
2034
2035 /* note: would use tex->coord_components.. except txs.. also,
2036 * since array index goes after shadow ref, we don't want to
2037 * count it:
2038 */
2039 if (coords == 3)
2040 flags |= IR3_INSTR_3D;
2041
2042 if (tex->is_shadow && tex->op != nir_texop_lod)
2043 flags |= IR3_INSTR_S;
2044
2045 if (tex->is_array && tex->op != nir_texop_lod)
2046 flags |= IR3_INSTR_A;
2047
2048 *flagsp = flags;
2049 *coordsp = coords;
2050 }
2051
2052 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
2053 * or immediate (in which case it will get lowered later to a non .s2en
2054 * version of the tex instruction which encode tex/samp as immediates:
2055 */
2056 static struct tex_src_info
2057 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
2058 {
2059 struct ir3_block *b = ctx->block;
2060 struct tex_src_info info = { 0 };
2061 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_handle);
2062 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_handle);
2063 struct ir3_instruction *texture, *sampler;
2064
2065 if (texture_idx >= 0 || sampler_idx >= 0) {
2066 /* Bindless case */
2067 info.flags |= IR3_INSTR_B;
2068
2069 /* Gather information required to determine which encoding to
2070 * choose as well as for prefetch.
2071 */
2072 nir_intrinsic_instr *bindless_tex = NULL;
2073 bool tex_const;
2074 if (texture_idx >= 0) {
2075 ctx->so->bindless_tex = true;
2076 bindless_tex = ir3_bindless_resource(tex->src[texture_idx].src);
2077 assert(bindless_tex);
2078 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
2079 tex_const = nir_src_is_const(bindless_tex->src[0]);
2080 if (tex_const)
2081 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
2082 } else {
2083 /* To simplify some of the logic below, assume the index is
2084 * constant 0 when it's not enabled.
2085 */
2086 tex_const = true;
2087 info.tex_idx = 0;
2088 }
2089 nir_intrinsic_instr *bindless_samp = NULL;
2090 bool samp_const;
2091 if (sampler_idx >= 0) {
2092 ctx->so->bindless_samp = true;
2093 bindless_samp = ir3_bindless_resource(tex->src[sampler_idx].src);
2094 assert(bindless_samp);
2095 info.samp_base = nir_intrinsic_desc_set(bindless_samp);
2096 samp_const = nir_src_is_const(bindless_samp->src[0]);
2097 if (samp_const)
2098 info.samp_idx = nir_src_as_uint(bindless_samp->src[0]);
2099 } else {
2100 samp_const = true;
2101 info.samp_idx = 0;
2102 }
2103
2104 /* Choose encoding. */
2105 if (tex_const && samp_const && info.tex_idx < 256 && info.samp_idx < 256) {
2106 if (info.tex_idx < 16 && info.samp_idx < 16 &&
2107 (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base)) {
2108 /* Everything fits within the instruction */
2109 info.base = info.tex_base;
2110 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
2111 } else {
2112 info.base = info.tex_base;
2113 info.a1_val = info.tex_idx << 3 | info.samp_base;
2114 info.combined_idx = info.samp_idx;
2115 info.flags |= IR3_INSTR_A1EN;
2116 }
2117 info.samp_tex = NULL;
2118 } else {
2119 info.flags |= IR3_INSTR_S2EN;
2120 /* In the indirect case, we only use a1.x to store the sampler
2121 * base if it differs from the texture base.
2122 */
2123 if (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base) {
2124 info.base = info.tex_base;
2125 } else {
2126 info.base = info.tex_base;
2127 info.a1_val = info.samp_base;
2128 info.flags |= IR3_INSTR_A1EN;
2129 }
2130
2131 /* Note: the indirect source is now a vec2 instead of hvec2, and
2132 * for some reason the texture and sampler are swapped.
2133 */
2134 struct ir3_instruction *texture, *sampler;
2135
2136 if (bindless_tex) {
2137 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2138 } else {
2139 texture = create_immed(b, 0);
2140 }
2141
2142 if (bindless_samp) {
2143 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2144 } else {
2145 sampler = create_immed(b, 0);
2146 }
2147 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2148 texture,
2149 sampler,
2150 }, 2);
2151 }
2152 } else {
2153 info.flags |= IR3_INSTR_S2EN;
2154 texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
2155 sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
2156 if (texture_idx >= 0) {
2157 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2158 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
2159 } else {
2160 /* TODO what to do for dynamic case? I guess we only need the
2161 * max index for astc srgb workaround so maybe not a problem
2162 * to worry about if we don't enable indirect samplers for
2163 * a4xx?
2164 */
2165 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
2166 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
2167 info.tex_idx = tex->texture_index;
2168 }
2169
2170 if (sampler_idx >= 0) {
2171 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2172 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
2173 } else {
2174 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
2175 info.samp_idx = tex->texture_index;
2176 }
2177
2178 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2179 sampler,
2180 texture,
2181 }, 2);
2182 }
2183
2184 return info;
2185 }
2186
2187 static void
2188 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
2189 {
2190 struct ir3_block *b = ctx->block;
2191 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
2192 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
2193 struct ir3_instruction *lod, *compare, *proj, *sample_index;
2194 struct tex_src_info info = { 0 };
2195 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
2196 unsigned i, coords, flags, ncomp;
2197 unsigned nsrc0 = 0, nsrc1 = 0;
2198 type_t type;
2199 opc_t opc = 0;
2200
2201 ncomp = nir_dest_num_components(tex->dest);
2202
2203 coord = off = ddx = ddy = NULL;
2204 lod = proj = compare = sample_index = NULL;
2205
2206 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
2207
2208 for (unsigned i = 0; i < tex->num_srcs; i++) {
2209 switch (tex->src[i].src_type) {
2210 case nir_tex_src_coord:
2211 coord = ir3_get_src(ctx, &tex->src[i].src);
2212 break;
2213 case nir_tex_src_bias:
2214 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2215 has_bias = true;
2216 break;
2217 case nir_tex_src_lod:
2218 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2219 has_lod = true;
2220 break;
2221 case nir_tex_src_comparator: /* shadow comparator */
2222 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
2223 break;
2224 case nir_tex_src_projector:
2225 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
2226 has_proj = true;
2227 break;
2228 case nir_tex_src_offset:
2229 off = ir3_get_src(ctx, &tex->src[i].src);
2230 has_off = true;
2231 break;
2232 case nir_tex_src_ddx:
2233 ddx = ir3_get_src(ctx, &tex->src[i].src);
2234 break;
2235 case nir_tex_src_ddy:
2236 ddy = ir3_get_src(ctx, &tex->src[i].src);
2237 break;
2238 case nir_tex_src_ms_index:
2239 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
2240 break;
2241 case nir_tex_src_texture_offset:
2242 case nir_tex_src_sampler_offset:
2243 case nir_tex_src_texture_handle:
2244 case nir_tex_src_sampler_handle:
2245 /* handled in get_tex_samp_src() */
2246 break;
2247 default:
2248 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
2249 tex->src[i].src_type);
2250 return;
2251 }
2252 }
2253
2254 switch (tex->op) {
2255 case nir_texop_tex_prefetch:
2256 compile_assert(ctx, !has_bias);
2257 compile_assert(ctx, !has_lod);
2258 compile_assert(ctx, !compare);
2259 compile_assert(ctx, !has_proj);
2260 compile_assert(ctx, !has_off);
2261 compile_assert(ctx, !ddx);
2262 compile_assert(ctx, !ddy);
2263 compile_assert(ctx, !sample_index);
2264 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
2265 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
2266
2267 if (ctx->so->num_sampler_prefetch < IR3_MAX_SAMPLER_PREFETCH) {
2268 opc = OPC_META_TEX_PREFETCH;
2269 ctx->so->num_sampler_prefetch++;
2270 break;
2271 }
2272 /* fallthru */
2273 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
2274 case nir_texop_txb: opc = OPC_SAMB; break;
2275 case nir_texop_txl: opc = OPC_SAML; break;
2276 case nir_texop_txd: opc = OPC_SAMGQ; break;
2277 case nir_texop_txf: opc = OPC_ISAML; break;
2278 case nir_texop_lod: opc = OPC_GETLOD; break;
2279 case nir_texop_tg4:
2280 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2281 * what blob does, seems gather is broken?), and a3xx did
2282 * not support it (but probably could also emulate).
2283 */
2284 switch (tex->component) {
2285 case 0: opc = OPC_GATHER4R; break;
2286 case 1: opc = OPC_GATHER4G; break;
2287 case 2: opc = OPC_GATHER4B; break;
2288 case 3: opc = OPC_GATHER4A; break;
2289 }
2290 break;
2291 case nir_texop_txf_ms_fb:
2292 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2293 default:
2294 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2295 return;
2296 }
2297
2298 tex_info(tex, &flags, &coords);
2299
2300 /*
2301 * lay out the first argument in the proper order:
2302 * - actual coordinates first
2303 * - shadow reference
2304 * - array index
2305 * - projection w
2306 * - starting at offset 4, dpdx.xy, dpdy.xy
2307 *
2308 * bias/lod go into the second arg
2309 */
2310
2311 /* insert tex coords: */
2312 for (i = 0; i < coords; i++)
2313 src0[i] = coord[i];
2314
2315 nsrc0 = i;
2316
2317 /* scale up integer coords for TXF based on the LOD */
2318 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2319 assert(has_lod);
2320 for (i = 0; i < coords; i++)
2321 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2322 }
2323
2324 if (coords == 1) {
2325 /* hw doesn't do 1d, so we treat it as 2d with
2326 * height of 1, and patch up the y coord.
2327 */
2328 if (is_isam(opc)) {
2329 src0[nsrc0++] = create_immed(b, 0);
2330 } else {
2331 src0[nsrc0++] = create_immed(b, fui(0.5));
2332 }
2333 }
2334
2335 if (tex->is_shadow && tex->op != nir_texop_lod)
2336 src0[nsrc0++] = compare;
2337
2338 if (tex->is_array && tex->op != nir_texop_lod) {
2339 struct ir3_instruction *idx = coord[coords];
2340
2341 /* the array coord for cube arrays needs 0.5 added to it */
2342 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2343 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2344
2345 src0[nsrc0++] = idx;
2346 }
2347
2348 if (has_proj) {
2349 src0[nsrc0++] = proj;
2350 flags |= IR3_INSTR_P;
2351 }
2352
2353 /* pad to 4, then ddx/ddy: */
2354 if (tex->op == nir_texop_txd) {
2355 while (nsrc0 < 4)
2356 src0[nsrc0++] = create_immed(b, fui(0.0));
2357 for (i = 0; i < coords; i++)
2358 src0[nsrc0++] = ddx[i];
2359 if (coords < 2)
2360 src0[nsrc0++] = create_immed(b, fui(0.0));
2361 for (i = 0; i < coords; i++)
2362 src0[nsrc0++] = ddy[i];
2363 if (coords < 2)
2364 src0[nsrc0++] = create_immed(b, fui(0.0));
2365 }
2366
2367 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2368 * with scaled x coord according to requested sample:
2369 */
2370 if (opc == OPC_ISAMM) {
2371 if (ctx->compiler->txf_ms_with_isaml) {
2372 /* the samples are laid out in x dimension as
2373 * 0 1 2 3
2374 * x_ms = (x << ms) + sample_index;
2375 */
2376 struct ir3_instruction *ms;
2377 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2378
2379 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2380 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2381
2382 opc = OPC_ISAML;
2383 } else {
2384 src0[nsrc0++] = sample_index;
2385 }
2386 }
2387
2388 /*
2389 * second argument (if applicable):
2390 * - offsets
2391 * - lod
2392 * - bias
2393 */
2394 if (has_off | has_lod | has_bias) {
2395 if (has_off) {
2396 unsigned off_coords = coords;
2397 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2398 off_coords--;
2399 for (i = 0; i < off_coords; i++)
2400 src1[nsrc1++] = off[i];
2401 if (off_coords < 2)
2402 src1[nsrc1++] = create_immed(b, fui(0.0));
2403 flags |= IR3_INSTR_O;
2404 }
2405
2406 if (has_lod | has_bias)
2407 src1[nsrc1++] = lod;
2408 }
2409
2410 type = get_tex_dest_type(tex);
2411
2412 if (opc == OPC_GETLOD)
2413 type = TYPE_S32;
2414
2415
2416 if (tex->op == nir_texop_txf_ms_fb) {
2417 /* only expect a single txf_ms_fb per shader: */
2418 compile_assert(ctx, !ctx->so->fb_read);
2419 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2420
2421 ctx->so->fb_read = true;
2422 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2423 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2424 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2425 }, 2);
2426 info.flags = IR3_INSTR_S2EN;
2427
2428 ctx->so->num_samp++;
2429 } else {
2430 info = get_tex_samp_tex_src(ctx, tex);
2431 }
2432
2433 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2434 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2435
2436 if (opc == OPC_META_TEX_PREFETCH) {
2437 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2438
2439 compile_assert(ctx, tex->src[idx].src.is_ssa);
2440
2441 sam = ir3_META_TEX_PREFETCH(b);
2442 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2443 __ssa_src(sam, get_barycentric_pixel(ctx), 0);
2444 sam->prefetch.input_offset =
2445 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2446 /* make sure not to add irrelevant flags like S2EN */
2447 sam->flags = flags | (info.flags & IR3_INSTR_B);
2448 sam->prefetch.tex = info.tex_idx;
2449 sam->prefetch.samp = info.samp_idx;
2450 sam->prefetch.tex_base = info.tex_base;
2451 sam->prefetch.samp_base = info.samp_base;
2452 } else {
2453 info.flags |= flags;
2454 sam = emit_sam(ctx, opc, info, type, MASK(ncomp), col0, col1);
2455 }
2456
2457 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2458 assert(opc != OPC_META_TEX_PREFETCH);
2459
2460 /* only need first 3 components: */
2461 sam->regs[0]->wrmask = 0x7;
2462 ir3_split_dest(b, dst, sam, 0, 3);
2463
2464 /* we need to sample the alpha separately with a non-ASTC
2465 * texture state:
2466 */
2467 sam = ir3_SAM(b, opc, type, 0b1000, flags | info.flags,
2468 info.samp_tex, col0, col1);
2469
2470 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2471
2472 /* fixup .w component: */
2473 ir3_split_dest(b, &dst[3], sam, 3, 1);
2474 } else {
2475 /* normal (non-workaround) case: */
2476 ir3_split_dest(b, dst, sam, 0, ncomp);
2477 }
2478
2479 /* GETLOD returns results in 4.8 fixed point */
2480 if (opc == OPC_GETLOD) {
2481 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2482
2483 compile_assert(ctx, tex->dest_type == nir_type_float);
2484 for (i = 0; i < 2; i++) {
2485 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2486 factor, 0);
2487 }
2488 }
2489
2490 ir3_put_dst(ctx, &tex->dest);
2491 }
2492
2493 static void
2494 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2495 {
2496 struct ir3_block *b = ctx->block;
2497 struct ir3_instruction **dst, *sam;
2498 type_t dst_type = get_tex_dest_type(tex);
2499 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2500
2501 dst = ir3_get_dst(ctx, &tex->dest, 1);
2502
2503 sam = emit_sam(ctx, OPC_GETINFO, info, dst_type, 1 << idx, NULL, NULL);
2504
2505 /* even though there is only one component, since it ends
2506 * up in .y/.z/.w rather than .x, we need a split_dest()
2507 */
2508 ir3_split_dest(b, dst, sam, idx, 1);
2509
2510 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2511 * the value in TEX_CONST_0 is zero-based.
2512 */
2513 if (ctx->compiler->levels_add_one)
2514 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2515
2516 ir3_put_dst(ctx, &tex->dest);
2517 }
2518
2519 static void
2520 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2521 {
2522 struct ir3_block *b = ctx->block;
2523 struct ir3_instruction **dst, *sam;
2524 struct ir3_instruction *lod;
2525 unsigned flags, coords;
2526 type_t dst_type = get_tex_dest_type(tex);
2527 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2528
2529 tex_info(tex, &flags, &coords);
2530 info.flags |= flags;
2531
2532 /* Actually we want the number of dimensions, not coordinates. This
2533 * distinction only matters for cubes.
2534 */
2535 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2536 coords = 2;
2537
2538 dst = ir3_get_dst(ctx, &tex->dest, 4);
2539
2540 int lod_idx = nir_tex_instr_src_index(tex, nir_tex_src_lod);
2541 compile_assert(ctx, lod_idx >= 0);
2542
2543 lod = ir3_get_src(ctx, &tex->src[lod_idx].src)[0];
2544
2545 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
2546 ir3_split_dest(b, dst, sam, 0, 4);
2547
2548 /* Array size actually ends up in .w rather than .z. This doesn't
2549 * matter for miplevel 0, but for higher mips the value in z is
2550 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2551 * returned, which means that we have to add 1 to it for arrays.
2552 */
2553 if (tex->is_array) {
2554 if (ctx->compiler->levels_add_one) {
2555 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2556 } else {
2557 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2558 }
2559 }
2560
2561 ir3_put_dst(ctx, &tex->dest);
2562 }
2563
2564 static void
2565 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2566 {
2567 switch (jump->type) {
2568 case nir_jump_break:
2569 case nir_jump_continue:
2570 case nir_jump_return:
2571 /* I *think* we can simply just ignore this, and use the
2572 * successor block link to figure out where we need to
2573 * jump to for break/continue
2574 */
2575 break;
2576 default:
2577 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2578 break;
2579 }
2580 }
2581
2582 static void
2583 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2584 {
2585 switch (instr->type) {
2586 case nir_instr_type_alu:
2587 emit_alu(ctx, nir_instr_as_alu(instr));
2588 break;
2589 case nir_instr_type_deref:
2590 /* ignored, handled as part of the intrinsic they are src to */
2591 break;
2592 case nir_instr_type_intrinsic:
2593 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2594 break;
2595 case nir_instr_type_load_const:
2596 emit_load_const(ctx, nir_instr_as_load_const(instr));
2597 break;
2598 case nir_instr_type_ssa_undef:
2599 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2600 break;
2601 case nir_instr_type_tex: {
2602 nir_tex_instr *tex = nir_instr_as_tex(instr);
2603 /* couple tex instructions get special-cased:
2604 */
2605 switch (tex->op) {
2606 case nir_texop_txs:
2607 emit_tex_txs(ctx, tex);
2608 break;
2609 case nir_texop_query_levels:
2610 emit_tex_info(ctx, tex, 2);
2611 break;
2612 case nir_texop_texture_samples:
2613 emit_tex_info(ctx, tex, 3);
2614 break;
2615 default:
2616 emit_tex(ctx, tex);
2617 break;
2618 }
2619 break;
2620 }
2621 case nir_instr_type_jump:
2622 emit_jump(ctx, nir_instr_as_jump(instr));
2623 break;
2624 case nir_instr_type_phi:
2625 /* we have converted phi webs to regs in NIR by now */
2626 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2627 break;
2628 case nir_instr_type_call:
2629 case nir_instr_type_parallel_copy:
2630 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2631 break;
2632 }
2633 }
2634
2635 static struct ir3_block *
2636 get_block(struct ir3_context *ctx, const nir_block *nblock)
2637 {
2638 struct ir3_block *block;
2639 struct hash_entry *hentry;
2640
2641 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2642 if (hentry)
2643 return hentry->data;
2644
2645 block = ir3_block_create(ctx->ir);
2646 block->nblock = nblock;
2647 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2648
2649 set_foreach(nblock->predecessors, sentry) {
2650 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2651 }
2652
2653 return block;
2654 }
2655
2656 static void
2657 emit_block(struct ir3_context *ctx, nir_block *nblock)
2658 {
2659 struct ir3_block *block = get_block(ctx, nblock);
2660
2661 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2662 if (nblock->successors[i]) {
2663 block->successors[i] =
2664 get_block(ctx, nblock->successors[i]);
2665 }
2666 }
2667
2668 ctx->block = block;
2669 list_addtail(&block->node, &ctx->ir->block_list);
2670
2671 /* re-emit addr register in each block if needed: */
2672 for (int i = 0; i < ARRAY_SIZE(ctx->addr0_ht); i++) {
2673 _mesa_hash_table_destroy(ctx->addr0_ht[i], NULL);
2674 ctx->addr0_ht[i] = NULL;
2675 }
2676
2677 _mesa_hash_table_u64_destroy(ctx->addr1_ht, NULL);
2678 ctx->addr1_ht = NULL;
2679
2680 nir_foreach_instr (instr, nblock) {
2681 ctx->cur_instr = instr;
2682 emit_instr(ctx, instr);
2683 ctx->cur_instr = NULL;
2684 if (ctx->error)
2685 return;
2686 }
2687
2688 _mesa_hash_table_clear(ctx->sel_cond_conversions, NULL);
2689 }
2690
2691 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2692
2693 static void
2694 emit_if(struct ir3_context *ctx, nir_if *nif)
2695 {
2696 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2697
2698 ctx->block->condition = ir3_get_predicate(ctx, condition);
2699
2700 emit_cf_list(ctx, &nif->then_list);
2701 emit_cf_list(ctx, &nif->else_list);
2702 }
2703
2704 static void
2705 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2706 {
2707 emit_cf_list(ctx, &nloop->body);
2708 ctx->so->loops++;
2709 }
2710
2711 static void
2712 stack_push(struct ir3_context *ctx)
2713 {
2714 ctx->stack++;
2715 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2716 }
2717
2718 static void
2719 stack_pop(struct ir3_context *ctx)
2720 {
2721 compile_assert(ctx, ctx->stack > 0);
2722 ctx->stack--;
2723 }
2724
2725 static void
2726 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2727 {
2728 foreach_list_typed (nir_cf_node, node, node, list) {
2729 switch (node->type) {
2730 case nir_cf_node_block:
2731 emit_block(ctx, nir_cf_node_as_block(node));
2732 break;
2733 case nir_cf_node_if:
2734 stack_push(ctx);
2735 emit_if(ctx, nir_cf_node_as_if(node));
2736 stack_pop(ctx);
2737 break;
2738 case nir_cf_node_loop:
2739 stack_push(ctx);
2740 emit_loop(ctx, nir_cf_node_as_loop(node));
2741 stack_pop(ctx);
2742 break;
2743 case nir_cf_node_function:
2744 ir3_context_error(ctx, "TODO\n");
2745 break;
2746 }
2747 }
2748 }
2749
2750 /* emit stream-out code. At this point, the current block is the original
2751 * (nir) end block, and nir ensures that all flow control paths terminate
2752 * into the end block. We re-purpose the original end block to generate
2753 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2754 * block holding stream-out write instructions, followed by the new end
2755 * block:
2756 *
2757 * blockOrigEnd {
2758 * p0.x = (vtxcnt < maxvtxcnt)
2759 * // succs: blockStreamOut, blockNewEnd
2760 * }
2761 * blockStreamOut {
2762 * // preds: blockOrigEnd
2763 * ... stream-out instructions ...
2764 * // succs: blockNewEnd
2765 * }
2766 * blockNewEnd {
2767 * // preds: blockOrigEnd, blockStreamOut
2768 * }
2769 */
2770 static void
2771 emit_stream_out(struct ir3_context *ctx)
2772 {
2773 struct ir3 *ir = ctx->ir;
2774 struct ir3_stream_output_info *strmout =
2775 &ctx->so->shader->stream_output;
2776 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2777 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2778 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2779
2780 /* create vtxcnt input in input block at top of shader,
2781 * so that it is seen as live over the entire duration
2782 * of the shader:
2783 */
2784 vtxcnt = create_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, 0x1);
2785 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2786
2787 /* at this point, we are at the original 'end' block,
2788 * re-purpose this block to stream-out condition, then
2789 * append stream-out block and new-end block
2790 */
2791 orig_end_block = ctx->block;
2792
2793 // maybe w/ store_global intrinsic, we could do this
2794 // stuff in nir->nir pass
2795
2796 stream_out_block = ir3_block_create(ir);
2797 list_addtail(&stream_out_block->node, &ir->block_list);
2798
2799 new_end_block = ir3_block_create(ir);
2800 list_addtail(&new_end_block->node, &ir->block_list);
2801
2802 orig_end_block->successors[0] = stream_out_block;
2803 orig_end_block->successors[1] = new_end_block;
2804
2805 stream_out_block->successors[0] = new_end_block;
2806 _mesa_set_add(stream_out_block->predecessors, orig_end_block);
2807
2808 _mesa_set_add(new_end_block->predecessors, orig_end_block);
2809 _mesa_set_add(new_end_block->predecessors, stream_out_block);
2810
2811 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2812 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2813 cond->regs[0]->num = regid(REG_P0, 0);
2814 cond->regs[0]->flags &= ~IR3_REG_SSA;
2815 cond->cat2.condition = IR3_COND_LT;
2816
2817 /* condition goes on previous block to the conditional,
2818 * since it is used to pick which of the two successor
2819 * paths to take:
2820 */
2821 orig_end_block->condition = cond;
2822
2823 /* switch to stream_out_block to generate the stream-out
2824 * instructions:
2825 */
2826 ctx->block = stream_out_block;
2827
2828 /* Calculate base addresses based on vtxcnt. Instructions
2829 * generated for bases not used in following loop will be
2830 * stripped out in the backend.
2831 */
2832 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2833 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2834 unsigned stride = strmout->stride[i];
2835 struct ir3_instruction *base, *off;
2836
2837 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2838
2839 /* 24-bit should be enough: */
2840 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2841 create_immed(ctx->block, stride * 4), 0);
2842
2843 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2844 }
2845
2846 /* Generate the per-output store instructions: */
2847 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2848 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2849 unsigned c = j + strmout->output[i].start_component;
2850 struct ir3_instruction *base, *out, *stg;
2851
2852 base = bases[strmout->output[i].output_buffer];
2853 out = ctx->outputs[regid(strmout->output[i].register_index, c)];
2854
2855 stg = ir3_STG(ctx->block, base, 0, out, 0,
2856 create_immed(ctx->block, 1), 0);
2857 stg->cat6.type = TYPE_U32;
2858 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2859
2860 array_insert(ctx->block, ctx->block->keeps, stg);
2861 }
2862 }
2863
2864 /* and finally switch to the new_end_block: */
2865 ctx->block = new_end_block;
2866 }
2867
2868 static void
2869 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2870 {
2871 nir_metadata_require(impl, nir_metadata_block_index);
2872
2873 compile_assert(ctx, ctx->stack == 0);
2874
2875 emit_cf_list(ctx, &impl->body);
2876 emit_block(ctx, impl->end_block);
2877
2878 compile_assert(ctx, ctx->stack == 0);
2879
2880 /* at this point, we should have a single empty block,
2881 * into which we emit the 'end' instruction.
2882 */
2883 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2884
2885 /* If stream-out (aka transform-feedback) enabled, emit the
2886 * stream-out instructions, followed by a new empty block (into
2887 * which the 'end' instruction lands).
2888 *
2889 * NOTE: it is done in this order, rather than inserting before
2890 * we emit end_block, because NIR guarantees that all blocks
2891 * flow into end_block, and that end_block has no successors.
2892 * So by re-purposing end_block as the first block of stream-
2893 * out, we guarantee that all exit paths flow into the stream-
2894 * out instructions.
2895 */
2896 if ((ctx->compiler->gpu_id < 500) &&
2897 (ctx->so->shader->stream_output.num_outputs > 0) &&
2898 !ctx->so->binning_pass) {
2899 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2900 emit_stream_out(ctx);
2901 }
2902
2903 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2904 * NOP and has an epilogue that writes the VS outputs to local storage, to
2905 * be read by the HS. Then it resets execution mask (chmask) and chains
2906 * to the next shader (chsh).
2907 */
2908 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2909 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2910 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2911 struct ir3_instruction *chmask =
2912 ir3_CHMASK(ctx->block);
2913 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2914 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2915
2916 struct ir3_instruction *chsh =
2917 ir3_CHSH(ctx->block);
2918 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2919 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2920 } else {
2921 ir3_END(ctx->block);
2922 }
2923 }
2924
2925 static void
2926 setup_input(struct ir3_context *ctx, nir_variable *in)
2927 {
2928 struct ir3_shader_variant *so = ctx->so;
2929 unsigned ncomp = glsl_get_components(in->type);
2930 unsigned n = in->data.driver_location;
2931 unsigned frac = in->data.location_frac;
2932 unsigned slot = in->data.location;
2933
2934 /* Inputs are loaded using ldlw or ldg for these stages. */
2935 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2936 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2937 ctx->so->type == MESA_SHADER_GEOMETRY)
2938 return;
2939
2940 /* skip unread inputs, we could end up with (for example), unsplit
2941 * matrix/etc inputs in the case they are not read, so just silently
2942 * skip these.
2943 */
2944 if (ncomp > 4)
2945 return;
2946
2947 so->inputs[n].slot = slot;
2948 so->inputs[n].compmask |= (1 << (ncomp + frac)) - 1;
2949 so->inputs_count = MAX2(so->inputs_count, n + 1);
2950 so->inputs[n].interpolate = in->data.interpolation;
2951
2952 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2953
2954 /* if any varyings have 'sample' qualifer, that triggers us
2955 * to run in per-sample mode:
2956 */
2957 so->per_samp |= in->data.sample;
2958
2959 for (int i = 0; i < ncomp; i++) {
2960 struct ir3_instruction *instr = NULL;
2961 unsigned idx = (n * 4) + i + frac;
2962
2963 if (slot == VARYING_SLOT_POS) {
2964 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2965 } else {
2966 /* detect the special case for front/back colors where
2967 * we need to do flat vs smooth shading depending on
2968 * rast state:
2969 */
2970 if (in->data.interpolation == INTERP_MODE_NONE) {
2971 switch (slot) {
2972 case VARYING_SLOT_COL0:
2973 case VARYING_SLOT_COL1:
2974 case VARYING_SLOT_BFC0:
2975 case VARYING_SLOT_BFC1:
2976 so->inputs[n].rasterflat = true;
2977 break;
2978 default:
2979 break;
2980 }
2981 }
2982
2983 if (ctx->compiler->flat_bypass) {
2984 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2985 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2986 so->inputs[n].use_ldlv = true;
2987 }
2988
2989 so->inputs[n].bary = true;
2990
2991 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2992 }
2993
2994 compile_assert(ctx, idx < ctx->ninputs);
2995
2996 ctx->inputs[idx] = instr;
2997 }
2998 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2999 struct ir3_instruction *input = NULL, *in;
3000 struct ir3_instruction *components[4];
3001 unsigned mask = (1 << (ncomp + frac)) - 1;
3002
3003 foreach_input (in, ctx->ir) {
3004 if (in->input.inidx == n) {
3005 input = in;
3006 break;
3007 }
3008 }
3009
3010 if (!input) {
3011 input = create_input(ctx, mask);
3012 input->input.inidx = n;
3013 } else {
3014 input->regs[0]->wrmask |= mask;
3015 }
3016
3017 ir3_split_dest(ctx->block, components, input, frac, ncomp);
3018
3019 for (int i = 0; i < ncomp; i++) {
3020 unsigned idx = (n * 4) + i + frac;
3021 compile_assert(ctx, idx < ctx->ninputs);
3022 ctx->inputs[idx] = components[i];
3023 }
3024 } else {
3025 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
3026 }
3027
3028 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
3029 so->total_in += ncomp;
3030 }
3031 }
3032
3033 /* Initially we assign non-packed inloc's for varyings, as we don't really
3034 * know up-front which components will be unused. After all the compilation
3035 * stages we scan the shader to see which components are actually used, and
3036 * re-pack the inlocs to eliminate unneeded varyings.
3037 */
3038 static void
3039 pack_inlocs(struct ir3_context *ctx)
3040 {
3041 struct ir3_shader_variant *so = ctx->so;
3042 uint8_t used_components[so->inputs_count];
3043
3044 memset(used_components, 0, sizeof(used_components));
3045
3046 /*
3047 * First Step: scan shader to find which bary.f/ldlv remain:
3048 */
3049
3050 foreach_block (block, &ctx->ir->block_list) {
3051 foreach_instr (instr, &block->instr_list) {
3052 if (is_input(instr)) {
3053 unsigned inloc = instr->regs[1]->iim_val;
3054 unsigned i = inloc / 4;
3055 unsigned j = inloc % 4;
3056
3057 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
3058 compile_assert(ctx, i < so->inputs_count);
3059
3060 used_components[i] |= 1 << j;
3061 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3062 for (int n = 0; n < 2; n++) {
3063 unsigned inloc = instr->prefetch.input_offset + n;
3064 unsigned i = inloc / 4;
3065 unsigned j = inloc % 4;
3066
3067 compile_assert(ctx, i < so->inputs_count);
3068
3069 used_components[i] |= 1 << j;
3070 }
3071 }
3072 }
3073 }
3074
3075 /*
3076 * Second Step: reassign varying inloc/slots:
3077 */
3078
3079 unsigned actual_in = 0;
3080 unsigned inloc = 0;
3081
3082 for (unsigned i = 0; i < so->inputs_count; i++) {
3083 unsigned compmask = 0, maxcomp = 0;
3084
3085 so->inputs[i].inloc = inloc;
3086 so->inputs[i].bary = false;
3087
3088 for (unsigned j = 0; j < 4; j++) {
3089 if (!(used_components[i] & (1 << j)))
3090 continue;
3091
3092 compmask |= (1 << j);
3093 actual_in++;
3094 maxcomp = j + 1;
3095
3096 /* at this point, since used_components[i] mask is only
3097 * considering varyings (ie. not sysvals) we know this
3098 * is a varying:
3099 */
3100 so->inputs[i].bary = true;
3101 }
3102
3103 if (so->inputs[i].bary) {
3104 so->varying_in++;
3105 so->inputs[i].compmask = (1 << maxcomp) - 1;
3106 inloc += maxcomp;
3107 }
3108 }
3109
3110 /*
3111 * Third Step: reassign packed inloc's:
3112 */
3113
3114 foreach_block (block, &ctx->ir->block_list) {
3115 foreach_instr (instr, &block->instr_list) {
3116 if (is_input(instr)) {
3117 unsigned inloc = instr->regs[1]->iim_val;
3118 unsigned i = inloc / 4;
3119 unsigned j = inloc % 4;
3120
3121 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
3122 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3123 unsigned i = instr->prefetch.input_offset / 4;
3124 unsigned j = instr->prefetch.input_offset % 4;
3125 instr->prefetch.input_offset = so->inputs[i].inloc + j;
3126 }
3127 }
3128 }
3129 }
3130
3131 static void
3132 setup_output(struct ir3_context *ctx, nir_variable *out)
3133 {
3134 struct ir3_shader_variant *so = ctx->so;
3135 unsigned slots = glsl_count_vec4_slots(out->type, false, false);
3136 unsigned ncomp = glsl_get_components(glsl_without_array(out->type));
3137 unsigned n = out->data.driver_location;
3138 unsigned frac = out->data.location_frac;
3139 unsigned slot = out->data.location;
3140
3141 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3142 switch (slot) {
3143 case FRAG_RESULT_DEPTH:
3144 so->writes_pos = true;
3145 break;
3146 case FRAG_RESULT_COLOR:
3147 so->color0_mrt = 1;
3148 break;
3149 case FRAG_RESULT_SAMPLE_MASK:
3150 so->writes_smask = true;
3151 break;
3152 default:
3153 if (slot >= FRAG_RESULT_DATA0)
3154 break;
3155 ir3_context_error(ctx, "unknown FS output name: %s\n",
3156 gl_frag_result_name(slot));
3157 }
3158 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
3159 ctx->so->type == MESA_SHADER_TESS_EVAL ||
3160 ctx->so->type == MESA_SHADER_GEOMETRY) {
3161 switch (slot) {
3162 case VARYING_SLOT_POS:
3163 so->writes_pos = true;
3164 break;
3165 case VARYING_SLOT_PSIZ:
3166 so->writes_psize = true;
3167 break;
3168 case VARYING_SLOT_PRIMITIVE_ID:
3169 case VARYING_SLOT_LAYER:
3170 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
3171 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
3172 /* fall through */
3173 case VARYING_SLOT_COL0:
3174 case VARYING_SLOT_COL1:
3175 case VARYING_SLOT_BFC0:
3176 case VARYING_SLOT_BFC1:
3177 case VARYING_SLOT_FOGC:
3178 case VARYING_SLOT_CLIP_DIST0:
3179 case VARYING_SLOT_CLIP_DIST1:
3180 case VARYING_SLOT_CLIP_VERTEX:
3181 break;
3182 default:
3183 if (slot >= VARYING_SLOT_VAR0)
3184 break;
3185 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
3186 break;
3187 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
3188 _mesa_shader_stage_to_string(ctx->so->type),
3189 gl_varying_slot_name(slot));
3190 }
3191 } else if (ctx->so->type == MESA_SHADER_TESS_CTRL) {
3192 /* output lowered to buffer writes. */
3193 return;
3194 } else {
3195 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
3196 }
3197
3198
3199 so->outputs_count = out->data.driver_location + slots;
3200 compile_assert(ctx, so->outputs_count < ARRAY_SIZE(so->outputs));
3201
3202 for (int i = 0; i < slots; i++) {
3203 int slot_base = n + i;
3204 so->outputs[slot_base].slot = slot + i;
3205
3206 for (int i = 0; i < ncomp; i++) {
3207 unsigned idx = (slot_base * 4) + i + frac;
3208 compile_assert(ctx, idx < ctx->noutputs);
3209 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3210 }
3211
3212 /* if varying packing doesn't happen, we could end up in a situation
3213 * with "holes" in the output, and since the per-generation code that
3214 * sets up varying linkage registers doesn't expect to have more than
3215 * one varying per vec4 slot, pad the holes.
3216 *
3217 * Note that this should probably generate a performance warning of
3218 * some sort.
3219 */
3220 for (int i = 0; i < frac; i++) {
3221 unsigned idx = (slot_base * 4) + i;
3222 if (!ctx->outputs[idx]) {
3223 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3224 }
3225 }
3226 }
3227 }
3228
3229 static void
3230 emit_instructions(struct ir3_context *ctx)
3231 {
3232 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
3233
3234 ctx->ninputs = ctx->s->num_inputs * 4;
3235 ctx->noutputs = ctx->s->num_outputs * 4;
3236 ctx->inputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->ninputs);
3237 ctx->outputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->noutputs);
3238
3239 ctx->ir = ir3_create(ctx->compiler, ctx->so->type);
3240
3241 /* Create inputs in first block: */
3242 ctx->block = get_block(ctx, nir_start_block(fxn));
3243 ctx->in_block = ctx->block;
3244
3245 /* for fragment shader, the vcoord input register is used as the
3246 * base for bary.f varying fetch instrs:
3247 *
3248 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3249 * until emit_intrinsic when we know they are actually needed.
3250 * For now, we defer creating ctx->ij_centroid, etc, since we
3251 * only need ij_pixel for "old style" varying inputs (ie.
3252 * tgsi_to_nir)
3253 */
3254 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3255 ctx->ij_pixel = create_input(ctx, 0x3);
3256 }
3257
3258 /* Setup inputs: */
3259 nir_foreach_variable (var, &ctx->s->inputs) {
3260 setup_input(ctx, var);
3261 }
3262
3263 /* Defer add_sysval_input() stuff until after setup_inputs(),
3264 * because sysvals need to be appended after varyings:
3265 */
3266 if (ctx->ij_pixel) {
3267 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL,
3268 0x3, ctx->ij_pixel);
3269 }
3270
3271
3272 /* Tesselation shaders always need primitive ID for indexing the
3273 * BO. Geometry shaders don't always need it but when they do it has be
3274 * delivered and unclobbered in the VS. To make things easy, we always
3275 * make room for it in VS/DS.
3276 */
3277 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
3278 bool has_gs = ctx->so->key.has_gs;
3279 switch (ctx->so->type) {
3280 case MESA_SHADER_VERTEX:
3281 if (has_tess) {
3282 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3283 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3284 } else if (has_gs) {
3285 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3286 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3287 }
3288 break;
3289 case MESA_SHADER_TESS_CTRL:
3290 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3291 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3292 break;
3293 case MESA_SHADER_TESS_EVAL:
3294 if (has_gs)
3295 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3296 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3297 break;
3298 case MESA_SHADER_GEOMETRY:
3299 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3300 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3301 break;
3302 default:
3303 break;
3304 }
3305
3306 /* Setup outputs: */
3307 nir_foreach_variable (var, &ctx->s->outputs) {
3308 setup_output(ctx, var);
3309 }
3310
3311 /* Find # of samplers: */
3312 nir_foreach_variable (var, &ctx->s->uniforms) {
3313 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
3314 /* just assume that we'll be reading from images.. if it
3315 * is write-only we don't have to count it, but not sure
3316 * if there is a good way to know?
3317 */
3318 ctx->so->num_samp += glsl_type_get_image_count(var->type);
3319 }
3320
3321 /* NOTE: need to do something more clever when we support >1 fxn */
3322 nir_foreach_register (reg, &fxn->registers) {
3323 ir3_declare_array(ctx, reg);
3324 }
3325 /* And emit the body: */
3326 ctx->impl = fxn;
3327 emit_function(ctx, fxn);
3328 }
3329
3330 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3331 * need to assign the tex state indexes for these after we know the
3332 * max tex index.
3333 */
3334 static void
3335 fixup_astc_srgb(struct ir3_context *ctx)
3336 {
3337 struct ir3_shader_variant *so = ctx->so;
3338 /* indexed by original tex idx, value is newly assigned alpha sampler
3339 * state tex idx. Zero is invalid since there is at least one sampler
3340 * if we get here.
3341 */
3342 unsigned alt_tex_state[16] = {0};
3343 unsigned tex_idx = ctx->max_texture_index + 1;
3344 unsigned idx = 0;
3345
3346 so->astc_srgb.base = tex_idx;
3347
3348 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3349 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3350
3351 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3352
3353 if (alt_tex_state[sam->cat5.tex] == 0) {
3354 /* assign new alternate/alpha tex state slot: */
3355 alt_tex_state[sam->cat5.tex] = tex_idx++;
3356 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3357 so->astc_srgb.count++;
3358 }
3359
3360 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3361 }
3362 }
3363
3364 static void
3365 fixup_binning_pass(struct ir3_context *ctx)
3366 {
3367 struct ir3_shader_variant *so = ctx->so;
3368 struct ir3 *ir = ctx->ir;
3369 unsigned i, j;
3370
3371 /* first pass, remove unused outputs from the IR level outputs: */
3372 for (i = 0, j = 0; i < ir->outputs_count; i++) {
3373 struct ir3_instruction *out = ir->outputs[i];
3374 assert(out->opc == OPC_META_COLLECT);
3375 unsigned outidx = out->collect.outidx;
3376 unsigned slot = so->outputs[outidx].slot;
3377
3378 /* throw away everything but first position/psize */
3379 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3380 ir->outputs[j] = ir->outputs[i];
3381 j++;
3382 }
3383 }
3384 ir->outputs_count = j;
3385
3386 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3387 * table:
3388 */
3389 for (i = 0, j = 0; i < so->outputs_count; i++) {
3390 unsigned slot = so->outputs[i].slot;
3391
3392 /* throw away everything but first position/psize */
3393 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3394 so->outputs[j] = so->outputs[i];
3395
3396 /* fixup outidx to point to new output table entry: */
3397 struct ir3_instruction *out;
3398 foreach_output (out, ir) {
3399 if (out->collect.outidx == i) {
3400 out->collect.outidx = j;
3401 break;
3402 }
3403 }
3404
3405 j++;
3406 }
3407 }
3408 so->outputs_count = j;
3409 }
3410
3411 static void
3412 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3413 {
3414 unsigned idx = 0;
3415
3416 /* Collect sampling instructions eligible for pre-dispatch. */
3417 foreach_block (block, &ir->block_list) {
3418 foreach_instr_safe (instr, &block->instr_list) {
3419 if (instr->opc == OPC_META_TEX_PREFETCH) {
3420 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3421 struct ir3_sampler_prefetch *fetch =
3422 &ctx->so->sampler_prefetch[idx];
3423 idx++;
3424
3425 if (instr->flags & IR3_INSTR_B) {
3426 fetch->cmd = IR3_SAMPLER_BINDLESS_PREFETCH_CMD;
3427 /* In bindless mode, the index is actually the base */
3428 fetch->tex_id = instr->prefetch.tex_base;
3429 fetch->samp_id = instr->prefetch.samp_base;
3430 fetch->tex_bindless_id = instr->prefetch.tex;
3431 fetch->samp_bindless_id = instr->prefetch.samp;
3432 } else {
3433 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3434 fetch->tex_id = instr->prefetch.tex;
3435 fetch->samp_id = instr->prefetch.samp;
3436 }
3437 fetch->wrmask = instr->regs[0]->wrmask;
3438 fetch->dst = instr->regs[0]->num;
3439 fetch->src = instr->prefetch.input_offset;
3440
3441 ctx->so->total_in =
3442 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3443
3444 /* Disable half precision until supported. */
3445 fetch->half_precision = !!(instr->regs[0]->flags & IR3_REG_HALF);
3446
3447 /* Remove the prefetch placeholder instruction: */
3448 list_delinit(&instr->node);
3449 }
3450 }
3451 }
3452 }
3453
3454 int
3455 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3456 struct ir3_shader_variant *so)
3457 {
3458 struct ir3_context *ctx;
3459 struct ir3 *ir;
3460 int ret = 0, max_bary;
3461
3462 assert(!so->ir);
3463
3464 ctx = ir3_context_init(compiler, so);
3465 if (!ctx) {
3466 DBG("INIT failed!");
3467 ret = -1;
3468 goto out;
3469 }
3470
3471 emit_instructions(ctx);
3472
3473 if (ctx->error) {
3474 DBG("EMIT failed!");
3475 ret = -1;
3476 goto out;
3477 }
3478
3479 ir = so->ir = ctx->ir;
3480
3481 assert((ctx->noutputs % 4) == 0);
3482
3483 /* Setup IR level outputs, which are "collects" that gather
3484 * the scalar components of outputs.
3485 */
3486 for (unsigned i = 0; i < ctx->noutputs; i += 4) {
3487 unsigned ncomp = 0;
3488 /* figure out the # of components written:
3489 *
3490 * TODO do we need to handle holes, ie. if .x and .z
3491 * components written, but .y component not written?
3492 */
3493 for (unsigned j = 0; j < 4; j++) {
3494 if (!ctx->outputs[i + j])
3495 break;
3496 ncomp++;
3497 }
3498
3499 /* Note that in some stages, like TCS, store_output is
3500 * lowered to memory writes, so no components of the
3501 * are "written" from the PoV of traditional store-
3502 * output instructions:
3503 */
3504 if (!ncomp)
3505 continue;
3506
3507 struct ir3_instruction *out =
3508 ir3_create_collect(ctx, &ctx->outputs[i], ncomp);
3509
3510 int outidx = i / 4;
3511 assert(outidx < so->outputs_count);
3512
3513 /* stash index into so->outputs[] so we can map the
3514 * output back to slot/etc later:
3515 */
3516 out->collect.outidx = outidx;
3517
3518 array_insert(ir, ir->outputs, out);
3519 }
3520
3521 /* Set up the gs header as an output for the vertex shader so it won't
3522 * clobber it for the tess ctrl shader.
3523 *
3524 * TODO this could probably be done more cleanly in a nir pass.
3525 */
3526 if (ctx->so->type == MESA_SHADER_VERTEX ||
3527 (ctx->so->key.has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3528 if (ctx->primitive_id) {
3529 unsigned n = so->outputs_count++;
3530 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3531
3532 struct ir3_instruction *out =
3533 ir3_create_collect(ctx, &ctx->primitive_id, 1);
3534 out->collect.outidx = n;
3535 array_insert(ir, ir->outputs, out);
3536 }
3537
3538 if (ctx->gs_header) {
3539 unsigned n = so->outputs_count++;
3540 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3541 struct ir3_instruction *out =
3542 ir3_create_collect(ctx, &ctx->gs_header, 1);
3543 out->collect.outidx = n;
3544 array_insert(ir, ir->outputs, out);
3545 }
3546
3547 if (ctx->tcs_header) {
3548 unsigned n = so->outputs_count++;
3549 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3550 struct ir3_instruction *out =
3551 ir3_create_collect(ctx, &ctx->tcs_header, 1);
3552 out->collect.outidx = n;
3553 array_insert(ir, ir->outputs, out);
3554 }
3555 }
3556
3557 /* at this point, for binning pass, throw away unneeded outputs: */
3558 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3559 fixup_binning_pass(ctx);
3560
3561 ir3_debug_print(ir, "BEFORE CF");
3562
3563 ir3_cf(ir);
3564
3565 ir3_debug_print(ir, "BEFORE CP");
3566
3567 ir3_cp(ir, so);
3568
3569 /* at this point, for binning pass, throw away unneeded outputs:
3570 * Note that for a6xx and later, we do this after ir3_cp to ensure
3571 * that the uniform/constant layout for BS and VS matches, so that
3572 * we can re-use same VS_CONST state group.
3573 */
3574 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
3575 fixup_binning_pass(ctx);
3576
3577 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3578 * need to make sure not to remove any inputs that are used by
3579 * the nonbinning VS.
3580 */
3581 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3582 so->type == MESA_SHADER_VERTEX) {
3583 for (int i = 0; i < ctx->ninputs; i++) {
3584 struct ir3_instruction *in = ctx->inputs[i];
3585
3586 if (!in)
3587 continue;
3588
3589 unsigned n = i / 4;
3590 unsigned c = i % 4;
3591
3592 debug_assert(n < so->nonbinning->inputs_count);
3593
3594 if (so->nonbinning->inputs[n].sysval)
3595 continue;
3596
3597 /* be sure to keep inputs, even if only used in VS */
3598 if (so->nonbinning->inputs[n].compmask & (1 << c))
3599 array_insert(in->block, in->block->keeps, in);
3600 }
3601 }
3602
3603 ir3_debug_print(ir, "BEFORE GROUPING");
3604
3605 ir3_sched_add_deps(ir);
3606
3607 /* Group left/right neighbors, inserting mov's where needed to
3608 * solve conflicts:
3609 */
3610 ir3_group(ir);
3611
3612 ir3_debug_print(ir, "AFTER GROUPING");
3613
3614 ir3_dce(ir, so);
3615
3616 ir3_debug_print(ir, "AFTER DCE");
3617
3618 /* do Sethi–Ullman numbering before scheduling: */
3619 ir3_sun(ir);
3620
3621 ret = ir3_sched(ir);
3622 if (ret) {
3623 DBG("SCHED failed!");
3624 goto out;
3625 }
3626
3627 ir3_debug_print(ir, "AFTER SCHED");
3628
3629 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3630 * with draw pass VS, so binning and draw pass can both use the
3631 * same VBO state.
3632 *
3633 * Note that VS inputs are expected to be full precision.
3634 */
3635 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3636 (ir->type == MESA_SHADER_VERTEX) &&
3637 so->binning_pass;
3638
3639 if (pre_assign_inputs) {
3640 for (unsigned i = 0; i < ctx->ninputs; i++) {
3641 struct ir3_instruction *instr = ctx->inputs[i];
3642
3643 if (!instr)
3644 continue;
3645
3646 unsigned n = i / 4;
3647 unsigned c = i % 4;
3648 unsigned regid = so->nonbinning->inputs[n].regid + c;
3649
3650 instr->regs[0]->num = regid;
3651 }
3652
3653 ret = ir3_ra(so, ctx->inputs, ctx->ninputs);
3654 } else if (ctx->tcs_header) {
3655 /* We need to have these values in the same registers between VS and TCS
3656 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3657 */
3658
3659 ctx->tcs_header->regs[0]->num = regid(0, 0);
3660 ctx->primitive_id->regs[0]->num = regid(0, 1);
3661 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3662 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3663 } else if (ctx->gs_header) {
3664 /* We need to have these values in the same registers between producer
3665 * (VS or DS) and GS since the producer chains to GS and doesn't get
3666 * the sysvals redelivered.
3667 */
3668
3669 ctx->gs_header->regs[0]->num = regid(0, 0);
3670 ctx->primitive_id->regs[0]->num = regid(0, 1);
3671 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3672 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3673 } else if (so->num_sampler_prefetch) {
3674 assert(so->type == MESA_SHADER_FRAGMENT);
3675 struct ir3_instruction *instr, *precolor[2];
3676 int idx = 0;
3677
3678 foreach_input (instr, ir) {
3679 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL)
3680 continue;
3681
3682 assert(idx < ARRAY_SIZE(precolor));
3683
3684 precolor[idx] = instr;
3685 instr->regs[0]->num = idx;
3686
3687 idx++;
3688 }
3689 ret = ir3_ra(so, precolor, idx);
3690 } else {
3691 ret = ir3_ra(so, NULL, 0);
3692 }
3693
3694 if (ret) {
3695 DBG("RA failed!");
3696 goto out;
3697 }
3698
3699 ir3_postsched(ctx);
3700 ir3_debug_print(ir, "AFTER POSTSCHED");
3701
3702 if (compiler->gpu_id >= 600) {
3703 if (ir3_a6xx_fixup_atomic_dests(ir, so)) {
3704 ir3_debug_print(ir, "AFTER ATOMIC FIXUP");
3705 }
3706 }
3707
3708 if (so->type == MESA_SHADER_FRAGMENT)
3709 pack_inlocs(ctx);
3710
3711 /*
3712 * Fixup inputs/outputs to point to the actual registers assigned:
3713 *
3714 * 1) initialize to r63.x (invalid/unused)
3715 * 2) iterate IR level inputs/outputs and update the variants
3716 * inputs/outputs table based on the assigned registers for
3717 * the remaining inputs/outputs.
3718 */
3719
3720 for (unsigned i = 0; i < so->inputs_count; i++)
3721 so->inputs[i].regid = INVALID_REG;
3722 for (unsigned i = 0; i < so->outputs_count; i++)
3723 so->outputs[i].regid = INVALID_REG;
3724
3725 struct ir3_instruction *out;
3726 foreach_output (out, ir) {
3727 assert(out->opc == OPC_META_COLLECT);
3728 unsigned outidx = out->collect.outidx;
3729
3730 so->outputs[outidx].regid = out->regs[0]->num;
3731 so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF);
3732 }
3733
3734 struct ir3_instruction *in;
3735 foreach_input (in, ir) {
3736 assert(in->opc == OPC_META_INPUT);
3737 unsigned inidx = in->input.inidx;
3738
3739 if (pre_assign_inputs && !so->inputs[inidx].sysval) {
3740 if (VALIDREG(so->nonbinning->inputs[inidx].regid)) {
3741 compile_assert(ctx, in->regs[0]->num ==
3742 so->nonbinning->inputs[inidx].regid);
3743 compile_assert(ctx, !!(in->regs[0]->flags & IR3_REG_HALF) ==
3744 so->nonbinning->inputs[inidx].half);
3745 }
3746 so->inputs[inidx].regid = so->nonbinning->inputs[inidx].regid;
3747 so->inputs[inidx].half = so->nonbinning->inputs[inidx].half;
3748 } else {
3749 so->inputs[inidx].regid = in->regs[0]->num;
3750 so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
3751 }
3752 }
3753
3754 if (ctx->astc_srgb)
3755 fixup_astc_srgb(ctx);
3756
3757 /* We need to do legalize after (for frag shader's) the "bary.f"
3758 * offsets (inloc) have been assigned.
3759 */
3760 ir3_legalize(ir, so, &max_bary);
3761
3762 ir3_debug_print(ir, "AFTER LEGALIZE");
3763
3764 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3765 * know what we might have to wait on when coming in from VS chsh.
3766 */
3767 if (so->type == MESA_SHADER_TESS_CTRL ||
3768 so->type == MESA_SHADER_GEOMETRY ) {
3769 foreach_block (block, &ir->block_list) {
3770 foreach_instr (instr, &block->instr_list) {
3771 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3772 break;
3773 }
3774 }
3775 }
3776
3777 so->branchstack = ctx->max_stack;
3778
3779 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3780 if (so->type == MESA_SHADER_FRAGMENT)
3781 so->total_in = max_bary + 1;
3782
3783 so->max_sun = ir->max_sun;
3784
3785 /* Collect sampling instructions eligible for pre-dispatch. */
3786 collect_tex_prefetches(ctx, ir);
3787
3788 if (so->type == MESA_SHADER_FRAGMENT &&
3789 ctx->s->info.fs.needs_helper_invocations)
3790 so->need_pixlod = true;
3791
3792 out:
3793 if (ret) {
3794 if (so->ir)
3795 ir3_destroy(so->ir);
3796 so->ir = NULL;
3797 }
3798 ir3_context_free(ctx);
3799
3800 return ret;
3801 }