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freedreno/ir3: implement fquantize2f16
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 ir3_reg_create(mov, 0, 0);
55 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
56 src->instr = collect;
57 src->size = arrsz;
58 src->array.offset = n;
59
60 ir3_instr_set_address(mov, address);
61
62 return mov;
63 }
64
65 static struct ir3_instruction *
66 create_input_compmask(struct ir3_context *ctx, unsigned n, unsigned compmask)
67 {
68 struct ir3_instruction *in;
69
70 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
71 in->inout.block = ctx->in_block;
72 ir3_reg_create(in, n, 0);
73
74 in->regs[0]->wrmask = compmask;
75
76 return in;
77 }
78
79 static struct ir3_instruction *
80 create_input(struct ir3_context *ctx, unsigned n)
81 {
82 return create_input_compmask(ctx, n, 0x1);
83 }
84
85 static struct ir3_instruction *
86 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
87 {
88 struct ir3_block *block = ctx->block;
89 struct ir3_instruction *instr;
90 /* packed inloc is fixed up later: */
91 struct ir3_instruction *inloc = create_immed(block, n);
92
93 if (use_ldlv) {
94 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
95 instr->cat6.type = TYPE_U32;
96 instr->cat6.iim_val = 1;
97 } else {
98 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
99 instr->regs[2]->wrmask = 0x3;
100 }
101
102 return instr;
103 }
104
105 static struct ir3_instruction *
106 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
107 {
108 /* first four vec4 sysval's reserved for UBOs: */
109 /* NOTE: dp is in scalar, but there can be >4 dp components: */
110 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
111 unsigned n = const_state->offsets.driver_param;
112 unsigned r = regid(n + dp / 4, dp % 4);
113 return create_uniform(ctx->block, r);
114 }
115
116 /*
117 * Adreno uses uint rather than having dedicated bool type,
118 * which (potentially) requires some conversion, in particular
119 * when using output of an bool instr to int input, or visa
120 * versa.
121 *
122 * | Adreno | NIR |
123 * -------+---------+-------+-
124 * true | 1 | ~0 |
125 * false | 0 | 0 |
126 *
127 * To convert from an adreno bool (uint) to nir, use:
128 *
129 * absneg.s dst, (neg)src
130 *
131 * To convert back in the other direction:
132 *
133 * absneg.s dst, (abs)arc
134 *
135 * The CP step can clean up the absneg.s that cancel each other
136 * out, and with a slight bit of extra cleverness (to recognize
137 * the instructions which produce either a 0 or 1) can eliminate
138 * the absneg.s's completely when an instruction that wants
139 * 0/1 consumes the result. For example, when a nir 'bcsel'
140 * consumes the result of 'feq'. So we should be able to get by
141 * without a boolean resolve step, and without incuring any
142 * extra penalty in instruction count.
143 */
144
145 /* NIR bool -> native (adreno): */
146 static struct ir3_instruction *
147 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
148 {
149 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
150 }
151
152 /* native (adreno) -> NIR bool: */
153 static struct ir3_instruction *
154 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
155 {
156 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
157 }
158
159 /*
160 * alu/sfu instructions:
161 */
162
163 static struct ir3_instruction *
164 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
165 unsigned src_bitsize, nir_op op)
166 {
167 type_t src_type, dst_type;
168
169 switch (op) {
170 case nir_op_f2f32:
171 case nir_op_f2f16_rtne:
172 case nir_op_f2f16_rtz:
173 case nir_op_f2f16:
174 case nir_op_f2i32:
175 case nir_op_f2i16:
176 case nir_op_f2i8:
177 case nir_op_f2u32:
178 case nir_op_f2u16:
179 case nir_op_f2u8:
180 switch (src_bitsize) {
181 case 32:
182 src_type = TYPE_F32;
183 break;
184 case 16:
185 src_type = TYPE_F16;
186 break;
187 default:
188 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
189 }
190 break;
191
192 case nir_op_i2f32:
193 case nir_op_i2f16:
194 case nir_op_i2i32:
195 case nir_op_i2i16:
196 case nir_op_i2i8:
197 switch (src_bitsize) {
198 case 32:
199 src_type = TYPE_S32;
200 break;
201 case 16:
202 src_type = TYPE_S16;
203 break;
204 case 8:
205 src_type = TYPE_S8;
206 break;
207 default:
208 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
209 }
210 break;
211
212 case nir_op_u2f32:
213 case nir_op_u2f16:
214 case nir_op_u2u32:
215 case nir_op_u2u16:
216 case nir_op_u2u8:
217 switch (src_bitsize) {
218 case 32:
219 src_type = TYPE_U32;
220 break;
221 case 16:
222 src_type = TYPE_U16;
223 break;
224 case 8:
225 src_type = TYPE_U8;
226 break;
227 default:
228 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
229 }
230 break;
231
232 default:
233 ir3_context_error(ctx, "invalid conversion op: %u", op);
234 }
235
236 switch (op) {
237 case nir_op_f2f32:
238 case nir_op_i2f32:
239 case nir_op_u2f32:
240 dst_type = TYPE_F32;
241 break;
242
243 case nir_op_f2f16_rtne:
244 case nir_op_f2f16_rtz:
245 case nir_op_f2f16:
246 /* TODO how to handle rounding mode? */
247 case nir_op_i2f16:
248 case nir_op_u2f16:
249 dst_type = TYPE_F16;
250 break;
251
252 case nir_op_f2i32:
253 case nir_op_i2i32:
254 dst_type = TYPE_S32;
255 break;
256
257 case nir_op_f2i16:
258 case nir_op_i2i16:
259 dst_type = TYPE_S16;
260 break;
261
262 case nir_op_f2i8:
263 case nir_op_i2i8:
264 dst_type = TYPE_S8;
265 break;
266
267 case nir_op_f2u32:
268 case nir_op_u2u32:
269 dst_type = TYPE_U32;
270 break;
271
272 case nir_op_f2u16:
273 case nir_op_u2u16:
274 dst_type = TYPE_U16;
275 break;
276
277 case nir_op_f2u8:
278 case nir_op_u2u8:
279 dst_type = TYPE_U8;
280 break;
281
282 default:
283 ir3_context_error(ctx, "invalid conversion op: %u", op);
284 }
285
286 return ir3_COV(ctx->block, src, src_type, dst_type);
287 }
288
289 static void
290 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
291 {
292 const nir_op_info *info = &nir_op_infos[alu->op];
293 struct ir3_instruction **dst, *src[info->num_inputs];
294 unsigned bs[info->num_inputs]; /* bit size */
295 struct ir3_block *b = ctx->block;
296 unsigned dst_sz, wrmask;
297 type_t dst_type = nir_dest_bit_size(alu->dest.dest) < 32 ?
298 TYPE_U16 : TYPE_U32;
299
300 if (alu->dest.dest.is_ssa) {
301 dst_sz = alu->dest.dest.ssa.num_components;
302 wrmask = (1 << dst_sz) - 1;
303 } else {
304 dst_sz = alu->dest.dest.reg.reg->num_components;
305 wrmask = alu->dest.write_mask;
306 }
307
308 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
309
310 /* Vectors are special in that they have non-scalarized writemasks,
311 * and just take the first swizzle channel for each argument in
312 * order into each writemask channel.
313 */
314 if ((alu->op == nir_op_vec2) ||
315 (alu->op == nir_op_vec3) ||
316 (alu->op == nir_op_vec4)) {
317
318 for (int i = 0; i < info->num_inputs; i++) {
319 nir_alu_src *asrc = &alu->src[i];
320
321 compile_assert(ctx, !asrc->abs);
322 compile_assert(ctx, !asrc->negate);
323
324 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
325 if (!src[i])
326 src[i] = create_immed_typed(ctx->block, 0, dst_type);
327 dst[i] = ir3_MOV(b, src[i], dst_type);
328 }
329
330 ir3_put_dst(ctx, &alu->dest.dest);
331 return;
332 }
333
334 /* We also get mov's with more than one component for mov's so
335 * handle those specially:
336 */
337 if (alu->op == nir_op_mov) {
338 nir_alu_src *asrc = &alu->src[0];
339 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
340
341 for (unsigned i = 0; i < dst_sz; i++) {
342 if (wrmask & (1 << i)) {
343 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
344 } else {
345 dst[i] = NULL;
346 }
347 }
348
349 ir3_put_dst(ctx, &alu->dest.dest);
350 return;
351 }
352
353 /* General case: We can just grab the one used channel per src. */
354 for (int i = 0; i < info->num_inputs; i++) {
355 unsigned chan = ffs(alu->dest.write_mask) - 1;
356 nir_alu_src *asrc = &alu->src[i];
357
358 compile_assert(ctx, !asrc->abs);
359 compile_assert(ctx, !asrc->negate);
360
361 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
362 bs[i] = nir_src_bit_size(asrc->src);
363
364 compile_assert(ctx, src[i]);
365 }
366
367 switch (alu->op) {
368 case nir_op_f2f32:
369 case nir_op_f2f16_rtne:
370 case nir_op_f2f16_rtz:
371 case nir_op_f2f16:
372 case nir_op_f2i32:
373 case nir_op_f2i16:
374 case nir_op_f2i8:
375 case nir_op_f2u32:
376 case nir_op_f2u16:
377 case nir_op_f2u8:
378 case nir_op_i2f32:
379 case nir_op_i2f16:
380 case nir_op_i2i32:
381 case nir_op_i2i16:
382 case nir_op_i2i8:
383 case nir_op_u2f32:
384 case nir_op_u2f16:
385 case nir_op_u2u32:
386 case nir_op_u2u16:
387 case nir_op_u2u8:
388 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
389 break;
390 case nir_op_fquantize2f16:
391 dst[0] = create_cov(ctx,
392 create_cov(ctx, src[0], 32, nir_op_f2f16),
393 16, nir_op_f2f32);
394 break;
395 case nir_op_f2b32:
396 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
397 dst[0]->cat2.condition = IR3_COND_NE;
398 dst[0] = ir3_n2b(b, dst[0]);
399 break;
400 case nir_op_b2f16:
401 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F16);
402 break;
403 case nir_op_b2f32:
404 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
405 break;
406 case nir_op_b2i8:
407 case nir_op_b2i16:
408 case nir_op_b2i32:
409 dst[0] = ir3_b2n(b, src[0]);
410 break;
411 case nir_op_i2b32:
412 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
413 dst[0]->cat2.condition = IR3_COND_NE;
414 dst[0] = ir3_n2b(b, dst[0]);
415 break;
416
417 case nir_op_fneg:
418 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
419 break;
420 case nir_op_fabs:
421 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
422 break;
423 case nir_op_fmax:
424 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
425 break;
426 case nir_op_fmin:
427 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
428 break;
429 case nir_op_fsat:
430 /* if there is just a single use of the src, and it supports
431 * (sat) bit, we can just fold the (sat) flag back to the
432 * src instruction and create a mov. This is easier for cp
433 * to eliminate.
434 *
435 * TODO probably opc_cat==4 is ok too
436 */
437 if (alu->src[0].src.is_ssa &&
438 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
439 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
440 src[0]->flags |= IR3_INSTR_SAT;
441 dst[0] = ir3_MOV(b, src[0], dst_type);
442 } else {
443 /* otherwise generate a max.f that saturates.. blob does
444 * similar (generating a cat2 mov using max.f)
445 */
446 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
447 dst[0]->flags |= IR3_INSTR_SAT;
448 }
449 break;
450 case nir_op_fmul:
451 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
452 break;
453 case nir_op_fadd:
454 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
455 break;
456 case nir_op_fsub:
457 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
458 break;
459 case nir_op_ffma:
460 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
461 break;
462 case nir_op_fddx:
463 case nir_op_fddx_coarse:
464 dst[0] = ir3_DSX(b, src[0], 0);
465 dst[0]->cat5.type = TYPE_F32;
466 break;
467 case nir_op_fddy:
468 case nir_op_fddy_coarse:
469 dst[0] = ir3_DSY(b, src[0], 0);
470 dst[0]->cat5.type = TYPE_F32;
471 break;
472 break;
473 case nir_op_flt32:
474 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
475 dst[0]->cat2.condition = IR3_COND_LT;
476 dst[0] = ir3_n2b(b, dst[0]);
477 break;
478 case nir_op_fge32:
479 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
480 dst[0]->cat2.condition = IR3_COND_GE;
481 dst[0] = ir3_n2b(b, dst[0]);
482 break;
483 case nir_op_feq32:
484 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
485 dst[0]->cat2.condition = IR3_COND_EQ;
486 dst[0] = ir3_n2b(b, dst[0]);
487 break;
488 case nir_op_fne32:
489 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
490 dst[0]->cat2.condition = IR3_COND_NE;
491 dst[0] = ir3_n2b(b, dst[0]);
492 break;
493 case nir_op_fceil:
494 dst[0] = ir3_CEIL_F(b, src[0], 0);
495 break;
496 case nir_op_ffloor:
497 dst[0] = ir3_FLOOR_F(b, src[0], 0);
498 break;
499 case nir_op_ftrunc:
500 dst[0] = ir3_TRUNC_F(b, src[0], 0);
501 break;
502 case nir_op_fround_even:
503 dst[0] = ir3_RNDNE_F(b, src[0], 0);
504 break;
505 case nir_op_fsign:
506 dst[0] = ir3_SIGN_F(b, src[0], 0);
507 break;
508
509 case nir_op_fsin:
510 dst[0] = ir3_SIN(b, src[0], 0);
511 break;
512 case nir_op_fcos:
513 dst[0] = ir3_COS(b, src[0], 0);
514 break;
515 case nir_op_frsq:
516 dst[0] = ir3_RSQ(b, src[0], 0);
517 break;
518 case nir_op_frcp:
519 dst[0] = ir3_RCP(b, src[0], 0);
520 break;
521 case nir_op_flog2:
522 dst[0] = ir3_LOG2(b, src[0], 0);
523 break;
524 case nir_op_fexp2:
525 dst[0] = ir3_EXP2(b, src[0], 0);
526 break;
527 case nir_op_fsqrt:
528 dst[0] = ir3_SQRT(b, src[0], 0);
529 break;
530
531 case nir_op_iabs:
532 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
533 break;
534 case nir_op_iadd:
535 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
536 break;
537 case nir_op_iand:
538 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
539 break;
540 case nir_op_imax:
541 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
542 break;
543 case nir_op_umax:
544 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
545 break;
546 case nir_op_imin:
547 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
548 break;
549 case nir_op_umin:
550 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
551 break;
552 case nir_op_umul_low:
553 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
554 break;
555 case nir_op_imadsh_mix16:
556 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
557 break;
558 case nir_op_ineg:
559 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
560 break;
561 case nir_op_inot:
562 dst[0] = ir3_NOT_B(b, src[0], 0);
563 break;
564 case nir_op_ior:
565 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
566 break;
567 case nir_op_ishl:
568 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
569 break;
570 case nir_op_ishr:
571 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
572 break;
573 case nir_op_isub:
574 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
575 break;
576 case nir_op_ixor:
577 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
578 break;
579 case nir_op_ushr:
580 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
581 break;
582 case nir_op_ilt32:
583 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
584 dst[0]->cat2.condition = IR3_COND_LT;
585 dst[0] = ir3_n2b(b, dst[0]);
586 break;
587 case nir_op_ige32:
588 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
589 dst[0]->cat2.condition = IR3_COND_GE;
590 dst[0] = ir3_n2b(b, dst[0]);
591 break;
592 case nir_op_ieq32:
593 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
594 dst[0]->cat2.condition = IR3_COND_EQ;
595 dst[0] = ir3_n2b(b, dst[0]);
596 break;
597 case nir_op_ine32:
598 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
599 dst[0]->cat2.condition = IR3_COND_NE;
600 dst[0] = ir3_n2b(b, dst[0]);
601 break;
602 case nir_op_ult32:
603 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
604 dst[0]->cat2.condition = IR3_COND_LT;
605 dst[0] = ir3_n2b(b, dst[0]);
606 break;
607 case nir_op_uge32:
608 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
609 dst[0]->cat2.condition = IR3_COND_GE;
610 dst[0] = ir3_n2b(b, dst[0]);
611 break;
612
613 case nir_op_b32csel: {
614 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
615 compile_assert(ctx, bs[1] == bs[2]);
616 /* the boolean condition is 32b even if src[1] and src[2] are
617 * half-precision, but sel.b16 wants all three src's to be the
618 * same type.
619 */
620 if (bs[1] < 32)
621 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
622 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
623 break;
624 }
625 case nir_op_bit_count: {
626 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
627 // double check on earlier gen's. Once half-precision support is
628 // in place, this should probably move to a NIR lowering pass:
629 struct ir3_instruction *hi, *lo;
630
631 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
632 TYPE_U32, TYPE_U16);
633 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
634
635 hi = ir3_CBITS_B(b, hi, 0);
636 lo = ir3_CBITS_B(b, lo, 0);
637
638 // TODO maybe the builders should default to making dst half-precision
639 // if the src's were half precision, to make this less awkward.. otoh
640 // we should probably just do this lowering in NIR.
641 hi->regs[0]->flags |= IR3_REG_HALF;
642 lo->regs[0]->flags |= IR3_REG_HALF;
643
644 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
645 dst[0]->regs[0]->flags |= IR3_REG_HALF;
646 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
647 break;
648 }
649 case nir_op_ifind_msb: {
650 struct ir3_instruction *cmp;
651 dst[0] = ir3_CLZ_S(b, src[0], 0);
652 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
653 cmp->cat2.condition = IR3_COND_GE;
654 dst[0] = ir3_SEL_B32(b,
655 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
656 cmp, 0, dst[0], 0);
657 break;
658 }
659 case nir_op_ufind_msb:
660 dst[0] = ir3_CLZ_B(b, src[0], 0);
661 dst[0] = ir3_SEL_B32(b,
662 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
663 src[0], 0, dst[0], 0);
664 break;
665 case nir_op_find_lsb:
666 dst[0] = ir3_BFREV_B(b, src[0], 0);
667 dst[0] = ir3_CLZ_B(b, dst[0], 0);
668 break;
669 case nir_op_bitfield_reverse:
670 dst[0] = ir3_BFREV_B(b, src[0], 0);
671 break;
672
673 default:
674 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
675 nir_op_infos[alu->op].name);
676 break;
677 }
678
679 ir3_put_dst(ctx, &alu->dest.dest);
680 }
681
682 /* handles direct/indirect UBO reads: */
683 static void
684 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
685 struct ir3_instruction **dst)
686 {
687 struct ir3_block *b = ctx->block;
688 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
689 /* UBO addresses are the first driver params, but subtract 2 here to
690 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
691 * is the uniforms: */
692 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
693 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
694 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
695
696 int off = 0;
697
698 /* First src is ubo index, which could either be an immed or not: */
699 src0 = ir3_get_src(ctx, &intr->src[0])[0];
700 if (is_same_type_mov(src0) &&
701 (src0->regs[1]->flags & IR3_REG_IMMED)) {
702 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
703 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
704 } else {
705 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
706 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
707
708 /* NOTE: since relative addressing is used, make sure constlen is
709 * at least big enough to cover all the UBO addresses, since the
710 * assembler won't know what the max address reg is.
711 */
712 ctx->so->constlen = MAX2(ctx->so->constlen,
713 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
714 }
715
716 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
717 addr = base_lo;
718
719 if (nir_src_is_const(intr->src[1])) {
720 off += nir_src_as_uint(intr->src[1]);
721 } else {
722 /* For load_ubo_indirect, second src is indirect offset: */
723 src1 = ir3_get_src(ctx, &intr->src[1])[0];
724
725 /* and add offset to addr: */
726 addr = ir3_ADD_S(b, addr, 0, src1, 0);
727 }
728
729 /* if offset is to large to encode in the ldg, split it out: */
730 if ((off + (intr->num_components * 4)) > 1024) {
731 /* split out the minimal amount to improve the odds that
732 * cp can fit the immediate in the add.s instruction:
733 */
734 unsigned off2 = off + (intr->num_components * 4) - 1024;
735 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
736 off -= off2;
737 }
738
739 if (ptrsz == 2) {
740 struct ir3_instruction *carry;
741
742 /* handle 32b rollover, ie:
743 * if (addr < base_lo)
744 * base_hi++
745 */
746 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
747 carry->cat2.condition = IR3_COND_LT;
748 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
749
750 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
751 }
752
753 for (int i = 0; i < intr->num_components; i++) {
754 struct ir3_instruction *load =
755 ir3_LDG(b, addr, 0, create_immed(b, 1), 0);
756 load->cat6.type = TYPE_U32;
757 load->cat6.src_offset = off + i * 4; /* byte offset */
758 dst[i] = load;
759 }
760 }
761
762 /* src[] = { block_index } */
763 static void
764 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
765 struct ir3_instruction **dst)
766 {
767 /* SSBO size stored as a const starting at ssbo_sizes: */
768 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
769 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
770 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
771 const_state->ssbo_size.off[blk_idx];
772
773 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
774
775 dst[0] = create_uniform(ctx->block, idx);
776 }
777
778 /* src[] = { offset }. const_index[] = { base } */
779 static void
780 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
781 struct ir3_instruction **dst)
782 {
783 struct ir3_block *b = ctx->block;
784 struct ir3_instruction *ldl, *offset;
785 unsigned base;
786
787 offset = ir3_get_src(ctx, &intr->src[0])[0];
788 base = nir_intrinsic_base(intr);
789
790 ldl = ir3_LDL(b, offset, 0, create_immed(b, intr->num_components), 0);
791 ldl->cat6.src_offset = base;
792 ldl->cat6.type = utype_dst(intr->dest);
793 ldl->regs[0]->wrmask = MASK(intr->num_components);
794
795 ldl->barrier_class = IR3_BARRIER_SHARED_R;
796 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
797
798 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
799 }
800
801 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
802 static void
803 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
804 {
805 struct ir3_block *b = ctx->block;
806 struct ir3_instruction *stl, *offset;
807 struct ir3_instruction * const *value;
808 unsigned base, wrmask;
809
810 value = ir3_get_src(ctx, &intr->src[0]);
811 offset = ir3_get_src(ctx, &intr->src[1])[0];
812
813 base = nir_intrinsic_base(intr);
814 wrmask = nir_intrinsic_write_mask(intr);
815
816 /* Combine groups of consecutive enabled channels in one write
817 * message. We use ffs to find the first enabled channel and then ffs on
818 * the bit-inverse, down-shifted writemask to determine the length of
819 * the block of enabled bits.
820 *
821 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
822 */
823 while (wrmask) {
824 unsigned first_component = ffs(wrmask) - 1;
825 unsigned length = ffs(~(wrmask >> first_component)) - 1;
826
827 stl = ir3_STL(b, offset, 0,
828 ir3_create_collect(ctx, &value[first_component], length), 0,
829 create_immed(b, length), 0);
830 stl->cat6.dst_offset = first_component + base;
831 stl->cat6.type = utype_src(intr->src[0]);
832 stl->barrier_class = IR3_BARRIER_SHARED_W;
833 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
834
835 array_insert(b, b->keeps, stl);
836
837 /* Clear the bits in the writemask that we just wrote, then try
838 * again to see if more channels are left.
839 */
840 wrmask &= (15 << (first_component + length));
841 }
842 }
843
844 /*
845 * CS shared variable atomic intrinsics
846 *
847 * All of the shared variable atomic memory operations read a value from
848 * memory, compute a new value using one of the operations below, write the
849 * new value to memory, and return the original value read.
850 *
851 * All operations take 2 sources except CompSwap that takes 3. These
852 * sources represent:
853 *
854 * 0: The offset into the shared variable storage region that the atomic
855 * operation will operate on.
856 * 1: The data parameter to the atomic function (i.e. the value to add
857 * in shared_atomic_add, etc).
858 * 2: For CompSwap only: the second data parameter.
859 */
860 static struct ir3_instruction *
861 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
862 {
863 struct ir3_block *b = ctx->block;
864 struct ir3_instruction *atomic, *src0, *src1;
865 type_t type = TYPE_U32;
866
867 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
868 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
869
870 switch (intr->intrinsic) {
871 case nir_intrinsic_shared_atomic_add:
872 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
873 break;
874 case nir_intrinsic_shared_atomic_imin:
875 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
876 type = TYPE_S32;
877 break;
878 case nir_intrinsic_shared_atomic_umin:
879 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
880 break;
881 case nir_intrinsic_shared_atomic_imax:
882 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
883 type = TYPE_S32;
884 break;
885 case nir_intrinsic_shared_atomic_umax:
886 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
887 break;
888 case nir_intrinsic_shared_atomic_and:
889 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
890 break;
891 case nir_intrinsic_shared_atomic_or:
892 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
893 break;
894 case nir_intrinsic_shared_atomic_xor:
895 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
896 break;
897 case nir_intrinsic_shared_atomic_exchange:
898 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
899 break;
900 case nir_intrinsic_shared_atomic_comp_swap:
901 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
902 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
903 ir3_get_src(ctx, &intr->src[2])[0],
904 src1,
905 }, 2);
906 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
907 break;
908 default:
909 unreachable("boo");
910 }
911
912 atomic->cat6.iim_val = 1;
913 atomic->cat6.d = 1;
914 atomic->cat6.type = type;
915 atomic->barrier_class = IR3_BARRIER_SHARED_W;
916 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
917
918 /* even if nothing consume the result, we can't DCE the instruction: */
919 array_insert(b, b->keeps, atomic);
920
921 return atomic;
922 }
923
924 /* TODO handle actual indirect/dynamic case.. which is going to be weird
925 * to handle with the image_mapping table..
926 */
927 static struct ir3_instruction *
928 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
929 {
930 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
931 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
932 struct ir3_instruction *texture, *sampler;
933
934 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
935 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
936
937 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
938 sampler,
939 texture,
940 }, 2);
941 }
942
943 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
944 static void
945 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
946 struct ir3_instruction **dst)
947 {
948 struct ir3_block *b = ctx->block;
949 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
950 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
951 struct ir3_instruction *sam;
952 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
953 struct ir3_instruction *coords[4];
954 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
955 type_t type = ir3_get_image_type(var);
956
957 /* hmm, this seems a bit odd, but it is what blob does and (at least
958 * a5xx) just faults on bogus addresses otherwise:
959 */
960 if (flags & IR3_INSTR_3D) {
961 flags &= ~IR3_INSTR_3D;
962 flags |= IR3_INSTR_A;
963 }
964
965 for (unsigned i = 0; i < ncoords; i++)
966 coords[i] = src0[i];
967
968 if (ncoords == 1)
969 coords[ncoords++] = create_immed(b, 0);
970
971 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
972 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
973
974 sam->barrier_class = IR3_BARRIER_IMAGE_R;
975 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
976
977 ir3_split_dest(b, dst, sam, 0, 4);
978 }
979
980 static void
981 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
982 struct ir3_instruction **dst)
983 {
984 struct ir3_block *b = ctx->block;
985 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
986 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
987 struct ir3_instruction *sam, *lod;
988 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
989
990 lod = create_immed(b, 0);
991 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
992 samp_tex, lod, NULL);
993
994 /* Array size actually ends up in .w rather than .z. This doesn't
995 * matter for miplevel 0, but for higher mips the value in z is
996 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
997 * returned, which means that we have to add 1 to it for arrays for
998 * a3xx.
999 *
1000 * Note use a temporary dst and then copy, since the size of the dst
1001 * array that is passed in is based on nir's understanding of the
1002 * result size, not the hardware's
1003 */
1004 struct ir3_instruction *tmp[4];
1005
1006 ir3_split_dest(b, tmp, sam, 0, 4);
1007
1008 /* get_size instruction returns size in bytes instead of texels
1009 * for imageBuffer, so we need to divide it by the pixel size
1010 * of the image format.
1011 *
1012 * TODO: This is at least true on a5xx. Check other gens.
1013 */
1014 enum glsl_sampler_dim dim =
1015 glsl_get_sampler_dim(glsl_without_array(var->type));
1016 if (dim == GLSL_SAMPLER_DIM_BUF) {
1017 /* Since all the possible values the divisor can take are
1018 * power-of-two (4, 8, or 16), the division is implemented
1019 * as a shift-right.
1020 * During shader setup, the log2 of the image format's
1021 * bytes-per-pixel should have been emitted in 2nd slot of
1022 * image_dims. See ir3_shader::emit_image_dims().
1023 */
1024 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1025 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1026 const_state->image_dims.off[var->data.driver_location];
1027 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1028
1029 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1030 }
1031
1032 for (unsigned i = 0; i < ncoords; i++)
1033 dst[i] = tmp[i];
1034
1035 if (flags & IR3_INSTR_A) {
1036 if (ctx->compiler->levels_add_one) {
1037 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1038 } else {
1039 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1040 }
1041 }
1042 }
1043
1044 static void
1045 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1046 {
1047 struct ir3_block *b = ctx->block;
1048 struct ir3_instruction *barrier;
1049
1050 switch (intr->intrinsic) {
1051 case nir_intrinsic_barrier:
1052 barrier = ir3_BAR(b);
1053 barrier->cat7.g = true;
1054 barrier->cat7.l = true;
1055 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1056 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1057 break;
1058 case nir_intrinsic_memory_barrier:
1059 barrier = ir3_FENCE(b);
1060 barrier->cat7.g = true;
1061 barrier->cat7.r = true;
1062 barrier->cat7.w = true;
1063 barrier->cat7.l = true;
1064 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1065 IR3_BARRIER_BUFFER_W;
1066 barrier->barrier_conflict =
1067 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1068 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1069 break;
1070 case nir_intrinsic_memory_barrier_atomic_counter:
1071 case nir_intrinsic_memory_barrier_buffer:
1072 barrier = ir3_FENCE(b);
1073 barrier->cat7.g = true;
1074 barrier->cat7.r = true;
1075 barrier->cat7.w = true;
1076 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1077 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1078 IR3_BARRIER_BUFFER_W;
1079 break;
1080 case nir_intrinsic_memory_barrier_image:
1081 // TODO double check if this should have .g set
1082 barrier = ir3_FENCE(b);
1083 barrier->cat7.g = true;
1084 barrier->cat7.r = true;
1085 barrier->cat7.w = true;
1086 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1087 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1088 IR3_BARRIER_IMAGE_W;
1089 break;
1090 case nir_intrinsic_memory_barrier_shared:
1091 barrier = ir3_FENCE(b);
1092 barrier->cat7.g = true;
1093 barrier->cat7.l = true;
1094 barrier->cat7.r = true;
1095 barrier->cat7.w = true;
1096 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1097 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1098 IR3_BARRIER_SHARED_W;
1099 break;
1100 case nir_intrinsic_group_memory_barrier:
1101 barrier = ir3_FENCE(b);
1102 barrier->cat7.g = true;
1103 barrier->cat7.l = true;
1104 barrier->cat7.r = true;
1105 barrier->cat7.w = true;
1106 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1107 IR3_BARRIER_IMAGE_W |
1108 IR3_BARRIER_BUFFER_W;
1109 barrier->barrier_conflict =
1110 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1111 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1112 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1113 break;
1114 default:
1115 unreachable("boo");
1116 }
1117
1118 /* make sure barrier doesn't get DCE'd */
1119 array_insert(b, b->keeps, barrier);
1120 }
1121
1122 static void add_sysval_input_compmask(struct ir3_context *ctx,
1123 gl_system_value slot, unsigned compmask,
1124 struct ir3_instruction *instr)
1125 {
1126 struct ir3_shader_variant *so = ctx->so;
1127 unsigned r = regid(so->inputs_count, 0);
1128 unsigned n = so->inputs_count++;
1129
1130 so->inputs[n].sysval = true;
1131 so->inputs[n].slot = slot;
1132 so->inputs[n].compmask = compmask;
1133 so->inputs[n].regid = r;
1134 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1135 so->total_in++;
1136
1137 ctx->ir->ninputs = MAX2(ctx->ir->ninputs, r + 1);
1138 ctx->ir->inputs[r] = instr;
1139 }
1140
1141 static void add_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1142 struct ir3_instruction *instr)
1143 {
1144 add_sysval_input_compmask(ctx, slot, 0x1, instr);
1145 }
1146
1147 static struct ir3_instruction *
1148 get_barycentric_centroid(struct ir3_context *ctx)
1149 {
1150 if (!ctx->ij_centroid) {
1151 struct ir3_instruction *xy[2];
1152 struct ir3_instruction *ij;
1153
1154 ij = create_input_compmask(ctx, 0, 0x3);
1155 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1156
1157 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1158
1159 add_sysval_input_compmask(ctx,
1160 SYSTEM_VALUE_BARYCENTRIC_CENTROID,
1161 0x3, ij);
1162 }
1163
1164 return ctx->ij_centroid;
1165 }
1166
1167 static struct ir3_instruction *
1168 get_barycentric_sample(struct ir3_context *ctx)
1169 {
1170 if (!ctx->ij_sample) {
1171 struct ir3_instruction *xy[2];
1172 struct ir3_instruction *ij;
1173
1174 ij = create_input_compmask(ctx, 0, 0x3);
1175 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1176
1177 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1178
1179 add_sysval_input_compmask(ctx,
1180 SYSTEM_VALUE_BARYCENTRIC_SAMPLE,
1181 0x3, ij);
1182 }
1183
1184 return ctx->ij_sample;
1185 }
1186
1187 static struct ir3_instruction *
1188 get_barycentric_pixel(struct ir3_context *ctx)
1189 {
1190 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1191 * this to create ij_pixel only on demand:
1192 */
1193 return ctx->ij_pixel;
1194 }
1195
1196 static struct ir3_instruction *
1197 get_frag_coord(struct ir3_context *ctx)
1198 {
1199 if (!ctx->frag_coord) {
1200 struct ir3_block *b = ctx->block;
1201 struct ir3_instruction *xyzw[4];
1202 struct ir3_instruction *hw_frag_coord;
1203
1204 hw_frag_coord = create_input_compmask(ctx, 0, 0xf);
1205 ir3_split_dest(ctx->block, xyzw, hw_frag_coord, 0, 4);
1206
1207 /* for frag_coord.xy, we get unsigned values.. we need
1208 * to subtract (integer) 8 and divide by 16 (right-
1209 * shift by 4) then convert to float:
1210 *
1211 * sub.s tmp, src, 8
1212 * shr.b tmp, tmp, 4
1213 * mov.u32f32 dst, tmp
1214 *
1215 */
1216 for (int i = 0; i < 2; i++) {
1217 xyzw[i] = ir3_SUB_S(b, xyzw[i], 0,
1218 create_immed(b, 8), 0);
1219 xyzw[i] = ir3_SHR_B(b, xyzw[i], 0,
1220 create_immed(b, 4), 0);
1221 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1222 }
1223
1224 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1225
1226 add_sysval_input_compmask(ctx,
1227 SYSTEM_VALUE_FRAG_COORD,
1228 0xf, hw_frag_coord);
1229
1230 ctx->so->frag_coord = true;
1231 }
1232
1233 return ctx->frag_coord;
1234 }
1235
1236 static void
1237 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1238 {
1239 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1240 struct ir3_instruction **dst;
1241 struct ir3_instruction * const *src;
1242 struct ir3_block *b = ctx->block;
1243 int idx, comp;
1244
1245 if (info->has_dest) {
1246 unsigned n = nir_intrinsic_dest_components(intr);
1247 dst = ir3_get_dst(ctx, &intr->dest, n);
1248 } else {
1249 dst = NULL;
1250 }
1251
1252 switch (intr->intrinsic) {
1253 case nir_intrinsic_load_uniform:
1254 idx = nir_intrinsic_base(intr);
1255 if (nir_src_is_const(intr->src[0])) {
1256 idx += nir_src_as_uint(intr->src[0]);
1257 for (int i = 0; i < intr->num_components; i++) {
1258 dst[i] = create_uniform_typed(b, idx + i,
1259 nir_dest_bit_size(intr->dest) < 32 ? TYPE_F16 : TYPE_F32);
1260 }
1261 } else {
1262 src = ir3_get_src(ctx, &intr->src[0]);
1263 for (int i = 0; i < intr->num_components; i++) {
1264 dst[i] = create_uniform_indirect(b, idx + i,
1265 ir3_get_addr(ctx, src[0], 1));
1266 }
1267 /* NOTE: if relative addressing is used, we set
1268 * constlen in the compiler (to worst-case value)
1269 * since we don't know in the assembler what the max
1270 * addr reg value can be:
1271 */
1272 ctx->so->constlen = MAX2(ctx->so->constlen,
1273 ctx->so->shader->ubo_state.size / 16);
1274 }
1275 break;
1276 case nir_intrinsic_load_ubo:
1277 emit_intrinsic_load_ubo(ctx, intr, dst);
1278 break;
1279 case nir_intrinsic_load_frag_coord:
1280 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1281 break;
1282 case nir_intrinsic_load_sample_pos_from_id: {
1283 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1284 * but that doesn't seem necessary.
1285 */
1286 struct ir3_instruction *offset =
1287 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1288 offset->regs[0]->wrmask = 0x3;
1289 offset->cat5.type = TYPE_F32;
1290
1291 ir3_split_dest(b, dst, offset, 0, 2);
1292
1293 break;
1294 }
1295 case nir_intrinsic_load_size_ir3:
1296 if (!ctx->ij_size) {
1297 ctx->ij_size = create_input(ctx, 0);
1298
1299 add_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SIZE,
1300 ctx->ij_size);
1301 }
1302 dst[0] = ctx->ij_size;
1303 break;
1304 case nir_intrinsic_load_barycentric_centroid:
1305 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1306 break;
1307 case nir_intrinsic_load_barycentric_sample:
1308 if (ctx->so->key.msaa) {
1309 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1310 } else {
1311 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1312 }
1313 break;
1314 case nir_intrinsic_load_barycentric_pixel:
1315 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1316 break;
1317 case nir_intrinsic_load_interpolated_input:
1318 idx = nir_intrinsic_base(intr);
1319 comp = nir_intrinsic_component(intr);
1320 src = ir3_get_src(ctx, &intr->src[0]);
1321 if (nir_src_is_const(intr->src[1])) {
1322 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1323 idx += nir_src_as_uint(intr->src[1]);
1324 for (int i = 0; i < intr->num_components; i++) {
1325 unsigned inloc = idx * 4 + i + comp;
1326 if (ctx->so->inputs[idx].bary &&
1327 !ctx->so->inputs[idx].use_ldlv) {
1328 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1329 } else {
1330 /* for non-varyings use the pre-setup input, since
1331 * that is easier than mapping things back to a
1332 * nir_variable to figure out what it is.
1333 */
1334 dst[i] = ctx->ir->inputs[inloc];
1335 }
1336 }
1337 } else {
1338 ir3_context_error(ctx, "unhandled");
1339 }
1340 break;
1341 case nir_intrinsic_load_input:
1342 idx = nir_intrinsic_base(intr);
1343 comp = nir_intrinsic_component(intr);
1344 if (nir_src_is_const(intr->src[0])) {
1345 idx += nir_src_as_uint(intr->src[0]);
1346 for (int i = 0; i < intr->num_components; i++) {
1347 unsigned n = idx * 4 + i + comp;
1348 dst[i] = ctx->ir->inputs[n];
1349 compile_assert(ctx, ctx->ir->inputs[n]);
1350 }
1351 } else {
1352 src = ir3_get_src(ctx, &intr->src[0]);
1353 struct ir3_instruction *collect =
1354 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ir->ninputs);
1355 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1356 for (int i = 0; i < intr->num_components; i++) {
1357 unsigned n = idx * 4 + i + comp;
1358 dst[i] = create_indirect_load(ctx, ctx->ir->ninputs,
1359 n, addr, collect);
1360 }
1361 }
1362 break;
1363 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1364 * pass and replaced by an ir3-specifc version that adds the
1365 * dword-offset in the last source.
1366 */
1367 case nir_intrinsic_load_ssbo_ir3:
1368 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1369 break;
1370 case nir_intrinsic_store_ssbo_ir3:
1371 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1372 !ctx->s->info.fs.early_fragment_tests)
1373 ctx->so->no_earlyz = true;
1374 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1375 break;
1376 case nir_intrinsic_get_buffer_size:
1377 emit_intrinsic_ssbo_size(ctx, intr, dst);
1378 break;
1379 case nir_intrinsic_ssbo_atomic_add_ir3:
1380 case nir_intrinsic_ssbo_atomic_imin_ir3:
1381 case nir_intrinsic_ssbo_atomic_umin_ir3:
1382 case nir_intrinsic_ssbo_atomic_imax_ir3:
1383 case nir_intrinsic_ssbo_atomic_umax_ir3:
1384 case nir_intrinsic_ssbo_atomic_and_ir3:
1385 case nir_intrinsic_ssbo_atomic_or_ir3:
1386 case nir_intrinsic_ssbo_atomic_xor_ir3:
1387 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1388 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1389 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1390 !ctx->s->info.fs.early_fragment_tests)
1391 ctx->so->no_earlyz = true;
1392 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1393 break;
1394 case nir_intrinsic_load_shared:
1395 emit_intrinsic_load_shared(ctx, intr, dst);
1396 break;
1397 case nir_intrinsic_store_shared:
1398 emit_intrinsic_store_shared(ctx, intr);
1399 break;
1400 case nir_intrinsic_shared_atomic_add:
1401 case nir_intrinsic_shared_atomic_imin:
1402 case nir_intrinsic_shared_atomic_umin:
1403 case nir_intrinsic_shared_atomic_imax:
1404 case nir_intrinsic_shared_atomic_umax:
1405 case nir_intrinsic_shared_atomic_and:
1406 case nir_intrinsic_shared_atomic_or:
1407 case nir_intrinsic_shared_atomic_xor:
1408 case nir_intrinsic_shared_atomic_exchange:
1409 case nir_intrinsic_shared_atomic_comp_swap:
1410 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1411 break;
1412 case nir_intrinsic_image_deref_load:
1413 emit_intrinsic_load_image(ctx, intr, dst);
1414 break;
1415 case nir_intrinsic_image_deref_store:
1416 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1417 !ctx->s->info.fs.early_fragment_tests)
1418 ctx->so->no_earlyz = true;
1419 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1420 break;
1421 case nir_intrinsic_image_deref_size:
1422 emit_intrinsic_image_size(ctx, intr, dst);
1423 break;
1424 case nir_intrinsic_image_deref_atomic_add:
1425 case nir_intrinsic_image_deref_atomic_imin:
1426 case nir_intrinsic_image_deref_atomic_umin:
1427 case nir_intrinsic_image_deref_atomic_imax:
1428 case nir_intrinsic_image_deref_atomic_umax:
1429 case nir_intrinsic_image_deref_atomic_and:
1430 case nir_intrinsic_image_deref_atomic_or:
1431 case nir_intrinsic_image_deref_atomic_xor:
1432 case nir_intrinsic_image_deref_atomic_exchange:
1433 case nir_intrinsic_image_deref_atomic_comp_swap:
1434 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1435 !ctx->s->info.fs.early_fragment_tests)
1436 ctx->so->no_earlyz = true;
1437 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1438 break;
1439 case nir_intrinsic_barrier:
1440 case nir_intrinsic_memory_barrier:
1441 case nir_intrinsic_group_memory_barrier:
1442 case nir_intrinsic_memory_barrier_atomic_counter:
1443 case nir_intrinsic_memory_barrier_buffer:
1444 case nir_intrinsic_memory_barrier_image:
1445 case nir_intrinsic_memory_barrier_shared:
1446 emit_intrinsic_barrier(ctx, intr);
1447 /* note that blk ptr no longer valid, make that obvious: */
1448 b = NULL;
1449 break;
1450 case nir_intrinsic_store_output:
1451 idx = nir_intrinsic_base(intr);
1452 comp = nir_intrinsic_component(intr);
1453 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1454 idx += nir_src_as_uint(intr->src[1]);
1455
1456 src = ir3_get_src(ctx, &intr->src[0]);
1457 for (int i = 0; i < intr->num_components; i++) {
1458 unsigned n = idx * 4 + i + comp;
1459 ctx->ir->outputs[n] = src[i];
1460 }
1461 break;
1462 case nir_intrinsic_load_base_vertex:
1463 case nir_intrinsic_load_first_vertex:
1464 if (!ctx->basevertex) {
1465 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1466 add_sysval_input(ctx, SYSTEM_VALUE_FIRST_VERTEX, ctx->basevertex);
1467 }
1468 dst[0] = ctx->basevertex;
1469 break;
1470 case nir_intrinsic_load_vertex_id_zero_base:
1471 case nir_intrinsic_load_vertex_id:
1472 if (!ctx->vertex_id) {
1473 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1474 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1475 ctx->vertex_id = create_input(ctx, 0);
1476 add_sysval_input(ctx, sv, ctx->vertex_id);
1477 }
1478 dst[0] = ctx->vertex_id;
1479 break;
1480 case nir_intrinsic_load_instance_id:
1481 if (!ctx->instance_id) {
1482 ctx->instance_id = create_input(ctx, 0);
1483 add_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID,
1484 ctx->instance_id);
1485 }
1486 dst[0] = ctx->instance_id;
1487 break;
1488 case nir_intrinsic_load_sample_id:
1489 ctx->so->per_samp = true;
1490 /* fall-thru */
1491 case nir_intrinsic_load_sample_id_no_per_sample:
1492 if (!ctx->samp_id) {
1493 ctx->samp_id = create_input(ctx, 0);
1494 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1495 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID,
1496 ctx->samp_id);
1497 }
1498 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1499 break;
1500 case nir_intrinsic_load_sample_mask_in:
1501 if (!ctx->samp_mask_in) {
1502 ctx->samp_mask_in = create_input(ctx, 0);
1503 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN,
1504 ctx->samp_mask_in);
1505 }
1506 dst[0] = ctx->samp_mask_in;
1507 break;
1508 case nir_intrinsic_load_user_clip_plane:
1509 idx = nir_intrinsic_ucp_id(intr);
1510 for (int i = 0; i < intr->num_components; i++) {
1511 unsigned n = idx * 4 + i;
1512 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1513 }
1514 break;
1515 case nir_intrinsic_load_front_face:
1516 if (!ctx->frag_face) {
1517 ctx->so->frag_face = true;
1518 ctx->frag_face = create_input(ctx, 0);
1519 add_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, ctx->frag_face);
1520 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1521 }
1522 /* for fragface, we get -1 for back and 0 for front. However this is
1523 * the inverse of what nir expects (where ~0 is true).
1524 */
1525 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1526 dst[0] = ir3_NOT_B(b, dst[0], 0);
1527 break;
1528 case nir_intrinsic_load_local_invocation_id:
1529 if (!ctx->local_invocation_id) {
1530 ctx->local_invocation_id = create_input_compmask(ctx, 0, 0x7);
1531 add_sysval_input_compmask(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID,
1532 0x7, ctx->local_invocation_id);
1533 }
1534 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1535 break;
1536 case nir_intrinsic_load_work_group_id:
1537 if (!ctx->work_group_id) {
1538 ctx->work_group_id = create_input_compmask(ctx, 0, 0x7);
1539 add_sysval_input_compmask(ctx, SYSTEM_VALUE_WORK_GROUP_ID,
1540 0x7, ctx->work_group_id);
1541 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1542 }
1543 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1544 break;
1545 case nir_intrinsic_load_num_work_groups:
1546 for (int i = 0; i < intr->num_components; i++) {
1547 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1548 }
1549 break;
1550 case nir_intrinsic_load_local_group_size:
1551 for (int i = 0; i < intr->num_components; i++) {
1552 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1553 }
1554 break;
1555 case nir_intrinsic_discard_if:
1556 case nir_intrinsic_discard: {
1557 struct ir3_instruction *cond, *kill;
1558
1559 if (intr->intrinsic == nir_intrinsic_discard_if) {
1560 /* conditional discard: */
1561 src = ir3_get_src(ctx, &intr->src[0]);
1562 cond = ir3_b2n(b, src[0]);
1563 } else {
1564 /* unconditional discard: */
1565 cond = create_immed(b, 1);
1566 }
1567
1568 /* NOTE: only cmps.*.* can write p0.x: */
1569 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1570 cond->cat2.condition = IR3_COND_NE;
1571
1572 /* condition always goes in predicate register: */
1573 cond->regs[0]->num = regid(REG_P0, 0);
1574
1575 kill = ir3_KILL(b, cond, 0);
1576 array_insert(ctx->ir, ctx->ir->predicates, kill);
1577
1578 array_insert(b, b->keeps, kill);
1579 ctx->so->no_earlyz = true;
1580
1581 break;
1582 }
1583 default:
1584 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1585 nir_intrinsic_infos[intr->intrinsic].name);
1586 break;
1587 }
1588
1589 if (info->has_dest)
1590 ir3_put_dst(ctx, &intr->dest);
1591 }
1592
1593 static void
1594 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1595 {
1596 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1597 instr->def.num_components);
1598
1599 if (instr->def.bit_size < 32) {
1600 for (int i = 0; i < instr->def.num_components; i++)
1601 dst[i] = create_immed_typed(ctx->block,
1602 instr->value[i].u16,
1603 TYPE_U16);
1604 } else {
1605 for (int i = 0; i < instr->def.num_components; i++)
1606 dst[i] = create_immed_typed(ctx->block,
1607 instr->value[i].u32,
1608 TYPE_U32);
1609 }
1610
1611 }
1612
1613 static void
1614 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1615 {
1616 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1617 undef->def.num_components);
1618 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1619
1620 /* backend doesn't want undefined instructions, so just plug
1621 * in 0.0..
1622 */
1623 for (int i = 0; i < undef->def.num_components; i++)
1624 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1625 }
1626
1627 /*
1628 * texture fetch/sample instructions:
1629 */
1630
1631 static void
1632 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1633 {
1634 unsigned coords, flags = 0;
1635
1636 /* note: would use tex->coord_components.. except txs.. also,
1637 * since array index goes after shadow ref, we don't want to
1638 * count it:
1639 */
1640 switch (tex->sampler_dim) {
1641 case GLSL_SAMPLER_DIM_1D:
1642 case GLSL_SAMPLER_DIM_BUF:
1643 coords = 1;
1644 break;
1645 case GLSL_SAMPLER_DIM_2D:
1646 case GLSL_SAMPLER_DIM_RECT:
1647 case GLSL_SAMPLER_DIM_EXTERNAL:
1648 case GLSL_SAMPLER_DIM_MS:
1649 coords = 2;
1650 break;
1651 case GLSL_SAMPLER_DIM_3D:
1652 case GLSL_SAMPLER_DIM_CUBE:
1653 coords = 3;
1654 flags |= IR3_INSTR_3D;
1655 break;
1656 default:
1657 unreachable("bad sampler_dim");
1658 }
1659
1660 if (tex->is_shadow && tex->op != nir_texop_lod)
1661 flags |= IR3_INSTR_S;
1662
1663 if (tex->is_array && tex->op != nir_texop_lod)
1664 flags |= IR3_INSTR_A;
1665
1666 *flagsp = flags;
1667 *coordsp = coords;
1668 }
1669
1670 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1671 * or immediate (in which case it will get lowered later to a non .s2en
1672 * version of the tex instruction which encode tex/samp as immediates:
1673 */
1674 static struct ir3_instruction *
1675 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1676 {
1677 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1678 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1679 struct ir3_instruction *texture, *sampler;
1680
1681 if (texture_idx >= 0) {
1682 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1683 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1684 } else {
1685 /* TODO what to do for dynamic case? I guess we only need the
1686 * max index for astc srgb workaround so maybe not a problem
1687 * to worry about if we don't enable indirect samplers for
1688 * a4xx?
1689 */
1690 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1691 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1692 }
1693
1694 if (sampler_idx >= 0) {
1695 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1696 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1697 } else {
1698 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1699 }
1700
1701 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1702 sampler,
1703 texture,
1704 }, 2);
1705 }
1706
1707 static void
1708 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1709 {
1710 struct ir3_block *b = ctx->block;
1711 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1712 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1713 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1714 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1715 unsigned i, coords, flags, ncomp;
1716 unsigned nsrc0 = 0, nsrc1 = 0;
1717 type_t type;
1718 opc_t opc = 0;
1719
1720 ncomp = nir_dest_num_components(tex->dest);
1721
1722 coord = off = ddx = ddy = NULL;
1723 lod = proj = compare = sample_index = NULL;
1724
1725 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1726
1727 for (unsigned i = 0; i < tex->num_srcs; i++) {
1728 switch (tex->src[i].src_type) {
1729 case nir_tex_src_coord:
1730 coord = ir3_get_src(ctx, &tex->src[i].src);
1731 break;
1732 case nir_tex_src_bias:
1733 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1734 has_bias = true;
1735 break;
1736 case nir_tex_src_lod:
1737 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1738 has_lod = true;
1739 break;
1740 case nir_tex_src_comparator: /* shadow comparator */
1741 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1742 break;
1743 case nir_tex_src_projector:
1744 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1745 has_proj = true;
1746 break;
1747 case nir_tex_src_offset:
1748 off = ir3_get_src(ctx, &tex->src[i].src);
1749 has_off = true;
1750 break;
1751 case nir_tex_src_ddx:
1752 ddx = ir3_get_src(ctx, &tex->src[i].src);
1753 break;
1754 case nir_tex_src_ddy:
1755 ddy = ir3_get_src(ctx, &tex->src[i].src);
1756 break;
1757 case nir_tex_src_ms_index:
1758 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
1759 break;
1760 case nir_tex_src_texture_offset:
1761 case nir_tex_src_sampler_offset:
1762 /* handled in get_tex_samp_src() */
1763 break;
1764 default:
1765 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
1766 tex->src[i].src_type);
1767 return;
1768 }
1769 }
1770
1771 switch (tex->op) {
1772 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
1773 case nir_texop_txb: opc = OPC_SAMB; break;
1774 case nir_texop_txl: opc = OPC_SAML; break;
1775 case nir_texop_txd: opc = OPC_SAMGQ; break;
1776 case nir_texop_txf: opc = OPC_ISAML; break;
1777 case nir_texop_lod: opc = OPC_GETLOD; break;
1778 case nir_texop_tg4:
1779 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1780 * what blob does, seems gather is broken?), and a3xx did
1781 * not support it (but probably could also emulate).
1782 */
1783 switch (tex->component) {
1784 case 0: opc = OPC_GATHER4R; break;
1785 case 1: opc = OPC_GATHER4G; break;
1786 case 2: opc = OPC_GATHER4B; break;
1787 case 3: opc = OPC_GATHER4A; break;
1788 }
1789 break;
1790 case nir_texop_txf_ms_fb:
1791 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
1792 default:
1793 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
1794 return;
1795 }
1796
1797 tex_info(tex, &flags, &coords);
1798
1799 /*
1800 * lay out the first argument in the proper order:
1801 * - actual coordinates first
1802 * - shadow reference
1803 * - array index
1804 * - projection w
1805 * - starting at offset 4, dpdx.xy, dpdy.xy
1806 *
1807 * bias/lod go into the second arg
1808 */
1809
1810 /* insert tex coords: */
1811 for (i = 0; i < coords; i++)
1812 src0[i] = coord[i];
1813
1814 nsrc0 = i;
1815
1816 /* scale up integer coords for TXF based on the LOD */
1817 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
1818 assert(has_lod);
1819 for (i = 0; i < coords; i++)
1820 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
1821 }
1822
1823 if (coords == 1) {
1824 /* hw doesn't do 1d, so we treat it as 2d with
1825 * height of 1, and patch up the y coord.
1826 */
1827 if (is_isam(opc)) {
1828 src0[nsrc0++] = create_immed(b, 0);
1829 } else {
1830 src0[nsrc0++] = create_immed(b, fui(0.5));
1831 }
1832 }
1833
1834 if (tex->is_shadow && tex->op != nir_texop_lod)
1835 src0[nsrc0++] = compare;
1836
1837 if (tex->is_array && tex->op != nir_texop_lod) {
1838 struct ir3_instruction *idx = coord[coords];
1839
1840 /* the array coord for cube arrays needs 0.5 added to it */
1841 if (ctx->compiler->array_index_add_half && !is_isam(opc))
1842 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
1843
1844 src0[nsrc0++] = idx;
1845 }
1846
1847 if (has_proj) {
1848 src0[nsrc0++] = proj;
1849 flags |= IR3_INSTR_P;
1850 }
1851
1852 /* pad to 4, then ddx/ddy: */
1853 if (tex->op == nir_texop_txd) {
1854 while (nsrc0 < 4)
1855 src0[nsrc0++] = create_immed(b, fui(0.0));
1856 for (i = 0; i < coords; i++)
1857 src0[nsrc0++] = ddx[i];
1858 if (coords < 2)
1859 src0[nsrc0++] = create_immed(b, fui(0.0));
1860 for (i = 0; i < coords; i++)
1861 src0[nsrc0++] = ddy[i];
1862 if (coords < 2)
1863 src0[nsrc0++] = create_immed(b, fui(0.0));
1864 }
1865
1866 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
1867 * with scaled x coord according to requested sample:
1868 */
1869 if (opc == OPC_ISAMM) {
1870 if (ctx->compiler->txf_ms_with_isaml) {
1871 /* the samples are laid out in x dimension as
1872 * 0 1 2 3
1873 * x_ms = (x << ms) + sample_index;
1874 */
1875 struct ir3_instruction *ms;
1876 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
1877
1878 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
1879 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
1880
1881 opc = OPC_ISAML;
1882 } else {
1883 src0[nsrc0++] = sample_index;
1884 }
1885 }
1886
1887 /*
1888 * second argument (if applicable):
1889 * - offsets
1890 * - lod
1891 * - bias
1892 */
1893 if (has_off | has_lod | has_bias) {
1894 if (has_off) {
1895 unsigned off_coords = coords;
1896 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
1897 off_coords--;
1898 for (i = 0; i < off_coords; i++)
1899 src1[nsrc1++] = off[i];
1900 if (off_coords < 2)
1901 src1[nsrc1++] = create_immed(b, fui(0.0));
1902 flags |= IR3_INSTR_O;
1903 }
1904
1905 if (has_lod | has_bias)
1906 src1[nsrc1++] = lod;
1907 }
1908
1909 switch (tex->dest_type) {
1910 case nir_type_invalid:
1911 case nir_type_float:
1912 type = TYPE_F32;
1913 break;
1914 case nir_type_int:
1915 type = TYPE_S32;
1916 break;
1917 case nir_type_uint:
1918 case nir_type_bool:
1919 type = TYPE_U32;
1920 break;
1921 default:
1922 unreachable("bad dest_type");
1923 }
1924
1925 if (opc == OPC_GETLOD)
1926 type = TYPE_S32;
1927
1928 struct ir3_instruction *samp_tex;
1929
1930 if (tex->op == nir_texop_txf_ms_fb) {
1931 /* only expect a single txf_ms_fb per shader: */
1932 compile_assert(ctx, !ctx->so->fb_read);
1933 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
1934
1935 ctx->so->fb_read = true;
1936 samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1937 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
1938 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
1939 }, 2);
1940
1941 ctx->so->num_samp++;
1942 } else {
1943 samp_tex = get_tex_samp_tex_src(ctx, tex);
1944 }
1945
1946 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
1947 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
1948
1949 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
1950 samp_tex, col0, col1);
1951
1952 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
1953 /* only need first 3 components: */
1954 sam->regs[0]->wrmask = 0x7;
1955 ir3_split_dest(b, dst, sam, 0, 3);
1956
1957 /* we need to sample the alpha separately with a non-ASTC
1958 * texture state:
1959 */
1960 sam = ir3_SAM(b, opc, type, 0b1000, flags,
1961 samp_tex, col0, col1);
1962
1963 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
1964
1965 /* fixup .w component: */
1966 ir3_split_dest(b, &dst[3], sam, 3, 1);
1967 } else {
1968 /* normal (non-workaround) case: */
1969 ir3_split_dest(b, dst, sam, 0, ncomp);
1970 }
1971
1972 /* GETLOD returns results in 4.8 fixed point */
1973 if (opc == OPC_GETLOD) {
1974 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
1975
1976 compile_assert(ctx, tex->dest_type == nir_type_float);
1977 for (i = 0; i < 2; i++) {
1978 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
1979 factor, 0);
1980 }
1981 }
1982
1983 ir3_put_dst(ctx, &tex->dest);
1984 }
1985
1986 static void
1987 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
1988 {
1989 struct ir3_block *b = ctx->block;
1990 struct ir3_instruction **dst, *sam;
1991
1992 dst = ir3_get_dst(ctx, &tex->dest, 1);
1993
1994 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, 1 << idx, 0,
1995 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
1996
1997 /* even though there is only one component, since it ends
1998 * up in .y/.z/.w rather than .x, we need a split_dest()
1999 */
2000 if (idx)
2001 ir3_split_dest(b, dst, sam, 0, idx + 1);
2002
2003 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2004 * the value in TEX_CONST_0 is zero-based.
2005 */
2006 if (ctx->compiler->levels_add_one)
2007 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2008
2009 ir3_put_dst(ctx, &tex->dest);
2010 }
2011
2012 static void
2013 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2014 {
2015 struct ir3_block *b = ctx->block;
2016 struct ir3_instruction **dst, *sam;
2017 struct ir3_instruction *lod;
2018 unsigned flags, coords;
2019
2020 tex_info(tex, &flags, &coords);
2021
2022 /* Actually we want the number of dimensions, not coordinates. This
2023 * distinction only matters for cubes.
2024 */
2025 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2026 coords = 2;
2027
2028 dst = ir3_get_dst(ctx, &tex->dest, 4);
2029
2030 compile_assert(ctx, tex->num_srcs == 1);
2031 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2032
2033 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2034
2035 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
2036 get_tex_samp_tex_src(ctx, tex), lod, NULL);
2037
2038 ir3_split_dest(b, dst, sam, 0, 4);
2039
2040 /* Array size actually ends up in .w rather than .z. This doesn't
2041 * matter for miplevel 0, but for higher mips the value in z is
2042 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2043 * returned, which means that we have to add 1 to it for arrays.
2044 */
2045 if (tex->is_array) {
2046 if (ctx->compiler->levels_add_one) {
2047 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2048 } else {
2049 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2050 }
2051 }
2052
2053 ir3_put_dst(ctx, &tex->dest);
2054 }
2055
2056 static void
2057 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2058 {
2059 switch (jump->type) {
2060 case nir_jump_break:
2061 case nir_jump_continue:
2062 case nir_jump_return:
2063 /* I *think* we can simply just ignore this, and use the
2064 * successor block link to figure out where we need to
2065 * jump to for break/continue
2066 */
2067 break;
2068 default:
2069 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2070 break;
2071 }
2072 }
2073
2074 static void
2075 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2076 {
2077 switch (instr->type) {
2078 case nir_instr_type_alu:
2079 emit_alu(ctx, nir_instr_as_alu(instr));
2080 break;
2081 case nir_instr_type_deref:
2082 /* ignored, handled as part of the intrinsic they are src to */
2083 break;
2084 case nir_instr_type_intrinsic:
2085 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2086 break;
2087 case nir_instr_type_load_const:
2088 emit_load_const(ctx, nir_instr_as_load_const(instr));
2089 break;
2090 case nir_instr_type_ssa_undef:
2091 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2092 break;
2093 case nir_instr_type_tex: {
2094 nir_tex_instr *tex = nir_instr_as_tex(instr);
2095 /* couple tex instructions get special-cased:
2096 */
2097 switch (tex->op) {
2098 case nir_texop_txs:
2099 emit_tex_txs(ctx, tex);
2100 break;
2101 case nir_texop_query_levels:
2102 emit_tex_info(ctx, tex, 2);
2103 break;
2104 case nir_texop_texture_samples:
2105 emit_tex_info(ctx, tex, 3);
2106 break;
2107 default:
2108 emit_tex(ctx, tex);
2109 break;
2110 }
2111 break;
2112 }
2113 case nir_instr_type_jump:
2114 emit_jump(ctx, nir_instr_as_jump(instr));
2115 break;
2116 case nir_instr_type_phi:
2117 /* we have converted phi webs to regs in NIR by now */
2118 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2119 break;
2120 case nir_instr_type_call:
2121 case nir_instr_type_parallel_copy:
2122 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2123 break;
2124 }
2125 }
2126
2127 static struct ir3_block *
2128 get_block(struct ir3_context *ctx, const nir_block *nblock)
2129 {
2130 struct ir3_block *block;
2131 struct hash_entry *hentry;
2132
2133 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2134 if (hentry)
2135 return hentry->data;
2136
2137 block = ir3_block_create(ctx->ir);
2138 block->nblock = nblock;
2139 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2140
2141 block->predecessors = _mesa_pointer_set_create(block);
2142 set_foreach(nblock->predecessors, sentry) {
2143 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2144 }
2145
2146 return block;
2147 }
2148
2149 static void
2150 emit_block(struct ir3_context *ctx, nir_block *nblock)
2151 {
2152 struct ir3_block *block = get_block(ctx, nblock);
2153
2154 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2155 if (nblock->successors[i]) {
2156 block->successors[i] =
2157 get_block(ctx, nblock->successors[i]);
2158 }
2159 }
2160
2161 ctx->block = block;
2162 list_addtail(&block->node, &ctx->ir->block_list);
2163
2164 /* re-emit addr register in each block if needed: */
2165 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2166 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2167 ctx->addr_ht[i] = NULL;
2168 }
2169
2170 nir_foreach_instr(instr, nblock) {
2171 ctx->cur_instr = instr;
2172 emit_instr(ctx, instr);
2173 ctx->cur_instr = NULL;
2174 if (ctx->error)
2175 return;
2176 }
2177 }
2178
2179 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2180
2181 static void
2182 emit_if(struct ir3_context *ctx, nir_if *nif)
2183 {
2184 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2185
2186 ctx->block->condition =
2187 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2188
2189 emit_cf_list(ctx, &nif->then_list);
2190 emit_cf_list(ctx, &nif->else_list);
2191 }
2192
2193 static void
2194 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2195 {
2196 emit_cf_list(ctx, &nloop->body);
2197 ctx->so->loops++;
2198 }
2199
2200 static void
2201 stack_push(struct ir3_context *ctx)
2202 {
2203 ctx->stack++;
2204 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2205 }
2206
2207 static void
2208 stack_pop(struct ir3_context *ctx)
2209 {
2210 compile_assert(ctx, ctx->stack > 0);
2211 ctx->stack--;
2212 }
2213
2214 static void
2215 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2216 {
2217 foreach_list_typed(nir_cf_node, node, node, list) {
2218 switch (node->type) {
2219 case nir_cf_node_block:
2220 emit_block(ctx, nir_cf_node_as_block(node));
2221 break;
2222 case nir_cf_node_if:
2223 stack_push(ctx);
2224 emit_if(ctx, nir_cf_node_as_if(node));
2225 stack_pop(ctx);
2226 break;
2227 case nir_cf_node_loop:
2228 stack_push(ctx);
2229 emit_loop(ctx, nir_cf_node_as_loop(node));
2230 stack_pop(ctx);
2231 break;
2232 case nir_cf_node_function:
2233 ir3_context_error(ctx, "TODO\n");
2234 break;
2235 }
2236 }
2237 }
2238
2239 /* emit stream-out code. At this point, the current block is the original
2240 * (nir) end block, and nir ensures that all flow control paths terminate
2241 * into the end block. We re-purpose the original end block to generate
2242 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2243 * block holding stream-out write instructions, followed by the new end
2244 * block:
2245 *
2246 * blockOrigEnd {
2247 * p0.x = (vtxcnt < maxvtxcnt)
2248 * // succs: blockStreamOut, blockNewEnd
2249 * }
2250 * blockStreamOut {
2251 * ... stream-out instructions ...
2252 * // succs: blockNewEnd
2253 * }
2254 * blockNewEnd {
2255 * }
2256 */
2257 static void
2258 emit_stream_out(struct ir3_context *ctx)
2259 {
2260 struct ir3 *ir = ctx->ir;
2261 struct ir3_stream_output_info *strmout =
2262 &ctx->so->shader->stream_output;
2263 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2264 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2265 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2266
2267 /* create vtxcnt input in input block at top of shader,
2268 * so that it is seen as live over the entire duration
2269 * of the shader:
2270 */
2271 vtxcnt = create_input(ctx, 0);
2272 add_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, vtxcnt);
2273
2274 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2275
2276 /* at this point, we are at the original 'end' block,
2277 * re-purpose this block to stream-out condition, then
2278 * append stream-out block and new-end block
2279 */
2280 orig_end_block = ctx->block;
2281
2282 // TODO these blocks need to update predecessors..
2283 // maybe w/ store_global intrinsic, we could do this
2284 // stuff in nir->nir pass
2285
2286 stream_out_block = ir3_block_create(ir);
2287 list_addtail(&stream_out_block->node, &ir->block_list);
2288
2289 new_end_block = ir3_block_create(ir);
2290 list_addtail(&new_end_block->node, &ir->block_list);
2291
2292 orig_end_block->successors[0] = stream_out_block;
2293 orig_end_block->successors[1] = new_end_block;
2294 stream_out_block->successors[0] = new_end_block;
2295
2296 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2297 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2298 cond->regs[0]->num = regid(REG_P0, 0);
2299 cond->cat2.condition = IR3_COND_LT;
2300
2301 /* condition goes on previous block to the conditional,
2302 * since it is used to pick which of the two successor
2303 * paths to take:
2304 */
2305 orig_end_block->condition = cond;
2306
2307 /* switch to stream_out_block to generate the stream-out
2308 * instructions:
2309 */
2310 ctx->block = stream_out_block;
2311
2312 /* Calculate base addresses based on vtxcnt. Instructions
2313 * generated for bases not used in following loop will be
2314 * stripped out in the backend.
2315 */
2316 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2317 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2318 unsigned stride = strmout->stride[i];
2319 struct ir3_instruction *base, *off;
2320
2321 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2322
2323 /* 24-bit should be enough: */
2324 off = ir3_MUL_U(ctx->block, vtxcnt, 0,
2325 create_immed(ctx->block, stride * 4), 0);
2326
2327 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2328 }
2329
2330 /* Generate the per-output store instructions: */
2331 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2332 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2333 unsigned c = j + strmout->output[i].start_component;
2334 struct ir3_instruction *base, *out, *stg;
2335
2336 base = bases[strmout->output[i].output_buffer];
2337 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2338
2339 stg = ir3_STG(ctx->block, base, 0, out, 0,
2340 create_immed(ctx->block, 1), 0);
2341 stg->cat6.type = TYPE_U32;
2342 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2343
2344 array_insert(ctx->block, ctx->block->keeps, stg);
2345 }
2346 }
2347
2348 /* and finally switch to the new_end_block: */
2349 ctx->block = new_end_block;
2350 }
2351
2352 static void
2353 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2354 {
2355 nir_metadata_require(impl, nir_metadata_block_index);
2356
2357 compile_assert(ctx, ctx->stack == 0);
2358
2359 emit_cf_list(ctx, &impl->body);
2360 emit_block(ctx, impl->end_block);
2361
2362 compile_assert(ctx, ctx->stack == 0);
2363
2364 /* at this point, we should have a single empty block,
2365 * into which we emit the 'end' instruction.
2366 */
2367 compile_assert(ctx, list_empty(&ctx->block->instr_list));
2368
2369 /* If stream-out (aka transform-feedback) enabled, emit the
2370 * stream-out instructions, followed by a new empty block (into
2371 * which the 'end' instruction lands).
2372 *
2373 * NOTE: it is done in this order, rather than inserting before
2374 * we emit end_block, because NIR guarantees that all blocks
2375 * flow into end_block, and that end_block has no successors.
2376 * So by re-purposing end_block as the first block of stream-
2377 * out, we guarantee that all exit paths flow into the stream-
2378 * out instructions.
2379 */
2380 if ((ctx->compiler->gpu_id < 500) &&
2381 (ctx->so->shader->stream_output.num_outputs > 0) &&
2382 !ctx->so->binning_pass) {
2383 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2384 emit_stream_out(ctx);
2385 }
2386
2387 ir3_END(ctx->block);
2388 }
2389
2390 static void
2391 setup_input(struct ir3_context *ctx, nir_variable *in)
2392 {
2393 struct ir3_shader_variant *so = ctx->so;
2394 unsigned ncomp = glsl_get_components(in->type);
2395 unsigned n = in->data.driver_location;
2396 unsigned frac = in->data.location_frac;
2397 unsigned slot = in->data.location;
2398
2399 /* skip unread inputs, we could end up with (for example), unsplit
2400 * matrix/etc inputs in the case they are not read, so just silently
2401 * skip these.
2402 */
2403 if (ncomp > 4)
2404 return;
2405
2406 so->inputs[n].slot = slot;
2407 so->inputs[n].compmask = (1 << (ncomp + frac)) - 1;
2408 so->inputs_count = MAX2(so->inputs_count, n + 1);
2409 so->inputs[n].interpolate = in->data.interpolation;
2410
2411 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2412
2413 /* if any varyings have 'sample' qualifer, that triggers us
2414 * to run in per-sample mode:
2415 */
2416 so->per_samp |= in->data.sample;
2417
2418 for (int i = 0; i < ncomp; i++) {
2419 struct ir3_instruction *instr = NULL;
2420 unsigned idx = (n * 4) + i + frac;
2421
2422 if (slot == VARYING_SLOT_POS) {
2423 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2424 } else if (slot == VARYING_SLOT_PNTC) {
2425 /* see for example st_nir_fixup_varying_slots().. this is
2426 * maybe a bit mesa/st specific. But we need things to line
2427 * up for this in fdN_program:
2428 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2429 * if (emit->sprite_coord_enable & texmask) {
2430 * ...
2431 * }
2432 */
2433 so->inputs[n].slot = VARYING_SLOT_VAR8;
2434 so->inputs[n].bary = true;
2435 instr = create_frag_input(ctx, false, idx);
2436 } else {
2437 /* detect the special case for front/back colors where
2438 * we need to do flat vs smooth shading depending on
2439 * rast state:
2440 */
2441 if (in->data.interpolation == INTERP_MODE_NONE) {
2442 switch (slot) {
2443 case VARYING_SLOT_COL0:
2444 case VARYING_SLOT_COL1:
2445 case VARYING_SLOT_BFC0:
2446 case VARYING_SLOT_BFC1:
2447 so->inputs[n].rasterflat = true;
2448 break;
2449 default:
2450 break;
2451 }
2452 }
2453
2454 if (ctx->compiler->flat_bypass) {
2455 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2456 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2457 so->inputs[n].use_ldlv = true;
2458 }
2459
2460 so->inputs[n].bary = true;
2461
2462 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2463 }
2464
2465 compile_assert(ctx, idx < ctx->ir->ninputs);
2466
2467 ctx->ir->inputs[idx] = instr;
2468 }
2469 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2470 for (int i = 0; i < ncomp; i++) {
2471 unsigned idx = (n * 4) + i + frac;
2472 compile_assert(ctx, idx < ctx->ir->ninputs);
2473 ctx->ir->inputs[idx] = create_input(ctx, idx);
2474 }
2475 } else {
2476 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2477 }
2478
2479 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2480 so->total_in += ncomp;
2481 }
2482 }
2483
2484 /* Initially we assign non-packed inloc's for varyings, as we don't really
2485 * know up-front which components will be unused. After all the compilation
2486 * stages we scan the shader to see which components are actually used, and
2487 * re-pack the inlocs to eliminate unneeded varyings.
2488 */
2489 static void
2490 pack_inlocs(struct ir3_context *ctx)
2491 {
2492 struct ir3_shader_variant *so = ctx->so;
2493 uint8_t used_components[so->inputs_count];
2494
2495 memset(used_components, 0, sizeof(used_components));
2496
2497 /*
2498 * First Step: scan shader to find which bary.f/ldlv remain:
2499 */
2500
2501 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2502 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2503 if (is_input(instr)) {
2504 unsigned inloc = instr->regs[1]->iim_val;
2505 unsigned i = inloc / 4;
2506 unsigned j = inloc % 4;
2507
2508 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
2509 compile_assert(ctx, i < so->inputs_count);
2510
2511 used_components[i] |= 1 << j;
2512 }
2513 }
2514 }
2515
2516 /*
2517 * Second Step: reassign varying inloc/slots:
2518 */
2519
2520 unsigned actual_in = 0;
2521 unsigned inloc = 0;
2522
2523 for (unsigned i = 0; i < so->inputs_count; i++) {
2524 unsigned compmask = 0, maxcomp = 0;
2525
2526 so->inputs[i].inloc = inloc;
2527 so->inputs[i].bary = false;
2528
2529 for (unsigned j = 0; j < 4; j++) {
2530 if (!(used_components[i] & (1 << j)))
2531 continue;
2532
2533 compmask |= (1 << j);
2534 actual_in++;
2535 maxcomp = j + 1;
2536
2537 /* at this point, since used_components[i] mask is only
2538 * considering varyings (ie. not sysvals) we know this
2539 * is a varying:
2540 */
2541 so->inputs[i].bary = true;
2542 }
2543
2544 if (so->inputs[i].bary) {
2545 so->varying_in++;
2546 so->inputs[i].compmask = (1 << maxcomp) - 1;
2547 inloc += maxcomp;
2548 }
2549 }
2550
2551 /*
2552 * Third Step: reassign packed inloc's:
2553 */
2554
2555 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2556 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2557 if (is_input(instr)) {
2558 unsigned inloc = instr->regs[1]->iim_val;
2559 unsigned i = inloc / 4;
2560 unsigned j = inloc % 4;
2561
2562 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
2563 }
2564 }
2565 }
2566 }
2567
2568 static void
2569 setup_output(struct ir3_context *ctx, nir_variable *out)
2570 {
2571 struct ir3_shader_variant *so = ctx->so;
2572 unsigned ncomp = glsl_get_components(out->type);
2573 unsigned n = out->data.driver_location;
2574 unsigned frac = out->data.location_frac;
2575 unsigned slot = out->data.location;
2576 unsigned comp = 0;
2577
2578 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2579 switch (slot) {
2580 case FRAG_RESULT_DEPTH:
2581 comp = 2; /* tgsi will write to .z component */
2582 so->writes_pos = true;
2583 break;
2584 case FRAG_RESULT_COLOR:
2585 so->color0_mrt = 1;
2586 break;
2587 case FRAG_RESULT_SAMPLE_MASK:
2588 so->writes_smask = true;
2589 break;
2590 default:
2591 if (slot >= FRAG_RESULT_DATA0)
2592 break;
2593 ir3_context_error(ctx, "unknown FS output name: %s\n",
2594 gl_frag_result_name(slot));
2595 }
2596 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2597 switch (slot) {
2598 case VARYING_SLOT_POS:
2599 so->writes_pos = true;
2600 break;
2601 case VARYING_SLOT_PSIZ:
2602 so->writes_psize = true;
2603 break;
2604 case VARYING_SLOT_COL0:
2605 case VARYING_SLOT_COL1:
2606 case VARYING_SLOT_BFC0:
2607 case VARYING_SLOT_BFC1:
2608 case VARYING_SLOT_FOGC:
2609 case VARYING_SLOT_CLIP_DIST0:
2610 case VARYING_SLOT_CLIP_DIST1:
2611 case VARYING_SLOT_CLIP_VERTEX:
2612 break;
2613 default:
2614 if (slot >= VARYING_SLOT_VAR0)
2615 break;
2616 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2617 break;
2618 ir3_context_error(ctx, "unknown VS output name: %s\n",
2619 gl_varying_slot_name(slot));
2620 }
2621 } else {
2622 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2623 }
2624
2625 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2626
2627 so->outputs[n].slot = slot;
2628 so->outputs[n].regid = regid(n, comp);
2629 so->outputs_count = MAX2(so->outputs_count, n + 1);
2630
2631 for (int i = 0; i < ncomp; i++) {
2632 unsigned idx = (n * 4) + i + frac;
2633 compile_assert(ctx, idx < ctx->ir->noutputs);
2634 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2635 }
2636
2637 /* if varying packing doesn't happen, we could end up in a situation
2638 * with "holes" in the output, and since the per-generation code that
2639 * sets up varying linkage registers doesn't expect to have more than
2640 * one varying per vec4 slot, pad the holes.
2641 *
2642 * Note that this should probably generate a performance warning of
2643 * some sort.
2644 */
2645 for (int i = 0; i < frac; i++) {
2646 unsigned idx = (n * 4) + i;
2647 if (!ctx->ir->outputs[idx]) {
2648 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2649 }
2650 }
2651 }
2652
2653 static int
2654 max_drvloc(struct exec_list *vars)
2655 {
2656 int drvloc = -1;
2657 nir_foreach_variable(var, vars) {
2658 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2659 }
2660 return drvloc;
2661 }
2662
2663 static const unsigned max_sysvals[] = {
2664 [MESA_SHADER_FRAGMENT] = 24, // TODO
2665 [MESA_SHADER_VERTEX] = 16,
2666 [MESA_SHADER_COMPUTE] = 16, // TODO how many do we actually need?
2667 [MESA_SHADER_KERNEL] = 16, // TODO how many do we actually need?
2668 };
2669
2670 static void
2671 emit_instructions(struct ir3_context *ctx)
2672 {
2673 unsigned ninputs, noutputs;
2674 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
2675
2676 ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
2677 noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
2678
2679 /* we need to leave room for sysvals:
2680 */
2681 ninputs += max_sysvals[ctx->so->type];
2682
2683 ctx->ir = ir3_create(ctx->compiler, ctx->so->type, ninputs, noutputs);
2684
2685 /* Create inputs in first block: */
2686 ctx->block = get_block(ctx, nir_start_block(fxn));
2687 ctx->in_block = ctx->block;
2688 list_addtail(&ctx->block->node, &ctx->ir->block_list);
2689
2690 ninputs -= max_sysvals[ctx->so->type];
2691
2692 /* for fragment shader, the vcoord input register is used as the
2693 * base for bary.f varying fetch instrs:
2694 *
2695 * TODO defer creating ctx->ij_pixel and corresponding sysvals
2696 * until emit_intrinsic when we know they are actually needed.
2697 * For now, we defer creating ctx->ij_centroid, etc, since we
2698 * only need ij_pixel for "old style" varying inputs (ie.
2699 * tgsi_to_nir)
2700 */
2701 struct ir3_instruction *vcoord = NULL;
2702 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2703 struct ir3_instruction *xy[2];
2704
2705 vcoord = create_input_compmask(ctx, 0, 0x3);
2706 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
2707
2708 ctx->ij_pixel = ir3_create_collect(ctx, xy, 2);
2709 }
2710
2711 /* Setup inputs: */
2712 nir_foreach_variable(var, &ctx->s->inputs) {
2713 setup_input(ctx, var);
2714 }
2715
2716 /* Defer add_sysval_input() stuff until after setup_inputs(),
2717 * because sysvals need to be appended after varyings:
2718 */
2719 if (vcoord) {
2720 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PIXEL,
2721 0x3, vcoord);
2722 }
2723
2724 /* Setup outputs: */
2725 nir_foreach_variable(var, &ctx->s->outputs) {
2726 setup_output(ctx, var);
2727 }
2728
2729 /* Find # of samplers: */
2730 nir_foreach_variable(var, &ctx->s->uniforms) {
2731 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
2732 /* just assume that we'll be reading from images.. if it
2733 * is write-only we don't have to count it, but not sure
2734 * if there is a good way to know?
2735 */
2736 ctx->so->num_samp += glsl_type_get_image_count(var->type);
2737 }
2738
2739 /* NOTE: need to do something more clever when we support >1 fxn */
2740 nir_foreach_register(reg, &fxn->registers) {
2741 ir3_declare_array(ctx, reg);
2742 }
2743 /* And emit the body: */
2744 ctx->impl = fxn;
2745 emit_function(ctx, fxn);
2746 }
2747
2748 /* from NIR perspective, we actually have varying inputs. But the varying
2749 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
2750 * only actual inputs are the sysvals.
2751 */
2752 static void
2753 fixup_frag_inputs(struct ir3_context *ctx)
2754 {
2755 struct ir3_shader_variant *so = ctx->so;
2756 struct ir3 *ir = ctx->ir;
2757 unsigned i = 0;
2758
2759 /* sysvals should appear at the end of the inputs, drop everything else: */
2760 while ((i < so->inputs_count) && !so->inputs[i].sysval)
2761 i++;
2762
2763 /* at IR level, inputs are always blocks of 4 scalars: */
2764 i *= 4;
2765
2766 ir->inputs = &ir->inputs[i];
2767 ir->ninputs -= i;
2768 }
2769
2770 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2771 * need to assign the tex state indexes for these after we know the
2772 * max tex index.
2773 */
2774 static void
2775 fixup_astc_srgb(struct ir3_context *ctx)
2776 {
2777 struct ir3_shader_variant *so = ctx->so;
2778 /* indexed by original tex idx, value is newly assigned alpha sampler
2779 * state tex idx. Zero is invalid since there is at least one sampler
2780 * if we get here.
2781 */
2782 unsigned alt_tex_state[16] = {0};
2783 unsigned tex_idx = ctx->max_texture_index + 1;
2784 unsigned idx = 0;
2785
2786 so->astc_srgb.base = tex_idx;
2787
2788 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
2789 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
2790
2791 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
2792
2793 if (alt_tex_state[sam->cat5.tex] == 0) {
2794 /* assign new alternate/alpha tex state slot: */
2795 alt_tex_state[sam->cat5.tex] = tex_idx++;
2796 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
2797 so->astc_srgb.count++;
2798 }
2799
2800 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
2801 }
2802 }
2803
2804 static void
2805 fixup_binning_pass(struct ir3_context *ctx)
2806 {
2807 struct ir3_shader_variant *so = ctx->so;
2808 struct ir3 *ir = ctx->ir;
2809 unsigned i, j;
2810
2811 for (i = 0, j = 0; i < so->outputs_count; i++) {
2812 unsigned slot = so->outputs[i].slot;
2813
2814 /* throw away everything but first position/psize */
2815 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
2816 if (i != j) {
2817 so->outputs[j] = so->outputs[i];
2818 ir->outputs[(j*4)+0] = ir->outputs[(i*4)+0];
2819 ir->outputs[(j*4)+1] = ir->outputs[(i*4)+1];
2820 ir->outputs[(j*4)+2] = ir->outputs[(i*4)+2];
2821 ir->outputs[(j*4)+3] = ir->outputs[(i*4)+3];
2822 }
2823 j++;
2824 }
2825 }
2826 so->outputs_count = j;
2827 ir->noutputs = j * 4;
2828 }
2829
2830 int
2831 ir3_compile_shader_nir(struct ir3_compiler *compiler,
2832 struct ir3_shader_variant *so)
2833 {
2834 struct ir3_context *ctx;
2835 struct ir3 *ir;
2836 struct ir3_instruction **inputs;
2837 unsigned i;
2838 int ret = 0, max_bary;
2839
2840 assert(!so->ir);
2841
2842 ctx = ir3_context_init(compiler, so);
2843 if (!ctx) {
2844 DBG("INIT failed!");
2845 ret = -1;
2846 goto out;
2847 }
2848
2849 emit_instructions(ctx);
2850
2851 if (ctx->error) {
2852 DBG("EMIT failed!");
2853 ret = -1;
2854 goto out;
2855 }
2856
2857 ir = so->ir = ctx->ir;
2858
2859 /* keep track of the inputs from TGSI perspective.. */
2860 inputs = ir->inputs;
2861
2862 /* but fixup actual inputs for frag shader: */
2863 if (so->type == MESA_SHADER_FRAGMENT)
2864 fixup_frag_inputs(ctx);
2865
2866 /* at this point, for binning pass, throw away unneeded outputs: */
2867 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
2868 fixup_binning_pass(ctx);
2869
2870 /* if we want half-precision outputs, mark the output registers
2871 * as half:
2872 */
2873 if (so->key.half_precision) {
2874 for (i = 0; i < ir->noutputs; i++) {
2875 struct ir3_instruction *out = ir->outputs[i];
2876
2877 if (!out)
2878 continue;
2879
2880 /* if frag shader writes z, that needs to be full precision: */
2881 if (so->outputs[i/4].slot == FRAG_RESULT_DEPTH)
2882 continue;
2883
2884 out->regs[0]->flags |= IR3_REG_HALF;
2885 /* output could be a fanout (ie. texture fetch output)
2886 * in which case we need to propagate the half-reg flag
2887 * up to the definer so that RA sees it:
2888 */
2889 if (out->opc == OPC_META_FO) {
2890 out = out->regs[1]->instr;
2891 out->regs[0]->flags |= IR3_REG_HALF;
2892 }
2893
2894 if (out->opc == OPC_MOV) {
2895 out->cat1.dst_type = half_type(out->cat1.dst_type);
2896 }
2897 }
2898 }
2899
2900 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2901 printf("BEFORE CP:\n");
2902 ir3_print(ir);
2903 }
2904
2905 ir3_cp(ir, so);
2906
2907 /* at this point, for binning pass, throw away unneeded outputs:
2908 * Note that for a6xx and later, we do this after ir3_cp to ensure
2909 * that the uniform/constant layout for BS and VS matches, so that
2910 * we can re-use same VS_CONST state group.
2911 */
2912 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
2913 fixup_binning_pass(ctx);
2914
2915 /* for a6xx+, binning and draw pass VS use same VBO state, so we
2916 * need to make sure not to remove any inputs that are used by
2917 * the nonbinning VS.
2918 */
2919 if (ctx->compiler->gpu_id >= 600 && so->binning_pass) {
2920 debug_assert(so->type == MESA_SHADER_VERTEX);
2921 for (int i = 0; i < ir->ninputs; i++) {
2922 struct ir3_instruction *in = ir->inputs[i];
2923
2924 if (!in)
2925 continue;
2926
2927 unsigned n = i / 4;
2928 unsigned c = i % 4;
2929
2930 debug_assert(n < so->nonbinning->inputs_count);
2931
2932 if (so->nonbinning->inputs[n].sysval)
2933 continue;
2934
2935 /* be sure to keep inputs, even if only used in VS */
2936 if (so->nonbinning->inputs[n].compmask & (1 << c))
2937 array_insert(in->block, in->block->keeps, in);
2938 }
2939 }
2940
2941 /* Insert mov if there's same instruction for each output.
2942 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
2943 */
2944 for (int i = ir->noutputs - 1; i >= 0; i--) {
2945 if (!ir->outputs[i])
2946 continue;
2947 for (unsigned j = 0; j < i; j++) {
2948 if (ir->outputs[i] == ir->outputs[j]) {
2949 ir->outputs[i] =
2950 ir3_MOV(ir->outputs[i]->block, ir->outputs[i], TYPE_F32);
2951 }
2952 }
2953 }
2954
2955 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2956 printf("BEFORE GROUPING:\n");
2957 ir3_print(ir);
2958 }
2959
2960 ir3_sched_add_deps(ir);
2961
2962 /* Group left/right neighbors, inserting mov's where needed to
2963 * solve conflicts:
2964 */
2965 ir3_group(ir);
2966
2967 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2968 printf("AFTER GROUPING:\n");
2969 ir3_print(ir);
2970 }
2971
2972 ir3_depth(ir);
2973
2974 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2975 printf("AFTER DEPTH:\n");
2976 ir3_print(ir);
2977 }
2978
2979 /* do Sethi–Ullman numbering before scheduling: */
2980 ir3_sun(ir);
2981
2982 ret = ir3_sched(ir);
2983 if (ret) {
2984 DBG("SCHED failed!");
2985 goto out;
2986 }
2987
2988 if (compiler->gpu_id >= 600) {
2989 ir3_a6xx_fixup_atomic_dests(ir, so);
2990 }
2991
2992 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2993 printf("AFTER SCHED:\n");
2994 ir3_print(ir);
2995 }
2996
2997 ret = ir3_ra(so);
2998 if (ret) {
2999 DBG("RA failed!");
3000 goto out;
3001 }
3002
3003 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3004 printf("AFTER RA:\n");
3005 ir3_print(ir);
3006 }
3007
3008 if (so->type == MESA_SHADER_FRAGMENT)
3009 pack_inlocs(ctx);
3010
3011 /* fixup input/outputs: */
3012 for (i = 0; i < so->outputs_count; i++) {
3013 /* sometimes we get outputs that don't write the .x coord, like:
3014 *
3015 * decl_var shader_out INTERP_MODE_NONE float Color (VARYING_SLOT_VAR9.z, 1, 0)
3016 *
3017 * Presumably the result of varying packing and then eliminating
3018 * some unneeded varyings? Just skip head to the first valid
3019 * component of the output.
3020 */
3021 for (unsigned j = 0; j < 4; j++) {
3022 struct ir3_instruction *instr = ir->outputs[(i*4) + j];
3023 if (instr) {
3024 so->outputs[i].regid = instr->regs[0]->num;
3025 so->outputs[i].half = !!(instr->regs[0]->flags & IR3_REG_HALF);
3026 break;
3027 }
3028 }
3029 }
3030
3031 /* Note that some or all channels of an input may be unused: */
3032 for (i = 0; i < so->inputs_count; i++) {
3033 unsigned j, reg = regid(63,0);
3034 bool half = false;
3035 for (j = 0; j < 4; j++) {
3036 struct ir3_instruction *in = inputs[(i*4) + j];
3037
3038 if (!in)
3039 continue;
3040
3041 if (in->flags & IR3_INSTR_UNUSED)
3042 continue;
3043
3044 reg = in->regs[0]->num - j;
3045 if (half) {
3046 compile_assert(ctx, in->regs[0]->flags & IR3_REG_HALF);
3047 } else {
3048 half = !!(in->regs[0]->flags & IR3_REG_HALF);
3049 }
3050 }
3051 so->inputs[i].regid = reg;
3052 so->inputs[i].half = half;
3053 }
3054
3055 if (ctx->astc_srgb)
3056 fixup_astc_srgb(ctx);
3057
3058 /* We need to do legalize after (for frag shader's) the "bary.f"
3059 * offsets (inloc) have been assigned.
3060 */
3061 ir3_legalize(ir, &so->has_ssbo, &so->need_pixlod, &max_bary);
3062
3063 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3064 printf("AFTER LEGALIZE:\n");
3065 ir3_print(ir);
3066 }
3067
3068 so->branchstack = ctx->max_stack;
3069
3070 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3071 if (so->type == MESA_SHADER_FRAGMENT)
3072 so->total_in = max_bary + 1;
3073
3074 so->max_sun = ir->max_sun;
3075
3076 out:
3077 if (ret) {
3078 if (so->ir)
3079 ir3_destroy(so->ir);
3080 so->ir = NULL;
3081 }
3082 ir3_context_free(ctx);
3083
3084 return ret;
3085 }