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freedreno/ir3: simplify creating sysval inputs
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 __ssa_dst(mov);
55 src = __ssa_src(mov, collect, IR3_REG_RELATIV);
56 src->size = arrsz;
57 src->array.offset = n;
58
59 ir3_instr_set_address(mov, address);
60
61 return mov;
62 }
63
64 static struct ir3_instruction *
65 create_input_compmask(struct ir3_context *ctx, unsigned n, unsigned compmask)
66 {
67 struct ir3_instruction *in;
68
69 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
70 in->input.sysval = ~0;
71 __ssa_dst(in)->wrmask = compmask;
72
73 return in;
74 }
75
76 static struct ir3_instruction *
77 create_input(struct ir3_context *ctx, unsigned n)
78 {
79 return create_input_compmask(ctx, n, 0x1);
80 }
81
82 static struct ir3_instruction *
83 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
84 {
85 struct ir3_block *block = ctx->block;
86 struct ir3_instruction *instr;
87 /* packed inloc is fixed up later: */
88 struct ir3_instruction *inloc = create_immed(block, n);
89
90 if (use_ldlv) {
91 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
92 instr->cat6.type = TYPE_U32;
93 instr->cat6.iim_val = 1;
94 } else {
95 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
96 instr->regs[2]->wrmask = 0x3;
97 }
98
99 return instr;
100 }
101
102 static struct ir3_instruction *
103 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
104 {
105 /* first four vec4 sysval's reserved for UBOs: */
106 /* NOTE: dp is in scalar, but there can be >4 dp components: */
107 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
108 unsigned n = const_state->offsets.driver_param;
109 unsigned r = regid(n + dp / 4, dp % 4);
110 return create_uniform(ctx->block, r);
111 }
112
113 /*
114 * Adreno uses uint rather than having dedicated bool type,
115 * which (potentially) requires some conversion, in particular
116 * when using output of an bool instr to int input, or visa
117 * versa.
118 *
119 * | Adreno | NIR |
120 * -------+---------+-------+-
121 * true | 1 | ~0 |
122 * false | 0 | 0 |
123 *
124 * To convert from an adreno bool (uint) to nir, use:
125 *
126 * absneg.s dst, (neg)src
127 *
128 * To convert back in the other direction:
129 *
130 * absneg.s dst, (abs)arc
131 *
132 * The CP step can clean up the absneg.s that cancel each other
133 * out, and with a slight bit of extra cleverness (to recognize
134 * the instructions which produce either a 0 or 1) can eliminate
135 * the absneg.s's completely when an instruction that wants
136 * 0/1 consumes the result. For example, when a nir 'bcsel'
137 * consumes the result of 'feq'. So we should be able to get by
138 * without a boolean resolve step, and without incuring any
139 * extra penalty in instruction count.
140 */
141
142 /* NIR bool -> native (adreno): */
143 static struct ir3_instruction *
144 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
145 {
146 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
147 }
148
149 /* native (adreno) -> NIR bool: */
150 static struct ir3_instruction *
151 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
152 {
153 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
154 }
155
156 /*
157 * alu/sfu instructions:
158 */
159
160 static struct ir3_instruction *
161 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
162 unsigned src_bitsize, nir_op op)
163 {
164 type_t src_type, dst_type;
165
166 switch (op) {
167 case nir_op_f2f32:
168 case nir_op_f2f16_rtne:
169 case nir_op_f2f16_rtz:
170 case nir_op_f2f16:
171 case nir_op_f2i32:
172 case nir_op_f2i16:
173 case nir_op_f2i8:
174 case nir_op_f2u32:
175 case nir_op_f2u16:
176 case nir_op_f2u8:
177 switch (src_bitsize) {
178 case 32:
179 src_type = TYPE_F32;
180 break;
181 case 16:
182 src_type = TYPE_F16;
183 break;
184 default:
185 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
186 }
187 break;
188
189 case nir_op_i2f32:
190 case nir_op_i2f16:
191 case nir_op_i2i32:
192 case nir_op_i2i16:
193 case nir_op_i2i8:
194 switch (src_bitsize) {
195 case 32:
196 src_type = TYPE_S32;
197 break;
198 case 16:
199 src_type = TYPE_S16;
200 break;
201 case 8:
202 src_type = TYPE_S8;
203 break;
204 default:
205 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
206 }
207 break;
208
209 case nir_op_u2f32:
210 case nir_op_u2f16:
211 case nir_op_u2u32:
212 case nir_op_u2u16:
213 case nir_op_u2u8:
214 switch (src_bitsize) {
215 case 32:
216 src_type = TYPE_U32;
217 break;
218 case 16:
219 src_type = TYPE_U16;
220 break;
221 case 8:
222 src_type = TYPE_U8;
223 break;
224 default:
225 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
226 }
227 break;
228
229 default:
230 ir3_context_error(ctx, "invalid conversion op: %u", op);
231 }
232
233 switch (op) {
234 case nir_op_f2f32:
235 case nir_op_i2f32:
236 case nir_op_u2f32:
237 dst_type = TYPE_F32;
238 break;
239
240 case nir_op_f2f16_rtne:
241 case nir_op_f2f16_rtz:
242 case nir_op_f2f16:
243 /* TODO how to handle rounding mode? */
244 case nir_op_i2f16:
245 case nir_op_u2f16:
246 dst_type = TYPE_F16;
247 break;
248
249 case nir_op_f2i32:
250 case nir_op_i2i32:
251 dst_type = TYPE_S32;
252 break;
253
254 case nir_op_f2i16:
255 case nir_op_i2i16:
256 dst_type = TYPE_S16;
257 break;
258
259 case nir_op_f2i8:
260 case nir_op_i2i8:
261 dst_type = TYPE_S8;
262 break;
263
264 case nir_op_f2u32:
265 case nir_op_u2u32:
266 dst_type = TYPE_U32;
267 break;
268
269 case nir_op_f2u16:
270 case nir_op_u2u16:
271 dst_type = TYPE_U16;
272 break;
273
274 case nir_op_f2u8:
275 case nir_op_u2u8:
276 dst_type = TYPE_U8;
277 break;
278
279 default:
280 ir3_context_error(ctx, "invalid conversion op: %u", op);
281 }
282
283 return ir3_COV(ctx->block, src, src_type, dst_type);
284 }
285
286 static void
287 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
288 {
289 const nir_op_info *info = &nir_op_infos[alu->op];
290 struct ir3_instruction **dst, *src[info->num_inputs];
291 unsigned bs[info->num_inputs]; /* bit size */
292 struct ir3_block *b = ctx->block;
293 unsigned dst_sz, wrmask;
294 type_t dst_type = nir_dest_bit_size(alu->dest.dest) < 32 ?
295 TYPE_U16 : TYPE_U32;
296
297 if (alu->dest.dest.is_ssa) {
298 dst_sz = alu->dest.dest.ssa.num_components;
299 wrmask = (1 << dst_sz) - 1;
300 } else {
301 dst_sz = alu->dest.dest.reg.reg->num_components;
302 wrmask = alu->dest.write_mask;
303 }
304
305 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
306
307 /* Vectors are special in that they have non-scalarized writemasks,
308 * and just take the first swizzle channel for each argument in
309 * order into each writemask channel.
310 */
311 if ((alu->op == nir_op_vec2) ||
312 (alu->op == nir_op_vec3) ||
313 (alu->op == nir_op_vec4)) {
314
315 for (int i = 0; i < info->num_inputs; i++) {
316 nir_alu_src *asrc = &alu->src[i];
317
318 compile_assert(ctx, !asrc->abs);
319 compile_assert(ctx, !asrc->negate);
320
321 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
322 if (!src[i])
323 src[i] = create_immed_typed(ctx->block, 0, dst_type);
324 dst[i] = ir3_MOV(b, src[i], dst_type);
325 }
326
327 ir3_put_dst(ctx, &alu->dest.dest);
328 return;
329 }
330
331 /* We also get mov's with more than one component for mov's so
332 * handle those specially:
333 */
334 if (alu->op == nir_op_mov) {
335 nir_alu_src *asrc = &alu->src[0];
336 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
337
338 for (unsigned i = 0; i < dst_sz; i++) {
339 if (wrmask & (1 << i)) {
340 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
341 } else {
342 dst[i] = NULL;
343 }
344 }
345
346 ir3_put_dst(ctx, &alu->dest.dest);
347 return;
348 }
349
350 /* General case: We can just grab the one used channel per src. */
351 for (int i = 0; i < info->num_inputs; i++) {
352 unsigned chan = ffs(alu->dest.write_mask) - 1;
353 nir_alu_src *asrc = &alu->src[i];
354
355 compile_assert(ctx, !asrc->abs);
356 compile_assert(ctx, !asrc->negate);
357
358 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
359 bs[i] = nir_src_bit_size(asrc->src);
360
361 compile_assert(ctx, src[i]);
362 }
363
364 switch (alu->op) {
365 case nir_op_f2f32:
366 case nir_op_f2f16_rtne:
367 case nir_op_f2f16_rtz:
368 case nir_op_f2f16:
369 case nir_op_f2i32:
370 case nir_op_f2i16:
371 case nir_op_f2i8:
372 case nir_op_f2u32:
373 case nir_op_f2u16:
374 case nir_op_f2u8:
375 case nir_op_i2f32:
376 case nir_op_i2f16:
377 case nir_op_i2i32:
378 case nir_op_i2i16:
379 case nir_op_i2i8:
380 case nir_op_u2f32:
381 case nir_op_u2f16:
382 case nir_op_u2u32:
383 case nir_op_u2u16:
384 case nir_op_u2u8:
385 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
386 break;
387 case nir_op_fquantize2f16:
388 dst[0] = create_cov(ctx,
389 create_cov(ctx, src[0], 32, nir_op_f2f16),
390 16, nir_op_f2f32);
391 break;
392 case nir_op_f2b32:
393 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
394 dst[0]->cat2.condition = IR3_COND_NE;
395 dst[0] = ir3_n2b(b, dst[0]);
396 break;
397 case nir_op_b2f16:
398 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F16);
399 break;
400 case nir_op_b2f32:
401 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
402 break;
403 case nir_op_b2i8:
404 case nir_op_b2i16:
405 case nir_op_b2i32:
406 dst[0] = ir3_b2n(b, src[0]);
407 break;
408 case nir_op_i2b32:
409 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
410 dst[0]->cat2.condition = IR3_COND_NE;
411 dst[0] = ir3_n2b(b, dst[0]);
412 break;
413
414 case nir_op_fneg:
415 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
416 break;
417 case nir_op_fabs:
418 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
419 break;
420 case nir_op_fmax:
421 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
422 break;
423 case nir_op_fmin:
424 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
425 break;
426 case nir_op_fsat:
427 /* if there is just a single use of the src, and it supports
428 * (sat) bit, we can just fold the (sat) flag back to the
429 * src instruction and create a mov. This is easier for cp
430 * to eliminate.
431 *
432 * TODO probably opc_cat==4 is ok too
433 */
434 if (alu->src[0].src.is_ssa &&
435 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
436 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
437 src[0]->flags |= IR3_INSTR_SAT;
438 dst[0] = ir3_MOV(b, src[0], dst_type);
439 } else {
440 /* otherwise generate a max.f that saturates.. blob does
441 * similar (generating a cat2 mov using max.f)
442 */
443 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
444 dst[0]->flags |= IR3_INSTR_SAT;
445 }
446 break;
447 case nir_op_fmul:
448 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
449 break;
450 case nir_op_fadd:
451 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
452 break;
453 case nir_op_fsub:
454 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
455 break;
456 case nir_op_ffma:
457 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
458 break;
459 case nir_op_fddx:
460 case nir_op_fddx_coarse:
461 dst[0] = ir3_DSX(b, src[0], 0);
462 dst[0]->cat5.type = TYPE_F32;
463 break;
464 case nir_op_fddy:
465 case nir_op_fddy_coarse:
466 dst[0] = ir3_DSY(b, src[0], 0);
467 dst[0]->cat5.type = TYPE_F32;
468 break;
469 break;
470 case nir_op_flt32:
471 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
472 dst[0]->cat2.condition = IR3_COND_LT;
473 dst[0] = ir3_n2b(b, dst[0]);
474 break;
475 case nir_op_fge32:
476 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
477 dst[0]->cat2.condition = IR3_COND_GE;
478 dst[0] = ir3_n2b(b, dst[0]);
479 break;
480 case nir_op_feq32:
481 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
482 dst[0]->cat2.condition = IR3_COND_EQ;
483 dst[0] = ir3_n2b(b, dst[0]);
484 break;
485 case nir_op_fne32:
486 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
487 dst[0]->cat2.condition = IR3_COND_NE;
488 dst[0] = ir3_n2b(b, dst[0]);
489 break;
490 case nir_op_fceil:
491 dst[0] = ir3_CEIL_F(b, src[0], 0);
492 break;
493 case nir_op_ffloor:
494 dst[0] = ir3_FLOOR_F(b, src[0], 0);
495 break;
496 case nir_op_ftrunc:
497 dst[0] = ir3_TRUNC_F(b, src[0], 0);
498 break;
499 case nir_op_fround_even:
500 dst[0] = ir3_RNDNE_F(b, src[0], 0);
501 break;
502 case nir_op_fsign:
503 dst[0] = ir3_SIGN_F(b, src[0], 0);
504 break;
505
506 case nir_op_fsin:
507 dst[0] = ir3_SIN(b, src[0], 0);
508 break;
509 case nir_op_fcos:
510 dst[0] = ir3_COS(b, src[0], 0);
511 break;
512 case nir_op_frsq:
513 dst[0] = ir3_RSQ(b, src[0], 0);
514 break;
515 case nir_op_frcp:
516 dst[0] = ir3_RCP(b, src[0], 0);
517 break;
518 case nir_op_flog2:
519 dst[0] = ir3_LOG2(b, src[0], 0);
520 break;
521 case nir_op_fexp2:
522 dst[0] = ir3_EXP2(b, src[0], 0);
523 break;
524 case nir_op_fsqrt:
525 dst[0] = ir3_SQRT(b, src[0], 0);
526 break;
527
528 case nir_op_iabs:
529 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
530 break;
531 case nir_op_iadd:
532 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
533 break;
534 case nir_op_iand:
535 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
536 break;
537 case nir_op_imax:
538 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
539 break;
540 case nir_op_umax:
541 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
542 break;
543 case nir_op_imin:
544 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
545 break;
546 case nir_op_umin:
547 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
548 break;
549 case nir_op_umul_low:
550 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
551 break;
552 case nir_op_imadsh_mix16:
553 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
554 break;
555 case nir_op_imad24_ir3:
556 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
557 break;
558 case nir_op_imul24:
559 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
560 break;
561 case nir_op_ineg:
562 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
563 break;
564 case nir_op_inot:
565 dst[0] = ir3_NOT_B(b, src[0], 0);
566 break;
567 case nir_op_ior:
568 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
569 break;
570 case nir_op_ishl:
571 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
572 break;
573 case nir_op_ishr:
574 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
575 break;
576 case nir_op_isub:
577 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
578 break;
579 case nir_op_ixor:
580 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
581 break;
582 case nir_op_ushr:
583 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
584 break;
585 case nir_op_ilt32:
586 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
587 dst[0]->cat2.condition = IR3_COND_LT;
588 dst[0] = ir3_n2b(b, dst[0]);
589 break;
590 case nir_op_ige32:
591 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
592 dst[0]->cat2.condition = IR3_COND_GE;
593 dst[0] = ir3_n2b(b, dst[0]);
594 break;
595 case nir_op_ieq32:
596 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
597 dst[0]->cat2.condition = IR3_COND_EQ;
598 dst[0] = ir3_n2b(b, dst[0]);
599 break;
600 case nir_op_ine32:
601 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
602 dst[0]->cat2.condition = IR3_COND_NE;
603 dst[0] = ir3_n2b(b, dst[0]);
604 break;
605 case nir_op_ult32:
606 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
607 dst[0]->cat2.condition = IR3_COND_LT;
608 dst[0] = ir3_n2b(b, dst[0]);
609 break;
610 case nir_op_uge32:
611 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
612 dst[0]->cat2.condition = IR3_COND_GE;
613 dst[0] = ir3_n2b(b, dst[0]);
614 break;
615
616 case nir_op_b32csel: {
617 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
618 compile_assert(ctx, bs[1] == bs[2]);
619 /* the boolean condition is 32b even if src[1] and src[2] are
620 * half-precision, but sel.b16 wants all three src's to be the
621 * same type.
622 */
623 if (bs[1] < 32)
624 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
625 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
626 break;
627 }
628 case nir_op_bit_count: {
629 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
630 // double check on earlier gen's. Once half-precision support is
631 // in place, this should probably move to a NIR lowering pass:
632 struct ir3_instruction *hi, *lo;
633
634 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
635 TYPE_U32, TYPE_U16);
636 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
637
638 hi = ir3_CBITS_B(b, hi, 0);
639 lo = ir3_CBITS_B(b, lo, 0);
640
641 // TODO maybe the builders should default to making dst half-precision
642 // if the src's were half precision, to make this less awkward.. otoh
643 // we should probably just do this lowering in NIR.
644 hi->regs[0]->flags |= IR3_REG_HALF;
645 lo->regs[0]->flags |= IR3_REG_HALF;
646
647 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
648 dst[0]->regs[0]->flags |= IR3_REG_HALF;
649 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
650 break;
651 }
652 case nir_op_ifind_msb: {
653 struct ir3_instruction *cmp;
654 dst[0] = ir3_CLZ_S(b, src[0], 0);
655 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
656 cmp->cat2.condition = IR3_COND_GE;
657 dst[0] = ir3_SEL_B32(b,
658 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
659 cmp, 0, dst[0], 0);
660 break;
661 }
662 case nir_op_ufind_msb:
663 dst[0] = ir3_CLZ_B(b, src[0], 0);
664 dst[0] = ir3_SEL_B32(b,
665 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
666 src[0], 0, dst[0], 0);
667 break;
668 case nir_op_find_lsb:
669 dst[0] = ir3_BFREV_B(b, src[0], 0);
670 dst[0] = ir3_CLZ_B(b, dst[0], 0);
671 break;
672 case nir_op_bitfield_reverse:
673 dst[0] = ir3_BFREV_B(b, src[0], 0);
674 break;
675
676 default:
677 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
678 nir_op_infos[alu->op].name);
679 break;
680 }
681
682 ir3_put_dst(ctx, &alu->dest.dest);
683 }
684
685 /* handles direct/indirect UBO reads: */
686 static void
687 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
688 struct ir3_instruction **dst)
689 {
690 struct ir3_block *b = ctx->block;
691 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
692 /* UBO addresses are the first driver params, but subtract 2 here to
693 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
694 * is the uniforms: */
695 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
696 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
697 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
698
699 int off = 0;
700
701 /* First src is ubo index, which could either be an immed or not: */
702 src0 = ir3_get_src(ctx, &intr->src[0])[0];
703 if (is_same_type_mov(src0) &&
704 (src0->regs[1]->flags & IR3_REG_IMMED)) {
705 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
706 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
707 } else {
708 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
709 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
710
711 /* NOTE: since relative addressing is used, make sure constlen is
712 * at least big enough to cover all the UBO addresses, since the
713 * assembler won't know what the max address reg is.
714 */
715 ctx->so->constlen = MAX2(ctx->so->constlen,
716 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
717 }
718
719 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
720 addr = base_lo;
721
722 if (nir_src_is_const(intr->src[1])) {
723 off += nir_src_as_uint(intr->src[1]);
724 } else {
725 /* For load_ubo_indirect, second src is indirect offset: */
726 src1 = ir3_get_src(ctx, &intr->src[1])[0];
727
728 /* and add offset to addr: */
729 addr = ir3_ADD_S(b, addr, 0, src1, 0);
730 }
731
732 /* if offset is to large to encode in the ldg, split it out: */
733 if ((off + (intr->num_components * 4)) > 1024) {
734 /* split out the minimal amount to improve the odds that
735 * cp can fit the immediate in the add.s instruction:
736 */
737 unsigned off2 = off + (intr->num_components * 4) - 1024;
738 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
739 off -= off2;
740 }
741
742 if (ptrsz == 2) {
743 struct ir3_instruction *carry;
744
745 /* handle 32b rollover, ie:
746 * if (addr < base_lo)
747 * base_hi++
748 */
749 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
750 carry->cat2.condition = IR3_COND_LT;
751 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
752
753 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
754 }
755
756 for (int i = 0; i < intr->num_components; i++) {
757 struct ir3_instruction *load =
758 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
759 create_immed(b, off + i * 4), 0);
760 load->cat6.type = TYPE_U32;
761 dst[i] = load;
762 }
763 }
764
765 /* src[] = { block_index } */
766 static void
767 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
768 struct ir3_instruction **dst)
769 {
770 /* SSBO size stored as a const starting at ssbo_sizes: */
771 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
772 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
773 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
774 const_state->ssbo_size.off[blk_idx];
775
776 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
777
778 dst[0] = create_uniform(ctx->block, idx);
779 }
780
781 /* src[] = { offset }. const_index[] = { base } */
782 static void
783 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
784 struct ir3_instruction **dst)
785 {
786 struct ir3_block *b = ctx->block;
787 struct ir3_instruction *ldl, *offset;
788 unsigned base;
789
790 offset = ir3_get_src(ctx, &intr->src[0])[0];
791 base = nir_intrinsic_base(intr);
792
793 ldl = ir3_LDL(b, offset, 0,
794 create_immed(b, intr->num_components), 0,
795 create_immed(b, base), 0);
796
797 ldl->cat6.type = utype_dst(intr->dest);
798 ldl->regs[0]->wrmask = MASK(intr->num_components);
799
800 ldl->barrier_class = IR3_BARRIER_SHARED_R;
801 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
802
803 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
804 }
805
806 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
807 static void
808 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
809 {
810 struct ir3_block *b = ctx->block;
811 struct ir3_instruction *stl, *offset;
812 struct ir3_instruction * const *value;
813 unsigned base, wrmask;
814
815 value = ir3_get_src(ctx, &intr->src[0]);
816 offset = ir3_get_src(ctx, &intr->src[1])[0];
817
818 base = nir_intrinsic_base(intr);
819 wrmask = nir_intrinsic_write_mask(intr);
820
821 /* Combine groups of consecutive enabled channels in one write
822 * message. We use ffs to find the first enabled channel and then ffs on
823 * the bit-inverse, down-shifted writemask to determine the length of
824 * the block of enabled bits.
825 *
826 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
827 */
828 while (wrmask) {
829 unsigned first_component = ffs(wrmask) - 1;
830 unsigned length = ffs(~(wrmask >> first_component)) - 1;
831
832 stl = ir3_STL(b, offset, 0,
833 ir3_create_collect(ctx, &value[first_component], length), 0,
834 create_immed(b, length), 0);
835 stl->cat6.dst_offset = first_component + base;
836 stl->cat6.type = utype_src(intr->src[0]);
837 stl->barrier_class = IR3_BARRIER_SHARED_W;
838 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
839
840 array_insert(b, b->keeps, stl);
841
842 /* Clear the bits in the writemask that we just wrote, then try
843 * again to see if more channels are left.
844 */
845 wrmask &= (15 << (first_component + length));
846 }
847 }
848
849 /* src[] = { offset }. const_index[] = { base } */
850 static void
851 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
852 struct ir3_instruction **dst)
853 {
854 struct ir3_block *b = ctx->block;
855 struct ir3_instruction *load, *offset;
856 unsigned base;
857
858 offset = ir3_get_src(ctx, &intr->src[0])[0];
859 base = nir_intrinsic_base(intr);
860
861 load = ir3_LDLW(b, offset, 0,
862 create_immed(b, intr->num_components), 0,
863 create_immed(b, base), 0);
864
865 load->cat6.type = utype_dst(intr->dest);
866 load->regs[0]->wrmask = MASK(intr->num_components);
867
868 load->barrier_class = IR3_BARRIER_SHARED_R;
869 load->barrier_conflict = IR3_BARRIER_SHARED_W;
870
871 ir3_split_dest(b, dst, load, 0, intr->num_components);
872 }
873
874 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
875 static void
876 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
877 {
878 struct ir3_block *b = ctx->block;
879 struct ir3_instruction *store, *offset;
880 struct ir3_instruction * const *value;
881 unsigned base, wrmask;
882
883 value = ir3_get_src(ctx, &intr->src[0]);
884 offset = ir3_get_src(ctx, &intr->src[1])[0];
885
886 base = nir_intrinsic_base(intr);
887 wrmask = nir_intrinsic_write_mask(intr);
888
889 /* Combine groups of consecutive enabled channels in one write
890 * message. We use ffs to find the first enabled channel and then ffs on
891 * the bit-inverse, down-shifted writemask to determine the length of
892 * the block of enabled bits.
893 *
894 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
895 */
896 while (wrmask) {
897 unsigned first_component = ffs(wrmask) - 1;
898 unsigned length = ffs(~(wrmask >> first_component)) - 1;
899
900 store = ir3_STLW(b, offset, 0,
901 ir3_create_collect(ctx, &value[first_component], length), 0,
902 create_immed(b, length), 0);
903
904 store->cat6.dst_offset = first_component + base;
905 store->cat6.type = utype_src(intr->src[0]);
906 store->barrier_class = IR3_BARRIER_SHARED_W;
907 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
908
909 array_insert(b, b->keeps, store);
910
911 /* Clear the bits in the writemask that we just wrote, then try
912 * again to see if more channels are left.
913 */
914 wrmask &= (15 << (first_component + length));
915 }
916 }
917
918 /*
919 * CS shared variable atomic intrinsics
920 *
921 * All of the shared variable atomic memory operations read a value from
922 * memory, compute a new value using one of the operations below, write the
923 * new value to memory, and return the original value read.
924 *
925 * All operations take 2 sources except CompSwap that takes 3. These
926 * sources represent:
927 *
928 * 0: The offset into the shared variable storage region that the atomic
929 * operation will operate on.
930 * 1: The data parameter to the atomic function (i.e. the value to add
931 * in shared_atomic_add, etc).
932 * 2: For CompSwap only: the second data parameter.
933 */
934 static struct ir3_instruction *
935 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
936 {
937 struct ir3_block *b = ctx->block;
938 struct ir3_instruction *atomic, *src0, *src1;
939 type_t type = TYPE_U32;
940
941 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
942 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
943
944 switch (intr->intrinsic) {
945 case nir_intrinsic_shared_atomic_add:
946 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
947 break;
948 case nir_intrinsic_shared_atomic_imin:
949 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
950 type = TYPE_S32;
951 break;
952 case nir_intrinsic_shared_atomic_umin:
953 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
954 break;
955 case nir_intrinsic_shared_atomic_imax:
956 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
957 type = TYPE_S32;
958 break;
959 case nir_intrinsic_shared_atomic_umax:
960 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
961 break;
962 case nir_intrinsic_shared_atomic_and:
963 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
964 break;
965 case nir_intrinsic_shared_atomic_or:
966 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
967 break;
968 case nir_intrinsic_shared_atomic_xor:
969 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
970 break;
971 case nir_intrinsic_shared_atomic_exchange:
972 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
973 break;
974 case nir_intrinsic_shared_atomic_comp_swap:
975 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
976 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
977 ir3_get_src(ctx, &intr->src[2])[0],
978 src1,
979 }, 2);
980 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
981 break;
982 default:
983 unreachable("boo");
984 }
985
986 atomic->cat6.iim_val = 1;
987 atomic->cat6.d = 1;
988 atomic->cat6.type = type;
989 atomic->barrier_class = IR3_BARRIER_SHARED_W;
990 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
991
992 /* even if nothing consume the result, we can't DCE the instruction: */
993 array_insert(b, b->keeps, atomic);
994
995 return atomic;
996 }
997
998 /* TODO handle actual indirect/dynamic case.. which is going to be weird
999 * to handle with the image_mapping table..
1000 */
1001 static struct ir3_instruction *
1002 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1003 {
1004 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
1005 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1006 struct ir3_instruction *texture, *sampler;
1007
1008 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1009 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1010
1011 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1012 sampler,
1013 texture,
1014 }, 2);
1015 }
1016
1017 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1018 static void
1019 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1020 struct ir3_instruction **dst)
1021 {
1022 struct ir3_block *b = ctx->block;
1023 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1024 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1025 struct ir3_instruction *sam;
1026 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1027 struct ir3_instruction *coords[4];
1028 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1029 type_t type = ir3_get_image_type(var);
1030
1031 /* hmm, this seems a bit odd, but it is what blob does and (at least
1032 * a5xx) just faults on bogus addresses otherwise:
1033 */
1034 if (flags & IR3_INSTR_3D) {
1035 flags &= ~IR3_INSTR_3D;
1036 flags |= IR3_INSTR_A;
1037 }
1038
1039 for (unsigned i = 0; i < ncoords; i++)
1040 coords[i] = src0[i];
1041
1042 if (ncoords == 1)
1043 coords[ncoords++] = create_immed(b, 0);
1044
1045 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
1046 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
1047
1048 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1049 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1050
1051 ir3_split_dest(b, dst, sam, 0, 4);
1052 }
1053
1054 static void
1055 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1056 struct ir3_instruction **dst)
1057 {
1058 struct ir3_block *b = ctx->block;
1059 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1060 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1061 struct ir3_instruction *sam, *lod;
1062 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1063
1064 lod = create_immed(b, 0);
1065 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
1066 samp_tex, lod, NULL);
1067
1068 /* Array size actually ends up in .w rather than .z. This doesn't
1069 * matter for miplevel 0, but for higher mips the value in z is
1070 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1071 * returned, which means that we have to add 1 to it for arrays for
1072 * a3xx.
1073 *
1074 * Note use a temporary dst and then copy, since the size of the dst
1075 * array that is passed in is based on nir's understanding of the
1076 * result size, not the hardware's
1077 */
1078 struct ir3_instruction *tmp[4];
1079
1080 ir3_split_dest(b, tmp, sam, 0, 4);
1081
1082 /* get_size instruction returns size in bytes instead of texels
1083 * for imageBuffer, so we need to divide it by the pixel size
1084 * of the image format.
1085 *
1086 * TODO: This is at least true on a5xx. Check other gens.
1087 */
1088 enum glsl_sampler_dim dim =
1089 glsl_get_sampler_dim(glsl_without_array(var->type));
1090 if (dim == GLSL_SAMPLER_DIM_BUF) {
1091 /* Since all the possible values the divisor can take are
1092 * power-of-two (4, 8, or 16), the division is implemented
1093 * as a shift-right.
1094 * During shader setup, the log2 of the image format's
1095 * bytes-per-pixel should have been emitted in 2nd slot of
1096 * image_dims. See ir3_shader::emit_image_dims().
1097 */
1098 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1099 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1100 const_state->image_dims.off[var->data.driver_location];
1101 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1102
1103 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1104 }
1105
1106 for (unsigned i = 0; i < ncoords; i++)
1107 dst[i] = tmp[i];
1108
1109 if (flags & IR3_INSTR_A) {
1110 if (ctx->compiler->levels_add_one) {
1111 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1112 } else {
1113 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1114 }
1115 }
1116 }
1117
1118 static void
1119 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1120 {
1121 struct ir3_block *b = ctx->block;
1122 struct ir3_instruction *barrier;
1123
1124 switch (intr->intrinsic) {
1125 case nir_intrinsic_barrier:
1126 barrier = ir3_BAR(b);
1127 barrier->cat7.g = true;
1128 barrier->cat7.l = true;
1129 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1130 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1131 break;
1132 case nir_intrinsic_memory_barrier:
1133 barrier = ir3_FENCE(b);
1134 barrier->cat7.g = true;
1135 barrier->cat7.r = true;
1136 barrier->cat7.w = true;
1137 barrier->cat7.l = true;
1138 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1139 IR3_BARRIER_BUFFER_W;
1140 barrier->barrier_conflict =
1141 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1142 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1143 break;
1144 case nir_intrinsic_memory_barrier_atomic_counter:
1145 case nir_intrinsic_memory_barrier_buffer:
1146 barrier = ir3_FENCE(b);
1147 barrier->cat7.g = true;
1148 barrier->cat7.r = true;
1149 barrier->cat7.w = true;
1150 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1151 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1152 IR3_BARRIER_BUFFER_W;
1153 break;
1154 case nir_intrinsic_memory_barrier_image:
1155 // TODO double check if this should have .g set
1156 barrier = ir3_FENCE(b);
1157 barrier->cat7.g = true;
1158 barrier->cat7.r = true;
1159 barrier->cat7.w = true;
1160 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1161 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1162 IR3_BARRIER_IMAGE_W;
1163 break;
1164 case nir_intrinsic_memory_barrier_shared:
1165 barrier = ir3_FENCE(b);
1166 barrier->cat7.g = true;
1167 barrier->cat7.l = true;
1168 barrier->cat7.r = true;
1169 barrier->cat7.w = true;
1170 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1171 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1172 IR3_BARRIER_SHARED_W;
1173 break;
1174 case nir_intrinsic_group_memory_barrier:
1175 barrier = ir3_FENCE(b);
1176 barrier->cat7.g = true;
1177 barrier->cat7.l = true;
1178 barrier->cat7.r = true;
1179 barrier->cat7.w = true;
1180 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1181 IR3_BARRIER_IMAGE_W |
1182 IR3_BARRIER_BUFFER_W;
1183 barrier->barrier_conflict =
1184 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1185 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1186 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1187 break;
1188 default:
1189 unreachable("boo");
1190 }
1191
1192 /* make sure barrier doesn't get DCE'd */
1193 array_insert(b, b->keeps, barrier);
1194 }
1195
1196 static void add_sysval_input_compmask(struct ir3_context *ctx,
1197 gl_system_value slot, unsigned compmask,
1198 struct ir3_instruction *instr)
1199 {
1200 struct ir3_shader_variant *so = ctx->so;
1201 unsigned r = regid(so->inputs_count, 0);
1202 unsigned n = so->inputs_count++;
1203
1204 assert(instr->opc == OPC_META_INPUT);
1205 instr->input.sysval = slot;
1206
1207 so->inputs[n].sysval = true;
1208 so->inputs[n].slot = slot;
1209 so->inputs[n].compmask = compmask;
1210 so->inputs[n].regid = r;
1211 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1212 so->total_in++;
1213
1214 ctx->ir->ninputs = MAX2(ctx->ir->ninputs, r + 1);
1215 ctx->ir->inputs[r] = instr;
1216 }
1217
1218 static struct ir3_instruction *
1219 create_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1220 unsigned compmask)
1221 {
1222 assert(compmask);
1223 struct ir3_instruction *sysval = create_input_compmask(ctx, 0, compmask);
1224 add_sysval_input_compmask(ctx, slot, compmask, sysval);
1225 return sysval;
1226 }
1227
1228 static struct ir3_instruction *
1229 get_barycentric_centroid(struct ir3_context *ctx)
1230 {
1231 if (!ctx->ij_centroid) {
1232 struct ir3_instruction *xy[2];
1233 struct ir3_instruction *ij;
1234
1235 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_CENTROID, 0x3);
1236 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1237
1238 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1239 }
1240
1241 return ctx->ij_centroid;
1242 }
1243
1244 static struct ir3_instruction *
1245 get_barycentric_sample(struct ir3_context *ctx)
1246 {
1247 if (!ctx->ij_sample) {
1248 struct ir3_instruction *xy[2];
1249 struct ir3_instruction *ij;
1250
1251 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SAMPLE, 0x3);
1252 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1253
1254 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1255 }
1256
1257 return ctx->ij_sample;
1258 }
1259
1260 static struct ir3_instruction *
1261 get_barycentric_pixel(struct ir3_context *ctx)
1262 {
1263 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1264 * this to create ij_pixel only on demand:
1265 */
1266 return ctx->ij_pixel;
1267 }
1268
1269 static struct ir3_instruction *
1270 get_frag_coord(struct ir3_context *ctx)
1271 {
1272 if (!ctx->frag_coord) {
1273 struct ir3_block *b = ctx->block;
1274 struct ir3_instruction *xyzw[4];
1275 struct ir3_instruction *hw_frag_coord;
1276
1277 hw_frag_coord = create_sysval_input(ctx, SYSTEM_VALUE_FRAG_COORD, 0xf);
1278 ir3_split_dest(ctx->block, xyzw, hw_frag_coord, 0, 4);
1279
1280 /* for frag_coord.xy, we get unsigned values.. we need
1281 * to subtract (integer) 8 and divide by 16 (right-
1282 * shift by 4) then convert to float:
1283 *
1284 * sub.s tmp, src, 8
1285 * shr.b tmp, tmp, 4
1286 * mov.u32f32 dst, tmp
1287 *
1288 */
1289 for (int i = 0; i < 2; i++) {
1290 xyzw[i] = ir3_SUB_S(b, xyzw[i], 0,
1291 create_immed(b, 8), 0);
1292 xyzw[i] = ir3_SHR_B(b, xyzw[i], 0,
1293 create_immed(b, 4), 0);
1294 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1295 }
1296
1297 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1298 ctx->so->frag_coord = true;
1299 }
1300
1301 return ctx->frag_coord;
1302 }
1303
1304 static void
1305 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1306 {
1307 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1308 struct ir3_instruction **dst;
1309 struct ir3_instruction * const *src;
1310 struct ir3_block *b = ctx->block;
1311 int idx, comp;
1312
1313 if (info->has_dest) {
1314 unsigned n = nir_intrinsic_dest_components(intr);
1315 dst = ir3_get_dst(ctx, &intr->dest, n);
1316 } else {
1317 dst = NULL;
1318 }
1319
1320 const unsigned primitive_param = ctx->so->shader->const_state.offsets.primitive_param * 4;
1321 const unsigned primitive_map = ctx->so->shader->const_state.offsets.primitive_map * 4;
1322
1323 switch (intr->intrinsic) {
1324 case nir_intrinsic_load_uniform:
1325 idx = nir_intrinsic_base(intr);
1326 if (nir_src_is_const(intr->src[0])) {
1327 idx += nir_src_as_uint(intr->src[0]);
1328 for (int i = 0; i < intr->num_components; i++) {
1329 dst[i] = create_uniform_typed(b, idx + i,
1330 nir_dest_bit_size(intr->dest) < 32 ? TYPE_F16 : TYPE_F32);
1331 }
1332 } else {
1333 src = ir3_get_src(ctx, &intr->src[0]);
1334 for (int i = 0; i < intr->num_components; i++) {
1335 dst[i] = create_uniform_indirect(b, idx + i,
1336 ir3_get_addr(ctx, src[0], 1));
1337 }
1338 /* NOTE: if relative addressing is used, we set
1339 * constlen in the compiler (to worst-case value)
1340 * since we don't know in the assembler what the max
1341 * addr reg value can be:
1342 */
1343 ctx->so->constlen = MAX2(ctx->so->constlen,
1344 ctx->so->shader->ubo_state.size / 16);
1345 }
1346 break;
1347
1348 case nir_intrinsic_load_vs_primitive_stride_ir3:
1349 dst[0] = create_uniform(b, primitive_param + 0);
1350 break;
1351 case nir_intrinsic_load_vs_vertex_stride_ir3:
1352 dst[0] = create_uniform(b, primitive_param + 1);
1353 break;
1354 case nir_intrinsic_load_hs_patch_stride_ir3:
1355 dst[0] = create_uniform(b, primitive_param + 2);
1356 break;
1357 case nir_intrinsic_load_patch_vertices_in:
1358 dst[0] = create_uniform(b, primitive_param + 3);
1359 break;
1360 case nir_intrinsic_load_tess_param_base_ir3:
1361 dst[0] = create_uniform(b, primitive_param + 4);
1362 dst[1] = create_uniform(b, primitive_param + 5);
1363 break;
1364 case nir_intrinsic_load_tess_factor_base_ir3:
1365 dst[0] = create_uniform(b, primitive_param + 6);
1366 dst[1] = create_uniform(b, primitive_param + 7);
1367 break;
1368
1369 case nir_intrinsic_load_primitive_location_ir3:
1370 idx = nir_intrinsic_driver_location(intr);
1371 dst[0] = create_uniform(b, primitive_map + idx);
1372 break;
1373
1374 case nir_intrinsic_load_gs_header_ir3:
1375 dst[0] = ctx->gs_header;
1376 break;
1377 case nir_intrinsic_load_tcs_header_ir3:
1378 dst[0] = ctx->tcs_header;
1379 break;
1380
1381 case nir_intrinsic_load_primitive_id:
1382 dst[0] = ctx->primitive_id;
1383 break;
1384
1385 case nir_intrinsic_load_tess_coord:
1386 if (!ctx->tess_coord) {
1387 ctx->tess_coord =
1388 create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
1389 }
1390 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1391
1392 /* Unused, but ir3_put_dst() below wants to free something */
1393 dst[2] = create_immed(b, 0);
1394 break;
1395
1396 case nir_intrinsic_end_patch_ir3:
1397 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1398 struct ir3_instruction *end = ir3_ENDPATCH(b);
1399 array_insert(b, b->keeps, end);
1400
1401 end->barrier_class = IR3_BARRIER_EVERYTHING;
1402 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1403 break;
1404
1405 case nir_intrinsic_store_global_ir3: {
1406 struct ir3_instruction *value, *addr, *offset;
1407
1408 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1409 ir3_get_src(ctx, &intr->src[1])[0],
1410 ir3_get_src(ctx, &intr->src[1])[1]
1411 }, 2);
1412
1413 offset = ir3_get_src(ctx, &intr->src[2])[0];
1414
1415 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]),
1416 intr->num_components);
1417
1418 struct ir3_instruction *stg =
1419 ir3_STG_G(ctx->block, addr, 0, value, 0,
1420 create_immed(ctx->block, intr->num_components), 0, offset, 0);
1421 stg->cat6.type = TYPE_U32;
1422 stg->cat6.iim_val = 1;
1423
1424 array_insert(b, b->keeps, stg);
1425
1426 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1427 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1428 break;
1429 }
1430
1431 case nir_intrinsic_load_global_ir3: {
1432 struct ir3_instruction *addr, *offset;
1433
1434 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1435 ir3_get_src(ctx, &intr->src[0])[0],
1436 ir3_get_src(ctx, &intr->src[0])[1]
1437 }, 2);
1438
1439 offset = ir3_get_src(ctx, &intr->src[1])[0];
1440
1441 struct ir3_instruction *load =
1442 ir3_LDG(b, addr, 0, create_immed(ctx->block, intr->num_components),
1443 0, offset, 0);
1444 load->cat6.type = TYPE_U32;
1445 load->regs[0]->wrmask = MASK(intr->num_components);
1446
1447 load->barrier_class = IR3_BARRIER_BUFFER_R;
1448 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1449
1450 ir3_split_dest(b, dst, load, 0, intr->num_components);
1451 break;
1452 }
1453
1454 case nir_intrinsic_load_ubo:
1455 emit_intrinsic_load_ubo(ctx, intr, dst);
1456 break;
1457 case nir_intrinsic_load_frag_coord:
1458 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1459 break;
1460 case nir_intrinsic_load_sample_pos_from_id: {
1461 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1462 * but that doesn't seem necessary.
1463 */
1464 struct ir3_instruction *offset =
1465 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1466 offset->regs[0]->wrmask = 0x3;
1467 offset->cat5.type = TYPE_F32;
1468
1469 ir3_split_dest(b, dst, offset, 0, 2);
1470
1471 break;
1472 }
1473 case nir_intrinsic_load_size_ir3:
1474 if (!ctx->ij_size) {
1475 ctx->ij_size =
1476 create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SIZE, 0x1);
1477 }
1478 dst[0] = ctx->ij_size;
1479 break;
1480 case nir_intrinsic_load_barycentric_centroid:
1481 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1482 break;
1483 case nir_intrinsic_load_barycentric_sample:
1484 if (ctx->so->key.msaa) {
1485 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1486 } else {
1487 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1488 }
1489 break;
1490 case nir_intrinsic_load_barycentric_pixel:
1491 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1492 break;
1493 case nir_intrinsic_load_interpolated_input:
1494 idx = nir_intrinsic_base(intr);
1495 comp = nir_intrinsic_component(intr);
1496 src = ir3_get_src(ctx, &intr->src[0]);
1497 if (nir_src_is_const(intr->src[1])) {
1498 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1499 idx += nir_src_as_uint(intr->src[1]);
1500 for (int i = 0; i < intr->num_components; i++) {
1501 unsigned inloc = idx * 4 + i + comp;
1502 if (ctx->so->inputs[idx].bary &&
1503 !ctx->so->inputs[idx].use_ldlv) {
1504 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1505 } else {
1506 /* for non-varyings use the pre-setup input, since
1507 * that is easier than mapping things back to a
1508 * nir_variable to figure out what it is.
1509 */
1510 dst[i] = ctx->ir->inputs[inloc];
1511 }
1512 }
1513 } else {
1514 ir3_context_error(ctx, "unhandled");
1515 }
1516 break;
1517 case nir_intrinsic_load_input:
1518 idx = nir_intrinsic_base(intr);
1519 comp = nir_intrinsic_component(intr);
1520 if (nir_src_is_const(intr->src[0])) {
1521 idx += nir_src_as_uint(intr->src[0]);
1522 for (int i = 0; i < intr->num_components; i++) {
1523 unsigned n = idx * 4 + i + comp;
1524 dst[i] = ctx->ir->inputs[n];
1525 compile_assert(ctx, ctx->ir->inputs[n]);
1526 }
1527 } else {
1528 src = ir3_get_src(ctx, &intr->src[0]);
1529 struct ir3_instruction *collect =
1530 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ir->ninputs);
1531 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1532 for (int i = 0; i < intr->num_components; i++) {
1533 unsigned n = idx * 4 + i + comp;
1534 dst[i] = create_indirect_load(ctx, ctx->ir->ninputs,
1535 n, addr, collect);
1536 }
1537 }
1538 break;
1539 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1540 * pass and replaced by an ir3-specifc version that adds the
1541 * dword-offset in the last source.
1542 */
1543 case nir_intrinsic_load_ssbo_ir3:
1544 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1545 break;
1546 case nir_intrinsic_store_ssbo_ir3:
1547 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1548 !ctx->s->info.fs.early_fragment_tests)
1549 ctx->so->no_earlyz = true;
1550 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1551 break;
1552 case nir_intrinsic_get_buffer_size:
1553 emit_intrinsic_ssbo_size(ctx, intr, dst);
1554 break;
1555 case nir_intrinsic_ssbo_atomic_add_ir3:
1556 case nir_intrinsic_ssbo_atomic_imin_ir3:
1557 case nir_intrinsic_ssbo_atomic_umin_ir3:
1558 case nir_intrinsic_ssbo_atomic_imax_ir3:
1559 case nir_intrinsic_ssbo_atomic_umax_ir3:
1560 case nir_intrinsic_ssbo_atomic_and_ir3:
1561 case nir_intrinsic_ssbo_atomic_or_ir3:
1562 case nir_intrinsic_ssbo_atomic_xor_ir3:
1563 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1564 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1565 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1566 !ctx->s->info.fs.early_fragment_tests)
1567 ctx->so->no_earlyz = true;
1568 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1569 break;
1570 case nir_intrinsic_load_shared:
1571 emit_intrinsic_load_shared(ctx, intr, dst);
1572 break;
1573 case nir_intrinsic_store_shared:
1574 emit_intrinsic_store_shared(ctx, intr);
1575 break;
1576 case nir_intrinsic_shared_atomic_add:
1577 case nir_intrinsic_shared_atomic_imin:
1578 case nir_intrinsic_shared_atomic_umin:
1579 case nir_intrinsic_shared_atomic_imax:
1580 case nir_intrinsic_shared_atomic_umax:
1581 case nir_intrinsic_shared_atomic_and:
1582 case nir_intrinsic_shared_atomic_or:
1583 case nir_intrinsic_shared_atomic_xor:
1584 case nir_intrinsic_shared_atomic_exchange:
1585 case nir_intrinsic_shared_atomic_comp_swap:
1586 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1587 break;
1588 case nir_intrinsic_image_deref_load:
1589 emit_intrinsic_load_image(ctx, intr, dst);
1590 break;
1591 case nir_intrinsic_image_deref_store:
1592 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1593 !ctx->s->info.fs.early_fragment_tests)
1594 ctx->so->no_earlyz = true;
1595 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1596 break;
1597 case nir_intrinsic_image_deref_size:
1598 emit_intrinsic_image_size(ctx, intr, dst);
1599 break;
1600 case nir_intrinsic_image_deref_atomic_add:
1601 case nir_intrinsic_image_deref_atomic_imin:
1602 case nir_intrinsic_image_deref_atomic_umin:
1603 case nir_intrinsic_image_deref_atomic_imax:
1604 case nir_intrinsic_image_deref_atomic_umax:
1605 case nir_intrinsic_image_deref_atomic_and:
1606 case nir_intrinsic_image_deref_atomic_or:
1607 case nir_intrinsic_image_deref_atomic_xor:
1608 case nir_intrinsic_image_deref_atomic_exchange:
1609 case nir_intrinsic_image_deref_atomic_comp_swap:
1610 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1611 !ctx->s->info.fs.early_fragment_tests)
1612 ctx->so->no_earlyz = true;
1613 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1614 break;
1615 case nir_intrinsic_barrier:
1616 case nir_intrinsic_memory_barrier:
1617 case nir_intrinsic_group_memory_barrier:
1618 case nir_intrinsic_memory_barrier_atomic_counter:
1619 case nir_intrinsic_memory_barrier_buffer:
1620 case nir_intrinsic_memory_barrier_image:
1621 case nir_intrinsic_memory_barrier_shared:
1622 emit_intrinsic_barrier(ctx, intr);
1623 /* note that blk ptr no longer valid, make that obvious: */
1624 b = NULL;
1625 break;
1626 case nir_intrinsic_store_output:
1627 idx = nir_intrinsic_base(intr);
1628 comp = nir_intrinsic_component(intr);
1629 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1630 idx += nir_src_as_uint(intr->src[1]);
1631
1632 src = ir3_get_src(ctx, &intr->src[0]);
1633 for (int i = 0; i < intr->num_components; i++) {
1634 unsigned n = idx * 4 + i + comp;
1635 ctx->ir->outputs[n] = src[i];
1636 }
1637 break;
1638 case nir_intrinsic_load_base_vertex:
1639 case nir_intrinsic_load_first_vertex:
1640 if (!ctx->basevertex) {
1641 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1642 }
1643 dst[0] = ctx->basevertex;
1644 break;
1645 case nir_intrinsic_load_vertex_id_zero_base:
1646 case nir_intrinsic_load_vertex_id:
1647 if (!ctx->vertex_id) {
1648 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1649 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1650 ctx->vertex_id = create_sysval_input(ctx, sv, 0x1);
1651 }
1652 dst[0] = ctx->vertex_id;
1653 break;
1654 case nir_intrinsic_load_instance_id:
1655 if (!ctx->instance_id) {
1656 ctx->instance_id = create_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 0x1);
1657 }
1658 dst[0] = ctx->instance_id;
1659 break;
1660 case nir_intrinsic_load_sample_id:
1661 ctx->so->per_samp = true;
1662 /* fall-thru */
1663 case nir_intrinsic_load_sample_id_no_per_sample:
1664 if (!ctx->samp_id) {
1665 ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1);
1666 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1667 }
1668 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1669 break;
1670 case nir_intrinsic_load_sample_mask_in:
1671 if (!ctx->samp_mask_in) {
1672 ctx->samp_mask_in = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
1673 }
1674 dst[0] = ctx->samp_mask_in;
1675 break;
1676 case nir_intrinsic_load_user_clip_plane:
1677 idx = nir_intrinsic_ucp_id(intr);
1678 for (int i = 0; i < intr->num_components; i++) {
1679 unsigned n = idx * 4 + i;
1680 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1681 }
1682 break;
1683 case nir_intrinsic_load_front_face:
1684 if (!ctx->frag_face) {
1685 ctx->so->frag_face = true;
1686 ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1);
1687 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1688 }
1689 /* for fragface, we get -1 for back and 0 for front. However this is
1690 * the inverse of what nir expects (where ~0 is true).
1691 */
1692 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1693 dst[0] = ir3_NOT_B(b, dst[0], 0);
1694 break;
1695 case nir_intrinsic_load_local_invocation_id:
1696 if (!ctx->local_invocation_id) {
1697 ctx->local_invocation_id =
1698 create_sysval_input(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 0x7);
1699 }
1700 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1701 break;
1702 case nir_intrinsic_load_work_group_id:
1703 if (!ctx->work_group_id) {
1704 ctx->work_group_id =
1705 create_sysval_input(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 0x7);
1706 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1707 }
1708 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1709 break;
1710 case nir_intrinsic_load_num_work_groups:
1711 for (int i = 0; i < intr->num_components; i++) {
1712 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1713 }
1714 break;
1715 case nir_intrinsic_load_local_group_size:
1716 for (int i = 0; i < intr->num_components; i++) {
1717 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1718 }
1719 break;
1720 case nir_intrinsic_discard_if:
1721 case nir_intrinsic_discard: {
1722 struct ir3_instruction *cond, *kill;
1723
1724 if (intr->intrinsic == nir_intrinsic_discard_if) {
1725 /* conditional discard: */
1726 src = ir3_get_src(ctx, &intr->src[0]);
1727 cond = ir3_b2n(b, src[0]);
1728 } else {
1729 /* unconditional discard: */
1730 cond = create_immed(b, 1);
1731 }
1732
1733 /* NOTE: only cmps.*.* can write p0.x: */
1734 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1735 cond->cat2.condition = IR3_COND_NE;
1736
1737 /* condition always goes in predicate register: */
1738 cond->regs[0]->num = regid(REG_P0, 0);
1739 cond->regs[0]->flags &= ~IR3_REG_SSA;
1740
1741 kill = ir3_KILL(b, cond, 0);
1742 array_insert(ctx->ir, ctx->ir->predicates, kill);
1743
1744 array_insert(b, b->keeps, kill);
1745 ctx->so->no_earlyz = true;
1746
1747 break;
1748 }
1749
1750 case nir_intrinsic_cond_end_ir3: {
1751 struct ir3_instruction *cond, *kill;
1752
1753 src = ir3_get_src(ctx, &intr->src[0]);
1754 cond = ir3_b2n(b, src[0]);
1755
1756 /* NOTE: only cmps.*.* can write p0.x: */
1757 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1758 cond->cat2.condition = IR3_COND_NE;
1759
1760 /* condition always goes in predicate register: */
1761 cond->regs[0]->num = regid(REG_P0, 0);
1762
1763 kill = ir3_CONDEND(b, cond, 0);
1764
1765 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1766 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1767
1768 array_insert(ctx->ir, ctx->ir->predicates, kill);
1769 array_insert(b, b->keeps, kill);
1770 break;
1771 }
1772
1773 case nir_intrinsic_load_shared_ir3:
1774 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1775 break;
1776 case nir_intrinsic_store_shared_ir3:
1777 emit_intrinsic_store_shared_ir3(ctx, intr);
1778 break;
1779 default:
1780 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1781 nir_intrinsic_infos[intr->intrinsic].name);
1782 break;
1783 }
1784
1785 if (info->has_dest)
1786 ir3_put_dst(ctx, &intr->dest);
1787 }
1788
1789 static void
1790 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1791 {
1792 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1793 instr->def.num_components);
1794
1795 if (instr->def.bit_size < 32) {
1796 for (int i = 0; i < instr->def.num_components; i++)
1797 dst[i] = create_immed_typed(ctx->block,
1798 instr->value[i].u16,
1799 TYPE_U16);
1800 } else {
1801 for (int i = 0; i < instr->def.num_components; i++)
1802 dst[i] = create_immed_typed(ctx->block,
1803 instr->value[i].u32,
1804 TYPE_U32);
1805 }
1806
1807 }
1808
1809 static void
1810 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1811 {
1812 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1813 undef->def.num_components);
1814 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1815
1816 /* backend doesn't want undefined instructions, so just plug
1817 * in 0.0..
1818 */
1819 for (int i = 0; i < undef->def.num_components; i++)
1820 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1821 }
1822
1823 /*
1824 * texture fetch/sample instructions:
1825 */
1826
1827 static void
1828 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1829 {
1830 unsigned coords, flags = 0;
1831
1832 /* note: would use tex->coord_components.. except txs.. also,
1833 * since array index goes after shadow ref, we don't want to
1834 * count it:
1835 */
1836 switch (tex->sampler_dim) {
1837 case GLSL_SAMPLER_DIM_1D:
1838 case GLSL_SAMPLER_DIM_BUF:
1839 coords = 1;
1840 break;
1841 case GLSL_SAMPLER_DIM_2D:
1842 case GLSL_SAMPLER_DIM_RECT:
1843 case GLSL_SAMPLER_DIM_EXTERNAL:
1844 case GLSL_SAMPLER_DIM_MS:
1845 coords = 2;
1846 break;
1847 case GLSL_SAMPLER_DIM_3D:
1848 case GLSL_SAMPLER_DIM_CUBE:
1849 coords = 3;
1850 flags |= IR3_INSTR_3D;
1851 break;
1852 default:
1853 unreachable("bad sampler_dim");
1854 }
1855
1856 if (tex->is_shadow && tex->op != nir_texop_lod)
1857 flags |= IR3_INSTR_S;
1858
1859 if (tex->is_array && tex->op != nir_texop_lod)
1860 flags |= IR3_INSTR_A;
1861
1862 *flagsp = flags;
1863 *coordsp = coords;
1864 }
1865
1866 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1867 * or immediate (in which case it will get lowered later to a non .s2en
1868 * version of the tex instruction which encode tex/samp as immediates:
1869 */
1870 static struct ir3_instruction *
1871 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1872 {
1873 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1874 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1875 struct ir3_instruction *texture, *sampler;
1876
1877 if (texture_idx >= 0) {
1878 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1879 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1880 } else {
1881 /* TODO what to do for dynamic case? I guess we only need the
1882 * max index for astc srgb workaround so maybe not a problem
1883 * to worry about if we don't enable indirect samplers for
1884 * a4xx?
1885 */
1886 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1887 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1888 }
1889
1890 if (sampler_idx >= 0) {
1891 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1892 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1893 } else {
1894 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1895 }
1896
1897 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1898 sampler,
1899 texture,
1900 }, 2);
1901 }
1902
1903 static void
1904 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1905 {
1906 struct ir3_block *b = ctx->block;
1907 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1908 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1909 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1910 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1911 unsigned i, coords, flags, ncomp;
1912 unsigned nsrc0 = 0, nsrc1 = 0;
1913 type_t type;
1914 opc_t opc = 0;
1915
1916 ncomp = nir_dest_num_components(tex->dest);
1917
1918 coord = off = ddx = ddy = NULL;
1919 lod = proj = compare = sample_index = NULL;
1920
1921 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1922
1923 for (unsigned i = 0; i < tex->num_srcs; i++) {
1924 switch (tex->src[i].src_type) {
1925 case nir_tex_src_coord:
1926 coord = ir3_get_src(ctx, &tex->src[i].src);
1927 break;
1928 case nir_tex_src_bias:
1929 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1930 has_bias = true;
1931 break;
1932 case nir_tex_src_lod:
1933 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1934 has_lod = true;
1935 break;
1936 case nir_tex_src_comparator: /* shadow comparator */
1937 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1938 break;
1939 case nir_tex_src_projector:
1940 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1941 has_proj = true;
1942 break;
1943 case nir_tex_src_offset:
1944 off = ir3_get_src(ctx, &tex->src[i].src);
1945 has_off = true;
1946 break;
1947 case nir_tex_src_ddx:
1948 ddx = ir3_get_src(ctx, &tex->src[i].src);
1949 break;
1950 case nir_tex_src_ddy:
1951 ddy = ir3_get_src(ctx, &tex->src[i].src);
1952 break;
1953 case nir_tex_src_ms_index:
1954 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
1955 break;
1956 case nir_tex_src_texture_offset:
1957 case nir_tex_src_sampler_offset:
1958 /* handled in get_tex_samp_src() */
1959 break;
1960 default:
1961 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
1962 tex->src[i].src_type);
1963 return;
1964 }
1965 }
1966
1967 switch (tex->op) {
1968 case nir_texop_tex_prefetch:
1969 compile_assert(ctx, !has_bias);
1970 compile_assert(ctx, !has_lod);
1971 compile_assert(ctx, !compare);
1972 compile_assert(ctx, !has_proj);
1973 compile_assert(ctx, !has_off);
1974 compile_assert(ctx, !ddx);
1975 compile_assert(ctx, !ddy);
1976 compile_assert(ctx, !sample_index);
1977 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
1978 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
1979
1980 if (ctx->so->num_sampler_prefetch < IR3_MAX_SAMPLER_PREFETCH) {
1981 opc = OPC_META_TEX_PREFETCH;
1982 ctx->so->num_sampler_prefetch++;
1983 break;
1984 }
1985 /* fallthru */
1986 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
1987 case nir_texop_txb: opc = OPC_SAMB; break;
1988 case nir_texop_txl: opc = OPC_SAML; break;
1989 case nir_texop_txd: opc = OPC_SAMGQ; break;
1990 case nir_texop_txf: opc = OPC_ISAML; break;
1991 case nir_texop_lod: opc = OPC_GETLOD; break;
1992 case nir_texop_tg4:
1993 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1994 * what blob does, seems gather is broken?), and a3xx did
1995 * not support it (but probably could also emulate).
1996 */
1997 switch (tex->component) {
1998 case 0: opc = OPC_GATHER4R; break;
1999 case 1: opc = OPC_GATHER4G; break;
2000 case 2: opc = OPC_GATHER4B; break;
2001 case 3: opc = OPC_GATHER4A; break;
2002 }
2003 break;
2004 case nir_texop_txf_ms_fb:
2005 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2006 default:
2007 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2008 return;
2009 }
2010
2011 tex_info(tex, &flags, &coords);
2012
2013 /*
2014 * lay out the first argument in the proper order:
2015 * - actual coordinates first
2016 * - shadow reference
2017 * - array index
2018 * - projection w
2019 * - starting at offset 4, dpdx.xy, dpdy.xy
2020 *
2021 * bias/lod go into the second arg
2022 */
2023
2024 /* insert tex coords: */
2025 for (i = 0; i < coords; i++)
2026 src0[i] = coord[i];
2027
2028 nsrc0 = i;
2029
2030 /* scale up integer coords for TXF based on the LOD */
2031 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2032 assert(has_lod);
2033 for (i = 0; i < coords; i++)
2034 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2035 }
2036
2037 if (coords == 1) {
2038 /* hw doesn't do 1d, so we treat it as 2d with
2039 * height of 1, and patch up the y coord.
2040 */
2041 if (is_isam(opc)) {
2042 src0[nsrc0++] = create_immed(b, 0);
2043 } else {
2044 src0[nsrc0++] = create_immed(b, fui(0.5));
2045 }
2046 }
2047
2048 if (tex->is_shadow && tex->op != nir_texop_lod)
2049 src0[nsrc0++] = compare;
2050
2051 if (tex->is_array && tex->op != nir_texop_lod) {
2052 struct ir3_instruction *idx = coord[coords];
2053
2054 /* the array coord for cube arrays needs 0.5 added to it */
2055 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2056 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2057
2058 src0[nsrc0++] = idx;
2059 }
2060
2061 if (has_proj) {
2062 src0[nsrc0++] = proj;
2063 flags |= IR3_INSTR_P;
2064 }
2065
2066 /* pad to 4, then ddx/ddy: */
2067 if (tex->op == nir_texop_txd) {
2068 while (nsrc0 < 4)
2069 src0[nsrc0++] = create_immed(b, fui(0.0));
2070 for (i = 0; i < coords; i++)
2071 src0[nsrc0++] = ddx[i];
2072 if (coords < 2)
2073 src0[nsrc0++] = create_immed(b, fui(0.0));
2074 for (i = 0; i < coords; i++)
2075 src0[nsrc0++] = ddy[i];
2076 if (coords < 2)
2077 src0[nsrc0++] = create_immed(b, fui(0.0));
2078 }
2079
2080 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2081 * with scaled x coord according to requested sample:
2082 */
2083 if (opc == OPC_ISAMM) {
2084 if (ctx->compiler->txf_ms_with_isaml) {
2085 /* the samples are laid out in x dimension as
2086 * 0 1 2 3
2087 * x_ms = (x << ms) + sample_index;
2088 */
2089 struct ir3_instruction *ms;
2090 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2091
2092 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2093 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2094
2095 opc = OPC_ISAML;
2096 } else {
2097 src0[nsrc0++] = sample_index;
2098 }
2099 }
2100
2101 /*
2102 * second argument (if applicable):
2103 * - offsets
2104 * - lod
2105 * - bias
2106 */
2107 if (has_off | has_lod | has_bias) {
2108 if (has_off) {
2109 unsigned off_coords = coords;
2110 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2111 off_coords--;
2112 for (i = 0; i < off_coords; i++)
2113 src1[nsrc1++] = off[i];
2114 if (off_coords < 2)
2115 src1[nsrc1++] = create_immed(b, fui(0.0));
2116 flags |= IR3_INSTR_O;
2117 }
2118
2119 if (has_lod | has_bias)
2120 src1[nsrc1++] = lod;
2121 }
2122
2123 switch (tex->dest_type) {
2124 case nir_type_invalid:
2125 case nir_type_float:
2126 type = TYPE_F32;
2127 break;
2128 case nir_type_int:
2129 type = TYPE_S32;
2130 break;
2131 case nir_type_uint:
2132 case nir_type_bool:
2133 type = TYPE_U32;
2134 break;
2135 default:
2136 unreachable("bad dest_type");
2137 }
2138
2139 if (opc == OPC_GETLOD)
2140 type = TYPE_S32;
2141
2142 struct ir3_instruction *samp_tex;
2143
2144 if (tex->op == nir_texop_txf_ms_fb) {
2145 /* only expect a single txf_ms_fb per shader: */
2146 compile_assert(ctx, !ctx->so->fb_read);
2147 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2148
2149 ctx->so->fb_read = true;
2150 samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2151 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2152 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2153 }, 2);
2154
2155 ctx->so->num_samp++;
2156 } else {
2157 samp_tex = get_tex_samp_tex_src(ctx, tex);
2158 }
2159
2160 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2161 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2162
2163 if (opc == OPC_META_TEX_PREFETCH) {
2164 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2165
2166 compile_assert(ctx, tex->src[idx].src.is_ssa);
2167
2168 sam = ir3_META_TEX_PREFETCH(b);
2169 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2170 sam->prefetch.input_offset =
2171 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2172 sam->prefetch.tex = tex->texture_index;
2173 sam->prefetch.samp = tex->sampler_index;
2174 } else {
2175 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
2176 samp_tex, col0, col1);
2177 }
2178
2179 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2180 assert(opc != OPC_META_TEX_PREFETCH);
2181
2182 /* only need first 3 components: */
2183 sam->regs[0]->wrmask = 0x7;
2184 ir3_split_dest(b, dst, sam, 0, 3);
2185
2186 /* we need to sample the alpha separately with a non-ASTC
2187 * texture state:
2188 */
2189 sam = ir3_SAM(b, opc, type, 0b1000, flags,
2190 samp_tex, col0, col1);
2191
2192 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2193
2194 /* fixup .w component: */
2195 ir3_split_dest(b, &dst[3], sam, 3, 1);
2196 } else {
2197 /* normal (non-workaround) case: */
2198 ir3_split_dest(b, dst, sam, 0, ncomp);
2199 }
2200
2201 /* GETLOD returns results in 4.8 fixed point */
2202 if (opc == OPC_GETLOD) {
2203 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2204
2205 compile_assert(ctx, tex->dest_type == nir_type_float);
2206 for (i = 0; i < 2; i++) {
2207 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2208 factor, 0);
2209 }
2210 }
2211
2212 ir3_put_dst(ctx, &tex->dest);
2213 }
2214
2215 static void
2216 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2217 {
2218 struct ir3_block *b = ctx->block;
2219 struct ir3_instruction **dst, *sam;
2220
2221 dst = ir3_get_dst(ctx, &tex->dest, 1);
2222
2223 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, 1 << idx, 0,
2224 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
2225
2226 /* even though there is only one component, since it ends
2227 * up in .y/.z/.w rather than .x, we need a split_dest()
2228 */
2229 if (idx)
2230 ir3_split_dest(b, dst, sam, 0, idx + 1);
2231
2232 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2233 * the value in TEX_CONST_0 is zero-based.
2234 */
2235 if (ctx->compiler->levels_add_one)
2236 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2237
2238 ir3_put_dst(ctx, &tex->dest);
2239 }
2240
2241 static void
2242 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2243 {
2244 struct ir3_block *b = ctx->block;
2245 struct ir3_instruction **dst, *sam;
2246 struct ir3_instruction *lod;
2247 unsigned flags, coords;
2248
2249 tex_info(tex, &flags, &coords);
2250
2251 /* Actually we want the number of dimensions, not coordinates. This
2252 * distinction only matters for cubes.
2253 */
2254 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2255 coords = 2;
2256
2257 dst = ir3_get_dst(ctx, &tex->dest, 4);
2258
2259 compile_assert(ctx, tex->num_srcs == 1);
2260 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2261
2262 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2263
2264 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
2265 get_tex_samp_tex_src(ctx, tex), lod, NULL);
2266
2267 ir3_split_dest(b, dst, sam, 0, 4);
2268
2269 /* Array size actually ends up in .w rather than .z. This doesn't
2270 * matter for miplevel 0, but for higher mips the value in z is
2271 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2272 * returned, which means that we have to add 1 to it for arrays.
2273 */
2274 if (tex->is_array) {
2275 if (ctx->compiler->levels_add_one) {
2276 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2277 } else {
2278 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2279 }
2280 }
2281
2282 ir3_put_dst(ctx, &tex->dest);
2283 }
2284
2285 static void
2286 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2287 {
2288 switch (jump->type) {
2289 case nir_jump_break:
2290 case nir_jump_continue:
2291 case nir_jump_return:
2292 /* I *think* we can simply just ignore this, and use the
2293 * successor block link to figure out where we need to
2294 * jump to for break/continue
2295 */
2296 break;
2297 default:
2298 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2299 break;
2300 }
2301 }
2302
2303 static void
2304 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2305 {
2306 switch (instr->type) {
2307 case nir_instr_type_alu:
2308 emit_alu(ctx, nir_instr_as_alu(instr));
2309 break;
2310 case nir_instr_type_deref:
2311 /* ignored, handled as part of the intrinsic they are src to */
2312 break;
2313 case nir_instr_type_intrinsic:
2314 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2315 break;
2316 case nir_instr_type_load_const:
2317 emit_load_const(ctx, nir_instr_as_load_const(instr));
2318 break;
2319 case nir_instr_type_ssa_undef:
2320 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2321 break;
2322 case nir_instr_type_tex: {
2323 nir_tex_instr *tex = nir_instr_as_tex(instr);
2324 /* couple tex instructions get special-cased:
2325 */
2326 switch (tex->op) {
2327 case nir_texop_txs:
2328 emit_tex_txs(ctx, tex);
2329 break;
2330 case nir_texop_query_levels:
2331 emit_tex_info(ctx, tex, 2);
2332 break;
2333 case nir_texop_texture_samples:
2334 emit_tex_info(ctx, tex, 3);
2335 break;
2336 default:
2337 emit_tex(ctx, tex);
2338 break;
2339 }
2340 break;
2341 }
2342 case nir_instr_type_jump:
2343 emit_jump(ctx, nir_instr_as_jump(instr));
2344 break;
2345 case nir_instr_type_phi:
2346 /* we have converted phi webs to regs in NIR by now */
2347 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2348 break;
2349 case nir_instr_type_call:
2350 case nir_instr_type_parallel_copy:
2351 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2352 break;
2353 }
2354 }
2355
2356 static struct ir3_block *
2357 get_block(struct ir3_context *ctx, const nir_block *nblock)
2358 {
2359 struct ir3_block *block;
2360 struct hash_entry *hentry;
2361
2362 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2363 if (hentry)
2364 return hentry->data;
2365
2366 block = ir3_block_create(ctx->ir);
2367 block->nblock = nblock;
2368 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2369
2370 block->predecessors = _mesa_pointer_set_create(block);
2371 set_foreach(nblock->predecessors, sentry) {
2372 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2373 }
2374
2375 return block;
2376 }
2377
2378 static void
2379 emit_block(struct ir3_context *ctx, nir_block *nblock)
2380 {
2381 struct ir3_block *block = get_block(ctx, nblock);
2382
2383 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2384 if (nblock->successors[i]) {
2385 block->successors[i] =
2386 get_block(ctx, nblock->successors[i]);
2387 }
2388 }
2389
2390 ctx->block = block;
2391 list_addtail(&block->node, &ctx->ir->block_list);
2392
2393 /* re-emit addr register in each block if needed: */
2394 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2395 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2396 ctx->addr_ht[i] = NULL;
2397 }
2398
2399 nir_foreach_instr(instr, nblock) {
2400 ctx->cur_instr = instr;
2401 emit_instr(ctx, instr);
2402 ctx->cur_instr = NULL;
2403 if (ctx->error)
2404 return;
2405 }
2406 }
2407
2408 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2409
2410 static void
2411 emit_if(struct ir3_context *ctx, nir_if *nif)
2412 {
2413 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2414
2415 ctx->block->condition =
2416 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2417
2418 emit_cf_list(ctx, &nif->then_list);
2419 emit_cf_list(ctx, &nif->else_list);
2420 }
2421
2422 static void
2423 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2424 {
2425 emit_cf_list(ctx, &nloop->body);
2426 ctx->so->loops++;
2427 }
2428
2429 static void
2430 stack_push(struct ir3_context *ctx)
2431 {
2432 ctx->stack++;
2433 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2434 }
2435
2436 static void
2437 stack_pop(struct ir3_context *ctx)
2438 {
2439 compile_assert(ctx, ctx->stack > 0);
2440 ctx->stack--;
2441 }
2442
2443 static void
2444 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2445 {
2446 foreach_list_typed(nir_cf_node, node, node, list) {
2447 switch (node->type) {
2448 case nir_cf_node_block:
2449 emit_block(ctx, nir_cf_node_as_block(node));
2450 break;
2451 case nir_cf_node_if:
2452 stack_push(ctx);
2453 emit_if(ctx, nir_cf_node_as_if(node));
2454 stack_pop(ctx);
2455 break;
2456 case nir_cf_node_loop:
2457 stack_push(ctx);
2458 emit_loop(ctx, nir_cf_node_as_loop(node));
2459 stack_pop(ctx);
2460 break;
2461 case nir_cf_node_function:
2462 ir3_context_error(ctx, "TODO\n");
2463 break;
2464 }
2465 }
2466 }
2467
2468 /* emit stream-out code. At this point, the current block is the original
2469 * (nir) end block, and nir ensures that all flow control paths terminate
2470 * into the end block. We re-purpose the original end block to generate
2471 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2472 * block holding stream-out write instructions, followed by the new end
2473 * block:
2474 *
2475 * blockOrigEnd {
2476 * p0.x = (vtxcnt < maxvtxcnt)
2477 * // succs: blockStreamOut, blockNewEnd
2478 * }
2479 * blockStreamOut {
2480 * ... stream-out instructions ...
2481 * // succs: blockNewEnd
2482 * }
2483 * blockNewEnd {
2484 * }
2485 */
2486 static void
2487 emit_stream_out(struct ir3_context *ctx)
2488 {
2489 struct ir3 *ir = ctx->ir;
2490 struct ir3_stream_output_info *strmout =
2491 &ctx->so->shader->stream_output;
2492 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2493 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2494 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2495
2496 /* create vtxcnt input in input block at top of shader,
2497 * so that it is seen as live over the entire duration
2498 * of the shader:
2499 */
2500 vtxcnt = create_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, 0x1);
2501 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2502
2503 /* at this point, we are at the original 'end' block,
2504 * re-purpose this block to stream-out condition, then
2505 * append stream-out block and new-end block
2506 */
2507 orig_end_block = ctx->block;
2508
2509 // TODO these blocks need to update predecessors..
2510 // maybe w/ store_global intrinsic, we could do this
2511 // stuff in nir->nir pass
2512
2513 stream_out_block = ir3_block_create(ir);
2514 list_addtail(&stream_out_block->node, &ir->block_list);
2515
2516 new_end_block = ir3_block_create(ir);
2517 list_addtail(&new_end_block->node, &ir->block_list);
2518
2519 orig_end_block->successors[0] = stream_out_block;
2520 orig_end_block->successors[1] = new_end_block;
2521 stream_out_block->successors[0] = new_end_block;
2522
2523 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2524 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2525 cond->regs[0]->num = regid(REG_P0, 0);
2526 cond->regs[0]->flags &= ~IR3_REG_SSA;
2527 cond->cat2.condition = IR3_COND_LT;
2528
2529 /* condition goes on previous block to the conditional,
2530 * since it is used to pick which of the two successor
2531 * paths to take:
2532 */
2533 orig_end_block->condition = cond;
2534
2535 /* switch to stream_out_block to generate the stream-out
2536 * instructions:
2537 */
2538 ctx->block = stream_out_block;
2539
2540 /* Calculate base addresses based on vtxcnt. Instructions
2541 * generated for bases not used in following loop will be
2542 * stripped out in the backend.
2543 */
2544 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2545 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2546 unsigned stride = strmout->stride[i];
2547 struct ir3_instruction *base, *off;
2548
2549 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2550
2551 /* 24-bit should be enough: */
2552 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2553 create_immed(ctx->block, stride * 4), 0);
2554
2555 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2556 }
2557
2558 /* Generate the per-output store instructions: */
2559 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2560 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2561 unsigned c = j + strmout->output[i].start_component;
2562 struct ir3_instruction *base, *out, *stg;
2563
2564 base = bases[strmout->output[i].output_buffer];
2565 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2566
2567 stg = ir3_STG(ctx->block, base, 0, out, 0,
2568 create_immed(ctx->block, 1), 0);
2569 stg->cat6.type = TYPE_U32;
2570 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2571
2572 array_insert(ctx->block, ctx->block->keeps, stg);
2573 }
2574 }
2575
2576 /* and finally switch to the new_end_block: */
2577 ctx->block = new_end_block;
2578 }
2579
2580 static void
2581 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2582 {
2583 nir_metadata_require(impl, nir_metadata_block_index);
2584
2585 compile_assert(ctx, ctx->stack == 0);
2586
2587 emit_cf_list(ctx, &impl->body);
2588 emit_block(ctx, impl->end_block);
2589
2590 compile_assert(ctx, ctx->stack == 0);
2591
2592 /* at this point, we should have a single empty block,
2593 * into which we emit the 'end' instruction.
2594 */
2595 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2596
2597 /* If stream-out (aka transform-feedback) enabled, emit the
2598 * stream-out instructions, followed by a new empty block (into
2599 * which the 'end' instruction lands).
2600 *
2601 * NOTE: it is done in this order, rather than inserting before
2602 * we emit end_block, because NIR guarantees that all blocks
2603 * flow into end_block, and that end_block has no successors.
2604 * So by re-purposing end_block as the first block of stream-
2605 * out, we guarantee that all exit paths flow into the stream-
2606 * out instructions.
2607 */
2608 if ((ctx->compiler->gpu_id < 500) &&
2609 (ctx->so->shader->stream_output.num_outputs > 0) &&
2610 !ctx->so->binning_pass) {
2611 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2612 emit_stream_out(ctx);
2613 }
2614
2615 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2616 * NOP and has an epilogue that writes the VS outputs to local storage, to
2617 * be read by the HS. Then it resets execution mask (chmask) and chains
2618 * to the next shader (chsh).
2619 */
2620 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2621 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2622 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2623 struct ir3_instruction *chmask =
2624 ir3_CHMASK(ctx->block);
2625 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2626 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2627
2628 struct ir3_instruction *chsh =
2629 ir3_CHSH(ctx->block);
2630 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2631 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2632 } else {
2633 ir3_END(ctx->block);
2634 }
2635 }
2636
2637 static void
2638 setup_input(struct ir3_context *ctx, nir_variable *in)
2639 {
2640 struct ir3_shader_variant *so = ctx->so;
2641 unsigned ncomp = glsl_get_components(in->type);
2642 unsigned n = in->data.driver_location;
2643 unsigned frac = in->data.location_frac;
2644 unsigned slot = in->data.location;
2645
2646 /* Inputs are loaded using ldlw or ldg for these stages. */
2647 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2648 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2649 ctx->so->type == MESA_SHADER_GEOMETRY)
2650 return;
2651
2652 /* skip unread inputs, we could end up with (for example), unsplit
2653 * matrix/etc inputs in the case they are not read, so just silently
2654 * skip these.
2655 */
2656 if (ncomp > 4)
2657 return;
2658
2659 so->inputs[n].slot = slot;
2660 so->inputs[n].compmask = (1 << (ncomp + frac)) - 1;
2661 so->inputs_count = MAX2(so->inputs_count, n + 1);
2662 so->inputs[n].interpolate = in->data.interpolation;
2663
2664 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2665
2666 /* if any varyings have 'sample' qualifer, that triggers us
2667 * to run in per-sample mode:
2668 */
2669 so->per_samp |= in->data.sample;
2670
2671 for (int i = 0; i < ncomp; i++) {
2672 struct ir3_instruction *instr = NULL;
2673 unsigned idx = (n * 4) + i + frac;
2674
2675 if (slot == VARYING_SLOT_POS) {
2676 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2677 } else if (slot == VARYING_SLOT_PNTC) {
2678 /* see for example st_nir_fixup_varying_slots().. this is
2679 * maybe a bit mesa/st specific. But we need things to line
2680 * up for this in fdN_program:
2681 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2682 * if (emit->sprite_coord_enable & texmask) {
2683 * ...
2684 * }
2685 */
2686 so->inputs[n].slot = VARYING_SLOT_VAR8;
2687 so->inputs[n].bary = true;
2688 instr = create_frag_input(ctx, false, idx);
2689 } else {
2690 /* detect the special case for front/back colors where
2691 * we need to do flat vs smooth shading depending on
2692 * rast state:
2693 */
2694 if (in->data.interpolation == INTERP_MODE_NONE) {
2695 switch (slot) {
2696 case VARYING_SLOT_COL0:
2697 case VARYING_SLOT_COL1:
2698 case VARYING_SLOT_BFC0:
2699 case VARYING_SLOT_BFC1:
2700 so->inputs[n].rasterflat = true;
2701 break;
2702 default:
2703 break;
2704 }
2705 }
2706
2707 if (ctx->compiler->flat_bypass) {
2708 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2709 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2710 so->inputs[n].use_ldlv = true;
2711 }
2712
2713 so->inputs[n].bary = true;
2714
2715 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2716 }
2717
2718 compile_assert(ctx, idx < ctx->ir->ninputs);
2719
2720 ctx->ir->inputs[idx] = instr;
2721 }
2722 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2723 for (int i = 0; i < ncomp; i++) {
2724 unsigned idx = (n * 4) + i + frac;
2725 compile_assert(ctx, idx < ctx->ir->ninputs);
2726 ctx->ir->inputs[idx] = create_input(ctx, idx);
2727 }
2728 } else {
2729 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2730 }
2731
2732 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2733 so->total_in += ncomp;
2734 }
2735 }
2736
2737 /* Initially we assign non-packed inloc's for varyings, as we don't really
2738 * know up-front which components will be unused. After all the compilation
2739 * stages we scan the shader to see which components are actually used, and
2740 * re-pack the inlocs to eliminate unneeded varyings.
2741 */
2742 static void
2743 pack_inlocs(struct ir3_context *ctx)
2744 {
2745 struct ir3_shader_variant *so = ctx->so;
2746 uint8_t used_components[so->inputs_count];
2747
2748 memset(used_components, 0, sizeof(used_components));
2749
2750 /*
2751 * First Step: scan shader to find which bary.f/ldlv remain:
2752 */
2753
2754 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2755 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2756 if (is_input(instr)) {
2757 unsigned inloc = instr->regs[1]->iim_val;
2758 unsigned i = inloc / 4;
2759 unsigned j = inloc % 4;
2760
2761 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
2762 compile_assert(ctx, i < so->inputs_count);
2763
2764 used_components[i] |= 1 << j;
2765 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
2766 for (int n = 0; n < 2; n++) {
2767 unsigned inloc = instr->prefetch.input_offset + n;
2768 unsigned i = inloc / 4;
2769 unsigned j = inloc % 4;
2770
2771 compile_assert(ctx, i < so->inputs_count);
2772
2773 used_components[i] |= 1 << j;
2774 }
2775 }
2776 }
2777 }
2778
2779 /*
2780 * Second Step: reassign varying inloc/slots:
2781 */
2782
2783 unsigned actual_in = 0;
2784 unsigned inloc = 0;
2785
2786 for (unsigned i = 0; i < so->inputs_count; i++) {
2787 unsigned compmask = 0, maxcomp = 0;
2788
2789 so->inputs[i].inloc = inloc;
2790 so->inputs[i].bary = false;
2791
2792 for (unsigned j = 0; j < 4; j++) {
2793 if (!(used_components[i] & (1 << j)))
2794 continue;
2795
2796 compmask |= (1 << j);
2797 actual_in++;
2798 maxcomp = j + 1;
2799
2800 /* at this point, since used_components[i] mask is only
2801 * considering varyings (ie. not sysvals) we know this
2802 * is a varying:
2803 */
2804 so->inputs[i].bary = true;
2805 }
2806
2807 if (so->inputs[i].bary) {
2808 so->varying_in++;
2809 so->inputs[i].compmask = (1 << maxcomp) - 1;
2810 inloc += maxcomp;
2811 }
2812 }
2813
2814 /*
2815 * Third Step: reassign packed inloc's:
2816 */
2817
2818 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2819 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2820 if (is_input(instr)) {
2821 unsigned inloc = instr->regs[1]->iim_val;
2822 unsigned i = inloc / 4;
2823 unsigned j = inloc % 4;
2824
2825 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
2826 }
2827 }
2828 }
2829 }
2830
2831 static void
2832 setup_output(struct ir3_context *ctx, nir_variable *out)
2833 {
2834 struct ir3_shader_variant *so = ctx->so;
2835 unsigned ncomp = glsl_get_components(out->type);
2836 unsigned n = out->data.driver_location;
2837 unsigned frac = out->data.location_frac;
2838 unsigned slot = out->data.location;
2839 unsigned comp = 0;
2840
2841 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2842 switch (slot) {
2843 case FRAG_RESULT_DEPTH:
2844 comp = 2; /* tgsi will write to .z component */
2845 so->writes_pos = true;
2846 break;
2847 case FRAG_RESULT_COLOR:
2848 so->color0_mrt = 1;
2849 break;
2850 case FRAG_RESULT_SAMPLE_MASK:
2851 so->writes_smask = true;
2852 break;
2853 default:
2854 if (slot >= FRAG_RESULT_DATA0)
2855 break;
2856 ir3_context_error(ctx, "unknown FS output name: %s\n",
2857 gl_frag_result_name(slot));
2858 }
2859 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
2860 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2861 ctx->so->type == MESA_SHADER_GEOMETRY) {
2862 switch (slot) {
2863 case VARYING_SLOT_POS:
2864 so->writes_pos = true;
2865 break;
2866 case VARYING_SLOT_PSIZ:
2867 so->writes_psize = true;
2868 break;
2869 case VARYING_SLOT_PRIMITIVE_ID:
2870 case VARYING_SLOT_LAYER:
2871 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
2872 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
2873 /* fall through */
2874 case VARYING_SLOT_COL0:
2875 case VARYING_SLOT_COL1:
2876 case VARYING_SLOT_BFC0:
2877 case VARYING_SLOT_BFC1:
2878 case VARYING_SLOT_FOGC:
2879 case VARYING_SLOT_CLIP_DIST0:
2880 case VARYING_SLOT_CLIP_DIST1:
2881 case VARYING_SLOT_CLIP_VERTEX:
2882 break;
2883 default:
2884 if (slot >= VARYING_SLOT_VAR0)
2885 break;
2886 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2887 break;
2888 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
2889 _mesa_shader_stage_to_string(ctx->so->type),
2890 gl_varying_slot_name(slot));
2891 }
2892 } else if (ctx->so->type == MESA_SHADER_TESS_CTRL) {
2893 /* output lowered to buffer writes. */
2894 return;
2895 } else {
2896 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2897 }
2898
2899 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2900
2901 so->outputs[n].slot = slot;
2902 so->outputs[n].regid = regid(n, comp);
2903 so->outputs_count = MAX2(so->outputs_count, n + 1);
2904
2905 for (int i = 0; i < ncomp; i++) {
2906 unsigned idx = (n * 4) + i + frac;
2907 compile_assert(ctx, idx < ctx->ir->noutputs);
2908 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2909 }
2910
2911 /* if varying packing doesn't happen, we could end up in a situation
2912 * with "holes" in the output, and since the per-generation code that
2913 * sets up varying linkage registers doesn't expect to have more than
2914 * one varying per vec4 slot, pad the holes.
2915 *
2916 * Note that this should probably generate a performance warning of
2917 * some sort.
2918 */
2919 for (int i = 0; i < frac; i++) {
2920 unsigned idx = (n * 4) + i;
2921 if (!ctx->ir->outputs[idx]) {
2922 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2923 }
2924 }
2925 }
2926
2927 static int
2928 max_drvloc(struct exec_list *vars)
2929 {
2930 int drvloc = -1;
2931 nir_foreach_variable(var, vars) {
2932 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2933 }
2934 return drvloc;
2935 }
2936
2937 static const unsigned max_sysvals[] = {
2938 [MESA_SHADER_VERTEX] = 16,
2939 [MESA_SHADER_TESS_CTRL] = 16,
2940 [MESA_SHADER_TESS_EVAL] = 16,
2941 [MESA_SHADER_GEOMETRY] = 16,
2942 [MESA_SHADER_FRAGMENT] = 24, // TODO
2943 [MESA_SHADER_COMPUTE] = 16, // TODO how many do we actually need?
2944 [MESA_SHADER_KERNEL] = 16, // TODO how many do we actually need?
2945 };
2946
2947 static void
2948 emit_instructions(struct ir3_context *ctx)
2949 {
2950 unsigned ninputs, noutputs;
2951 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
2952
2953 ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
2954 noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
2955
2956 /* we need to leave room for sysvals:
2957 */
2958 ninputs += max_sysvals[ctx->so->type];
2959 if (ctx->so->type == MESA_SHADER_VERTEX ||
2960 ctx->so->type == MESA_SHADER_TESS_EVAL)
2961 noutputs += 8; /* gs or tess header + primitive_id */
2962
2963 ctx->ir = ir3_create(ctx->compiler, ctx->so->type, ninputs, noutputs);
2964
2965 /* Create inputs in first block: */
2966 ctx->block = get_block(ctx, nir_start_block(fxn));
2967 ctx->in_block = ctx->block;
2968 list_addtail(&ctx->block->node, &ctx->ir->block_list);
2969
2970 /* for fragment shader, the vcoord input register is used as the
2971 * base for bary.f varying fetch instrs:
2972 *
2973 * TODO defer creating ctx->ij_pixel and corresponding sysvals
2974 * until emit_intrinsic when we know they are actually needed.
2975 * For now, we defer creating ctx->ij_centroid, etc, since we
2976 * only need ij_pixel for "old style" varying inputs (ie.
2977 * tgsi_to_nir)
2978 */
2979 struct ir3_instruction *vcoord = NULL;
2980 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2981 struct ir3_instruction *xy[2];
2982
2983 vcoord = create_input_compmask(ctx, 0, 0x3);
2984 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
2985
2986 ctx->ij_pixel = ir3_create_collect(ctx, xy, 2);
2987 }
2988
2989 /* Setup inputs: */
2990 nir_foreach_variable(var, &ctx->s->inputs) {
2991 setup_input(ctx, var);
2992 }
2993
2994 /* Defer add_sysval_input() stuff until after setup_inputs(),
2995 * because sysvals need to be appended after varyings:
2996 */
2997 if (vcoord) {
2998 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PIXEL,
2999 0x3, vcoord);
3000 }
3001
3002
3003 /* Tesselation shaders always need primitive ID for indexing the
3004 * BO. Geometry shaders don't always need it but when they do it has be
3005 * delivered and unclobbered in the VS. To make things easy, we always
3006 * make room for it in VS/DS.
3007 */
3008 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
3009 bool has_gs = ctx->so->key.has_gs;
3010 switch (ctx->so->type) {
3011 case MESA_SHADER_VERTEX:
3012 if (has_tess) {
3013 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3014 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3015 } else if (has_gs) {
3016 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3017 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3018 }
3019 break;
3020 case MESA_SHADER_TESS_CTRL:
3021 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3022 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3023 break;
3024 case MESA_SHADER_TESS_EVAL:
3025 if (has_gs)
3026 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3027 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3028 break;
3029 case MESA_SHADER_GEOMETRY:
3030 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3031 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3032 break;
3033 default:
3034 break;
3035 }
3036
3037 /* Setup outputs: */
3038 nir_foreach_variable(var, &ctx->s->outputs) {
3039 setup_output(ctx, var);
3040 }
3041
3042 /* Set up the shared system values as outputs for the vertex and tess eval
3043 * shaders so they don't clobber them for the next shader in the pipeline.
3044 */
3045 if (ctx->so->type == MESA_SHADER_VERTEX ||
3046 (has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3047 struct ir3_shader_variant *so = ctx->so;
3048 if (ctx->primitive_id) {
3049 unsigned n = so->outputs_count++;
3050 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3051 so->outputs[n].regid = regid(n, 0);
3052 ctx->ir->outputs[n * 4] = ctx->primitive_id;
3053
3054 compile_assert(ctx, n * 4 < ctx->ir->noutputs);
3055 }
3056
3057 if (ctx->gs_header) {
3058 unsigned n = so->outputs_count++;
3059 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3060 so->outputs[n].regid = regid(n, 0);
3061 ctx->ir->outputs[n * 4] = ctx->gs_header;
3062
3063 compile_assert(ctx, n * 4 < ctx->ir->noutputs);
3064 }
3065
3066 if (ctx->tcs_header) {
3067 unsigned n = so->outputs_count++;
3068 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3069 so->outputs[n].regid = regid(n, 0);
3070 ctx->ir->outputs[n * 4] = ctx->tcs_header;
3071
3072 compile_assert(ctx, n * 4 < ctx->ir->noutputs);
3073 }
3074 }
3075
3076 /* Find # of samplers: */
3077 nir_foreach_variable(var, &ctx->s->uniforms) {
3078 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
3079 /* just assume that we'll be reading from images.. if it
3080 * is write-only we don't have to count it, but not sure
3081 * if there is a good way to know?
3082 */
3083 ctx->so->num_samp += glsl_type_get_image_count(var->type);
3084 }
3085
3086 /* NOTE: need to do something more clever when we support >1 fxn */
3087 nir_foreach_register(reg, &fxn->registers) {
3088 ir3_declare_array(ctx, reg);
3089 }
3090 /* And emit the body: */
3091 ctx->impl = fxn;
3092 emit_function(ctx, fxn);
3093 }
3094
3095 /* from NIR perspective, we actually have varying inputs. But the varying
3096 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
3097 * only actual inputs are the sysvals.
3098 */
3099 static void
3100 fixup_frag_inputs(struct ir3_context *ctx)
3101 {
3102 struct ir3_shader_variant *so = ctx->so;
3103 struct ir3 *ir = ctx->ir;
3104 unsigned i = 0;
3105
3106 /* sysvals should appear at the end of the inputs, drop everything else: */
3107 while ((i < so->inputs_count) && !so->inputs[i].sysval)
3108 i++;
3109
3110 /* at IR level, inputs are always blocks of 4 scalars: */
3111 i *= 4;
3112
3113 ir->inputs = &ir->inputs[i];
3114 ir->ninputs -= i;
3115 }
3116
3117 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3118 * need to assign the tex state indexes for these after we know the
3119 * max tex index.
3120 */
3121 static void
3122 fixup_astc_srgb(struct ir3_context *ctx)
3123 {
3124 struct ir3_shader_variant *so = ctx->so;
3125 /* indexed by original tex idx, value is newly assigned alpha sampler
3126 * state tex idx. Zero is invalid since there is at least one sampler
3127 * if we get here.
3128 */
3129 unsigned alt_tex_state[16] = {0};
3130 unsigned tex_idx = ctx->max_texture_index + 1;
3131 unsigned idx = 0;
3132
3133 so->astc_srgb.base = tex_idx;
3134
3135 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3136 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3137
3138 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3139
3140 if (alt_tex_state[sam->cat5.tex] == 0) {
3141 /* assign new alternate/alpha tex state slot: */
3142 alt_tex_state[sam->cat5.tex] = tex_idx++;
3143 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3144 so->astc_srgb.count++;
3145 }
3146
3147 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3148 }
3149 }
3150
3151 static void
3152 fixup_binning_pass(struct ir3_context *ctx)
3153 {
3154 struct ir3_shader_variant *so = ctx->so;
3155 struct ir3 *ir = ctx->ir;
3156 unsigned i, j;
3157
3158 for (i = 0, j = 0; i < so->outputs_count; i++) {
3159 unsigned slot = so->outputs[i].slot;
3160
3161 /* throw away everything but first position/psize */
3162 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3163 if (i != j) {
3164 so->outputs[j] = so->outputs[i];
3165 ir->outputs[(j*4)+0] = ir->outputs[(i*4)+0];
3166 ir->outputs[(j*4)+1] = ir->outputs[(i*4)+1];
3167 ir->outputs[(j*4)+2] = ir->outputs[(i*4)+2];
3168 ir->outputs[(j*4)+3] = ir->outputs[(i*4)+3];
3169 }
3170 j++;
3171 }
3172 }
3173 so->outputs_count = j;
3174 ir->noutputs = j * 4;
3175 }
3176
3177 static void
3178 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3179 {
3180 unsigned idx = 0;
3181
3182 /* Collect sampling instructions eligible for pre-dispatch. */
3183 list_for_each_entry(struct ir3_block, block, &ir->block_list, node) {
3184 list_for_each_entry_safe(struct ir3_instruction, instr,
3185 &block->instr_list, node) {
3186 if (instr->opc == OPC_META_TEX_PREFETCH) {
3187 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3188 struct ir3_sampler_prefetch *fetch =
3189 &ctx->so->sampler_prefetch[idx];
3190 idx++;
3191
3192 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3193 fetch->wrmask = instr->regs[0]->wrmask;
3194 fetch->tex_id = instr->prefetch.tex;
3195 fetch->samp_id = instr->prefetch.samp;
3196 fetch->dst = instr->regs[0]->num;
3197 fetch->src = instr->prefetch.input_offset;
3198
3199 ctx->so->total_in =
3200 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3201
3202 /* Disable half precision until supported. */
3203 fetch->half_precision = 0x0;
3204
3205 /* Remove the prefetch placeholder instruction: */
3206 list_delinit(&instr->node);
3207 }
3208 }
3209 }
3210 }
3211
3212 int
3213 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3214 struct ir3_shader_variant *so)
3215 {
3216 struct ir3_context *ctx;
3217 struct ir3 *ir;
3218 struct ir3_instruction **inputs;
3219 unsigned i;
3220 int ret = 0, max_bary;
3221
3222 assert(!so->ir);
3223
3224 ctx = ir3_context_init(compiler, so);
3225 if (!ctx) {
3226 DBG("INIT failed!");
3227 ret = -1;
3228 goto out;
3229 }
3230
3231 emit_instructions(ctx);
3232
3233 if (ctx->error) {
3234 DBG("EMIT failed!");
3235 ret = -1;
3236 goto out;
3237 }
3238
3239 ir = so->ir = ctx->ir;
3240
3241 /* keep track of the inputs from TGSI perspective.. */
3242 inputs = ir->inputs;
3243
3244 /* but fixup actual inputs for frag shader: */
3245 if (so->type == MESA_SHADER_FRAGMENT)
3246 fixup_frag_inputs(ctx);
3247
3248 /* at this point, for binning pass, throw away unneeded outputs: */
3249 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3250 fixup_binning_pass(ctx);
3251
3252 ir3_debug_print(ir, "BEFORE CP");
3253
3254 ir3_cp(ir, so);
3255
3256 /* at this point, for binning pass, throw away unneeded outputs:
3257 * Note that for a6xx and later, we do this after ir3_cp to ensure
3258 * that the uniform/constant layout for BS and VS matches, so that
3259 * we can re-use same VS_CONST state group.
3260 */
3261 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
3262 fixup_binning_pass(ctx);
3263
3264 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3265 * need to make sure not to remove any inputs that are used by
3266 * the nonbinning VS.
3267 */
3268 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3269 so->type == MESA_SHADER_VERTEX) {
3270 for (int i = 0; i < ir->ninputs; i++) {
3271 struct ir3_instruction *in = ir->inputs[i];
3272
3273 if (!in)
3274 continue;
3275
3276 unsigned n = i / 4;
3277 unsigned c = i % 4;
3278
3279 debug_assert(n < so->nonbinning->inputs_count);
3280
3281 if (so->nonbinning->inputs[n].sysval)
3282 continue;
3283
3284 /* be sure to keep inputs, even if only used in VS */
3285 if (so->nonbinning->inputs[n].compmask & (1 << c))
3286 array_insert(in->block, in->block->keeps, in);
3287 }
3288 }
3289
3290 /* Insert mov if there's same instruction for each output.
3291 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
3292 */
3293 for (int i = ir->noutputs - 1; i >= 0; i--) {
3294 if (!ir->outputs[i])
3295 continue;
3296 for (unsigned j = 0; j < i; j++) {
3297 if (ir->outputs[i] == ir->outputs[j]) {
3298 ir->outputs[i] =
3299 ir3_MOV(ir->outputs[i]->block, ir->outputs[i], TYPE_F32);
3300 }
3301 }
3302 }
3303
3304 ir3_debug_print(ir, "BEFORE GROUPING");
3305
3306 ir3_sched_add_deps(ir);
3307
3308 /* Group left/right neighbors, inserting mov's where needed to
3309 * solve conflicts:
3310 */
3311 ir3_group(ir);
3312
3313 ir3_debug_print(ir, "AFTER GROUPING");
3314
3315 ir3_depth(ir, so);
3316
3317 ir3_debug_print(ir, "AFTER DEPTH");
3318
3319 /* do Sethi–Ullman numbering before scheduling: */
3320 ir3_sun(ir);
3321
3322 ret = ir3_sched(ir);
3323 if (ret) {
3324 DBG("SCHED failed!");
3325 goto out;
3326 }
3327
3328 if (compiler->gpu_id >= 600) {
3329 ir3_a6xx_fixup_atomic_dests(ir, so);
3330 }
3331
3332 ir3_debug_print(ir, "AFTER SCHED");
3333
3334 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3335 * with draw pass VS, so binning and draw pass can both use the
3336 * same VBO state.
3337 *
3338 * Note that VS inputs are expected to be full precision.
3339 */
3340 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3341 (ir->type == MESA_SHADER_VERTEX) &&
3342 so->binning_pass;
3343
3344 if (pre_assign_inputs) {
3345 for (unsigned i = 0; i < ir->ninputs; i++) {
3346 struct ir3_instruction *instr = ir->inputs[i];
3347
3348 if (!instr)
3349 continue;
3350
3351 unsigned n = i / 4;
3352 unsigned c = i % 4;
3353 unsigned regid = so->nonbinning->inputs[n].regid + c;
3354
3355 instr->regs[0]->num = regid;
3356 }
3357
3358 ret = ir3_ra(so, ir->inputs, ir->ninputs);
3359 } else if (ctx->tcs_header) {
3360 /* We need to have these values in the same registers between VS and TCS
3361 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3362 */
3363
3364 ctx->tcs_header->regs[0]->num = regid(0, 0);
3365 ctx->primitive_id->regs[0]->num = regid(0, 1);
3366 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3367 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3368 } else if (ctx->gs_header) {
3369 /* We need to have these values in the same registers between producer
3370 * (VS or DS) and GS since the producer chains to GS and doesn't get
3371 * the sysvals redelivered.
3372 */
3373
3374 ctx->gs_header->regs[0]->num = regid(0, 0);
3375 ctx->primitive_id->regs[0]->num = regid(0, 1);
3376 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3377 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3378 } else if (so->num_sampler_prefetch) {
3379 assert(so->type == MESA_SHADER_FRAGMENT);
3380 struct ir3_instruction *instr, *precolor[2];
3381 int idx = 0;
3382
3383 foreach_input(instr, ir) {
3384 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PIXEL)
3385 continue;
3386
3387 assert(idx < ARRAY_SIZE(precolor));
3388
3389 precolor[idx] = instr;
3390 instr->regs[0]->num = idx;
3391
3392 idx++;
3393 }
3394 ret = ir3_ra(so, precolor, idx);
3395 } else {
3396 ret = ir3_ra(so, NULL, 0);
3397 }
3398
3399 if (ret) {
3400 DBG("RA failed!");
3401 goto out;
3402 }
3403
3404 ir3_debug_print(ir, "AFTER RA");
3405
3406 if (so->type == MESA_SHADER_FRAGMENT)
3407 pack_inlocs(ctx);
3408
3409 /* fixup input/outputs: */
3410 for (i = 0; i < so->outputs_count; i++) {
3411 /* sometimes we get outputs that don't write the .x coord, like:
3412 *
3413 * decl_var shader_out INTERP_MODE_NONE float Color (VARYING_SLOT_VAR9.z, 1, 0)
3414 *
3415 * Presumably the result of varying packing and then eliminating
3416 * some unneeded varyings? Just skip head to the first valid
3417 * component of the output.
3418 */
3419 for (unsigned j = 0; j < 4; j++) {
3420 struct ir3_instruction *instr = ir->outputs[(i*4) + j];
3421 if (instr) {
3422 so->outputs[i].regid = instr->regs[0]->num;
3423 so->outputs[i].half = !!(instr->regs[0]->flags & IR3_REG_HALF);
3424 break;
3425 }
3426 }
3427 }
3428
3429 /* Note that some or all channels of an input may be unused: */
3430 for (i = 0; i < so->inputs_count; i++) {
3431 unsigned j, reg = regid(63,0);
3432 bool half = false;
3433 for (j = 0; j < 4; j++) {
3434 struct ir3_instruction *in = inputs[(i*4) + j];
3435
3436 if (!in)
3437 continue;
3438
3439 if (in->flags & IR3_INSTR_UNUSED)
3440 continue;
3441
3442 reg = in->regs[0]->num - j;
3443 if (half) {
3444 compile_assert(ctx, in->regs[0]->flags & IR3_REG_HALF);
3445 } else {
3446 half = !!(in->regs[0]->flags & IR3_REG_HALF);
3447 }
3448 }
3449 so->inputs[i].regid = reg;
3450 so->inputs[i].half = half;
3451 }
3452
3453 if (ctx->astc_srgb)
3454 fixup_astc_srgb(ctx);
3455
3456 /* We need to do legalize after (for frag shader's) the "bary.f"
3457 * offsets (inloc) have been assigned.
3458 */
3459 ir3_legalize(ir, &so->has_ssbo, &so->need_pixlod, &max_bary);
3460
3461 ir3_debug_print(ir, "AFTER LEGALIZE");
3462
3463 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3464 * know what we might have to wait on when coming in from VS chsh.
3465 */
3466 if (so->type == MESA_SHADER_TESS_CTRL ||
3467 so->type == MESA_SHADER_GEOMETRY ) {
3468 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
3469 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
3470 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3471 break;
3472 }
3473 }
3474 }
3475
3476 so->branchstack = ctx->max_stack;
3477
3478 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3479 if (so->type == MESA_SHADER_FRAGMENT)
3480 so->total_in = max_bary + 1;
3481
3482 so->max_sun = ir->max_sun;
3483
3484 /* Collect sampling instructions eligible for pre-dispatch. */
3485 collect_tex_prefetches(ctx, ir);
3486
3487 out:
3488 if (ret) {
3489 if (so->ir)
3490 ir3_destroy(so->ir);
3491 so->ir = NULL;
3492 }
3493 ir3_context_free(ctx);
3494
3495 return ret;
3496 }