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freedreno: Use the NIR lowering for isign.
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_shader.h"
35 #include "ir3_nir.h"
36
37 #include "instr-a3xx.h"
38 #include "ir3.h"
39 #include "ir3_context.h"
40
41
42 static struct ir3_instruction *
43 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
44 struct ir3_instruction *address, struct ir3_instruction *collect)
45 {
46 struct ir3_block *block = ctx->block;
47 struct ir3_instruction *mov;
48 struct ir3_register *src;
49
50 mov = ir3_instr_create(block, OPC_MOV);
51 mov->cat1.src_type = TYPE_U32;
52 mov->cat1.dst_type = TYPE_U32;
53 ir3_reg_create(mov, 0, 0);
54 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
55 src->instr = collect;
56 src->size = arrsz;
57 src->array.offset = n;
58
59 ir3_instr_set_address(mov, address);
60
61 return mov;
62 }
63
64 static struct ir3_instruction *
65 create_input_compmask(struct ir3_context *ctx, unsigned n, unsigned compmask)
66 {
67 struct ir3_instruction *in;
68
69 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
70 in->inout.block = ctx->in_block;
71 ir3_reg_create(in, n, 0);
72
73 in->regs[0]->wrmask = compmask;
74
75 return in;
76 }
77
78 static struct ir3_instruction *
79 create_input(struct ir3_context *ctx, unsigned n)
80 {
81 return create_input_compmask(ctx, n, 0x1);
82 }
83
84 static struct ir3_instruction *
85 create_frag_input(struct ir3_context *ctx, bool use_ldlv)
86 {
87 struct ir3_block *block = ctx->block;
88 struct ir3_instruction *instr;
89 /* actual inloc is assigned and fixed up later: */
90 struct ir3_instruction *inloc = create_immed(block, 0);
91
92 if (use_ldlv) {
93 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
94 instr->cat6.type = TYPE_U32;
95 instr->cat6.iim_val = 1;
96 } else {
97 instr = ir3_BARY_F(block, inloc, 0, ctx->frag_vcoord, 0);
98 instr->regs[2]->wrmask = 0x3;
99 }
100
101 return instr;
102 }
103
104 static struct ir3_instruction *
105 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
106 {
107 /* first four vec4 sysval's reserved for UBOs: */
108 /* NOTE: dp is in scalar, but there can be >4 dp components: */
109 unsigned n = ctx->so->constbase.driver_param;
110 unsigned r = regid(n + dp / 4, dp % 4);
111 return create_uniform(ctx->block, r);
112 }
113
114 /*
115 * Adreno uses uint rather than having dedicated bool type,
116 * which (potentially) requires some conversion, in particular
117 * when using output of an bool instr to int input, or visa
118 * versa.
119 *
120 * | Adreno | NIR |
121 * -------+---------+-------+-
122 * true | 1 | ~0 |
123 * false | 0 | 0 |
124 *
125 * To convert from an adreno bool (uint) to nir, use:
126 *
127 * absneg.s dst, (neg)src
128 *
129 * To convert back in the other direction:
130 *
131 * absneg.s dst, (abs)arc
132 *
133 * The CP step can clean up the absneg.s that cancel each other
134 * out, and with a slight bit of extra cleverness (to recognize
135 * the instructions which produce either a 0 or 1) can eliminate
136 * the absneg.s's completely when an instruction that wants
137 * 0/1 consumes the result. For example, when a nir 'bcsel'
138 * consumes the result of 'feq'. So we should be able to get by
139 * without a boolean resolve step, and without incuring any
140 * extra penalty in instruction count.
141 */
142
143 /* NIR bool -> native (adreno): */
144 static struct ir3_instruction *
145 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
146 {
147 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
148 }
149
150 /* native (adreno) -> NIR bool: */
151 static struct ir3_instruction *
152 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
153 {
154 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
155 }
156
157 /*
158 * alu/sfu instructions:
159 */
160
161 static struct ir3_instruction *
162 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
163 unsigned src_bitsize, nir_op op)
164 {
165 type_t src_type, dst_type;
166
167 switch (op) {
168 case nir_op_f2f32:
169 case nir_op_f2f16_rtne:
170 case nir_op_f2f16_rtz:
171 case nir_op_f2f16:
172 case nir_op_f2i32:
173 case nir_op_f2i16:
174 case nir_op_f2i8:
175 case nir_op_f2u32:
176 case nir_op_f2u16:
177 case nir_op_f2u8:
178 switch (src_bitsize) {
179 case 32:
180 src_type = TYPE_F32;
181 break;
182 case 16:
183 src_type = TYPE_F16;
184 break;
185 default:
186 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
187 }
188 break;
189
190 case nir_op_i2f32:
191 case nir_op_i2f16:
192 case nir_op_i2i32:
193 case nir_op_i2i16:
194 case nir_op_i2i8:
195 switch (src_bitsize) {
196 case 32:
197 src_type = TYPE_S32;
198 break;
199 case 16:
200 src_type = TYPE_S16;
201 break;
202 case 8:
203 src_type = TYPE_S8;
204 break;
205 default:
206 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
207 }
208 break;
209
210 case nir_op_u2f32:
211 case nir_op_u2f16:
212 case nir_op_u2u32:
213 case nir_op_u2u16:
214 case nir_op_u2u8:
215 switch (src_bitsize) {
216 case 32:
217 src_type = TYPE_U32;
218 break;
219 case 16:
220 src_type = TYPE_U16;
221 break;
222 case 8:
223 src_type = TYPE_U8;
224 break;
225 default:
226 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
227 }
228 break;
229
230 default:
231 ir3_context_error(ctx, "invalid conversion op: %u", op);
232 }
233
234 switch (op) {
235 case nir_op_f2f32:
236 case nir_op_i2f32:
237 case nir_op_u2f32:
238 dst_type = TYPE_F32;
239 break;
240
241 case nir_op_f2f16_rtne:
242 case nir_op_f2f16_rtz:
243 case nir_op_f2f16:
244 /* TODO how to handle rounding mode? */
245 case nir_op_i2f16:
246 case nir_op_u2f16:
247 dst_type = TYPE_F16;
248 break;
249
250 case nir_op_f2i32:
251 case nir_op_i2i32:
252 dst_type = TYPE_S32;
253 break;
254
255 case nir_op_f2i16:
256 case nir_op_i2i16:
257 dst_type = TYPE_S16;
258 break;
259
260 case nir_op_f2i8:
261 case nir_op_i2i8:
262 dst_type = TYPE_S8;
263 break;
264
265 case nir_op_f2u32:
266 case nir_op_u2u32:
267 dst_type = TYPE_U32;
268 break;
269
270 case nir_op_f2u16:
271 case nir_op_u2u16:
272 dst_type = TYPE_U16;
273 break;
274
275 case nir_op_f2u8:
276 case nir_op_u2u8:
277 dst_type = TYPE_U8;
278 break;
279
280 default:
281 ir3_context_error(ctx, "invalid conversion op: %u", op);
282 }
283
284 return ir3_COV(ctx->block, src, src_type, dst_type);
285 }
286
287 static void
288 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
289 {
290 const nir_op_info *info = &nir_op_infos[alu->op];
291 struct ir3_instruction **dst, *src[info->num_inputs];
292 unsigned bs[info->num_inputs]; /* bit size */
293 struct ir3_block *b = ctx->block;
294 unsigned dst_sz, wrmask;
295
296 if (alu->dest.dest.is_ssa) {
297 dst_sz = alu->dest.dest.ssa.num_components;
298 wrmask = (1 << dst_sz) - 1;
299 } else {
300 dst_sz = alu->dest.dest.reg.reg->num_components;
301 wrmask = alu->dest.write_mask;
302 }
303
304 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
305
306 /* Vectors are special in that they have non-scalarized writemasks,
307 * and just take the first swizzle channel for each argument in
308 * order into each writemask channel.
309 */
310 if ((alu->op == nir_op_vec2) ||
311 (alu->op == nir_op_vec3) ||
312 (alu->op == nir_op_vec4)) {
313
314 for (int i = 0; i < info->num_inputs; i++) {
315 nir_alu_src *asrc = &alu->src[i];
316
317 compile_assert(ctx, !asrc->abs);
318 compile_assert(ctx, !asrc->negate);
319
320 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
321 if (!src[i])
322 src[i] = create_immed(ctx->block, 0);
323 dst[i] = ir3_MOV(b, src[i], TYPE_U32);
324 }
325
326 put_dst(ctx, &alu->dest.dest);
327 return;
328 }
329
330 /* We also get mov's with more than one component for mov's so
331 * handle those specially:
332 */
333 if ((alu->op == nir_op_imov) || (alu->op == nir_op_fmov)) {
334 type_t type = (alu->op == nir_op_imov) ? TYPE_U32 : TYPE_F32;
335 nir_alu_src *asrc = &alu->src[0];
336 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
337
338 for (unsigned i = 0; i < dst_sz; i++) {
339 if (wrmask & (1 << i)) {
340 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], type);
341 } else {
342 dst[i] = NULL;
343 }
344 }
345
346 put_dst(ctx, &alu->dest.dest);
347 return;
348 }
349
350 /* General case: We can just grab the one used channel per src. */
351 for (int i = 0; i < info->num_inputs; i++) {
352 unsigned chan = ffs(alu->dest.write_mask) - 1;
353 nir_alu_src *asrc = &alu->src[i];
354
355 compile_assert(ctx, !asrc->abs);
356 compile_assert(ctx, !asrc->negate);
357
358 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
359 bs[i] = nir_src_bit_size(asrc->src);
360
361 compile_assert(ctx, src[i]);
362 }
363
364 switch (alu->op) {
365 case nir_op_f2f32:
366 case nir_op_f2f16_rtne:
367 case nir_op_f2f16_rtz:
368 case nir_op_f2f16:
369 case nir_op_f2i32:
370 case nir_op_f2i16:
371 case nir_op_f2i8:
372 case nir_op_f2u32:
373 case nir_op_f2u16:
374 case nir_op_f2u8:
375 case nir_op_i2f32:
376 case nir_op_i2f16:
377 case nir_op_i2i32:
378 case nir_op_i2i16:
379 case nir_op_i2i8:
380 case nir_op_u2f32:
381 case nir_op_u2f16:
382 case nir_op_u2u32:
383 case nir_op_u2u16:
384 case nir_op_u2u8:
385 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
386 break;
387 case nir_op_f2b32:
388 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
389 dst[0]->cat2.condition = IR3_COND_NE;
390 dst[0] = ir3_n2b(b, dst[0]);
391 break;
392 case nir_op_b2f16:
393 case nir_op_b2f32:
394 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
395 break;
396 case nir_op_b2i8:
397 case nir_op_b2i16:
398 case nir_op_b2i32:
399 dst[0] = ir3_b2n(b, src[0]);
400 break;
401 case nir_op_i2b32:
402 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
403 dst[0]->cat2.condition = IR3_COND_NE;
404 dst[0] = ir3_n2b(b, dst[0]);
405 break;
406
407 case nir_op_fneg:
408 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
409 break;
410 case nir_op_fabs:
411 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
412 break;
413 case nir_op_fmax:
414 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
415 break;
416 case nir_op_fmin:
417 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
418 break;
419 case nir_op_fsat:
420 /* if there is just a single use of the src, and it supports
421 * (sat) bit, we can just fold the (sat) flag back to the
422 * src instruction and create a mov. This is easier for cp
423 * to eliminate.
424 *
425 * TODO probably opc_cat==4 is ok too
426 */
427 if (alu->src[0].src.is_ssa &&
428 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
429 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
430 src[0]->flags |= IR3_INSTR_SAT;
431 dst[0] = ir3_MOV(b, src[0], TYPE_U32);
432 } else {
433 /* otherwise generate a max.f that saturates.. blob does
434 * similar (generating a cat2 mov using max.f)
435 */
436 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
437 dst[0]->flags |= IR3_INSTR_SAT;
438 }
439 break;
440 case nir_op_fmul:
441 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
442 break;
443 case nir_op_fadd:
444 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
445 break;
446 case nir_op_fsub:
447 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
448 break;
449 case nir_op_ffma:
450 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
451 break;
452 case nir_op_fddx:
453 dst[0] = ir3_DSX(b, src[0], 0);
454 dst[0]->cat5.type = TYPE_F32;
455 break;
456 case nir_op_fddy:
457 dst[0] = ir3_DSY(b, src[0], 0);
458 dst[0]->cat5.type = TYPE_F32;
459 break;
460 break;
461 case nir_op_flt32:
462 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
463 dst[0]->cat2.condition = IR3_COND_LT;
464 dst[0] = ir3_n2b(b, dst[0]);
465 break;
466 case nir_op_fge32:
467 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
468 dst[0]->cat2.condition = IR3_COND_GE;
469 dst[0] = ir3_n2b(b, dst[0]);
470 break;
471 case nir_op_feq32:
472 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
473 dst[0]->cat2.condition = IR3_COND_EQ;
474 dst[0] = ir3_n2b(b, dst[0]);
475 break;
476 case nir_op_fne32:
477 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
478 dst[0]->cat2.condition = IR3_COND_NE;
479 dst[0] = ir3_n2b(b, dst[0]);
480 break;
481 case nir_op_fceil:
482 dst[0] = ir3_CEIL_F(b, src[0], 0);
483 break;
484 case nir_op_ffloor:
485 dst[0] = ir3_FLOOR_F(b, src[0], 0);
486 break;
487 case nir_op_ftrunc:
488 dst[0] = ir3_TRUNC_F(b, src[0], 0);
489 break;
490 case nir_op_fround_even:
491 dst[0] = ir3_RNDNE_F(b, src[0], 0);
492 break;
493 case nir_op_fsign:
494 dst[0] = ir3_SIGN_F(b, src[0], 0);
495 break;
496
497 case nir_op_fsin:
498 dst[0] = ir3_SIN(b, src[0], 0);
499 break;
500 case nir_op_fcos:
501 dst[0] = ir3_COS(b, src[0], 0);
502 break;
503 case nir_op_frsq:
504 dst[0] = ir3_RSQ(b, src[0], 0);
505 break;
506 case nir_op_frcp:
507 dst[0] = ir3_RCP(b, src[0], 0);
508 break;
509 case nir_op_flog2:
510 dst[0] = ir3_LOG2(b, src[0], 0);
511 break;
512 case nir_op_fexp2:
513 dst[0] = ir3_EXP2(b, src[0], 0);
514 break;
515 case nir_op_fsqrt:
516 dst[0] = ir3_SQRT(b, src[0], 0);
517 break;
518
519 case nir_op_iabs:
520 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
521 break;
522 case nir_op_iadd:
523 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
524 break;
525 case nir_op_iand:
526 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
527 break;
528 case nir_op_imax:
529 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
530 break;
531 case nir_op_umax:
532 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
533 break;
534 case nir_op_imin:
535 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
536 break;
537 case nir_op_umin:
538 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
539 break;
540 case nir_op_imul:
541 /*
542 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
543 * mull.u tmp0, a, b ; mul low, i.e. al * bl
544 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
545 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
546 */
547 dst[0] = ir3_MADSH_M16(b, src[1], 0, src[0], 0,
548 ir3_MADSH_M16(b, src[0], 0, src[1], 0,
549 ir3_MULL_U(b, src[0], 0, src[1], 0), 0), 0);
550 break;
551 case nir_op_ineg:
552 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
553 break;
554 case nir_op_inot:
555 dst[0] = ir3_NOT_B(b, src[0], 0);
556 break;
557 case nir_op_ior:
558 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
559 break;
560 case nir_op_ishl:
561 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
562 break;
563 case nir_op_ishr:
564 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
565 break;
566 case nir_op_isub:
567 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
568 break;
569 case nir_op_ixor:
570 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
571 break;
572 case nir_op_ushr:
573 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
574 break;
575 case nir_op_ilt32:
576 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
577 dst[0]->cat2.condition = IR3_COND_LT;
578 dst[0] = ir3_n2b(b, dst[0]);
579 break;
580 case nir_op_ige32:
581 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
582 dst[0]->cat2.condition = IR3_COND_GE;
583 dst[0] = ir3_n2b(b, dst[0]);
584 break;
585 case nir_op_ieq32:
586 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
587 dst[0]->cat2.condition = IR3_COND_EQ;
588 dst[0] = ir3_n2b(b, dst[0]);
589 break;
590 case nir_op_ine32:
591 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
592 dst[0]->cat2.condition = IR3_COND_NE;
593 dst[0] = ir3_n2b(b, dst[0]);
594 break;
595 case nir_op_ult32:
596 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
597 dst[0]->cat2.condition = IR3_COND_LT;
598 dst[0] = ir3_n2b(b, dst[0]);
599 break;
600 case nir_op_uge32:
601 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
602 dst[0]->cat2.condition = IR3_COND_GE;
603 dst[0] = ir3_n2b(b, dst[0]);
604 break;
605
606 case nir_op_b32csel: {
607 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
608 compile_assert(ctx, bs[1] == bs[2]);
609 /* the boolean condition is 32b even if src[1] and src[2] are
610 * half-precision, but sel.b16 wants all three src's to be the
611 * same type.
612 */
613 if (bs[1] < 32)
614 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
615 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
616 break;
617 }
618 case nir_op_bit_count:
619 dst[0] = ir3_CBITS_B(b, src[0], 0);
620 break;
621 case nir_op_ifind_msb: {
622 struct ir3_instruction *cmp;
623 dst[0] = ir3_CLZ_S(b, src[0], 0);
624 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
625 cmp->cat2.condition = IR3_COND_GE;
626 dst[0] = ir3_SEL_B32(b,
627 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
628 cmp, 0, dst[0], 0);
629 break;
630 }
631 case nir_op_ufind_msb:
632 dst[0] = ir3_CLZ_B(b, src[0], 0);
633 dst[0] = ir3_SEL_B32(b,
634 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
635 src[0], 0, dst[0], 0);
636 break;
637 case nir_op_find_lsb:
638 dst[0] = ir3_BFREV_B(b, src[0], 0);
639 dst[0] = ir3_CLZ_B(b, dst[0], 0);
640 break;
641 case nir_op_bitfield_reverse:
642 dst[0] = ir3_BFREV_B(b, src[0], 0);
643 break;
644
645 default:
646 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
647 nir_op_infos[alu->op].name);
648 break;
649 }
650
651 put_dst(ctx, &alu->dest.dest);
652 }
653
654 /* handles direct/indirect UBO reads: */
655 static void
656 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
657 struct ir3_instruction **dst)
658 {
659 struct ir3_block *b = ctx->block;
660 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
661 nir_const_value *const_offset;
662 /* UBO addresses are the first driver params: */
663 unsigned ubo = regid(ctx->so->constbase.ubo, 0);
664 const unsigned ptrsz = ir3_pointer_size(ctx);
665
666 int off = 0;
667
668 /* First src is ubo index, which could either be an immed or not: */
669 src0 = ir3_get_src(ctx, &intr->src[0])[0];
670 if (is_same_type_mov(src0) &&
671 (src0->regs[1]->flags & IR3_REG_IMMED)) {
672 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
673 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
674 } else {
675 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, 4));
676 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, 4));
677 }
678
679 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
680 addr = base_lo;
681
682 const_offset = nir_src_as_const_value(intr->src[1]);
683 if (const_offset) {
684 off += const_offset->u32[0];
685 } else {
686 /* For load_ubo_indirect, second src is indirect offset: */
687 src1 = ir3_get_src(ctx, &intr->src[1])[0];
688
689 /* and add offset to addr: */
690 addr = ir3_ADD_S(b, addr, 0, src1, 0);
691 }
692
693 /* if offset is to large to encode in the ldg, split it out: */
694 if ((off + (intr->num_components * 4)) > 1024) {
695 /* split out the minimal amount to improve the odds that
696 * cp can fit the immediate in the add.s instruction:
697 */
698 unsigned off2 = off + (intr->num_components * 4) - 1024;
699 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
700 off -= off2;
701 }
702
703 if (ptrsz == 2) {
704 struct ir3_instruction *carry;
705
706 /* handle 32b rollover, ie:
707 * if (addr < base_lo)
708 * base_hi++
709 */
710 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
711 carry->cat2.condition = IR3_COND_LT;
712 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
713
714 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
715 }
716
717 for (int i = 0; i < intr->num_components; i++) {
718 struct ir3_instruction *load =
719 ir3_LDG(b, addr, 0, create_immed(b, 1), 0);
720 load->cat6.type = TYPE_U32;
721 load->cat6.src_offset = off + i * 4; /* byte offset */
722 dst[i] = load;
723 }
724 }
725
726 /* src[] = { buffer_index, offset }. No const_index */
727 static void
728 emit_intrinsic_load_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
729 struct ir3_instruction **dst)
730 {
731 struct ir3_block *b = ctx->block;
732 struct ir3_instruction *ldgb, *src0, *src1, *offset;
733 nir_const_value *const_offset;
734
735 /* can this be non-const buffer_index? how do we handle that? */
736 const_offset = nir_src_as_const_value(intr->src[0]);
737 compile_assert(ctx, const_offset);
738
739 offset = ir3_get_src(ctx, &intr->src[1])[0];
740
741 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
742 src0 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
743 offset,
744 create_immed(b, 0),
745 }, 2);
746 src1 = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0);
747
748 ldgb = ir3_LDGB(b, create_immed(b, const_offset->u32[0]), 0,
749 src0, 0, src1, 0);
750 ldgb->regs[0]->wrmask = MASK(intr->num_components);
751 ldgb->cat6.iim_val = intr->num_components;
752 ldgb->cat6.d = 4;
753 ldgb->cat6.type = TYPE_U32;
754 ldgb->barrier_class = IR3_BARRIER_BUFFER_R;
755 ldgb->barrier_conflict = IR3_BARRIER_BUFFER_W;
756
757 ir3_split_dest(b, dst, ldgb, 0, intr->num_components);
758 }
759
760 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
761 static void
762 emit_intrinsic_store_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
763 {
764 struct ir3_block *b = ctx->block;
765 struct ir3_instruction *stgb, *src0, *src1, *src2, *offset;
766 nir_const_value *const_offset;
767 /* TODO handle wrmask properly, see _store_shared().. but I think
768 * it is more a PITA than that, since blob ends up loading the
769 * masked components and writing them back out.
770 */
771 unsigned wrmask = intr->const_index[0];
772 unsigned ncomp = ffs(~wrmask) - 1;
773
774 /* can this be non-const buffer_index? how do we handle that? */
775 const_offset = nir_src_as_const_value(intr->src[1]);
776 compile_assert(ctx, const_offset);
777
778 offset = ir3_get_src(ctx, &intr->src[2])[0];
779
780 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
781 * nir already *= 4:
782 */
783 src0 = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]), ncomp);
784 src1 = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0);
785 src2 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
786 offset,
787 create_immed(b, 0),
788 }, 2);
789
790 stgb = ir3_STGB(b, create_immed(b, const_offset->u32[0]), 0,
791 src0, 0, src1, 0, src2, 0);
792 stgb->cat6.iim_val = ncomp;
793 stgb->cat6.d = 4;
794 stgb->cat6.type = TYPE_U32;
795 stgb->barrier_class = IR3_BARRIER_BUFFER_W;
796 stgb->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
797
798 array_insert(b, b->keeps, stgb);
799 }
800
801 /* src[] = { block_index } */
802 static void
803 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
804 struct ir3_instruction **dst)
805 {
806 /* SSBO size stored as a const starting at ssbo_sizes: */
807 unsigned blk_idx = nir_src_as_const_value(intr->src[0])->u32[0];
808 unsigned idx = regid(ctx->so->constbase.ssbo_sizes, 0) +
809 ctx->so->const_layout.ssbo_size.off[blk_idx];
810
811 debug_assert(ctx->so->const_layout.ssbo_size.mask & (1 << blk_idx));
812
813 dst[0] = create_uniform(ctx->block, idx);
814 }
815
816 /*
817 * SSBO atomic intrinsics
818 *
819 * All of the SSBO atomic memory operations read a value from memory,
820 * compute a new value using one of the operations below, write the new
821 * value to memory, and return the original value read.
822 *
823 * All operations take 3 sources except CompSwap that takes 4. These
824 * sources represent:
825 *
826 * 0: The SSBO buffer index.
827 * 1: The offset into the SSBO buffer of the variable that the atomic
828 * operation will operate on.
829 * 2: The data parameter to the atomic function (i.e. the value to add
830 * in ssbo_atomic_add, etc).
831 * 3: For CompSwap only: the second data parameter.
832 */
833 static struct ir3_instruction *
834 emit_intrinsic_atomic_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
835 {
836 struct ir3_block *b = ctx->block;
837 struct ir3_instruction *atomic, *ssbo, *src0, *src1, *src2, *offset;
838 nir_const_value *const_offset;
839 type_t type = TYPE_U32;
840
841 /* can this be non-const buffer_index? how do we handle that? */
842 const_offset = nir_src_as_const_value(intr->src[0]);
843 compile_assert(ctx, const_offset);
844 ssbo = create_immed(b, const_offset->u32[0]);
845
846 offset = ir3_get_src(ctx, &intr->src[1])[0];
847
848 /* src0 is data (or uvec2(data, compare))
849 * src1 is offset
850 * src2 is uvec2(offset*4, 0) (appears to be 64b byte offset)
851 *
852 * Note that nir already multiplies the offset by four
853 */
854 src0 = ir3_get_src(ctx, &intr->src[2])[0];
855 src1 = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0);
856 src2 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
857 offset,
858 create_immed(b, 0),
859 }, 2);
860
861 switch (intr->intrinsic) {
862 case nir_intrinsic_ssbo_atomic_add:
863 atomic = ir3_ATOMIC_ADD_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
864 break;
865 case nir_intrinsic_ssbo_atomic_imin:
866 atomic = ir3_ATOMIC_MIN_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
867 type = TYPE_S32;
868 break;
869 case nir_intrinsic_ssbo_atomic_umin:
870 atomic = ir3_ATOMIC_MIN_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
871 break;
872 case nir_intrinsic_ssbo_atomic_imax:
873 atomic = ir3_ATOMIC_MAX_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
874 type = TYPE_S32;
875 break;
876 case nir_intrinsic_ssbo_atomic_umax:
877 atomic = ir3_ATOMIC_MAX_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
878 break;
879 case nir_intrinsic_ssbo_atomic_and:
880 atomic = ir3_ATOMIC_AND_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
881 break;
882 case nir_intrinsic_ssbo_atomic_or:
883 atomic = ir3_ATOMIC_OR_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
884 break;
885 case nir_intrinsic_ssbo_atomic_xor:
886 atomic = ir3_ATOMIC_XOR_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
887 break;
888 case nir_intrinsic_ssbo_atomic_exchange:
889 atomic = ir3_ATOMIC_XCHG_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
890 break;
891 case nir_intrinsic_ssbo_atomic_comp_swap:
892 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
893 src0 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
894 ir3_get_src(ctx, &intr->src[3])[0],
895 src0,
896 }, 2);
897 atomic = ir3_ATOMIC_CMPXCHG_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
898 break;
899 default:
900 unreachable("boo");
901 }
902
903 atomic->cat6.iim_val = 1;
904 atomic->cat6.d = 4;
905 atomic->cat6.type = type;
906 atomic->barrier_class = IR3_BARRIER_BUFFER_W;
907 atomic->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
908
909 /* even if nothing consume the result, we can't DCE the instruction: */
910 array_insert(b, b->keeps, atomic);
911
912 return atomic;
913 }
914
915 /* src[] = { offset }. const_index[] = { base } */
916 static void
917 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
918 struct ir3_instruction **dst)
919 {
920 struct ir3_block *b = ctx->block;
921 struct ir3_instruction *ldl, *offset;
922 unsigned base;
923
924 offset = ir3_get_src(ctx, &intr->src[0])[0];
925 base = nir_intrinsic_base(intr);
926
927 ldl = ir3_LDL(b, offset, 0, create_immed(b, intr->num_components), 0);
928 ldl->cat6.src_offset = base;
929 ldl->cat6.type = utype_dst(intr->dest);
930 ldl->regs[0]->wrmask = MASK(intr->num_components);
931
932 ldl->barrier_class = IR3_BARRIER_SHARED_R;
933 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
934
935 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
936 }
937
938 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
939 static void
940 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
941 {
942 struct ir3_block *b = ctx->block;
943 struct ir3_instruction *stl, *offset;
944 struct ir3_instruction * const *value;
945 unsigned base, wrmask;
946
947 value = ir3_get_src(ctx, &intr->src[0]);
948 offset = ir3_get_src(ctx, &intr->src[1])[0];
949
950 base = nir_intrinsic_base(intr);
951 wrmask = nir_intrinsic_write_mask(intr);
952
953 /* Combine groups of consecutive enabled channels in one write
954 * message. We use ffs to find the first enabled channel and then ffs on
955 * the bit-inverse, down-shifted writemask to determine the length of
956 * the block of enabled bits.
957 *
958 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
959 */
960 while (wrmask) {
961 unsigned first_component = ffs(wrmask) - 1;
962 unsigned length = ffs(~(wrmask >> first_component)) - 1;
963
964 stl = ir3_STL(b, offset, 0,
965 ir3_create_collect(ctx, &value[first_component], length), 0,
966 create_immed(b, length), 0);
967 stl->cat6.dst_offset = first_component + base;
968 stl->cat6.type = utype_src(intr->src[0]);
969 stl->barrier_class = IR3_BARRIER_SHARED_W;
970 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
971
972 array_insert(b, b->keeps, stl);
973
974 /* Clear the bits in the writemask that we just wrote, then try
975 * again to see if more channels are left.
976 */
977 wrmask &= (15 << (first_component + length));
978 }
979 }
980
981 /*
982 * CS shared variable atomic intrinsics
983 *
984 * All of the shared variable atomic memory operations read a value from
985 * memory, compute a new value using one of the operations below, write the
986 * new value to memory, and return the original value read.
987 *
988 * All operations take 2 sources except CompSwap that takes 3. These
989 * sources represent:
990 *
991 * 0: The offset into the shared variable storage region that the atomic
992 * operation will operate on.
993 * 1: The data parameter to the atomic function (i.e. the value to add
994 * in shared_atomic_add, etc).
995 * 2: For CompSwap only: the second data parameter.
996 */
997 static struct ir3_instruction *
998 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
999 {
1000 struct ir3_block *b = ctx->block;
1001 struct ir3_instruction *atomic, *src0, *src1;
1002 type_t type = TYPE_U32;
1003
1004 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
1005 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
1006
1007 switch (intr->intrinsic) {
1008 case nir_intrinsic_shared_atomic_add:
1009 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
1010 break;
1011 case nir_intrinsic_shared_atomic_imin:
1012 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1013 type = TYPE_S32;
1014 break;
1015 case nir_intrinsic_shared_atomic_umin:
1016 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1017 break;
1018 case nir_intrinsic_shared_atomic_imax:
1019 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1020 type = TYPE_S32;
1021 break;
1022 case nir_intrinsic_shared_atomic_umax:
1023 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1024 break;
1025 case nir_intrinsic_shared_atomic_and:
1026 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
1027 break;
1028 case nir_intrinsic_shared_atomic_or:
1029 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
1030 break;
1031 case nir_intrinsic_shared_atomic_xor:
1032 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
1033 break;
1034 case nir_intrinsic_shared_atomic_exchange:
1035 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
1036 break;
1037 case nir_intrinsic_shared_atomic_comp_swap:
1038 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1039 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1040 ir3_get_src(ctx, &intr->src[2])[0],
1041 src1,
1042 }, 2);
1043 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
1044 break;
1045 default:
1046 unreachable("boo");
1047 }
1048
1049 atomic->cat6.iim_val = 1;
1050 atomic->cat6.d = 1;
1051 atomic->cat6.type = type;
1052 atomic->barrier_class = IR3_BARRIER_SHARED_W;
1053 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1054
1055 /* even if nothing consume the result, we can't DCE the instruction: */
1056 array_insert(b, b->keeps, atomic);
1057
1058 return atomic;
1059 }
1060
1061 /* Images get mapped into SSBO/image state (for store/atomic) and texture
1062 * state block (for load). To simplify things, invert the image id and
1063 * map it from end of state block, ie. image 0 becomes num-1, image 1
1064 * becomes num-2, etc. This potentially avoids needing to re-emit texture
1065 * state when switching shaders.
1066 *
1067 * TODO is max # of samplers and SSBOs the same. This shouldn't be hard-
1068 * coded. Also, since all the gl shader stages (ie. everything but CS)
1069 * share the same SSBO/image state block, this might require some more
1070 * logic if we supported images in anything other than FS..
1071 */
1072 static unsigned
1073 get_image_slot(struct ir3_context *ctx, nir_deref_instr *deref)
1074 {
1075 unsigned int loc = 0;
1076 unsigned inner_size = 1;
1077
1078 while (deref->deref_type != nir_deref_type_var) {
1079 assert(deref->deref_type == nir_deref_type_array);
1080 nir_const_value *const_index = nir_src_as_const_value(deref->arr.index);
1081 assert(const_index);
1082
1083 /* Go to the next instruction */
1084 deref = nir_deref_instr_parent(deref);
1085
1086 assert(glsl_type_is_array(deref->type));
1087 const unsigned array_len = glsl_get_length(deref->type);
1088 loc += MIN2(const_index->u32[0], array_len - 1) * inner_size;
1089
1090 /* Update the inner size */
1091 inner_size *= array_len;
1092 }
1093
1094 loc += deref->var->data.driver_location;
1095
1096 /* TODO figure out real limit per generation, and don't hardcode: */
1097 const unsigned max_samplers = 16;
1098 return max_samplers - loc - 1;
1099 }
1100
1101 /* see tex_info() for equiv logic for texture instructions.. it would be
1102 * nice if this could be better unified..
1103 */
1104 static unsigned
1105 get_image_coords(const nir_variable *var, unsigned *flagsp)
1106 {
1107 const struct glsl_type *type = glsl_without_array(var->type);
1108 unsigned coords, flags = 0;
1109
1110 switch (glsl_get_sampler_dim(type)) {
1111 case GLSL_SAMPLER_DIM_1D:
1112 case GLSL_SAMPLER_DIM_BUF:
1113 coords = 1;
1114 break;
1115 case GLSL_SAMPLER_DIM_2D:
1116 case GLSL_SAMPLER_DIM_RECT:
1117 case GLSL_SAMPLER_DIM_EXTERNAL:
1118 case GLSL_SAMPLER_DIM_MS:
1119 coords = 2;
1120 break;
1121 case GLSL_SAMPLER_DIM_3D:
1122 case GLSL_SAMPLER_DIM_CUBE:
1123 flags |= IR3_INSTR_3D;
1124 coords = 3;
1125 break;
1126 default:
1127 unreachable("bad sampler dim");
1128 return 0;
1129 }
1130
1131 if (glsl_sampler_type_is_array(type)) {
1132 /* note: unlike tex_info(), adjust # of coords to include array idx: */
1133 coords++;
1134 flags |= IR3_INSTR_A;
1135 }
1136
1137 if (flagsp)
1138 *flagsp = flags;
1139
1140 return coords;
1141 }
1142
1143 static type_t
1144 get_image_type(const nir_variable *var)
1145 {
1146 switch (glsl_get_sampler_result_type(glsl_without_array(var->type))) {
1147 case GLSL_TYPE_UINT:
1148 return TYPE_U32;
1149 case GLSL_TYPE_INT:
1150 return TYPE_S32;
1151 case GLSL_TYPE_FLOAT:
1152 return TYPE_F32;
1153 default:
1154 unreachable("bad sampler type.");
1155 return 0;
1156 }
1157 }
1158
1159 static struct ir3_instruction *
1160 get_image_offset(struct ir3_context *ctx, const nir_variable *var,
1161 struct ir3_instruction * const *coords, bool byteoff)
1162 {
1163 struct ir3_block *b = ctx->block;
1164 struct ir3_instruction *offset;
1165 unsigned ncoords = get_image_coords(var, NULL);
1166
1167 /* to calculate the byte offset (yes, uggg) we need (up to) three
1168 * const values to know the bytes per pixel, and y and z stride:
1169 */
1170 unsigned cb = regid(ctx->so->constbase.image_dims, 0) +
1171 ctx->so->const_layout.image_dims.off[var->data.driver_location];
1172
1173 debug_assert(ctx->so->const_layout.image_dims.mask &
1174 (1 << var->data.driver_location));
1175
1176 /* offset = coords.x * bytes_per_pixel: */
1177 offset = ir3_MUL_S(b, coords[0], 0, create_uniform(b, cb + 0), 0);
1178 if (ncoords > 1) {
1179 /* offset += coords.y * y_pitch: */
1180 offset = ir3_MAD_S24(b, create_uniform(b, cb + 1), 0,
1181 coords[1], 0, offset, 0);
1182 }
1183 if (ncoords > 2) {
1184 /* offset += coords.z * z_pitch: */
1185 offset = ir3_MAD_S24(b, create_uniform(b, cb + 2), 0,
1186 coords[2], 0, offset, 0);
1187 }
1188
1189 if (!byteoff) {
1190 /* Some cases, like atomics, seem to use dword offset instead
1191 * of byte offsets.. blob just puts an extra shr.b in there
1192 * in those cases:
1193 */
1194 offset = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0);
1195 }
1196
1197 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1198 offset,
1199 create_immed(b, 0),
1200 }, 2);
1201 }
1202
1203 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1204 static void
1205 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1206 struct ir3_instruction **dst)
1207 {
1208 struct ir3_block *b = ctx->block;
1209 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1210 struct ir3_instruction *sam;
1211 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1212 struct ir3_instruction *coords[4];
1213 unsigned flags, ncoords = get_image_coords(var, &flags);
1214 unsigned tex_idx = get_image_slot(ctx, nir_src_as_deref(intr->src[0]));
1215 type_t type = get_image_type(var);
1216
1217 /* hmm, this seems a bit odd, but it is what blob does and (at least
1218 * a5xx) just faults on bogus addresses otherwise:
1219 */
1220 if (flags & IR3_INSTR_3D) {
1221 flags &= ~IR3_INSTR_3D;
1222 flags |= IR3_INSTR_A;
1223 }
1224
1225 for (unsigned i = 0; i < ncoords; i++)
1226 coords[i] = src0[i];
1227
1228 if (ncoords == 1)
1229 coords[ncoords++] = create_immed(b, 0);
1230
1231 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
1232 tex_idx, tex_idx, ir3_create_collect(ctx, coords, ncoords), NULL);
1233
1234 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1235 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1236
1237 ir3_split_dest(b, dst, sam, 0, 4);
1238 }
1239
1240 /* Returns the number of components for the different image formats
1241 * supported by the GLES 3.1 spec, plus those added by the
1242 * GL_NV_image_formats extension.
1243 */
1244 static unsigned
1245 get_num_components_for_glformat(GLuint format)
1246 {
1247 switch (format) {
1248 case GL_R32F:
1249 case GL_R32I:
1250 case GL_R32UI:
1251 case GL_R16F:
1252 case GL_R16I:
1253 case GL_R16UI:
1254 case GL_R16:
1255 case GL_R16_SNORM:
1256 case GL_R8I:
1257 case GL_R8UI:
1258 case GL_R8:
1259 case GL_R8_SNORM:
1260 return 1;
1261
1262 case GL_RG32F:
1263 case GL_RG32I:
1264 case GL_RG32UI:
1265 case GL_RG16F:
1266 case GL_RG16I:
1267 case GL_RG16UI:
1268 case GL_RG16:
1269 case GL_RG16_SNORM:
1270 case GL_RG8I:
1271 case GL_RG8UI:
1272 case GL_RG8:
1273 case GL_RG8_SNORM:
1274 return 2;
1275
1276 case GL_R11F_G11F_B10F:
1277 return 3;
1278
1279 case GL_RGBA32F:
1280 case GL_RGBA32I:
1281 case GL_RGBA32UI:
1282 case GL_RGBA16F:
1283 case GL_RGBA16I:
1284 case GL_RGBA16UI:
1285 case GL_RGBA16:
1286 case GL_RGBA16_SNORM:
1287 case GL_RGBA8I:
1288 case GL_RGBA8UI:
1289 case GL_RGBA8:
1290 case GL_RGBA8_SNORM:
1291 case GL_RGB10_A2UI:
1292 case GL_RGB10_A2:
1293 return 4;
1294
1295 case GL_NONE:
1296 /* Omitting the image format qualifier is allowed on desktop GL
1297 * profiles. Assuming 4 components is always safe.
1298 */
1299 return 4;
1300
1301 default:
1302 /* Return 4 components also for all other formats we don't know
1303 * about. The format should have been validated already by
1304 * the higher level API, but drop a debug message just in case.
1305 */
1306 debug_printf("Unhandled GL format %u while emitting imageStore()\n",
1307 format);
1308 return 4;
1309 }
1310 }
1311
1312 /* src[] = { deref, coord, sample_index, value }. const_index[] = {} */
1313 static void
1314 emit_intrinsic_store_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1315 {
1316 struct ir3_block *b = ctx->block;
1317 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1318 struct ir3_instruction *stib, *offset;
1319 struct ir3_instruction * const *value = ir3_get_src(ctx, &intr->src[3]);
1320 struct ir3_instruction * const *coords = ir3_get_src(ctx, &intr->src[1]);
1321 unsigned ncoords = get_image_coords(var, NULL);
1322 unsigned tex_idx = get_image_slot(ctx, nir_src_as_deref(intr->src[0]));
1323 unsigned ncomp = get_num_components_for_glformat(var->data.image.format);
1324
1325 /* src0 is value
1326 * src1 is coords
1327 * src2 is 64b byte offset
1328 */
1329
1330 offset = get_image_offset(ctx, var, coords, true);
1331
1332 /* NOTE: stib seems to take byte offset, but stgb.typed can be used
1333 * too and takes a dword offset.. not quite sure yet why blob uses
1334 * one over the other in various cases.
1335 */
1336
1337 stib = ir3_STIB(b, create_immed(b, tex_idx), 0,
1338 ir3_create_collect(ctx, value, ncomp), 0,
1339 ir3_create_collect(ctx, coords, ncoords), 0,
1340 offset, 0);
1341 stib->cat6.iim_val = ncomp;
1342 stib->cat6.d = ncoords;
1343 stib->cat6.type = get_image_type(var);
1344 stib->cat6.typed = true;
1345 stib->barrier_class = IR3_BARRIER_IMAGE_W;
1346 stib->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W;
1347
1348 array_insert(b, b->keeps, stib);
1349 }
1350
1351 static void
1352 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1353 struct ir3_instruction **dst)
1354 {
1355 struct ir3_block *b = ctx->block;
1356 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1357 unsigned tex_idx = get_image_slot(ctx, nir_src_as_deref(intr->src[0]));
1358 struct ir3_instruction *sam, *lod;
1359 unsigned flags, ncoords = get_image_coords(var, &flags);
1360
1361 lod = create_immed(b, 0);
1362 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
1363 tex_idx, tex_idx, lod, NULL);
1364
1365 /* Array size actually ends up in .w rather than .z. This doesn't
1366 * matter for miplevel 0, but for higher mips the value in z is
1367 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1368 * returned, which means that we have to add 1 to it for arrays for
1369 * a3xx.
1370 *
1371 * Note use a temporary dst and then copy, since the size of the dst
1372 * array that is passed in is based on nir's understanding of the
1373 * result size, not the hardware's
1374 */
1375 struct ir3_instruction *tmp[4];
1376
1377 ir3_split_dest(b, tmp, sam, 0, 4);
1378
1379 /* get_size instruction returns size in bytes instead of texels
1380 * for imageBuffer, so we need to divide it by the pixel size
1381 * of the image format.
1382 *
1383 * TODO: This is at least true on a5xx. Check other gens.
1384 */
1385 enum glsl_sampler_dim dim =
1386 glsl_get_sampler_dim(glsl_without_array(var->type));
1387 if (dim == GLSL_SAMPLER_DIM_BUF) {
1388 /* Since all the possible values the divisor can take are
1389 * power-of-two (4, 8, or 16), the division is implemented
1390 * as a shift-right.
1391 * During shader setup, the log2 of the image format's
1392 * bytes-per-pixel should have been emitted in 2nd slot of
1393 * image_dims. See ir3_shader::emit_image_dims().
1394 */
1395 unsigned cb = regid(ctx->so->constbase.image_dims, 0) +
1396 ctx->so->const_layout.image_dims.off[var->data.driver_location];
1397 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1398
1399 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1400 }
1401
1402 for (unsigned i = 0; i < ncoords; i++)
1403 dst[i] = tmp[i];
1404
1405 if (flags & IR3_INSTR_A) {
1406 if (ctx->compiler->levels_add_one) {
1407 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1408 } else {
1409 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1410 }
1411 }
1412 }
1413
1414 /* src[] = { deref, coord, sample_index, value, compare }. const_index[] = {} */
1415 static struct ir3_instruction *
1416 emit_intrinsic_atomic_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1417 {
1418 struct ir3_block *b = ctx->block;
1419 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1420 struct ir3_instruction *atomic, *image, *src0, *src1, *src2;
1421 struct ir3_instruction * const *coords = ir3_get_src(ctx, &intr->src[1]);
1422 unsigned ncoords = get_image_coords(var, NULL);
1423
1424 image = create_immed(b, get_image_slot(ctx, nir_src_as_deref(intr->src[0])));
1425
1426 /* src0 is value (or uvec2(value, compare))
1427 * src1 is coords
1428 * src2 is 64b byte offset
1429 */
1430 src0 = ir3_get_src(ctx, &intr->src[3])[0];
1431 src1 = ir3_create_collect(ctx, coords, ncoords);
1432 src2 = get_image_offset(ctx, var, coords, false);
1433
1434 switch (intr->intrinsic) {
1435 case nir_intrinsic_image_deref_atomic_add:
1436 atomic = ir3_ATOMIC_ADD_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1437 break;
1438 case nir_intrinsic_image_deref_atomic_min:
1439 atomic = ir3_ATOMIC_MIN_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1440 break;
1441 case nir_intrinsic_image_deref_atomic_max:
1442 atomic = ir3_ATOMIC_MAX_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1443 break;
1444 case nir_intrinsic_image_deref_atomic_and:
1445 atomic = ir3_ATOMIC_AND_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1446 break;
1447 case nir_intrinsic_image_deref_atomic_or:
1448 atomic = ir3_ATOMIC_OR_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1449 break;
1450 case nir_intrinsic_image_deref_atomic_xor:
1451 atomic = ir3_ATOMIC_XOR_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1452 break;
1453 case nir_intrinsic_image_deref_atomic_exchange:
1454 atomic = ir3_ATOMIC_XCHG_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1455 break;
1456 case nir_intrinsic_image_deref_atomic_comp_swap:
1457 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1458 src0 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1459 ir3_get_src(ctx, &intr->src[4])[0],
1460 src0,
1461 }, 2);
1462 atomic = ir3_ATOMIC_CMPXCHG_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1463 break;
1464 default:
1465 unreachable("boo");
1466 }
1467
1468 atomic->cat6.iim_val = 1;
1469 atomic->cat6.d = ncoords;
1470 atomic->cat6.type = get_image_type(var);
1471 atomic->cat6.typed = true;
1472 atomic->barrier_class = IR3_BARRIER_IMAGE_W;
1473 atomic->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W;
1474
1475 /* even if nothing consume the result, we can't DCE the instruction: */
1476 array_insert(b, b->keeps, atomic);
1477
1478 return atomic;
1479 }
1480
1481 static void
1482 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1483 {
1484 struct ir3_block *b = ctx->block;
1485 struct ir3_instruction *barrier;
1486
1487 switch (intr->intrinsic) {
1488 case nir_intrinsic_barrier:
1489 barrier = ir3_BAR(b);
1490 barrier->cat7.g = true;
1491 barrier->cat7.l = true;
1492 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1493 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1494 break;
1495 case nir_intrinsic_memory_barrier:
1496 barrier = ir3_FENCE(b);
1497 barrier->cat7.g = true;
1498 barrier->cat7.r = true;
1499 barrier->cat7.w = true;
1500 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1501 IR3_BARRIER_BUFFER_W;
1502 barrier->barrier_conflict =
1503 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1504 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1505 break;
1506 case nir_intrinsic_memory_barrier_atomic_counter:
1507 case nir_intrinsic_memory_barrier_buffer:
1508 barrier = ir3_FENCE(b);
1509 barrier->cat7.g = true;
1510 barrier->cat7.r = true;
1511 barrier->cat7.w = true;
1512 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1513 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1514 IR3_BARRIER_BUFFER_W;
1515 break;
1516 case nir_intrinsic_memory_barrier_image:
1517 // TODO double check if this should have .g set
1518 barrier = ir3_FENCE(b);
1519 barrier->cat7.g = true;
1520 barrier->cat7.r = true;
1521 barrier->cat7.w = true;
1522 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1523 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1524 IR3_BARRIER_IMAGE_W;
1525 break;
1526 case nir_intrinsic_memory_barrier_shared:
1527 barrier = ir3_FENCE(b);
1528 barrier->cat7.g = true;
1529 barrier->cat7.l = true;
1530 barrier->cat7.r = true;
1531 barrier->cat7.w = true;
1532 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1533 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1534 IR3_BARRIER_SHARED_W;
1535 break;
1536 case nir_intrinsic_group_memory_barrier:
1537 barrier = ir3_FENCE(b);
1538 barrier->cat7.g = true;
1539 barrier->cat7.l = true;
1540 barrier->cat7.r = true;
1541 barrier->cat7.w = true;
1542 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1543 IR3_BARRIER_IMAGE_W |
1544 IR3_BARRIER_BUFFER_W;
1545 barrier->barrier_conflict =
1546 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1547 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1548 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1549 break;
1550 default:
1551 unreachable("boo");
1552 }
1553
1554 /* make sure barrier doesn't get DCE'd */
1555 array_insert(b, b->keeps, barrier);
1556 }
1557
1558 static void add_sysval_input_compmask(struct ir3_context *ctx,
1559 gl_system_value slot, unsigned compmask,
1560 struct ir3_instruction *instr)
1561 {
1562 struct ir3_shader_variant *so = ctx->so;
1563 unsigned r = regid(so->inputs_count, 0);
1564 unsigned n = so->inputs_count++;
1565
1566 so->inputs[n].sysval = true;
1567 so->inputs[n].slot = slot;
1568 so->inputs[n].compmask = compmask;
1569 so->inputs[n].regid = r;
1570 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1571 so->total_in++;
1572
1573 ctx->ir->ninputs = MAX2(ctx->ir->ninputs, r + 1);
1574 ctx->ir->inputs[r] = instr;
1575 }
1576
1577 static void add_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1578 struct ir3_instruction *instr)
1579 {
1580 add_sysval_input_compmask(ctx, slot, 0x1, instr);
1581 }
1582
1583 static void
1584 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1585 {
1586 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1587 struct ir3_instruction **dst;
1588 struct ir3_instruction * const *src;
1589 struct ir3_block *b = ctx->block;
1590 nir_const_value *const_offset;
1591 int idx, comp;
1592
1593 if (info->has_dest) {
1594 unsigned n = nir_intrinsic_dest_components(intr);
1595 dst = ir3_get_dst(ctx, &intr->dest, n);
1596 } else {
1597 dst = NULL;
1598 }
1599
1600 switch (intr->intrinsic) {
1601 case nir_intrinsic_load_uniform:
1602 idx = nir_intrinsic_base(intr);
1603 const_offset = nir_src_as_const_value(intr->src[0]);
1604 if (const_offset) {
1605 idx += const_offset->u32[0];
1606 for (int i = 0; i < intr->num_components; i++) {
1607 unsigned n = idx * 4 + i;
1608 dst[i] = create_uniform(b, n);
1609 }
1610 } else {
1611 src = ir3_get_src(ctx, &intr->src[0]);
1612 for (int i = 0; i < intr->num_components; i++) {
1613 int n = idx * 4 + i;
1614 dst[i] = create_uniform_indirect(b, n,
1615 ir3_get_addr(ctx, src[0], 4));
1616 }
1617 /* NOTE: if relative addressing is used, we set
1618 * constlen in the compiler (to worst-case value)
1619 * since we don't know in the assembler what the max
1620 * addr reg value can be:
1621 */
1622 ctx->so->constlen = ctx->s->num_uniforms;
1623 }
1624 break;
1625 case nir_intrinsic_load_ubo:
1626 emit_intrinsic_load_ubo(ctx, intr, dst);
1627 break;
1628 case nir_intrinsic_load_input:
1629 idx = nir_intrinsic_base(intr);
1630 comp = nir_intrinsic_component(intr);
1631 const_offset = nir_src_as_const_value(intr->src[0]);
1632 if (const_offset) {
1633 idx += const_offset->u32[0];
1634 for (int i = 0; i < intr->num_components; i++) {
1635 unsigned n = idx * 4 + i + comp;
1636 dst[i] = ctx->ir->inputs[n];
1637 }
1638 } else {
1639 src = ir3_get_src(ctx, &intr->src[0]);
1640 struct ir3_instruction *collect =
1641 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ir->ninputs);
1642 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1643 for (int i = 0; i < intr->num_components; i++) {
1644 unsigned n = idx * 4 + i + comp;
1645 dst[i] = create_indirect_load(ctx, ctx->ir->ninputs,
1646 n, addr, collect);
1647 }
1648 }
1649 break;
1650 case nir_intrinsic_load_ssbo:
1651 emit_intrinsic_load_ssbo(ctx, intr, dst);
1652 break;
1653 case nir_intrinsic_store_ssbo:
1654 emit_intrinsic_store_ssbo(ctx, intr);
1655 break;
1656 case nir_intrinsic_get_buffer_size:
1657 emit_intrinsic_ssbo_size(ctx, intr, dst);
1658 break;
1659 case nir_intrinsic_ssbo_atomic_add:
1660 case nir_intrinsic_ssbo_atomic_imin:
1661 case nir_intrinsic_ssbo_atomic_umin:
1662 case nir_intrinsic_ssbo_atomic_imax:
1663 case nir_intrinsic_ssbo_atomic_umax:
1664 case nir_intrinsic_ssbo_atomic_and:
1665 case nir_intrinsic_ssbo_atomic_or:
1666 case nir_intrinsic_ssbo_atomic_xor:
1667 case nir_intrinsic_ssbo_atomic_exchange:
1668 case nir_intrinsic_ssbo_atomic_comp_swap:
1669 dst[0] = emit_intrinsic_atomic_ssbo(ctx, intr);
1670 break;
1671 case nir_intrinsic_load_shared:
1672 emit_intrinsic_load_shared(ctx, intr, dst);
1673 break;
1674 case nir_intrinsic_store_shared:
1675 emit_intrinsic_store_shared(ctx, intr);
1676 break;
1677 case nir_intrinsic_shared_atomic_add:
1678 case nir_intrinsic_shared_atomic_imin:
1679 case nir_intrinsic_shared_atomic_umin:
1680 case nir_intrinsic_shared_atomic_imax:
1681 case nir_intrinsic_shared_atomic_umax:
1682 case nir_intrinsic_shared_atomic_and:
1683 case nir_intrinsic_shared_atomic_or:
1684 case nir_intrinsic_shared_atomic_xor:
1685 case nir_intrinsic_shared_atomic_exchange:
1686 case nir_intrinsic_shared_atomic_comp_swap:
1687 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1688 break;
1689 case nir_intrinsic_image_deref_load:
1690 emit_intrinsic_load_image(ctx, intr, dst);
1691 break;
1692 case nir_intrinsic_image_deref_store:
1693 emit_intrinsic_store_image(ctx, intr);
1694 break;
1695 case nir_intrinsic_image_deref_size:
1696 emit_intrinsic_image_size(ctx, intr, dst);
1697 break;
1698 case nir_intrinsic_image_deref_atomic_add:
1699 case nir_intrinsic_image_deref_atomic_min:
1700 case nir_intrinsic_image_deref_atomic_max:
1701 case nir_intrinsic_image_deref_atomic_and:
1702 case nir_intrinsic_image_deref_atomic_or:
1703 case nir_intrinsic_image_deref_atomic_xor:
1704 case nir_intrinsic_image_deref_atomic_exchange:
1705 case nir_intrinsic_image_deref_atomic_comp_swap:
1706 dst[0] = emit_intrinsic_atomic_image(ctx, intr);
1707 break;
1708 case nir_intrinsic_barrier:
1709 case nir_intrinsic_memory_barrier:
1710 case nir_intrinsic_group_memory_barrier:
1711 case nir_intrinsic_memory_barrier_atomic_counter:
1712 case nir_intrinsic_memory_barrier_buffer:
1713 case nir_intrinsic_memory_barrier_image:
1714 case nir_intrinsic_memory_barrier_shared:
1715 emit_intrinsic_barrier(ctx, intr);
1716 /* note that blk ptr no longer valid, make that obvious: */
1717 b = NULL;
1718 break;
1719 case nir_intrinsic_store_output:
1720 idx = nir_intrinsic_base(intr);
1721 comp = nir_intrinsic_component(intr);
1722 const_offset = nir_src_as_const_value(intr->src[1]);
1723 compile_assert(ctx, const_offset != NULL);
1724 idx += const_offset->u32[0];
1725
1726 src = ir3_get_src(ctx, &intr->src[0]);
1727 for (int i = 0; i < intr->num_components; i++) {
1728 unsigned n = idx * 4 + i + comp;
1729 ctx->ir->outputs[n] = src[i];
1730 }
1731 break;
1732 case nir_intrinsic_load_base_vertex:
1733 case nir_intrinsic_load_first_vertex:
1734 if (!ctx->basevertex) {
1735 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1736 add_sysval_input(ctx, SYSTEM_VALUE_FIRST_VERTEX, ctx->basevertex);
1737 }
1738 dst[0] = ctx->basevertex;
1739 break;
1740 case nir_intrinsic_load_vertex_id_zero_base:
1741 case nir_intrinsic_load_vertex_id:
1742 if (!ctx->vertex_id) {
1743 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1744 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1745 ctx->vertex_id = create_input(ctx, 0);
1746 add_sysval_input(ctx, sv, ctx->vertex_id);
1747 }
1748 dst[0] = ctx->vertex_id;
1749 break;
1750 case nir_intrinsic_load_instance_id:
1751 if (!ctx->instance_id) {
1752 ctx->instance_id = create_input(ctx, 0);
1753 add_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID,
1754 ctx->instance_id);
1755 }
1756 dst[0] = ctx->instance_id;
1757 break;
1758 case nir_intrinsic_load_sample_id:
1759 case nir_intrinsic_load_sample_id_no_per_sample:
1760 if (!ctx->samp_id) {
1761 ctx->samp_id = create_input(ctx, 0);
1762 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1763 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID,
1764 ctx->samp_id);
1765 }
1766 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1767 break;
1768 case nir_intrinsic_load_sample_mask_in:
1769 if (!ctx->samp_mask_in) {
1770 ctx->samp_mask_in = create_input(ctx, 0);
1771 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN,
1772 ctx->samp_mask_in);
1773 }
1774 dst[0] = ctx->samp_mask_in;
1775 break;
1776 case nir_intrinsic_load_user_clip_plane:
1777 idx = nir_intrinsic_ucp_id(intr);
1778 for (int i = 0; i < intr->num_components; i++) {
1779 unsigned n = idx * 4 + i;
1780 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1781 }
1782 break;
1783 case nir_intrinsic_load_front_face:
1784 if (!ctx->frag_face) {
1785 ctx->so->frag_face = true;
1786 ctx->frag_face = create_input(ctx, 0);
1787 add_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, ctx->frag_face);
1788 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1789 }
1790 /* for fragface, we get -1 for back and 0 for front. However this is
1791 * the inverse of what nir expects (where ~0 is true).
1792 */
1793 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1794 dst[0] = ir3_NOT_B(b, dst[0], 0);
1795 break;
1796 case nir_intrinsic_load_local_invocation_id:
1797 if (!ctx->local_invocation_id) {
1798 ctx->local_invocation_id = create_input_compmask(ctx, 0, 0x7);
1799 add_sysval_input_compmask(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID,
1800 0x7, ctx->local_invocation_id);
1801 }
1802 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1803 break;
1804 case nir_intrinsic_load_work_group_id:
1805 if (!ctx->work_group_id) {
1806 ctx->work_group_id = create_input_compmask(ctx, 0, 0x7);
1807 add_sysval_input_compmask(ctx, SYSTEM_VALUE_WORK_GROUP_ID,
1808 0x7, ctx->work_group_id);
1809 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1810 }
1811 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1812 break;
1813 case nir_intrinsic_load_num_work_groups:
1814 for (int i = 0; i < intr->num_components; i++) {
1815 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1816 }
1817 break;
1818 case nir_intrinsic_load_local_group_size:
1819 for (int i = 0; i < intr->num_components; i++) {
1820 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1821 }
1822 break;
1823 case nir_intrinsic_discard_if:
1824 case nir_intrinsic_discard: {
1825 struct ir3_instruction *cond, *kill;
1826
1827 if (intr->intrinsic == nir_intrinsic_discard_if) {
1828 /* conditional discard: */
1829 src = ir3_get_src(ctx, &intr->src[0]);
1830 cond = ir3_b2n(b, src[0]);
1831 } else {
1832 /* unconditional discard: */
1833 cond = create_immed(b, 1);
1834 }
1835
1836 /* NOTE: only cmps.*.* can write p0.x: */
1837 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1838 cond->cat2.condition = IR3_COND_NE;
1839
1840 /* condition always goes in predicate register: */
1841 cond->regs[0]->num = regid(REG_P0, 0);
1842
1843 kill = ir3_KILL(b, cond, 0);
1844 array_insert(ctx->ir, ctx->ir->predicates, kill);
1845
1846 array_insert(b, b->keeps, kill);
1847 ctx->so->has_kill = true;
1848
1849 break;
1850 }
1851 default:
1852 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1853 nir_intrinsic_infos[intr->intrinsic].name);
1854 break;
1855 }
1856
1857 if (info->has_dest)
1858 put_dst(ctx, &intr->dest);
1859 }
1860
1861 static void
1862 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1863 {
1864 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1865 instr->def.num_components);
1866 type_t type = (instr->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1867
1868 for (int i = 0; i < instr->def.num_components; i++)
1869 dst[i] = create_immed_typed(ctx->block, instr->value.u32[i], type);
1870 }
1871
1872 static void
1873 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1874 {
1875 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1876 undef->def.num_components);
1877 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1878
1879 /* backend doesn't want undefined instructions, so just plug
1880 * in 0.0..
1881 */
1882 for (int i = 0; i < undef->def.num_components; i++)
1883 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1884 }
1885
1886 /*
1887 * texture fetch/sample instructions:
1888 */
1889
1890 static void
1891 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1892 {
1893 unsigned coords, flags = 0;
1894
1895 /* note: would use tex->coord_components.. except txs.. also,
1896 * since array index goes after shadow ref, we don't want to
1897 * count it:
1898 */
1899 switch (tex->sampler_dim) {
1900 case GLSL_SAMPLER_DIM_1D:
1901 case GLSL_SAMPLER_DIM_BUF:
1902 coords = 1;
1903 break;
1904 case GLSL_SAMPLER_DIM_2D:
1905 case GLSL_SAMPLER_DIM_RECT:
1906 case GLSL_SAMPLER_DIM_EXTERNAL:
1907 case GLSL_SAMPLER_DIM_MS:
1908 coords = 2;
1909 break;
1910 case GLSL_SAMPLER_DIM_3D:
1911 case GLSL_SAMPLER_DIM_CUBE:
1912 coords = 3;
1913 flags |= IR3_INSTR_3D;
1914 break;
1915 default:
1916 unreachable("bad sampler_dim");
1917 }
1918
1919 if (tex->is_shadow && tex->op != nir_texop_lod)
1920 flags |= IR3_INSTR_S;
1921
1922 if (tex->is_array && tex->op != nir_texop_lod)
1923 flags |= IR3_INSTR_A;
1924
1925 *flagsp = flags;
1926 *coordsp = coords;
1927 }
1928
1929 static void
1930 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1931 {
1932 struct ir3_block *b = ctx->block;
1933 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1934 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1935 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1936 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1937 unsigned i, coords, flags;
1938 unsigned nsrc0 = 0, nsrc1 = 0;
1939 type_t type;
1940 opc_t opc = 0;
1941
1942 coord = off = ddx = ddy = NULL;
1943 lod = proj = compare = sample_index = NULL;
1944
1945 /* TODO: might just be one component for gathers? */
1946 dst = ir3_get_dst(ctx, &tex->dest, 4);
1947
1948 for (unsigned i = 0; i < tex->num_srcs; i++) {
1949 switch (tex->src[i].src_type) {
1950 case nir_tex_src_coord:
1951 coord = ir3_get_src(ctx, &tex->src[i].src);
1952 break;
1953 case nir_tex_src_bias:
1954 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1955 has_bias = true;
1956 break;
1957 case nir_tex_src_lod:
1958 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1959 has_lod = true;
1960 break;
1961 case nir_tex_src_comparator: /* shadow comparator */
1962 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1963 break;
1964 case nir_tex_src_projector:
1965 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1966 has_proj = true;
1967 break;
1968 case nir_tex_src_offset:
1969 off = ir3_get_src(ctx, &tex->src[i].src);
1970 has_off = true;
1971 break;
1972 case nir_tex_src_ddx:
1973 ddx = ir3_get_src(ctx, &tex->src[i].src);
1974 break;
1975 case nir_tex_src_ddy:
1976 ddy = ir3_get_src(ctx, &tex->src[i].src);
1977 break;
1978 case nir_tex_src_ms_index:
1979 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
1980 break;
1981 default:
1982 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
1983 tex->src[i].src_type);
1984 return;
1985 }
1986 }
1987
1988 switch (tex->op) {
1989 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
1990 case nir_texop_txb: opc = OPC_SAMB; break;
1991 case nir_texop_txl: opc = OPC_SAML; break;
1992 case nir_texop_txd: opc = OPC_SAMGQ; break;
1993 case nir_texop_txf: opc = OPC_ISAML; break;
1994 case nir_texop_lod: opc = OPC_GETLOD; break;
1995 case nir_texop_tg4:
1996 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1997 * what blob does, seems gather is broken?), and a3xx did
1998 * not support it (but probably could also emulate).
1999 */
2000 switch (tex->component) {
2001 case 0: opc = OPC_GATHER4R; break;
2002 case 1: opc = OPC_GATHER4G; break;
2003 case 2: opc = OPC_GATHER4B; break;
2004 case 3: opc = OPC_GATHER4A; break;
2005 }
2006 break;
2007 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2008 case nir_texop_txs:
2009 case nir_texop_query_levels:
2010 case nir_texop_texture_samples:
2011 case nir_texop_samples_identical:
2012 case nir_texop_txf_ms_mcs:
2013 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2014 return;
2015 }
2016
2017 tex_info(tex, &flags, &coords);
2018
2019 /*
2020 * lay out the first argument in the proper order:
2021 * - actual coordinates first
2022 * - shadow reference
2023 * - array index
2024 * - projection w
2025 * - starting at offset 4, dpdx.xy, dpdy.xy
2026 *
2027 * bias/lod go into the second arg
2028 */
2029
2030 /* insert tex coords: */
2031 for (i = 0; i < coords; i++)
2032 src0[i] = coord[i];
2033
2034 nsrc0 = i;
2035
2036 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2037 * with scaled x coord according to requested sample:
2038 */
2039 if (tex->op == nir_texop_txf_ms) {
2040 if (ctx->compiler->txf_ms_with_isaml) {
2041 /* the samples are laid out in x dimension as
2042 * 0 1 2 3
2043 * x_ms = (x << ms) + sample_index;
2044 */
2045 struct ir3_instruction *ms;
2046 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2047
2048 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2049 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2050
2051 opc = OPC_ISAML;
2052 } else {
2053 src0[nsrc0++] = sample_index;
2054 }
2055 }
2056
2057 /* scale up integer coords for TXF based on the LOD */
2058 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2059 assert(has_lod);
2060 for (i = 0; i < coords; i++)
2061 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2062 }
2063
2064 if (coords == 1) {
2065 /* hw doesn't do 1d, so we treat it as 2d with
2066 * height of 1, and patch up the y coord.
2067 * TODO: y coord should be (int)0 in some cases..
2068 */
2069 src0[nsrc0++] = create_immed(b, fui(0.5));
2070 }
2071
2072 if (tex->is_shadow && tex->op != nir_texop_lod)
2073 src0[nsrc0++] = compare;
2074
2075 if (tex->is_array && tex->op != nir_texop_lod) {
2076 struct ir3_instruction *idx = coord[coords];
2077
2078 /* the array coord for cube arrays needs 0.5 added to it */
2079 if (ctx->compiler->array_index_add_half && (opc != OPC_ISAML))
2080 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2081
2082 src0[nsrc0++] = idx;
2083 }
2084
2085 if (has_proj) {
2086 src0[nsrc0++] = proj;
2087 flags |= IR3_INSTR_P;
2088 }
2089
2090 /* pad to 4, then ddx/ddy: */
2091 if (tex->op == nir_texop_txd) {
2092 while (nsrc0 < 4)
2093 src0[nsrc0++] = create_immed(b, fui(0.0));
2094 for (i = 0; i < coords; i++)
2095 src0[nsrc0++] = ddx[i];
2096 if (coords < 2)
2097 src0[nsrc0++] = create_immed(b, fui(0.0));
2098 for (i = 0; i < coords; i++)
2099 src0[nsrc0++] = ddy[i];
2100 if (coords < 2)
2101 src0[nsrc0++] = create_immed(b, fui(0.0));
2102 }
2103
2104 /*
2105 * second argument (if applicable):
2106 * - offsets
2107 * - lod
2108 * - bias
2109 */
2110 if (has_off | has_lod | has_bias) {
2111 if (has_off) {
2112 unsigned off_coords = coords;
2113 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2114 off_coords--;
2115 for (i = 0; i < off_coords; i++)
2116 src1[nsrc1++] = off[i];
2117 if (off_coords < 2)
2118 src1[nsrc1++] = create_immed(b, fui(0.0));
2119 flags |= IR3_INSTR_O;
2120 }
2121
2122 if (has_lod | has_bias)
2123 src1[nsrc1++] = lod;
2124 }
2125
2126 switch (tex->dest_type) {
2127 case nir_type_invalid:
2128 case nir_type_float:
2129 type = TYPE_F32;
2130 break;
2131 case nir_type_int:
2132 type = TYPE_S32;
2133 break;
2134 case nir_type_uint:
2135 case nir_type_bool:
2136 type = TYPE_U32;
2137 break;
2138 default:
2139 unreachable("bad dest_type");
2140 }
2141
2142 if (opc == OPC_GETLOD)
2143 type = TYPE_U32;
2144
2145 unsigned tex_idx = tex->texture_index;
2146
2147 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex_idx);
2148
2149 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2150 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2151
2152 sam = ir3_SAM(b, opc, type, 0b1111, flags,
2153 tex_idx, tex_idx, col0, col1);
2154
2155 if ((ctx->astc_srgb & (1 << tex_idx)) && !nir_tex_instr_is_query(tex)) {
2156 /* only need first 3 components: */
2157 sam->regs[0]->wrmask = 0x7;
2158 ir3_split_dest(b, dst, sam, 0, 3);
2159
2160 /* we need to sample the alpha separately with a non-ASTC
2161 * texture state:
2162 */
2163 sam = ir3_SAM(b, opc, type, 0b1000, flags,
2164 tex_idx, tex_idx, col0, col1);
2165
2166 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2167
2168 /* fixup .w component: */
2169 ir3_split_dest(b, &dst[3], sam, 3, 1);
2170 } else {
2171 /* normal (non-workaround) case: */
2172 ir3_split_dest(b, dst, sam, 0, 4);
2173 }
2174
2175 /* GETLOD returns results in 4.8 fixed point */
2176 if (opc == OPC_GETLOD) {
2177 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2178
2179 compile_assert(ctx, tex->dest_type == nir_type_float);
2180 for (i = 0; i < 2; i++) {
2181 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_U32, TYPE_F32), 0,
2182 factor, 0);
2183 }
2184 }
2185
2186 put_dst(ctx, &tex->dest);
2187 }
2188
2189 static void
2190 emit_tex_query_levels(struct ir3_context *ctx, nir_tex_instr *tex)
2191 {
2192 struct ir3_block *b = ctx->block;
2193 struct ir3_instruction **dst, *sam;
2194
2195 dst = ir3_get_dst(ctx, &tex->dest, 1);
2196
2197 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, 0b0100, 0,
2198 tex->texture_index, tex->texture_index, NULL, NULL);
2199
2200 /* even though there is only one component, since it ends
2201 * up in .z rather than .x, we need a split_dest()
2202 */
2203 ir3_split_dest(b, dst, sam, 0, 3);
2204
2205 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2206 * the value in TEX_CONST_0 is zero-based.
2207 */
2208 if (ctx->compiler->levels_add_one)
2209 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2210
2211 put_dst(ctx, &tex->dest);
2212 }
2213
2214 static void
2215 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2216 {
2217 struct ir3_block *b = ctx->block;
2218 struct ir3_instruction **dst, *sam;
2219 struct ir3_instruction *lod;
2220 unsigned flags, coords;
2221
2222 tex_info(tex, &flags, &coords);
2223
2224 /* Actually we want the number of dimensions, not coordinates. This
2225 * distinction only matters for cubes.
2226 */
2227 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2228 coords = 2;
2229
2230 dst = ir3_get_dst(ctx, &tex->dest, 4);
2231
2232 compile_assert(ctx, tex->num_srcs == 1);
2233 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2234
2235 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2236
2237 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
2238 tex->texture_index, tex->texture_index, lod, NULL);
2239
2240 ir3_split_dest(b, dst, sam, 0, 4);
2241
2242 /* Array size actually ends up in .w rather than .z. This doesn't
2243 * matter for miplevel 0, but for higher mips the value in z is
2244 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2245 * returned, which means that we have to add 1 to it for arrays.
2246 */
2247 if (tex->is_array) {
2248 if (ctx->compiler->levels_add_one) {
2249 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2250 } else {
2251 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2252 }
2253 }
2254
2255 put_dst(ctx, &tex->dest);
2256 }
2257
2258 static void
2259 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2260 {
2261 switch (jump->type) {
2262 case nir_jump_break:
2263 case nir_jump_continue:
2264 case nir_jump_return:
2265 /* I *think* we can simply just ignore this, and use the
2266 * successor block link to figure out where we need to
2267 * jump to for break/continue
2268 */
2269 break;
2270 default:
2271 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2272 break;
2273 }
2274 }
2275
2276 static void
2277 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2278 {
2279 switch (instr->type) {
2280 case nir_instr_type_alu:
2281 emit_alu(ctx, nir_instr_as_alu(instr));
2282 break;
2283 case nir_instr_type_deref:
2284 /* ignored, handled as part of the intrinsic they are src to */
2285 break;
2286 case nir_instr_type_intrinsic:
2287 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2288 break;
2289 case nir_instr_type_load_const:
2290 emit_load_const(ctx, nir_instr_as_load_const(instr));
2291 break;
2292 case nir_instr_type_ssa_undef:
2293 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2294 break;
2295 case nir_instr_type_tex: {
2296 nir_tex_instr *tex = nir_instr_as_tex(instr);
2297 /* couple tex instructions get special-cased:
2298 */
2299 switch (tex->op) {
2300 case nir_texop_txs:
2301 emit_tex_txs(ctx, tex);
2302 break;
2303 case nir_texop_query_levels:
2304 emit_tex_query_levels(ctx, tex);
2305 break;
2306 default:
2307 emit_tex(ctx, tex);
2308 break;
2309 }
2310 break;
2311 }
2312 case nir_instr_type_jump:
2313 emit_jump(ctx, nir_instr_as_jump(instr));
2314 break;
2315 case nir_instr_type_phi:
2316 /* we have converted phi webs to regs in NIR by now */
2317 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2318 break;
2319 case nir_instr_type_call:
2320 case nir_instr_type_parallel_copy:
2321 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2322 break;
2323 }
2324 }
2325
2326 static struct ir3_block *
2327 get_block(struct ir3_context *ctx, const nir_block *nblock)
2328 {
2329 struct ir3_block *block;
2330 struct hash_entry *hentry;
2331 unsigned i;
2332
2333 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2334 if (hentry)
2335 return hentry->data;
2336
2337 block = ir3_block_create(ctx->ir);
2338 block->nblock = nblock;
2339 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2340
2341 block->predecessors_count = nblock->predecessors->entries;
2342 block->predecessors = ralloc_array_size(block,
2343 sizeof(block->predecessors[0]), block->predecessors_count);
2344 i = 0;
2345 set_foreach(nblock->predecessors, sentry) {
2346 block->predecessors[i++] = get_block(ctx, sentry->key);
2347 }
2348
2349 return block;
2350 }
2351
2352 static void
2353 emit_block(struct ir3_context *ctx, nir_block *nblock)
2354 {
2355 struct ir3_block *block = get_block(ctx, nblock);
2356
2357 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2358 if (nblock->successors[i]) {
2359 block->successors[i] =
2360 get_block(ctx, nblock->successors[i]);
2361 }
2362 }
2363
2364 ctx->block = block;
2365 list_addtail(&block->node, &ctx->ir->block_list);
2366
2367 /* re-emit addr register in each block if needed: */
2368 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2369 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2370 ctx->addr_ht[i] = NULL;
2371 }
2372
2373 nir_foreach_instr(instr, nblock) {
2374 ctx->cur_instr = instr;
2375 emit_instr(ctx, instr);
2376 ctx->cur_instr = NULL;
2377 if (ctx->error)
2378 return;
2379 }
2380 }
2381
2382 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2383
2384 static void
2385 emit_if(struct ir3_context *ctx, nir_if *nif)
2386 {
2387 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2388
2389 ctx->block->condition =
2390 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2391
2392 emit_cf_list(ctx, &nif->then_list);
2393 emit_cf_list(ctx, &nif->else_list);
2394 }
2395
2396 static void
2397 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2398 {
2399 emit_cf_list(ctx, &nloop->body);
2400 }
2401
2402 static void
2403 stack_push(struct ir3_context *ctx)
2404 {
2405 ctx->stack++;
2406 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2407 }
2408
2409 static void
2410 stack_pop(struct ir3_context *ctx)
2411 {
2412 compile_assert(ctx, ctx->stack > 0);
2413 ctx->stack--;
2414 }
2415
2416 static void
2417 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2418 {
2419 foreach_list_typed(nir_cf_node, node, node, list) {
2420 switch (node->type) {
2421 case nir_cf_node_block:
2422 emit_block(ctx, nir_cf_node_as_block(node));
2423 break;
2424 case nir_cf_node_if:
2425 stack_push(ctx);
2426 emit_if(ctx, nir_cf_node_as_if(node));
2427 stack_pop(ctx);
2428 break;
2429 case nir_cf_node_loop:
2430 stack_push(ctx);
2431 emit_loop(ctx, nir_cf_node_as_loop(node));
2432 stack_pop(ctx);
2433 break;
2434 case nir_cf_node_function:
2435 ir3_context_error(ctx, "TODO\n");
2436 break;
2437 }
2438 }
2439 }
2440
2441 /* emit stream-out code. At this point, the current block is the original
2442 * (nir) end block, and nir ensures that all flow control paths terminate
2443 * into the end block. We re-purpose the original end block to generate
2444 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2445 * block holding stream-out write instructions, followed by the new end
2446 * block:
2447 *
2448 * blockOrigEnd {
2449 * p0.x = (vtxcnt < maxvtxcnt)
2450 * // succs: blockStreamOut, blockNewEnd
2451 * }
2452 * blockStreamOut {
2453 * ... stream-out instructions ...
2454 * // succs: blockNewEnd
2455 * }
2456 * blockNewEnd {
2457 * }
2458 */
2459 static void
2460 emit_stream_out(struct ir3_context *ctx)
2461 {
2462 struct ir3_shader_variant *v = ctx->so;
2463 struct ir3 *ir = ctx->ir;
2464 struct ir3_stream_output_info *strmout =
2465 &ctx->so->shader->stream_output;
2466 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2467 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2468 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2469
2470 /* create vtxcnt input in input block at top of shader,
2471 * so that it is seen as live over the entire duration
2472 * of the shader:
2473 */
2474 vtxcnt = create_input(ctx, 0);
2475 add_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, vtxcnt);
2476
2477 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2478
2479 /* at this point, we are at the original 'end' block,
2480 * re-purpose this block to stream-out condition, then
2481 * append stream-out block and new-end block
2482 */
2483 orig_end_block = ctx->block;
2484
2485 // TODO these blocks need to update predecessors..
2486 // maybe w/ store_global intrinsic, we could do this
2487 // stuff in nir->nir pass
2488
2489 stream_out_block = ir3_block_create(ir);
2490 list_addtail(&stream_out_block->node, &ir->block_list);
2491
2492 new_end_block = ir3_block_create(ir);
2493 list_addtail(&new_end_block->node, &ir->block_list);
2494
2495 orig_end_block->successors[0] = stream_out_block;
2496 orig_end_block->successors[1] = new_end_block;
2497 stream_out_block->successors[0] = new_end_block;
2498
2499 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2500 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2501 cond->regs[0]->num = regid(REG_P0, 0);
2502 cond->cat2.condition = IR3_COND_LT;
2503
2504 /* condition goes on previous block to the conditional,
2505 * since it is used to pick which of the two successor
2506 * paths to take:
2507 */
2508 orig_end_block->condition = cond;
2509
2510 /* switch to stream_out_block to generate the stream-out
2511 * instructions:
2512 */
2513 ctx->block = stream_out_block;
2514
2515 /* Calculate base addresses based on vtxcnt. Instructions
2516 * generated for bases not used in following loop will be
2517 * stripped out in the backend.
2518 */
2519 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2520 unsigned stride = strmout->stride[i];
2521 struct ir3_instruction *base, *off;
2522
2523 base = create_uniform(ctx->block, regid(v->constbase.tfbo, i));
2524
2525 /* 24-bit should be enough: */
2526 off = ir3_MUL_U(ctx->block, vtxcnt, 0,
2527 create_immed(ctx->block, stride * 4), 0);
2528
2529 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2530 }
2531
2532 /* Generate the per-output store instructions: */
2533 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2534 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2535 unsigned c = j + strmout->output[i].start_component;
2536 struct ir3_instruction *base, *out, *stg;
2537
2538 base = bases[strmout->output[i].output_buffer];
2539 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2540
2541 stg = ir3_STG(ctx->block, base, 0, out, 0,
2542 create_immed(ctx->block, 1), 0);
2543 stg->cat6.type = TYPE_U32;
2544 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2545
2546 array_insert(ctx->block, ctx->block->keeps, stg);
2547 }
2548 }
2549
2550 /* and finally switch to the new_end_block: */
2551 ctx->block = new_end_block;
2552 }
2553
2554 static void
2555 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2556 {
2557 nir_metadata_require(impl, nir_metadata_block_index);
2558
2559 compile_assert(ctx, ctx->stack == 0);
2560
2561 emit_cf_list(ctx, &impl->body);
2562 emit_block(ctx, impl->end_block);
2563
2564 compile_assert(ctx, ctx->stack == 0);
2565
2566 /* at this point, we should have a single empty block,
2567 * into which we emit the 'end' instruction.
2568 */
2569 compile_assert(ctx, list_empty(&ctx->block->instr_list));
2570
2571 /* If stream-out (aka transform-feedback) enabled, emit the
2572 * stream-out instructions, followed by a new empty block (into
2573 * which the 'end' instruction lands).
2574 *
2575 * NOTE: it is done in this order, rather than inserting before
2576 * we emit end_block, because NIR guarantees that all blocks
2577 * flow into end_block, and that end_block has no successors.
2578 * So by re-purposing end_block as the first block of stream-
2579 * out, we guarantee that all exit paths flow into the stream-
2580 * out instructions.
2581 */
2582 if ((ctx->compiler->gpu_id < 500) &&
2583 (ctx->so->shader->stream_output.num_outputs > 0) &&
2584 !ctx->so->binning_pass) {
2585 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2586 emit_stream_out(ctx);
2587 }
2588
2589 ir3_END(ctx->block);
2590 }
2591
2592 static struct ir3_instruction *
2593 create_frag_coord(struct ir3_context *ctx, unsigned comp)
2594 {
2595 struct ir3_block *block = ctx->block;
2596 struct ir3_instruction *instr;
2597
2598 if (!ctx->frag_coord) {
2599 ctx->frag_coord = create_input_compmask(ctx, 0, 0xf);
2600 /* defer add_sysval_input() until after all inputs created */
2601 }
2602
2603 ir3_split_dest(block, &instr, ctx->frag_coord, comp, 1);
2604
2605 switch (comp) {
2606 case 0: /* .x */
2607 case 1: /* .y */
2608 /* for frag_coord, we get unsigned values.. we need
2609 * to subtract (integer) 8 and divide by 16 (right-
2610 * shift by 4) then convert to float:
2611 *
2612 * sub.s tmp, src, 8
2613 * shr.b tmp, tmp, 4
2614 * mov.u32f32 dst, tmp
2615 *
2616 */
2617 instr = ir3_SUB_S(block, instr, 0,
2618 create_immed(block, 8), 0);
2619 instr = ir3_SHR_B(block, instr, 0,
2620 create_immed(block, 4), 0);
2621 instr = ir3_COV(block, instr, TYPE_U32, TYPE_F32);
2622
2623 return instr;
2624 case 2: /* .z */
2625 case 3: /* .w */
2626 default:
2627 /* seems that we can use these as-is: */
2628 return instr;
2629 }
2630 }
2631
2632 static void
2633 setup_input(struct ir3_context *ctx, nir_variable *in)
2634 {
2635 struct ir3_shader_variant *so = ctx->so;
2636 unsigned ncomp = glsl_get_components(in->type);
2637 unsigned n = in->data.driver_location;
2638 unsigned frac = in->data.location_frac;
2639 unsigned slot = in->data.location;
2640
2641 /* skip unread inputs, we could end up with (for example), unsplit
2642 * matrix/etc inputs in the case they are not read, so just silently
2643 * skip these.
2644 */
2645 if (ncomp > 4)
2646 return;
2647
2648 so->inputs[n].slot = slot;
2649 so->inputs[n].compmask = (1 << (ncomp + frac)) - 1;
2650 so->inputs_count = MAX2(so->inputs_count, n + 1);
2651 so->inputs[n].interpolate = in->data.interpolation;
2652
2653 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2654 for (int i = 0; i < ncomp; i++) {
2655 struct ir3_instruction *instr = NULL;
2656 unsigned idx = (n * 4) + i + frac;
2657
2658 if (slot == VARYING_SLOT_POS) {
2659 so->inputs[n].bary = false;
2660 so->frag_coord = true;
2661 instr = create_frag_coord(ctx, i);
2662 } else if (slot == VARYING_SLOT_PNTC) {
2663 /* see for example st_nir_fixup_varying_slots().. this is
2664 * maybe a bit mesa/st specific. But we need things to line
2665 * up for this in fdN_program:
2666 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2667 * if (emit->sprite_coord_enable & texmask) {
2668 * ...
2669 * }
2670 */
2671 so->inputs[n].slot = VARYING_SLOT_VAR8;
2672 so->inputs[n].bary = true;
2673 instr = create_frag_input(ctx, false);
2674 } else {
2675 bool use_ldlv = false;
2676
2677 /* detect the special case for front/back colors where
2678 * we need to do flat vs smooth shading depending on
2679 * rast state:
2680 */
2681 if (in->data.interpolation == INTERP_MODE_NONE) {
2682 switch (slot) {
2683 case VARYING_SLOT_COL0:
2684 case VARYING_SLOT_COL1:
2685 case VARYING_SLOT_BFC0:
2686 case VARYING_SLOT_BFC1:
2687 so->inputs[n].rasterflat = true;
2688 break;
2689 default:
2690 break;
2691 }
2692 }
2693
2694 if (ctx->compiler->flat_bypass) {
2695 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2696 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2697 use_ldlv = true;
2698 }
2699
2700 so->inputs[n].bary = true;
2701
2702 instr = create_frag_input(ctx, use_ldlv);
2703 }
2704
2705 compile_assert(ctx, idx < ctx->ir->ninputs);
2706
2707 ctx->ir->inputs[idx] = instr;
2708 }
2709 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2710 for (int i = 0; i < ncomp; i++) {
2711 unsigned idx = (n * 4) + i + frac;
2712 compile_assert(ctx, idx < ctx->ir->ninputs);
2713 ctx->ir->inputs[idx] = create_input(ctx, idx);
2714 }
2715 } else {
2716 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2717 }
2718
2719 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2720 so->total_in += ncomp;
2721 }
2722 }
2723
2724 static void
2725 setup_output(struct ir3_context *ctx, nir_variable *out)
2726 {
2727 struct ir3_shader_variant *so = ctx->so;
2728 unsigned ncomp = glsl_get_components(out->type);
2729 unsigned n = out->data.driver_location;
2730 unsigned frac = out->data.location_frac;
2731 unsigned slot = out->data.location;
2732 unsigned comp = 0;
2733
2734 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2735 switch (slot) {
2736 case FRAG_RESULT_DEPTH:
2737 comp = 2; /* tgsi will write to .z component */
2738 so->writes_pos = true;
2739 break;
2740 case FRAG_RESULT_COLOR:
2741 so->color0_mrt = 1;
2742 break;
2743 default:
2744 if (slot >= FRAG_RESULT_DATA0)
2745 break;
2746 ir3_context_error(ctx, "unknown FS output name: %s\n",
2747 gl_frag_result_name(slot));
2748 }
2749 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2750 switch (slot) {
2751 case VARYING_SLOT_POS:
2752 so->writes_pos = true;
2753 break;
2754 case VARYING_SLOT_PSIZ:
2755 so->writes_psize = true;
2756 break;
2757 case VARYING_SLOT_COL0:
2758 case VARYING_SLOT_COL1:
2759 case VARYING_SLOT_BFC0:
2760 case VARYING_SLOT_BFC1:
2761 case VARYING_SLOT_FOGC:
2762 case VARYING_SLOT_CLIP_DIST0:
2763 case VARYING_SLOT_CLIP_DIST1:
2764 case VARYING_SLOT_CLIP_VERTEX:
2765 break;
2766 default:
2767 if (slot >= VARYING_SLOT_VAR0)
2768 break;
2769 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2770 break;
2771 ir3_context_error(ctx, "unknown VS output name: %s\n",
2772 gl_varying_slot_name(slot));
2773 }
2774 } else {
2775 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2776 }
2777
2778 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2779
2780 so->outputs[n].slot = slot;
2781 so->outputs[n].regid = regid(n, comp);
2782 so->outputs_count = MAX2(so->outputs_count, n + 1);
2783
2784 for (int i = 0; i < ncomp; i++) {
2785 unsigned idx = (n * 4) + i + frac;
2786 compile_assert(ctx, idx < ctx->ir->noutputs);
2787 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2788 }
2789
2790 /* if varying packing doesn't happen, we could end up in a situation
2791 * with "holes" in the output, and since the per-generation code that
2792 * sets up varying linkage registers doesn't expect to have more than
2793 * one varying per vec4 slot, pad the holes.
2794 *
2795 * Note that this should probably generate a performance warning of
2796 * some sort.
2797 */
2798 for (int i = 0; i < frac; i++) {
2799 unsigned idx = (n * 4) + i;
2800 if (!ctx->ir->outputs[idx]) {
2801 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2802 }
2803 }
2804 }
2805
2806 static int
2807 max_drvloc(struct exec_list *vars)
2808 {
2809 int drvloc = -1;
2810 nir_foreach_variable(var, vars) {
2811 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2812 }
2813 return drvloc;
2814 }
2815
2816 static const unsigned max_sysvals[] = {
2817 [MESA_SHADER_FRAGMENT] = 24, // TODO
2818 [MESA_SHADER_VERTEX] = 16,
2819 [MESA_SHADER_COMPUTE] = 16, // TODO how many do we actually need?
2820 [MESA_SHADER_KERNEL] = 16, // TODO how many do we actually need?
2821 };
2822
2823 static void
2824 emit_instructions(struct ir3_context *ctx)
2825 {
2826 unsigned ninputs, noutputs;
2827 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
2828
2829 ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
2830 noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
2831
2832 /* we need to leave room for sysvals:
2833 */
2834 ninputs += max_sysvals[ctx->so->type];
2835
2836 ctx->ir = ir3_create(ctx->compiler, ninputs, noutputs);
2837
2838 /* Create inputs in first block: */
2839 ctx->block = get_block(ctx, nir_start_block(fxn));
2840 ctx->in_block = ctx->block;
2841 list_addtail(&ctx->block->node, &ctx->ir->block_list);
2842
2843 ninputs -= max_sysvals[ctx->so->type];
2844
2845 /* for fragment shader, the vcoord input register is used as the
2846 * base for bary.f varying fetch instrs:
2847 */
2848 struct ir3_instruction *vcoord = NULL;
2849 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2850 struct ir3_instruction *xy[2];
2851
2852 vcoord = create_input_compmask(ctx, 0, 0x3);
2853 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
2854
2855 ctx->frag_vcoord = ir3_create_collect(ctx, xy, 2);
2856 }
2857
2858 /* Setup inputs: */
2859 nir_foreach_variable(var, &ctx->s->inputs) {
2860 setup_input(ctx, var);
2861 }
2862
2863 /* Defer add_sysval_input() stuff until after setup_inputs(),
2864 * because sysvals need to be appended after varyings:
2865 */
2866 if (vcoord) {
2867 add_sysval_input_compmask(ctx, SYSTEM_VALUE_VARYING_COORD,
2868 0x3, vcoord);
2869 }
2870
2871 if (ctx->frag_coord) {
2872 add_sysval_input_compmask(ctx, SYSTEM_VALUE_FRAG_COORD,
2873 0xf, ctx->frag_coord);
2874 }
2875
2876 /* Setup outputs: */
2877 nir_foreach_variable(var, &ctx->s->outputs) {
2878 setup_output(ctx, var);
2879 }
2880
2881 /* Setup registers (which should only be arrays): */
2882 nir_foreach_register(reg, &ctx->s->registers) {
2883 ir3_declare_array(ctx, reg);
2884 }
2885
2886 /* NOTE: need to do something more clever when we support >1 fxn */
2887 nir_foreach_register(reg, &fxn->registers) {
2888 ir3_declare_array(ctx, reg);
2889 }
2890 /* And emit the body: */
2891 ctx->impl = fxn;
2892 emit_function(ctx, fxn);
2893 }
2894
2895 /* from NIR perspective, we actually have varying inputs. But the varying
2896 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
2897 * only actual inputs are the sysvals.
2898 */
2899 static void
2900 fixup_frag_inputs(struct ir3_context *ctx)
2901 {
2902 struct ir3_shader_variant *so = ctx->so;
2903 struct ir3 *ir = ctx->ir;
2904 unsigned i = 0;
2905
2906 /* sysvals should appear at the end of the inputs, drop everything else: */
2907 while ((i < so->inputs_count) && !so->inputs[i].sysval)
2908 i++;
2909
2910 /* at IR level, inputs are always blocks of 4 scalars: */
2911 i *= 4;
2912
2913 ir->inputs = &ir->inputs[i];
2914 ir->ninputs -= i;
2915 }
2916
2917 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2918 * need to assign the tex state indexes for these after we know the
2919 * max tex index.
2920 */
2921 static void
2922 fixup_astc_srgb(struct ir3_context *ctx)
2923 {
2924 struct ir3_shader_variant *so = ctx->so;
2925 /* indexed by original tex idx, value is newly assigned alpha sampler
2926 * state tex idx. Zero is invalid since there is at least one sampler
2927 * if we get here.
2928 */
2929 unsigned alt_tex_state[16] = {0};
2930 unsigned tex_idx = ctx->max_texture_index + 1;
2931 unsigned idx = 0;
2932
2933 so->astc_srgb.base = tex_idx;
2934
2935 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
2936 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
2937
2938 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
2939
2940 if (alt_tex_state[sam->cat5.tex] == 0) {
2941 /* assign new alternate/alpha tex state slot: */
2942 alt_tex_state[sam->cat5.tex] = tex_idx++;
2943 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
2944 so->astc_srgb.count++;
2945 }
2946
2947 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
2948 }
2949 }
2950
2951 static void
2952 fixup_binning_pass(struct ir3_context *ctx)
2953 {
2954 struct ir3_shader_variant *so = ctx->so;
2955 struct ir3 *ir = ctx->ir;
2956 unsigned i, j;
2957
2958 for (i = 0, j = 0; i < so->outputs_count; i++) {
2959 unsigned slot = so->outputs[i].slot;
2960
2961 /* throw away everything but first position/psize */
2962 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
2963 if (i != j) {
2964 so->outputs[j] = so->outputs[i];
2965 ir->outputs[(j*4)+0] = ir->outputs[(i*4)+0];
2966 ir->outputs[(j*4)+1] = ir->outputs[(i*4)+1];
2967 ir->outputs[(j*4)+2] = ir->outputs[(i*4)+2];
2968 ir->outputs[(j*4)+3] = ir->outputs[(i*4)+3];
2969 }
2970 j++;
2971 }
2972 }
2973 so->outputs_count = j;
2974 ir->noutputs = j * 4;
2975 }
2976
2977 int
2978 ir3_compile_shader_nir(struct ir3_compiler *compiler,
2979 struct ir3_shader_variant *so)
2980 {
2981 struct ir3_context *ctx;
2982 struct ir3 *ir;
2983 struct ir3_instruction **inputs;
2984 unsigned i, actual_in, inloc;
2985 int ret = 0, max_bary;
2986
2987 assert(!so->ir);
2988
2989 ctx = ir3_context_init(compiler, so);
2990 if (!ctx) {
2991 DBG("INIT failed!");
2992 ret = -1;
2993 goto out;
2994 }
2995
2996 emit_instructions(ctx);
2997
2998 if (ctx->error) {
2999 DBG("EMIT failed!");
3000 ret = -1;
3001 goto out;
3002 }
3003
3004 ir = so->ir = ctx->ir;
3005
3006 /* keep track of the inputs from TGSI perspective.. */
3007 inputs = ir->inputs;
3008
3009 /* but fixup actual inputs for frag shader: */
3010 if (so->type == MESA_SHADER_FRAGMENT)
3011 fixup_frag_inputs(ctx);
3012
3013 /* at this point, for binning pass, throw away unneeded outputs: */
3014 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3015 fixup_binning_pass(ctx);
3016
3017 /* if we want half-precision outputs, mark the output registers
3018 * as half:
3019 */
3020 if (so->key.half_precision) {
3021 for (i = 0; i < ir->noutputs; i++) {
3022 struct ir3_instruction *out = ir->outputs[i];
3023
3024 if (!out)
3025 continue;
3026
3027 /* if frag shader writes z, that needs to be full precision: */
3028 if (so->outputs[i/4].slot == FRAG_RESULT_DEPTH)
3029 continue;
3030
3031 out->regs[0]->flags |= IR3_REG_HALF;
3032 /* output could be a fanout (ie. texture fetch output)
3033 * in which case we need to propagate the half-reg flag
3034 * up to the definer so that RA sees it:
3035 */
3036 if (out->opc == OPC_META_FO) {
3037 out = out->regs[1]->instr;
3038 out->regs[0]->flags |= IR3_REG_HALF;
3039 }
3040
3041 if (out->opc == OPC_MOV) {
3042 out->cat1.dst_type = half_type(out->cat1.dst_type);
3043 }
3044 }
3045 }
3046
3047 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3048 printf("BEFORE CP:\n");
3049 ir3_print(ir);
3050 }
3051
3052 ir3_cp(ir, so);
3053
3054 /* at this point, for binning pass, throw away unneeded outputs:
3055 * Note that for a6xx and later, we do this after ir3_cp to ensure
3056 * that the uniform/constant layout for BS and VS matches, so that
3057 * we can re-use same VS_CONST state group.
3058 */
3059 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
3060 fixup_binning_pass(ctx);
3061
3062 /* Insert mov if there's same instruction for each output.
3063 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
3064 */
3065 for (int i = ir->noutputs - 1; i >= 0; i--) {
3066 if (!ir->outputs[i])
3067 continue;
3068 for (unsigned j = 0; j < i; j++) {
3069 if (ir->outputs[i] == ir->outputs[j]) {
3070 ir->outputs[i] =
3071 ir3_MOV(ir->outputs[i]->block, ir->outputs[i], TYPE_F32);
3072 }
3073 }
3074 }
3075
3076 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3077 printf("BEFORE GROUPING:\n");
3078 ir3_print(ir);
3079 }
3080
3081 ir3_sched_add_deps(ir);
3082
3083 /* Group left/right neighbors, inserting mov's where needed to
3084 * solve conflicts:
3085 */
3086 ir3_group(ir);
3087
3088 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3089 printf("AFTER GROUPING:\n");
3090 ir3_print(ir);
3091 }
3092
3093 ir3_depth(ir);
3094
3095 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3096 printf("AFTER DEPTH:\n");
3097 ir3_print(ir);
3098 }
3099
3100 ret = ir3_sched(ir);
3101 if (ret) {
3102 DBG("SCHED failed!");
3103 goto out;
3104 }
3105
3106 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3107 printf("AFTER SCHED:\n");
3108 ir3_print(ir);
3109 }
3110
3111 ret = ir3_ra(ir, so->type, so->frag_coord, so->frag_face);
3112 if (ret) {
3113 DBG("RA failed!");
3114 goto out;
3115 }
3116
3117 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3118 printf("AFTER RA:\n");
3119 ir3_print(ir);
3120 }
3121
3122 /* fixup input/outputs: */
3123 for (i = 0; i < so->outputs_count; i++) {
3124 /* sometimes we get outputs that don't write the .x coord, like:
3125 *
3126 * decl_var shader_out INTERP_MODE_NONE float Color (VARYING_SLOT_VAR9.z, 1, 0)
3127 *
3128 * Presumably the result of varying packing and then eliminating
3129 * some unneeded varyings? Just skip head to the first valid
3130 * component of the output.
3131 */
3132 for (unsigned j = 0; j < 4; j++) {
3133 struct ir3_instruction *instr = ir->outputs[(i*4) + j];
3134 if (instr) {
3135 so->outputs[i].regid = instr->regs[0]->num;
3136 break;
3137 }
3138 }
3139 }
3140
3141 /* Note that some or all channels of an input may be unused: */
3142 actual_in = 0;
3143 inloc = 0;
3144 for (i = 0; i < so->inputs_count; i++) {
3145 unsigned j, reg = regid(63,0), compmask = 0, maxcomp = 0;
3146 so->inputs[i].ncomp = 0;
3147 so->inputs[i].inloc = inloc;
3148 for (j = 0; j < 4; j++) {
3149 struct ir3_instruction *in = inputs[(i*4) + j];
3150 if (in && !(in->flags & IR3_INSTR_UNUSED)) {
3151 compmask |= (1 << j);
3152 reg = in->regs[0]->num - j;
3153 actual_in++;
3154 so->inputs[i].ncomp++;
3155 if ((so->type == MESA_SHADER_FRAGMENT) && so->inputs[i].bary) {
3156 /* assign inloc: */
3157 assert(in->regs[1]->flags & IR3_REG_IMMED);
3158 in->regs[1]->iim_val = inloc + j;
3159 maxcomp = j + 1;
3160 }
3161 }
3162 }
3163 if ((so->type == MESA_SHADER_FRAGMENT) && compmask && so->inputs[i].bary) {
3164 so->varying_in++;
3165 so->inputs[i].compmask = (1 << maxcomp) - 1;
3166 inloc += maxcomp;
3167 } else if (!so->inputs[i].sysval) {
3168 so->inputs[i].compmask = compmask;
3169 }
3170 so->inputs[i].regid = reg;
3171 }
3172
3173 if (ctx->astc_srgb)
3174 fixup_astc_srgb(ctx);
3175
3176 /* We need to do legalize after (for frag shader's) the "bary.f"
3177 * offsets (inloc) have been assigned.
3178 */
3179 ir3_legalize(ir, &so->num_samp, &so->has_ssbo, &max_bary);
3180
3181 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3182 printf("AFTER LEGALIZE:\n");
3183 ir3_print(ir);
3184 }
3185
3186 so->branchstack = ctx->max_stack;
3187
3188 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3189 if (so->type == MESA_SHADER_VERTEX)
3190 so->total_in = actual_in;
3191 else
3192 so->total_in = max_bary + 1;
3193
3194 out:
3195 if (ret) {
3196 if (so->ir)
3197 ir3_destroy(so->ir);
3198 so->ir = NULL;
3199 }
3200 ir3_context_free(ctx);
3201
3202 return ret;
3203 }