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freedreno/ir3: split out image helpers
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 ir3_reg_create(mov, 0, 0);
55 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
56 src->instr = collect;
57 src->size = arrsz;
58 src->array.offset = n;
59
60 ir3_instr_set_address(mov, address);
61
62 return mov;
63 }
64
65 static struct ir3_instruction *
66 create_input_compmask(struct ir3_context *ctx, unsigned n, unsigned compmask)
67 {
68 struct ir3_instruction *in;
69
70 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
71 in->inout.block = ctx->in_block;
72 ir3_reg_create(in, n, 0);
73
74 in->regs[0]->wrmask = compmask;
75
76 return in;
77 }
78
79 static struct ir3_instruction *
80 create_input(struct ir3_context *ctx, unsigned n)
81 {
82 return create_input_compmask(ctx, n, 0x1);
83 }
84
85 static struct ir3_instruction *
86 create_frag_input(struct ir3_context *ctx, bool use_ldlv)
87 {
88 struct ir3_block *block = ctx->block;
89 struct ir3_instruction *instr;
90 /* actual inloc is assigned and fixed up later: */
91 struct ir3_instruction *inloc = create_immed(block, 0);
92
93 if (use_ldlv) {
94 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
95 instr->cat6.type = TYPE_U32;
96 instr->cat6.iim_val = 1;
97 } else {
98 instr = ir3_BARY_F(block, inloc, 0, ctx->frag_vcoord, 0);
99 instr->regs[2]->wrmask = 0x3;
100 }
101
102 return instr;
103 }
104
105 static struct ir3_instruction *
106 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
107 {
108 /* first four vec4 sysval's reserved for UBOs: */
109 /* NOTE: dp is in scalar, but there can be >4 dp components: */
110 unsigned n = ctx->so->constbase.driver_param;
111 unsigned r = regid(n + dp / 4, dp % 4);
112 return create_uniform(ctx->block, r);
113 }
114
115 /*
116 * Adreno uses uint rather than having dedicated bool type,
117 * which (potentially) requires some conversion, in particular
118 * when using output of an bool instr to int input, or visa
119 * versa.
120 *
121 * | Adreno | NIR |
122 * -------+---------+-------+-
123 * true | 1 | ~0 |
124 * false | 0 | 0 |
125 *
126 * To convert from an adreno bool (uint) to nir, use:
127 *
128 * absneg.s dst, (neg)src
129 *
130 * To convert back in the other direction:
131 *
132 * absneg.s dst, (abs)arc
133 *
134 * The CP step can clean up the absneg.s that cancel each other
135 * out, and with a slight bit of extra cleverness (to recognize
136 * the instructions which produce either a 0 or 1) can eliminate
137 * the absneg.s's completely when an instruction that wants
138 * 0/1 consumes the result. For example, when a nir 'bcsel'
139 * consumes the result of 'feq'. So we should be able to get by
140 * without a boolean resolve step, and without incuring any
141 * extra penalty in instruction count.
142 */
143
144 /* NIR bool -> native (adreno): */
145 static struct ir3_instruction *
146 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
147 {
148 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
149 }
150
151 /* native (adreno) -> NIR bool: */
152 static struct ir3_instruction *
153 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
154 {
155 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
156 }
157
158 /*
159 * alu/sfu instructions:
160 */
161
162 static struct ir3_instruction *
163 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
164 unsigned src_bitsize, nir_op op)
165 {
166 type_t src_type, dst_type;
167
168 switch (op) {
169 case nir_op_f2f32:
170 case nir_op_f2f16_rtne:
171 case nir_op_f2f16_rtz:
172 case nir_op_f2f16:
173 case nir_op_f2i32:
174 case nir_op_f2i16:
175 case nir_op_f2i8:
176 case nir_op_f2u32:
177 case nir_op_f2u16:
178 case nir_op_f2u8:
179 switch (src_bitsize) {
180 case 32:
181 src_type = TYPE_F32;
182 break;
183 case 16:
184 src_type = TYPE_F16;
185 break;
186 default:
187 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
188 }
189 break;
190
191 case nir_op_i2f32:
192 case nir_op_i2f16:
193 case nir_op_i2i32:
194 case nir_op_i2i16:
195 case nir_op_i2i8:
196 switch (src_bitsize) {
197 case 32:
198 src_type = TYPE_S32;
199 break;
200 case 16:
201 src_type = TYPE_S16;
202 break;
203 case 8:
204 src_type = TYPE_S8;
205 break;
206 default:
207 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
208 }
209 break;
210
211 case nir_op_u2f32:
212 case nir_op_u2f16:
213 case nir_op_u2u32:
214 case nir_op_u2u16:
215 case nir_op_u2u8:
216 switch (src_bitsize) {
217 case 32:
218 src_type = TYPE_U32;
219 break;
220 case 16:
221 src_type = TYPE_U16;
222 break;
223 case 8:
224 src_type = TYPE_U8;
225 break;
226 default:
227 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
228 }
229 break;
230
231 default:
232 ir3_context_error(ctx, "invalid conversion op: %u", op);
233 }
234
235 switch (op) {
236 case nir_op_f2f32:
237 case nir_op_i2f32:
238 case nir_op_u2f32:
239 dst_type = TYPE_F32;
240 break;
241
242 case nir_op_f2f16_rtne:
243 case nir_op_f2f16_rtz:
244 case nir_op_f2f16:
245 /* TODO how to handle rounding mode? */
246 case nir_op_i2f16:
247 case nir_op_u2f16:
248 dst_type = TYPE_F16;
249 break;
250
251 case nir_op_f2i32:
252 case nir_op_i2i32:
253 dst_type = TYPE_S32;
254 break;
255
256 case nir_op_f2i16:
257 case nir_op_i2i16:
258 dst_type = TYPE_S16;
259 break;
260
261 case nir_op_f2i8:
262 case nir_op_i2i8:
263 dst_type = TYPE_S8;
264 break;
265
266 case nir_op_f2u32:
267 case nir_op_u2u32:
268 dst_type = TYPE_U32;
269 break;
270
271 case nir_op_f2u16:
272 case nir_op_u2u16:
273 dst_type = TYPE_U16;
274 break;
275
276 case nir_op_f2u8:
277 case nir_op_u2u8:
278 dst_type = TYPE_U8;
279 break;
280
281 default:
282 ir3_context_error(ctx, "invalid conversion op: %u", op);
283 }
284
285 return ir3_COV(ctx->block, src, src_type, dst_type);
286 }
287
288 static void
289 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
290 {
291 const nir_op_info *info = &nir_op_infos[alu->op];
292 struct ir3_instruction **dst, *src[info->num_inputs];
293 unsigned bs[info->num_inputs]; /* bit size */
294 struct ir3_block *b = ctx->block;
295 unsigned dst_sz, wrmask;
296
297 if (alu->dest.dest.is_ssa) {
298 dst_sz = alu->dest.dest.ssa.num_components;
299 wrmask = (1 << dst_sz) - 1;
300 } else {
301 dst_sz = alu->dest.dest.reg.reg->num_components;
302 wrmask = alu->dest.write_mask;
303 }
304
305 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
306
307 /* Vectors are special in that they have non-scalarized writemasks,
308 * and just take the first swizzle channel for each argument in
309 * order into each writemask channel.
310 */
311 if ((alu->op == nir_op_vec2) ||
312 (alu->op == nir_op_vec3) ||
313 (alu->op == nir_op_vec4)) {
314
315 for (int i = 0; i < info->num_inputs; i++) {
316 nir_alu_src *asrc = &alu->src[i];
317
318 compile_assert(ctx, !asrc->abs);
319 compile_assert(ctx, !asrc->negate);
320
321 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
322 if (!src[i])
323 src[i] = create_immed(ctx->block, 0);
324 dst[i] = ir3_MOV(b, src[i], TYPE_U32);
325 }
326
327 put_dst(ctx, &alu->dest.dest);
328 return;
329 }
330
331 /* We also get mov's with more than one component for mov's so
332 * handle those specially:
333 */
334 if ((alu->op == nir_op_imov) || (alu->op == nir_op_fmov)) {
335 type_t type = (alu->op == nir_op_imov) ? TYPE_U32 : TYPE_F32;
336 nir_alu_src *asrc = &alu->src[0];
337 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
338
339 for (unsigned i = 0; i < dst_sz; i++) {
340 if (wrmask & (1 << i)) {
341 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], type);
342 } else {
343 dst[i] = NULL;
344 }
345 }
346
347 put_dst(ctx, &alu->dest.dest);
348 return;
349 }
350
351 /* General case: We can just grab the one used channel per src. */
352 for (int i = 0; i < info->num_inputs; i++) {
353 unsigned chan = ffs(alu->dest.write_mask) - 1;
354 nir_alu_src *asrc = &alu->src[i];
355
356 compile_assert(ctx, !asrc->abs);
357 compile_assert(ctx, !asrc->negate);
358
359 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
360 bs[i] = nir_src_bit_size(asrc->src);
361
362 compile_assert(ctx, src[i]);
363 }
364
365 switch (alu->op) {
366 case nir_op_f2f32:
367 case nir_op_f2f16_rtne:
368 case nir_op_f2f16_rtz:
369 case nir_op_f2f16:
370 case nir_op_f2i32:
371 case nir_op_f2i16:
372 case nir_op_f2i8:
373 case nir_op_f2u32:
374 case nir_op_f2u16:
375 case nir_op_f2u8:
376 case nir_op_i2f32:
377 case nir_op_i2f16:
378 case nir_op_i2i32:
379 case nir_op_i2i16:
380 case nir_op_i2i8:
381 case nir_op_u2f32:
382 case nir_op_u2f16:
383 case nir_op_u2u32:
384 case nir_op_u2u16:
385 case nir_op_u2u8:
386 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
387 break;
388 case nir_op_f2b32:
389 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
390 dst[0]->cat2.condition = IR3_COND_NE;
391 dst[0] = ir3_n2b(b, dst[0]);
392 break;
393 case nir_op_b2f16:
394 case nir_op_b2f32:
395 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
396 break;
397 case nir_op_b2i8:
398 case nir_op_b2i16:
399 case nir_op_b2i32:
400 dst[0] = ir3_b2n(b, src[0]);
401 break;
402 case nir_op_i2b32:
403 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
404 dst[0]->cat2.condition = IR3_COND_NE;
405 dst[0] = ir3_n2b(b, dst[0]);
406 break;
407
408 case nir_op_fneg:
409 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
410 break;
411 case nir_op_fabs:
412 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
413 break;
414 case nir_op_fmax:
415 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
416 break;
417 case nir_op_fmin:
418 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
419 break;
420 case nir_op_fsat:
421 /* if there is just a single use of the src, and it supports
422 * (sat) bit, we can just fold the (sat) flag back to the
423 * src instruction and create a mov. This is easier for cp
424 * to eliminate.
425 *
426 * TODO probably opc_cat==4 is ok too
427 */
428 if (alu->src[0].src.is_ssa &&
429 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
430 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
431 src[0]->flags |= IR3_INSTR_SAT;
432 dst[0] = ir3_MOV(b, src[0], TYPE_U32);
433 } else {
434 /* otherwise generate a max.f that saturates.. blob does
435 * similar (generating a cat2 mov using max.f)
436 */
437 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
438 dst[0]->flags |= IR3_INSTR_SAT;
439 }
440 break;
441 case nir_op_fmul:
442 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
443 break;
444 case nir_op_fadd:
445 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
446 break;
447 case nir_op_fsub:
448 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
449 break;
450 case nir_op_ffma:
451 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
452 break;
453 case nir_op_fddx:
454 dst[0] = ir3_DSX(b, src[0], 0);
455 dst[0]->cat5.type = TYPE_F32;
456 break;
457 case nir_op_fddy:
458 dst[0] = ir3_DSY(b, src[0], 0);
459 dst[0]->cat5.type = TYPE_F32;
460 break;
461 break;
462 case nir_op_flt32:
463 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
464 dst[0]->cat2.condition = IR3_COND_LT;
465 dst[0] = ir3_n2b(b, dst[0]);
466 break;
467 case nir_op_fge32:
468 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
469 dst[0]->cat2.condition = IR3_COND_GE;
470 dst[0] = ir3_n2b(b, dst[0]);
471 break;
472 case nir_op_feq32:
473 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
474 dst[0]->cat2.condition = IR3_COND_EQ;
475 dst[0] = ir3_n2b(b, dst[0]);
476 break;
477 case nir_op_fne32:
478 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
479 dst[0]->cat2.condition = IR3_COND_NE;
480 dst[0] = ir3_n2b(b, dst[0]);
481 break;
482 case nir_op_fceil:
483 dst[0] = ir3_CEIL_F(b, src[0], 0);
484 break;
485 case nir_op_ffloor:
486 dst[0] = ir3_FLOOR_F(b, src[0], 0);
487 break;
488 case nir_op_ftrunc:
489 dst[0] = ir3_TRUNC_F(b, src[0], 0);
490 break;
491 case nir_op_fround_even:
492 dst[0] = ir3_RNDNE_F(b, src[0], 0);
493 break;
494 case nir_op_fsign:
495 dst[0] = ir3_SIGN_F(b, src[0], 0);
496 break;
497
498 case nir_op_fsin:
499 dst[0] = ir3_SIN(b, src[0], 0);
500 break;
501 case nir_op_fcos:
502 dst[0] = ir3_COS(b, src[0], 0);
503 break;
504 case nir_op_frsq:
505 dst[0] = ir3_RSQ(b, src[0], 0);
506 break;
507 case nir_op_frcp:
508 dst[0] = ir3_RCP(b, src[0], 0);
509 break;
510 case nir_op_flog2:
511 dst[0] = ir3_LOG2(b, src[0], 0);
512 break;
513 case nir_op_fexp2:
514 dst[0] = ir3_EXP2(b, src[0], 0);
515 break;
516 case nir_op_fsqrt:
517 dst[0] = ir3_SQRT(b, src[0], 0);
518 break;
519
520 case nir_op_iabs:
521 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
522 break;
523 case nir_op_iadd:
524 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
525 break;
526 case nir_op_iand:
527 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
528 break;
529 case nir_op_imax:
530 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
531 break;
532 case nir_op_umax:
533 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
534 break;
535 case nir_op_imin:
536 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
537 break;
538 case nir_op_umin:
539 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
540 break;
541 case nir_op_imul:
542 /*
543 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
544 * mull.u tmp0, a, b ; mul low, i.e. al * bl
545 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
546 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
547 */
548 dst[0] = ir3_MADSH_M16(b, src[1], 0, src[0], 0,
549 ir3_MADSH_M16(b, src[0], 0, src[1], 0,
550 ir3_MULL_U(b, src[0], 0, src[1], 0), 0), 0);
551 break;
552 case nir_op_ineg:
553 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
554 break;
555 case nir_op_inot:
556 dst[0] = ir3_NOT_B(b, src[0], 0);
557 break;
558 case nir_op_ior:
559 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
560 break;
561 case nir_op_ishl:
562 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
563 break;
564 case nir_op_ishr:
565 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
566 break;
567 case nir_op_isub:
568 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
569 break;
570 case nir_op_ixor:
571 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
572 break;
573 case nir_op_ushr:
574 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
575 break;
576 case nir_op_ilt32:
577 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
578 dst[0]->cat2.condition = IR3_COND_LT;
579 dst[0] = ir3_n2b(b, dst[0]);
580 break;
581 case nir_op_ige32:
582 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
583 dst[0]->cat2.condition = IR3_COND_GE;
584 dst[0] = ir3_n2b(b, dst[0]);
585 break;
586 case nir_op_ieq32:
587 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
588 dst[0]->cat2.condition = IR3_COND_EQ;
589 dst[0] = ir3_n2b(b, dst[0]);
590 break;
591 case nir_op_ine32:
592 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
593 dst[0]->cat2.condition = IR3_COND_NE;
594 dst[0] = ir3_n2b(b, dst[0]);
595 break;
596 case nir_op_ult32:
597 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
598 dst[0]->cat2.condition = IR3_COND_LT;
599 dst[0] = ir3_n2b(b, dst[0]);
600 break;
601 case nir_op_uge32:
602 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
603 dst[0]->cat2.condition = IR3_COND_GE;
604 dst[0] = ir3_n2b(b, dst[0]);
605 break;
606
607 case nir_op_b32csel: {
608 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
609 compile_assert(ctx, bs[1] == bs[2]);
610 /* the boolean condition is 32b even if src[1] and src[2] are
611 * half-precision, but sel.b16 wants all three src's to be the
612 * same type.
613 */
614 if (bs[1] < 32)
615 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
616 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
617 break;
618 }
619 case nir_op_bit_count:
620 dst[0] = ir3_CBITS_B(b, src[0], 0);
621 break;
622 case nir_op_ifind_msb: {
623 struct ir3_instruction *cmp;
624 dst[0] = ir3_CLZ_S(b, src[0], 0);
625 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
626 cmp->cat2.condition = IR3_COND_GE;
627 dst[0] = ir3_SEL_B32(b,
628 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
629 cmp, 0, dst[0], 0);
630 break;
631 }
632 case nir_op_ufind_msb:
633 dst[0] = ir3_CLZ_B(b, src[0], 0);
634 dst[0] = ir3_SEL_B32(b,
635 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
636 src[0], 0, dst[0], 0);
637 break;
638 case nir_op_find_lsb:
639 dst[0] = ir3_BFREV_B(b, src[0], 0);
640 dst[0] = ir3_CLZ_B(b, dst[0], 0);
641 break;
642 case nir_op_bitfield_reverse:
643 dst[0] = ir3_BFREV_B(b, src[0], 0);
644 break;
645
646 default:
647 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
648 nir_op_infos[alu->op].name);
649 break;
650 }
651
652 put_dst(ctx, &alu->dest.dest);
653 }
654
655 /* handles direct/indirect UBO reads: */
656 static void
657 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
658 struct ir3_instruction **dst)
659 {
660 struct ir3_block *b = ctx->block;
661 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
662 nir_const_value *const_offset;
663 /* UBO addresses are the first driver params: */
664 unsigned ubo = regid(ctx->so->constbase.ubo, 0);
665 const unsigned ptrsz = ir3_pointer_size(ctx);
666
667 int off = 0;
668
669 /* First src is ubo index, which could either be an immed or not: */
670 src0 = ir3_get_src(ctx, &intr->src[0])[0];
671 if (is_same_type_mov(src0) &&
672 (src0->regs[1]->flags & IR3_REG_IMMED)) {
673 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
674 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
675 } else {
676 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, 4));
677 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, 4));
678 }
679
680 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
681 addr = base_lo;
682
683 const_offset = nir_src_as_const_value(intr->src[1]);
684 if (const_offset) {
685 off += const_offset->u32[0];
686 } else {
687 /* For load_ubo_indirect, second src is indirect offset: */
688 src1 = ir3_get_src(ctx, &intr->src[1])[0];
689
690 /* and add offset to addr: */
691 addr = ir3_ADD_S(b, addr, 0, src1, 0);
692 }
693
694 /* if offset is to large to encode in the ldg, split it out: */
695 if ((off + (intr->num_components * 4)) > 1024) {
696 /* split out the minimal amount to improve the odds that
697 * cp can fit the immediate in the add.s instruction:
698 */
699 unsigned off2 = off + (intr->num_components * 4) - 1024;
700 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
701 off -= off2;
702 }
703
704 if (ptrsz == 2) {
705 struct ir3_instruction *carry;
706
707 /* handle 32b rollover, ie:
708 * if (addr < base_lo)
709 * base_hi++
710 */
711 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
712 carry->cat2.condition = IR3_COND_LT;
713 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
714
715 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
716 }
717
718 for (int i = 0; i < intr->num_components; i++) {
719 struct ir3_instruction *load =
720 ir3_LDG(b, addr, 0, create_immed(b, 1), 0);
721 load->cat6.type = TYPE_U32;
722 load->cat6.src_offset = off + i * 4; /* byte offset */
723 dst[i] = load;
724 }
725 }
726
727 /* src[] = { buffer_index, offset }. No const_index */
728 static void
729 emit_intrinsic_load_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
730 struct ir3_instruction **dst)
731 {
732 struct ir3_block *b = ctx->block;
733 struct ir3_instruction *ldgb, *src0, *src1, *offset;
734 nir_const_value *const_offset;
735
736 /* can this be non-const buffer_index? how do we handle that? */
737 const_offset = nir_src_as_const_value(intr->src[0]);
738 compile_assert(ctx, const_offset);
739
740 offset = ir3_get_src(ctx, &intr->src[1])[0];
741
742 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
743 src0 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
744 offset,
745 create_immed(b, 0),
746 }, 2);
747 src1 = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0);
748
749 ldgb = ir3_LDGB(b, create_immed(b, const_offset->u32[0]), 0,
750 src0, 0, src1, 0);
751 ldgb->regs[0]->wrmask = MASK(intr->num_components);
752 ldgb->cat6.iim_val = intr->num_components;
753 ldgb->cat6.d = 4;
754 ldgb->cat6.type = TYPE_U32;
755 ldgb->barrier_class = IR3_BARRIER_BUFFER_R;
756 ldgb->barrier_conflict = IR3_BARRIER_BUFFER_W;
757
758 ir3_split_dest(b, dst, ldgb, 0, intr->num_components);
759 }
760
761 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
762 static void
763 emit_intrinsic_store_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
764 {
765 struct ir3_block *b = ctx->block;
766 struct ir3_instruction *stgb, *src0, *src1, *src2, *offset;
767 nir_const_value *const_offset;
768 /* TODO handle wrmask properly, see _store_shared().. but I think
769 * it is more a PITA than that, since blob ends up loading the
770 * masked components and writing them back out.
771 */
772 unsigned wrmask = intr->const_index[0];
773 unsigned ncomp = ffs(~wrmask) - 1;
774
775 /* can this be non-const buffer_index? how do we handle that? */
776 const_offset = nir_src_as_const_value(intr->src[1]);
777 compile_assert(ctx, const_offset);
778
779 offset = ir3_get_src(ctx, &intr->src[2])[0];
780
781 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
782 * nir already *= 4:
783 */
784 src0 = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]), ncomp);
785 src1 = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0);
786 src2 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
787 offset,
788 create_immed(b, 0),
789 }, 2);
790
791 stgb = ir3_STGB(b, create_immed(b, const_offset->u32[0]), 0,
792 src0, 0, src1, 0, src2, 0);
793 stgb->cat6.iim_val = ncomp;
794 stgb->cat6.d = 4;
795 stgb->cat6.type = TYPE_U32;
796 stgb->barrier_class = IR3_BARRIER_BUFFER_W;
797 stgb->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
798
799 array_insert(b, b->keeps, stgb);
800 }
801
802 /* src[] = { block_index } */
803 static void
804 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
805 struct ir3_instruction **dst)
806 {
807 /* SSBO size stored as a const starting at ssbo_sizes: */
808 unsigned blk_idx = nir_src_as_const_value(intr->src[0])->u32[0];
809 unsigned idx = regid(ctx->so->constbase.ssbo_sizes, 0) +
810 ctx->so->const_layout.ssbo_size.off[blk_idx];
811
812 debug_assert(ctx->so->const_layout.ssbo_size.mask & (1 << blk_idx));
813
814 dst[0] = create_uniform(ctx->block, idx);
815 }
816
817 /*
818 * SSBO atomic intrinsics
819 *
820 * All of the SSBO atomic memory operations read a value from memory,
821 * compute a new value using one of the operations below, write the new
822 * value to memory, and return the original value read.
823 *
824 * All operations take 3 sources except CompSwap that takes 4. These
825 * sources represent:
826 *
827 * 0: The SSBO buffer index.
828 * 1: The offset into the SSBO buffer of the variable that the atomic
829 * operation will operate on.
830 * 2: The data parameter to the atomic function (i.e. the value to add
831 * in ssbo_atomic_add, etc).
832 * 3: For CompSwap only: the second data parameter.
833 */
834 static struct ir3_instruction *
835 emit_intrinsic_atomic_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
836 {
837 struct ir3_block *b = ctx->block;
838 struct ir3_instruction *atomic, *ssbo, *src0, *src1, *src2, *offset;
839 nir_const_value *const_offset;
840 type_t type = TYPE_U32;
841
842 /* can this be non-const buffer_index? how do we handle that? */
843 const_offset = nir_src_as_const_value(intr->src[0]);
844 compile_assert(ctx, const_offset);
845 ssbo = create_immed(b, const_offset->u32[0]);
846
847 offset = ir3_get_src(ctx, &intr->src[1])[0];
848
849 /* src0 is data (or uvec2(data, compare))
850 * src1 is offset
851 * src2 is uvec2(offset*4, 0) (appears to be 64b byte offset)
852 *
853 * Note that nir already multiplies the offset by four
854 */
855 src0 = ir3_get_src(ctx, &intr->src[2])[0];
856 src1 = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0);
857 src2 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
858 offset,
859 create_immed(b, 0),
860 }, 2);
861
862 switch (intr->intrinsic) {
863 case nir_intrinsic_ssbo_atomic_add:
864 atomic = ir3_ATOMIC_ADD_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
865 break;
866 case nir_intrinsic_ssbo_atomic_imin:
867 atomic = ir3_ATOMIC_MIN_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
868 type = TYPE_S32;
869 break;
870 case nir_intrinsic_ssbo_atomic_umin:
871 atomic = ir3_ATOMIC_MIN_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
872 break;
873 case nir_intrinsic_ssbo_atomic_imax:
874 atomic = ir3_ATOMIC_MAX_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
875 type = TYPE_S32;
876 break;
877 case nir_intrinsic_ssbo_atomic_umax:
878 atomic = ir3_ATOMIC_MAX_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
879 break;
880 case nir_intrinsic_ssbo_atomic_and:
881 atomic = ir3_ATOMIC_AND_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
882 break;
883 case nir_intrinsic_ssbo_atomic_or:
884 atomic = ir3_ATOMIC_OR_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
885 break;
886 case nir_intrinsic_ssbo_atomic_xor:
887 atomic = ir3_ATOMIC_XOR_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
888 break;
889 case nir_intrinsic_ssbo_atomic_exchange:
890 atomic = ir3_ATOMIC_XCHG_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
891 break;
892 case nir_intrinsic_ssbo_atomic_comp_swap:
893 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
894 src0 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
895 ir3_get_src(ctx, &intr->src[3])[0],
896 src0,
897 }, 2);
898 atomic = ir3_ATOMIC_CMPXCHG_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
899 break;
900 default:
901 unreachable("boo");
902 }
903
904 atomic->cat6.iim_val = 1;
905 atomic->cat6.d = 4;
906 atomic->cat6.type = type;
907 atomic->barrier_class = IR3_BARRIER_BUFFER_W;
908 atomic->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
909
910 /* even if nothing consume the result, we can't DCE the instruction: */
911 array_insert(b, b->keeps, atomic);
912
913 return atomic;
914 }
915
916 /* src[] = { offset }. const_index[] = { base } */
917 static void
918 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
919 struct ir3_instruction **dst)
920 {
921 struct ir3_block *b = ctx->block;
922 struct ir3_instruction *ldl, *offset;
923 unsigned base;
924
925 offset = ir3_get_src(ctx, &intr->src[0])[0];
926 base = nir_intrinsic_base(intr);
927
928 ldl = ir3_LDL(b, offset, 0, create_immed(b, intr->num_components), 0);
929 ldl->cat6.src_offset = base;
930 ldl->cat6.type = utype_dst(intr->dest);
931 ldl->regs[0]->wrmask = MASK(intr->num_components);
932
933 ldl->barrier_class = IR3_BARRIER_SHARED_R;
934 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
935
936 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
937 }
938
939 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
940 static void
941 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
942 {
943 struct ir3_block *b = ctx->block;
944 struct ir3_instruction *stl, *offset;
945 struct ir3_instruction * const *value;
946 unsigned base, wrmask;
947
948 value = ir3_get_src(ctx, &intr->src[0]);
949 offset = ir3_get_src(ctx, &intr->src[1])[0];
950
951 base = nir_intrinsic_base(intr);
952 wrmask = nir_intrinsic_write_mask(intr);
953
954 /* Combine groups of consecutive enabled channels in one write
955 * message. We use ffs to find the first enabled channel and then ffs on
956 * the bit-inverse, down-shifted writemask to determine the length of
957 * the block of enabled bits.
958 *
959 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
960 */
961 while (wrmask) {
962 unsigned first_component = ffs(wrmask) - 1;
963 unsigned length = ffs(~(wrmask >> first_component)) - 1;
964
965 stl = ir3_STL(b, offset, 0,
966 ir3_create_collect(ctx, &value[first_component], length), 0,
967 create_immed(b, length), 0);
968 stl->cat6.dst_offset = first_component + base;
969 stl->cat6.type = utype_src(intr->src[0]);
970 stl->barrier_class = IR3_BARRIER_SHARED_W;
971 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
972
973 array_insert(b, b->keeps, stl);
974
975 /* Clear the bits in the writemask that we just wrote, then try
976 * again to see if more channels are left.
977 */
978 wrmask &= (15 << (first_component + length));
979 }
980 }
981
982 /*
983 * CS shared variable atomic intrinsics
984 *
985 * All of the shared variable atomic memory operations read a value from
986 * memory, compute a new value using one of the operations below, write the
987 * new value to memory, and return the original value read.
988 *
989 * All operations take 2 sources except CompSwap that takes 3. These
990 * sources represent:
991 *
992 * 0: The offset into the shared variable storage region that the atomic
993 * operation will operate on.
994 * 1: The data parameter to the atomic function (i.e. the value to add
995 * in shared_atomic_add, etc).
996 * 2: For CompSwap only: the second data parameter.
997 */
998 static struct ir3_instruction *
999 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1000 {
1001 struct ir3_block *b = ctx->block;
1002 struct ir3_instruction *atomic, *src0, *src1;
1003 type_t type = TYPE_U32;
1004
1005 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
1006 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
1007
1008 switch (intr->intrinsic) {
1009 case nir_intrinsic_shared_atomic_add:
1010 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
1011 break;
1012 case nir_intrinsic_shared_atomic_imin:
1013 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1014 type = TYPE_S32;
1015 break;
1016 case nir_intrinsic_shared_atomic_umin:
1017 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1018 break;
1019 case nir_intrinsic_shared_atomic_imax:
1020 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1021 type = TYPE_S32;
1022 break;
1023 case nir_intrinsic_shared_atomic_umax:
1024 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1025 break;
1026 case nir_intrinsic_shared_atomic_and:
1027 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
1028 break;
1029 case nir_intrinsic_shared_atomic_or:
1030 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
1031 break;
1032 case nir_intrinsic_shared_atomic_xor:
1033 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
1034 break;
1035 case nir_intrinsic_shared_atomic_exchange:
1036 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
1037 break;
1038 case nir_intrinsic_shared_atomic_comp_swap:
1039 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1040 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1041 ir3_get_src(ctx, &intr->src[2])[0],
1042 src1,
1043 }, 2);
1044 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
1045 break;
1046 default:
1047 unreachable("boo");
1048 }
1049
1050 atomic->cat6.iim_val = 1;
1051 atomic->cat6.d = 1;
1052 atomic->cat6.type = type;
1053 atomic->barrier_class = IR3_BARRIER_SHARED_W;
1054 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1055
1056 /* even if nothing consume the result, we can't DCE the instruction: */
1057 array_insert(b, b->keeps, atomic);
1058
1059 return atomic;
1060 }
1061
1062 static struct ir3_instruction *
1063 get_image_offset(struct ir3_context *ctx, const nir_variable *var,
1064 struct ir3_instruction * const *coords, bool byteoff)
1065 {
1066 struct ir3_block *b = ctx->block;
1067 struct ir3_instruction *offset;
1068 unsigned ncoords = ir3_get_image_coords(var, NULL);
1069
1070 /* to calculate the byte offset (yes, uggg) we need (up to) three
1071 * const values to know the bytes per pixel, and y and z stride:
1072 */
1073 unsigned cb = regid(ctx->so->constbase.image_dims, 0) +
1074 ctx->so->const_layout.image_dims.off[var->data.driver_location];
1075
1076 debug_assert(ctx->so->const_layout.image_dims.mask &
1077 (1 << var->data.driver_location));
1078
1079 /* offset = coords.x * bytes_per_pixel: */
1080 offset = ir3_MUL_S(b, coords[0], 0, create_uniform(b, cb + 0), 0);
1081 if (ncoords > 1) {
1082 /* offset += coords.y * y_pitch: */
1083 offset = ir3_MAD_S24(b, create_uniform(b, cb + 1), 0,
1084 coords[1], 0, offset, 0);
1085 }
1086 if (ncoords > 2) {
1087 /* offset += coords.z * z_pitch: */
1088 offset = ir3_MAD_S24(b, create_uniform(b, cb + 2), 0,
1089 coords[2], 0, offset, 0);
1090 }
1091
1092 if (!byteoff) {
1093 /* Some cases, like atomics, seem to use dword offset instead
1094 * of byte offsets.. blob just puts an extra shr.b in there
1095 * in those cases:
1096 */
1097 offset = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0);
1098 }
1099
1100 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1101 offset,
1102 create_immed(b, 0),
1103 }, 2);
1104 }
1105
1106 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1107 static void
1108 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1109 struct ir3_instruction **dst)
1110 {
1111 struct ir3_block *b = ctx->block;
1112 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1113 struct ir3_instruction *sam;
1114 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1115 struct ir3_instruction *coords[4];
1116 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1117 unsigned tex_idx = ir3_get_image_slot(ctx, nir_src_as_deref(intr->src[0]));
1118 type_t type = ir3_get_image_type(var);
1119
1120 /* hmm, this seems a bit odd, but it is what blob does and (at least
1121 * a5xx) just faults on bogus addresses otherwise:
1122 */
1123 if (flags & IR3_INSTR_3D) {
1124 flags &= ~IR3_INSTR_3D;
1125 flags |= IR3_INSTR_A;
1126 }
1127
1128 for (unsigned i = 0; i < ncoords; i++)
1129 coords[i] = src0[i];
1130
1131 if (ncoords == 1)
1132 coords[ncoords++] = create_immed(b, 0);
1133
1134 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
1135 tex_idx, tex_idx, ir3_create_collect(ctx, coords, ncoords), NULL);
1136
1137 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1138 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1139
1140 ir3_split_dest(b, dst, sam, 0, 4);
1141 }
1142
1143 /* src[] = { deref, coord, sample_index, value }. const_index[] = {} */
1144 static void
1145 emit_intrinsic_store_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1146 {
1147 struct ir3_block *b = ctx->block;
1148 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1149 struct ir3_instruction *stib, *offset;
1150 struct ir3_instruction * const *value = ir3_get_src(ctx, &intr->src[3]);
1151 struct ir3_instruction * const *coords = ir3_get_src(ctx, &intr->src[1]);
1152 unsigned ncoords = ir3_get_image_coords(var, NULL);
1153 unsigned tex_idx = ir3_get_image_slot(ctx, nir_src_as_deref(intr->src[0]));
1154 unsigned ncomp = ir3_get_num_components_for_glformat(var->data.image.format);
1155
1156 /* src0 is value
1157 * src1 is coords
1158 * src2 is 64b byte offset
1159 */
1160
1161 offset = get_image_offset(ctx, var, coords, true);
1162
1163 /* NOTE: stib seems to take byte offset, but stgb.typed can be used
1164 * too and takes a dword offset.. not quite sure yet why blob uses
1165 * one over the other in various cases.
1166 */
1167
1168 stib = ir3_STIB(b, create_immed(b, tex_idx), 0,
1169 ir3_create_collect(ctx, value, ncomp), 0,
1170 ir3_create_collect(ctx, coords, ncoords), 0,
1171 offset, 0);
1172 stib->cat6.iim_val = ncomp;
1173 stib->cat6.d = ncoords;
1174 stib->cat6.type = ir3_get_image_type(var);
1175 stib->cat6.typed = true;
1176 stib->barrier_class = IR3_BARRIER_IMAGE_W;
1177 stib->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W;
1178
1179 array_insert(b, b->keeps, stib);
1180 }
1181
1182 static void
1183 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1184 struct ir3_instruction **dst)
1185 {
1186 struct ir3_block *b = ctx->block;
1187 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1188 unsigned tex_idx = ir3_get_image_slot(ctx, nir_src_as_deref(intr->src[0]));
1189 struct ir3_instruction *sam, *lod;
1190 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1191
1192 lod = create_immed(b, 0);
1193 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
1194 tex_idx, tex_idx, lod, NULL);
1195
1196 /* Array size actually ends up in .w rather than .z. This doesn't
1197 * matter for miplevel 0, but for higher mips the value in z is
1198 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1199 * returned, which means that we have to add 1 to it for arrays for
1200 * a3xx.
1201 *
1202 * Note use a temporary dst and then copy, since the size of the dst
1203 * array that is passed in is based on nir's understanding of the
1204 * result size, not the hardware's
1205 */
1206 struct ir3_instruction *tmp[4];
1207
1208 ir3_split_dest(b, tmp, sam, 0, 4);
1209
1210 /* get_size instruction returns size in bytes instead of texels
1211 * for imageBuffer, so we need to divide it by the pixel size
1212 * of the image format.
1213 *
1214 * TODO: This is at least true on a5xx. Check other gens.
1215 */
1216 enum glsl_sampler_dim dim =
1217 glsl_get_sampler_dim(glsl_without_array(var->type));
1218 if (dim == GLSL_SAMPLER_DIM_BUF) {
1219 /* Since all the possible values the divisor can take are
1220 * power-of-two (4, 8, or 16), the division is implemented
1221 * as a shift-right.
1222 * During shader setup, the log2 of the image format's
1223 * bytes-per-pixel should have been emitted in 2nd slot of
1224 * image_dims. See ir3_shader::emit_image_dims().
1225 */
1226 unsigned cb = regid(ctx->so->constbase.image_dims, 0) +
1227 ctx->so->const_layout.image_dims.off[var->data.driver_location];
1228 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1229
1230 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1231 }
1232
1233 for (unsigned i = 0; i < ncoords; i++)
1234 dst[i] = tmp[i];
1235
1236 if (flags & IR3_INSTR_A) {
1237 if (ctx->compiler->levels_add_one) {
1238 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1239 } else {
1240 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1241 }
1242 }
1243 }
1244
1245 /* src[] = { deref, coord, sample_index, value, compare }. const_index[] = {} */
1246 static struct ir3_instruction *
1247 emit_intrinsic_atomic_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1248 {
1249 struct ir3_block *b = ctx->block;
1250 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1251 struct ir3_instruction *atomic, *image, *src0, *src1, *src2;
1252 struct ir3_instruction * const *coords = ir3_get_src(ctx, &intr->src[1]);
1253 unsigned ncoords = ir3_get_image_coords(var, NULL);
1254
1255 image = create_immed(b, ir3_get_image_slot(ctx, nir_src_as_deref(intr->src[0])));
1256
1257 /* src0 is value (or uvec2(value, compare))
1258 * src1 is coords
1259 * src2 is 64b byte offset
1260 */
1261 src0 = ir3_get_src(ctx, &intr->src[3])[0];
1262 src1 = ir3_create_collect(ctx, coords, ncoords);
1263 src2 = get_image_offset(ctx, var, coords, false);
1264
1265 switch (intr->intrinsic) {
1266 case nir_intrinsic_image_deref_atomic_add:
1267 atomic = ir3_ATOMIC_ADD_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1268 break;
1269 case nir_intrinsic_image_deref_atomic_min:
1270 atomic = ir3_ATOMIC_MIN_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1271 break;
1272 case nir_intrinsic_image_deref_atomic_max:
1273 atomic = ir3_ATOMIC_MAX_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1274 break;
1275 case nir_intrinsic_image_deref_atomic_and:
1276 atomic = ir3_ATOMIC_AND_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1277 break;
1278 case nir_intrinsic_image_deref_atomic_or:
1279 atomic = ir3_ATOMIC_OR_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1280 break;
1281 case nir_intrinsic_image_deref_atomic_xor:
1282 atomic = ir3_ATOMIC_XOR_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1283 break;
1284 case nir_intrinsic_image_deref_atomic_exchange:
1285 atomic = ir3_ATOMIC_XCHG_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1286 break;
1287 case nir_intrinsic_image_deref_atomic_comp_swap:
1288 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1289 src0 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1290 ir3_get_src(ctx, &intr->src[4])[0],
1291 src0,
1292 }, 2);
1293 atomic = ir3_ATOMIC_CMPXCHG_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1294 break;
1295 default:
1296 unreachable("boo");
1297 }
1298
1299 atomic->cat6.iim_val = 1;
1300 atomic->cat6.d = ncoords;
1301 atomic->cat6.type = ir3_get_image_type(var);
1302 atomic->cat6.typed = true;
1303 atomic->barrier_class = IR3_BARRIER_IMAGE_W;
1304 atomic->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W;
1305
1306 /* even if nothing consume the result, we can't DCE the instruction: */
1307 array_insert(b, b->keeps, atomic);
1308
1309 return atomic;
1310 }
1311
1312 static void
1313 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1314 {
1315 struct ir3_block *b = ctx->block;
1316 struct ir3_instruction *barrier;
1317
1318 switch (intr->intrinsic) {
1319 case nir_intrinsic_barrier:
1320 barrier = ir3_BAR(b);
1321 barrier->cat7.g = true;
1322 barrier->cat7.l = true;
1323 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1324 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1325 break;
1326 case nir_intrinsic_memory_barrier:
1327 barrier = ir3_FENCE(b);
1328 barrier->cat7.g = true;
1329 barrier->cat7.r = true;
1330 barrier->cat7.w = true;
1331 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1332 IR3_BARRIER_BUFFER_W;
1333 barrier->barrier_conflict =
1334 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1335 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1336 break;
1337 case nir_intrinsic_memory_barrier_atomic_counter:
1338 case nir_intrinsic_memory_barrier_buffer:
1339 barrier = ir3_FENCE(b);
1340 barrier->cat7.g = true;
1341 barrier->cat7.r = true;
1342 barrier->cat7.w = true;
1343 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1344 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1345 IR3_BARRIER_BUFFER_W;
1346 break;
1347 case nir_intrinsic_memory_barrier_image:
1348 // TODO double check if this should have .g set
1349 barrier = ir3_FENCE(b);
1350 barrier->cat7.g = true;
1351 barrier->cat7.r = true;
1352 barrier->cat7.w = true;
1353 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1354 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1355 IR3_BARRIER_IMAGE_W;
1356 break;
1357 case nir_intrinsic_memory_barrier_shared:
1358 barrier = ir3_FENCE(b);
1359 barrier->cat7.g = true;
1360 barrier->cat7.l = true;
1361 barrier->cat7.r = true;
1362 barrier->cat7.w = true;
1363 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1364 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1365 IR3_BARRIER_SHARED_W;
1366 break;
1367 case nir_intrinsic_group_memory_barrier:
1368 barrier = ir3_FENCE(b);
1369 barrier->cat7.g = true;
1370 barrier->cat7.l = true;
1371 barrier->cat7.r = true;
1372 barrier->cat7.w = true;
1373 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1374 IR3_BARRIER_IMAGE_W |
1375 IR3_BARRIER_BUFFER_W;
1376 barrier->barrier_conflict =
1377 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1378 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1379 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1380 break;
1381 default:
1382 unreachable("boo");
1383 }
1384
1385 /* make sure barrier doesn't get DCE'd */
1386 array_insert(b, b->keeps, barrier);
1387 }
1388
1389 static void add_sysval_input_compmask(struct ir3_context *ctx,
1390 gl_system_value slot, unsigned compmask,
1391 struct ir3_instruction *instr)
1392 {
1393 struct ir3_shader_variant *so = ctx->so;
1394 unsigned r = regid(so->inputs_count, 0);
1395 unsigned n = so->inputs_count++;
1396
1397 so->inputs[n].sysval = true;
1398 so->inputs[n].slot = slot;
1399 so->inputs[n].compmask = compmask;
1400 so->inputs[n].regid = r;
1401 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1402 so->total_in++;
1403
1404 ctx->ir->ninputs = MAX2(ctx->ir->ninputs, r + 1);
1405 ctx->ir->inputs[r] = instr;
1406 }
1407
1408 static void add_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1409 struct ir3_instruction *instr)
1410 {
1411 add_sysval_input_compmask(ctx, slot, 0x1, instr);
1412 }
1413
1414 static void
1415 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1416 {
1417 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1418 struct ir3_instruction **dst;
1419 struct ir3_instruction * const *src;
1420 struct ir3_block *b = ctx->block;
1421 nir_const_value *const_offset;
1422 int idx, comp;
1423
1424 if (info->has_dest) {
1425 unsigned n = nir_intrinsic_dest_components(intr);
1426 dst = ir3_get_dst(ctx, &intr->dest, n);
1427 } else {
1428 dst = NULL;
1429 }
1430
1431 switch (intr->intrinsic) {
1432 case nir_intrinsic_load_uniform:
1433 idx = nir_intrinsic_base(intr);
1434 const_offset = nir_src_as_const_value(intr->src[0]);
1435 if (const_offset) {
1436 idx += const_offset->u32[0];
1437 for (int i = 0; i < intr->num_components; i++) {
1438 unsigned n = idx * 4 + i;
1439 dst[i] = create_uniform(b, n);
1440 }
1441 } else {
1442 src = ir3_get_src(ctx, &intr->src[0]);
1443 for (int i = 0; i < intr->num_components; i++) {
1444 int n = idx * 4 + i;
1445 dst[i] = create_uniform_indirect(b, n,
1446 ir3_get_addr(ctx, src[0], 4));
1447 }
1448 /* NOTE: if relative addressing is used, we set
1449 * constlen in the compiler (to worst-case value)
1450 * since we don't know in the assembler what the max
1451 * addr reg value can be:
1452 */
1453 ctx->so->constlen = ctx->s->num_uniforms;
1454 }
1455 break;
1456 case nir_intrinsic_load_ubo:
1457 emit_intrinsic_load_ubo(ctx, intr, dst);
1458 break;
1459 case nir_intrinsic_load_input:
1460 idx = nir_intrinsic_base(intr);
1461 comp = nir_intrinsic_component(intr);
1462 const_offset = nir_src_as_const_value(intr->src[0]);
1463 if (const_offset) {
1464 idx += const_offset->u32[0];
1465 for (int i = 0; i < intr->num_components; i++) {
1466 unsigned n = idx * 4 + i + comp;
1467 dst[i] = ctx->ir->inputs[n];
1468 }
1469 } else {
1470 src = ir3_get_src(ctx, &intr->src[0]);
1471 struct ir3_instruction *collect =
1472 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ir->ninputs);
1473 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1474 for (int i = 0; i < intr->num_components; i++) {
1475 unsigned n = idx * 4 + i + comp;
1476 dst[i] = create_indirect_load(ctx, ctx->ir->ninputs,
1477 n, addr, collect);
1478 }
1479 }
1480 break;
1481 case nir_intrinsic_load_ssbo:
1482 emit_intrinsic_load_ssbo(ctx, intr, dst);
1483 break;
1484 case nir_intrinsic_store_ssbo:
1485 emit_intrinsic_store_ssbo(ctx, intr);
1486 break;
1487 case nir_intrinsic_get_buffer_size:
1488 emit_intrinsic_ssbo_size(ctx, intr, dst);
1489 break;
1490 case nir_intrinsic_ssbo_atomic_add:
1491 case nir_intrinsic_ssbo_atomic_imin:
1492 case nir_intrinsic_ssbo_atomic_umin:
1493 case nir_intrinsic_ssbo_atomic_imax:
1494 case nir_intrinsic_ssbo_atomic_umax:
1495 case nir_intrinsic_ssbo_atomic_and:
1496 case nir_intrinsic_ssbo_atomic_or:
1497 case nir_intrinsic_ssbo_atomic_xor:
1498 case nir_intrinsic_ssbo_atomic_exchange:
1499 case nir_intrinsic_ssbo_atomic_comp_swap:
1500 dst[0] = emit_intrinsic_atomic_ssbo(ctx, intr);
1501 break;
1502 case nir_intrinsic_load_shared:
1503 emit_intrinsic_load_shared(ctx, intr, dst);
1504 break;
1505 case nir_intrinsic_store_shared:
1506 emit_intrinsic_store_shared(ctx, intr);
1507 break;
1508 case nir_intrinsic_shared_atomic_add:
1509 case nir_intrinsic_shared_atomic_imin:
1510 case nir_intrinsic_shared_atomic_umin:
1511 case nir_intrinsic_shared_atomic_imax:
1512 case nir_intrinsic_shared_atomic_umax:
1513 case nir_intrinsic_shared_atomic_and:
1514 case nir_intrinsic_shared_atomic_or:
1515 case nir_intrinsic_shared_atomic_xor:
1516 case nir_intrinsic_shared_atomic_exchange:
1517 case nir_intrinsic_shared_atomic_comp_swap:
1518 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1519 break;
1520 case nir_intrinsic_image_deref_load:
1521 emit_intrinsic_load_image(ctx, intr, dst);
1522 break;
1523 case nir_intrinsic_image_deref_store:
1524 emit_intrinsic_store_image(ctx, intr);
1525 break;
1526 case nir_intrinsic_image_deref_size:
1527 emit_intrinsic_image_size(ctx, intr, dst);
1528 break;
1529 case nir_intrinsic_image_deref_atomic_add:
1530 case nir_intrinsic_image_deref_atomic_min:
1531 case nir_intrinsic_image_deref_atomic_max:
1532 case nir_intrinsic_image_deref_atomic_and:
1533 case nir_intrinsic_image_deref_atomic_or:
1534 case nir_intrinsic_image_deref_atomic_xor:
1535 case nir_intrinsic_image_deref_atomic_exchange:
1536 case nir_intrinsic_image_deref_atomic_comp_swap:
1537 dst[0] = emit_intrinsic_atomic_image(ctx, intr);
1538 break;
1539 case nir_intrinsic_barrier:
1540 case nir_intrinsic_memory_barrier:
1541 case nir_intrinsic_group_memory_barrier:
1542 case nir_intrinsic_memory_barrier_atomic_counter:
1543 case nir_intrinsic_memory_barrier_buffer:
1544 case nir_intrinsic_memory_barrier_image:
1545 case nir_intrinsic_memory_barrier_shared:
1546 emit_intrinsic_barrier(ctx, intr);
1547 /* note that blk ptr no longer valid, make that obvious: */
1548 b = NULL;
1549 break;
1550 case nir_intrinsic_store_output:
1551 idx = nir_intrinsic_base(intr);
1552 comp = nir_intrinsic_component(intr);
1553 const_offset = nir_src_as_const_value(intr->src[1]);
1554 compile_assert(ctx, const_offset != NULL);
1555 idx += const_offset->u32[0];
1556
1557 src = ir3_get_src(ctx, &intr->src[0]);
1558 for (int i = 0; i < intr->num_components; i++) {
1559 unsigned n = idx * 4 + i + comp;
1560 ctx->ir->outputs[n] = src[i];
1561 }
1562 break;
1563 case nir_intrinsic_load_base_vertex:
1564 case nir_intrinsic_load_first_vertex:
1565 if (!ctx->basevertex) {
1566 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1567 add_sysval_input(ctx, SYSTEM_VALUE_FIRST_VERTEX, ctx->basevertex);
1568 }
1569 dst[0] = ctx->basevertex;
1570 break;
1571 case nir_intrinsic_load_vertex_id_zero_base:
1572 case nir_intrinsic_load_vertex_id:
1573 if (!ctx->vertex_id) {
1574 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1575 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1576 ctx->vertex_id = create_input(ctx, 0);
1577 add_sysval_input(ctx, sv, ctx->vertex_id);
1578 }
1579 dst[0] = ctx->vertex_id;
1580 break;
1581 case nir_intrinsic_load_instance_id:
1582 if (!ctx->instance_id) {
1583 ctx->instance_id = create_input(ctx, 0);
1584 add_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID,
1585 ctx->instance_id);
1586 }
1587 dst[0] = ctx->instance_id;
1588 break;
1589 case nir_intrinsic_load_sample_id:
1590 case nir_intrinsic_load_sample_id_no_per_sample:
1591 if (!ctx->samp_id) {
1592 ctx->samp_id = create_input(ctx, 0);
1593 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1594 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID,
1595 ctx->samp_id);
1596 }
1597 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1598 break;
1599 case nir_intrinsic_load_sample_mask_in:
1600 if (!ctx->samp_mask_in) {
1601 ctx->samp_mask_in = create_input(ctx, 0);
1602 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN,
1603 ctx->samp_mask_in);
1604 }
1605 dst[0] = ctx->samp_mask_in;
1606 break;
1607 case nir_intrinsic_load_user_clip_plane:
1608 idx = nir_intrinsic_ucp_id(intr);
1609 for (int i = 0; i < intr->num_components; i++) {
1610 unsigned n = idx * 4 + i;
1611 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1612 }
1613 break;
1614 case nir_intrinsic_load_front_face:
1615 if (!ctx->frag_face) {
1616 ctx->so->frag_face = true;
1617 ctx->frag_face = create_input(ctx, 0);
1618 add_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, ctx->frag_face);
1619 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1620 }
1621 /* for fragface, we get -1 for back and 0 for front. However this is
1622 * the inverse of what nir expects (where ~0 is true).
1623 */
1624 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1625 dst[0] = ir3_NOT_B(b, dst[0], 0);
1626 break;
1627 case nir_intrinsic_load_local_invocation_id:
1628 if (!ctx->local_invocation_id) {
1629 ctx->local_invocation_id = create_input_compmask(ctx, 0, 0x7);
1630 add_sysval_input_compmask(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID,
1631 0x7, ctx->local_invocation_id);
1632 }
1633 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1634 break;
1635 case nir_intrinsic_load_work_group_id:
1636 if (!ctx->work_group_id) {
1637 ctx->work_group_id = create_input_compmask(ctx, 0, 0x7);
1638 add_sysval_input_compmask(ctx, SYSTEM_VALUE_WORK_GROUP_ID,
1639 0x7, ctx->work_group_id);
1640 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1641 }
1642 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1643 break;
1644 case nir_intrinsic_load_num_work_groups:
1645 for (int i = 0; i < intr->num_components; i++) {
1646 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1647 }
1648 break;
1649 case nir_intrinsic_load_local_group_size:
1650 for (int i = 0; i < intr->num_components; i++) {
1651 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1652 }
1653 break;
1654 case nir_intrinsic_discard_if:
1655 case nir_intrinsic_discard: {
1656 struct ir3_instruction *cond, *kill;
1657
1658 if (intr->intrinsic == nir_intrinsic_discard_if) {
1659 /* conditional discard: */
1660 src = ir3_get_src(ctx, &intr->src[0]);
1661 cond = ir3_b2n(b, src[0]);
1662 } else {
1663 /* unconditional discard: */
1664 cond = create_immed(b, 1);
1665 }
1666
1667 /* NOTE: only cmps.*.* can write p0.x: */
1668 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1669 cond->cat2.condition = IR3_COND_NE;
1670
1671 /* condition always goes in predicate register: */
1672 cond->regs[0]->num = regid(REG_P0, 0);
1673
1674 kill = ir3_KILL(b, cond, 0);
1675 array_insert(ctx->ir, ctx->ir->predicates, kill);
1676
1677 array_insert(b, b->keeps, kill);
1678 ctx->so->has_kill = true;
1679
1680 break;
1681 }
1682 default:
1683 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1684 nir_intrinsic_infos[intr->intrinsic].name);
1685 break;
1686 }
1687
1688 if (info->has_dest)
1689 put_dst(ctx, &intr->dest);
1690 }
1691
1692 static void
1693 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1694 {
1695 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1696 instr->def.num_components);
1697 type_t type = (instr->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1698
1699 for (int i = 0; i < instr->def.num_components; i++)
1700 dst[i] = create_immed_typed(ctx->block, instr->value.u32[i], type);
1701 }
1702
1703 static void
1704 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1705 {
1706 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1707 undef->def.num_components);
1708 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1709
1710 /* backend doesn't want undefined instructions, so just plug
1711 * in 0.0..
1712 */
1713 for (int i = 0; i < undef->def.num_components; i++)
1714 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1715 }
1716
1717 /*
1718 * texture fetch/sample instructions:
1719 */
1720
1721 static void
1722 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1723 {
1724 unsigned coords, flags = 0;
1725
1726 /* note: would use tex->coord_components.. except txs.. also,
1727 * since array index goes after shadow ref, we don't want to
1728 * count it:
1729 */
1730 switch (tex->sampler_dim) {
1731 case GLSL_SAMPLER_DIM_1D:
1732 case GLSL_SAMPLER_DIM_BUF:
1733 coords = 1;
1734 break;
1735 case GLSL_SAMPLER_DIM_2D:
1736 case GLSL_SAMPLER_DIM_RECT:
1737 case GLSL_SAMPLER_DIM_EXTERNAL:
1738 case GLSL_SAMPLER_DIM_MS:
1739 coords = 2;
1740 break;
1741 case GLSL_SAMPLER_DIM_3D:
1742 case GLSL_SAMPLER_DIM_CUBE:
1743 coords = 3;
1744 flags |= IR3_INSTR_3D;
1745 break;
1746 default:
1747 unreachable("bad sampler_dim");
1748 }
1749
1750 if (tex->is_shadow && tex->op != nir_texop_lod)
1751 flags |= IR3_INSTR_S;
1752
1753 if (tex->is_array && tex->op != nir_texop_lod)
1754 flags |= IR3_INSTR_A;
1755
1756 *flagsp = flags;
1757 *coordsp = coords;
1758 }
1759
1760 static void
1761 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1762 {
1763 struct ir3_block *b = ctx->block;
1764 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1765 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1766 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1767 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1768 unsigned i, coords, flags;
1769 unsigned nsrc0 = 0, nsrc1 = 0;
1770 type_t type;
1771 opc_t opc = 0;
1772
1773 coord = off = ddx = ddy = NULL;
1774 lod = proj = compare = sample_index = NULL;
1775
1776 /* TODO: might just be one component for gathers? */
1777 dst = ir3_get_dst(ctx, &tex->dest, 4);
1778
1779 for (unsigned i = 0; i < tex->num_srcs; i++) {
1780 switch (tex->src[i].src_type) {
1781 case nir_tex_src_coord:
1782 coord = ir3_get_src(ctx, &tex->src[i].src);
1783 break;
1784 case nir_tex_src_bias:
1785 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1786 has_bias = true;
1787 break;
1788 case nir_tex_src_lod:
1789 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1790 has_lod = true;
1791 break;
1792 case nir_tex_src_comparator: /* shadow comparator */
1793 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1794 break;
1795 case nir_tex_src_projector:
1796 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1797 has_proj = true;
1798 break;
1799 case nir_tex_src_offset:
1800 off = ir3_get_src(ctx, &tex->src[i].src);
1801 has_off = true;
1802 break;
1803 case nir_tex_src_ddx:
1804 ddx = ir3_get_src(ctx, &tex->src[i].src);
1805 break;
1806 case nir_tex_src_ddy:
1807 ddy = ir3_get_src(ctx, &tex->src[i].src);
1808 break;
1809 case nir_tex_src_ms_index:
1810 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
1811 break;
1812 default:
1813 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
1814 tex->src[i].src_type);
1815 return;
1816 }
1817 }
1818
1819 switch (tex->op) {
1820 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
1821 case nir_texop_txb: opc = OPC_SAMB; break;
1822 case nir_texop_txl: opc = OPC_SAML; break;
1823 case nir_texop_txd: opc = OPC_SAMGQ; break;
1824 case nir_texop_txf: opc = OPC_ISAML; break;
1825 case nir_texop_lod: opc = OPC_GETLOD; break;
1826 case nir_texop_tg4:
1827 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1828 * what blob does, seems gather is broken?), and a3xx did
1829 * not support it (but probably could also emulate).
1830 */
1831 switch (tex->component) {
1832 case 0: opc = OPC_GATHER4R; break;
1833 case 1: opc = OPC_GATHER4G; break;
1834 case 2: opc = OPC_GATHER4B; break;
1835 case 3: opc = OPC_GATHER4A; break;
1836 }
1837 break;
1838 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
1839 case nir_texop_txs:
1840 case nir_texop_query_levels:
1841 case nir_texop_texture_samples:
1842 case nir_texop_samples_identical:
1843 case nir_texop_txf_ms_mcs:
1844 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
1845 return;
1846 }
1847
1848 tex_info(tex, &flags, &coords);
1849
1850 /*
1851 * lay out the first argument in the proper order:
1852 * - actual coordinates first
1853 * - shadow reference
1854 * - array index
1855 * - projection w
1856 * - starting at offset 4, dpdx.xy, dpdy.xy
1857 *
1858 * bias/lod go into the second arg
1859 */
1860
1861 /* insert tex coords: */
1862 for (i = 0; i < coords; i++)
1863 src0[i] = coord[i];
1864
1865 nsrc0 = i;
1866
1867 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
1868 * with scaled x coord according to requested sample:
1869 */
1870 if (tex->op == nir_texop_txf_ms) {
1871 if (ctx->compiler->txf_ms_with_isaml) {
1872 /* the samples are laid out in x dimension as
1873 * 0 1 2 3
1874 * x_ms = (x << ms) + sample_index;
1875 */
1876 struct ir3_instruction *ms;
1877 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
1878
1879 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
1880 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
1881
1882 opc = OPC_ISAML;
1883 } else {
1884 src0[nsrc0++] = sample_index;
1885 }
1886 }
1887
1888 /* scale up integer coords for TXF based on the LOD */
1889 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
1890 assert(has_lod);
1891 for (i = 0; i < coords; i++)
1892 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
1893 }
1894
1895 if (coords == 1) {
1896 /* hw doesn't do 1d, so we treat it as 2d with
1897 * height of 1, and patch up the y coord.
1898 * TODO: y coord should be (int)0 in some cases..
1899 */
1900 src0[nsrc0++] = create_immed(b, fui(0.5));
1901 }
1902
1903 if (tex->is_shadow && tex->op != nir_texop_lod)
1904 src0[nsrc0++] = compare;
1905
1906 if (tex->is_array && tex->op != nir_texop_lod) {
1907 struct ir3_instruction *idx = coord[coords];
1908
1909 /* the array coord for cube arrays needs 0.5 added to it */
1910 if (ctx->compiler->array_index_add_half && (opc != OPC_ISAML))
1911 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
1912
1913 src0[nsrc0++] = idx;
1914 }
1915
1916 if (has_proj) {
1917 src0[nsrc0++] = proj;
1918 flags |= IR3_INSTR_P;
1919 }
1920
1921 /* pad to 4, then ddx/ddy: */
1922 if (tex->op == nir_texop_txd) {
1923 while (nsrc0 < 4)
1924 src0[nsrc0++] = create_immed(b, fui(0.0));
1925 for (i = 0; i < coords; i++)
1926 src0[nsrc0++] = ddx[i];
1927 if (coords < 2)
1928 src0[nsrc0++] = create_immed(b, fui(0.0));
1929 for (i = 0; i < coords; i++)
1930 src0[nsrc0++] = ddy[i];
1931 if (coords < 2)
1932 src0[nsrc0++] = create_immed(b, fui(0.0));
1933 }
1934
1935 /*
1936 * second argument (if applicable):
1937 * - offsets
1938 * - lod
1939 * - bias
1940 */
1941 if (has_off | has_lod | has_bias) {
1942 if (has_off) {
1943 unsigned off_coords = coords;
1944 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
1945 off_coords--;
1946 for (i = 0; i < off_coords; i++)
1947 src1[nsrc1++] = off[i];
1948 if (off_coords < 2)
1949 src1[nsrc1++] = create_immed(b, fui(0.0));
1950 flags |= IR3_INSTR_O;
1951 }
1952
1953 if (has_lod | has_bias)
1954 src1[nsrc1++] = lod;
1955 }
1956
1957 switch (tex->dest_type) {
1958 case nir_type_invalid:
1959 case nir_type_float:
1960 type = TYPE_F32;
1961 break;
1962 case nir_type_int:
1963 type = TYPE_S32;
1964 break;
1965 case nir_type_uint:
1966 case nir_type_bool:
1967 type = TYPE_U32;
1968 break;
1969 default:
1970 unreachable("bad dest_type");
1971 }
1972
1973 if (opc == OPC_GETLOD)
1974 type = TYPE_U32;
1975
1976 unsigned tex_idx = tex->texture_index;
1977
1978 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex_idx);
1979
1980 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
1981 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
1982
1983 sam = ir3_SAM(b, opc, type, 0b1111, flags,
1984 tex_idx, tex_idx, col0, col1);
1985
1986 if ((ctx->astc_srgb & (1 << tex_idx)) && !nir_tex_instr_is_query(tex)) {
1987 /* only need first 3 components: */
1988 sam->regs[0]->wrmask = 0x7;
1989 ir3_split_dest(b, dst, sam, 0, 3);
1990
1991 /* we need to sample the alpha separately with a non-ASTC
1992 * texture state:
1993 */
1994 sam = ir3_SAM(b, opc, type, 0b1000, flags,
1995 tex_idx, tex_idx, col0, col1);
1996
1997 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
1998
1999 /* fixup .w component: */
2000 ir3_split_dest(b, &dst[3], sam, 3, 1);
2001 } else {
2002 /* normal (non-workaround) case: */
2003 ir3_split_dest(b, dst, sam, 0, 4);
2004 }
2005
2006 /* GETLOD returns results in 4.8 fixed point */
2007 if (opc == OPC_GETLOD) {
2008 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2009
2010 compile_assert(ctx, tex->dest_type == nir_type_float);
2011 for (i = 0; i < 2; i++) {
2012 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_U32, TYPE_F32), 0,
2013 factor, 0);
2014 }
2015 }
2016
2017 put_dst(ctx, &tex->dest);
2018 }
2019
2020 static void
2021 emit_tex_query_levels(struct ir3_context *ctx, nir_tex_instr *tex)
2022 {
2023 struct ir3_block *b = ctx->block;
2024 struct ir3_instruction **dst, *sam;
2025
2026 dst = ir3_get_dst(ctx, &tex->dest, 1);
2027
2028 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, 0b0100, 0,
2029 tex->texture_index, tex->texture_index, NULL, NULL);
2030
2031 /* even though there is only one component, since it ends
2032 * up in .z rather than .x, we need a split_dest()
2033 */
2034 ir3_split_dest(b, dst, sam, 0, 3);
2035
2036 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2037 * the value in TEX_CONST_0 is zero-based.
2038 */
2039 if (ctx->compiler->levels_add_one)
2040 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2041
2042 put_dst(ctx, &tex->dest);
2043 }
2044
2045 static void
2046 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2047 {
2048 struct ir3_block *b = ctx->block;
2049 struct ir3_instruction **dst, *sam;
2050 struct ir3_instruction *lod;
2051 unsigned flags, coords;
2052
2053 tex_info(tex, &flags, &coords);
2054
2055 /* Actually we want the number of dimensions, not coordinates. This
2056 * distinction only matters for cubes.
2057 */
2058 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2059 coords = 2;
2060
2061 dst = ir3_get_dst(ctx, &tex->dest, 4);
2062
2063 compile_assert(ctx, tex->num_srcs == 1);
2064 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2065
2066 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2067
2068 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
2069 tex->texture_index, tex->texture_index, lod, NULL);
2070
2071 ir3_split_dest(b, dst, sam, 0, 4);
2072
2073 /* Array size actually ends up in .w rather than .z. This doesn't
2074 * matter for miplevel 0, but for higher mips the value in z is
2075 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2076 * returned, which means that we have to add 1 to it for arrays.
2077 */
2078 if (tex->is_array) {
2079 if (ctx->compiler->levels_add_one) {
2080 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2081 } else {
2082 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2083 }
2084 }
2085
2086 put_dst(ctx, &tex->dest);
2087 }
2088
2089 static void
2090 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2091 {
2092 switch (jump->type) {
2093 case nir_jump_break:
2094 case nir_jump_continue:
2095 case nir_jump_return:
2096 /* I *think* we can simply just ignore this, and use the
2097 * successor block link to figure out where we need to
2098 * jump to for break/continue
2099 */
2100 break;
2101 default:
2102 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2103 break;
2104 }
2105 }
2106
2107 static void
2108 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2109 {
2110 switch (instr->type) {
2111 case nir_instr_type_alu:
2112 emit_alu(ctx, nir_instr_as_alu(instr));
2113 break;
2114 case nir_instr_type_deref:
2115 /* ignored, handled as part of the intrinsic they are src to */
2116 break;
2117 case nir_instr_type_intrinsic:
2118 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2119 break;
2120 case nir_instr_type_load_const:
2121 emit_load_const(ctx, nir_instr_as_load_const(instr));
2122 break;
2123 case nir_instr_type_ssa_undef:
2124 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2125 break;
2126 case nir_instr_type_tex: {
2127 nir_tex_instr *tex = nir_instr_as_tex(instr);
2128 /* couple tex instructions get special-cased:
2129 */
2130 switch (tex->op) {
2131 case nir_texop_txs:
2132 emit_tex_txs(ctx, tex);
2133 break;
2134 case nir_texop_query_levels:
2135 emit_tex_query_levels(ctx, tex);
2136 break;
2137 default:
2138 emit_tex(ctx, tex);
2139 break;
2140 }
2141 break;
2142 }
2143 case nir_instr_type_jump:
2144 emit_jump(ctx, nir_instr_as_jump(instr));
2145 break;
2146 case nir_instr_type_phi:
2147 /* we have converted phi webs to regs in NIR by now */
2148 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2149 break;
2150 case nir_instr_type_call:
2151 case nir_instr_type_parallel_copy:
2152 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2153 break;
2154 }
2155 }
2156
2157 static struct ir3_block *
2158 get_block(struct ir3_context *ctx, const nir_block *nblock)
2159 {
2160 struct ir3_block *block;
2161 struct hash_entry *hentry;
2162 unsigned i;
2163
2164 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2165 if (hentry)
2166 return hentry->data;
2167
2168 block = ir3_block_create(ctx->ir);
2169 block->nblock = nblock;
2170 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2171
2172 block->predecessors_count = nblock->predecessors->entries;
2173 block->predecessors = ralloc_array_size(block,
2174 sizeof(block->predecessors[0]), block->predecessors_count);
2175 i = 0;
2176 set_foreach(nblock->predecessors, sentry) {
2177 block->predecessors[i++] = get_block(ctx, sentry->key);
2178 }
2179
2180 return block;
2181 }
2182
2183 static void
2184 emit_block(struct ir3_context *ctx, nir_block *nblock)
2185 {
2186 struct ir3_block *block = get_block(ctx, nblock);
2187
2188 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2189 if (nblock->successors[i]) {
2190 block->successors[i] =
2191 get_block(ctx, nblock->successors[i]);
2192 }
2193 }
2194
2195 ctx->block = block;
2196 list_addtail(&block->node, &ctx->ir->block_list);
2197
2198 /* re-emit addr register in each block if needed: */
2199 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2200 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2201 ctx->addr_ht[i] = NULL;
2202 }
2203
2204 nir_foreach_instr(instr, nblock) {
2205 ctx->cur_instr = instr;
2206 emit_instr(ctx, instr);
2207 ctx->cur_instr = NULL;
2208 if (ctx->error)
2209 return;
2210 }
2211 }
2212
2213 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2214
2215 static void
2216 emit_if(struct ir3_context *ctx, nir_if *nif)
2217 {
2218 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2219
2220 ctx->block->condition =
2221 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2222
2223 emit_cf_list(ctx, &nif->then_list);
2224 emit_cf_list(ctx, &nif->else_list);
2225 }
2226
2227 static void
2228 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2229 {
2230 emit_cf_list(ctx, &nloop->body);
2231 }
2232
2233 static void
2234 stack_push(struct ir3_context *ctx)
2235 {
2236 ctx->stack++;
2237 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2238 }
2239
2240 static void
2241 stack_pop(struct ir3_context *ctx)
2242 {
2243 compile_assert(ctx, ctx->stack > 0);
2244 ctx->stack--;
2245 }
2246
2247 static void
2248 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2249 {
2250 foreach_list_typed(nir_cf_node, node, node, list) {
2251 switch (node->type) {
2252 case nir_cf_node_block:
2253 emit_block(ctx, nir_cf_node_as_block(node));
2254 break;
2255 case nir_cf_node_if:
2256 stack_push(ctx);
2257 emit_if(ctx, nir_cf_node_as_if(node));
2258 stack_pop(ctx);
2259 break;
2260 case nir_cf_node_loop:
2261 stack_push(ctx);
2262 emit_loop(ctx, nir_cf_node_as_loop(node));
2263 stack_pop(ctx);
2264 break;
2265 case nir_cf_node_function:
2266 ir3_context_error(ctx, "TODO\n");
2267 break;
2268 }
2269 }
2270 }
2271
2272 /* emit stream-out code. At this point, the current block is the original
2273 * (nir) end block, and nir ensures that all flow control paths terminate
2274 * into the end block. We re-purpose the original end block to generate
2275 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2276 * block holding stream-out write instructions, followed by the new end
2277 * block:
2278 *
2279 * blockOrigEnd {
2280 * p0.x = (vtxcnt < maxvtxcnt)
2281 * // succs: blockStreamOut, blockNewEnd
2282 * }
2283 * blockStreamOut {
2284 * ... stream-out instructions ...
2285 * // succs: blockNewEnd
2286 * }
2287 * blockNewEnd {
2288 * }
2289 */
2290 static void
2291 emit_stream_out(struct ir3_context *ctx)
2292 {
2293 struct ir3_shader_variant *v = ctx->so;
2294 struct ir3 *ir = ctx->ir;
2295 struct ir3_stream_output_info *strmout =
2296 &ctx->so->shader->stream_output;
2297 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2298 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2299 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2300
2301 /* create vtxcnt input in input block at top of shader,
2302 * so that it is seen as live over the entire duration
2303 * of the shader:
2304 */
2305 vtxcnt = create_input(ctx, 0);
2306 add_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, vtxcnt);
2307
2308 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2309
2310 /* at this point, we are at the original 'end' block,
2311 * re-purpose this block to stream-out condition, then
2312 * append stream-out block and new-end block
2313 */
2314 orig_end_block = ctx->block;
2315
2316 // TODO these blocks need to update predecessors..
2317 // maybe w/ store_global intrinsic, we could do this
2318 // stuff in nir->nir pass
2319
2320 stream_out_block = ir3_block_create(ir);
2321 list_addtail(&stream_out_block->node, &ir->block_list);
2322
2323 new_end_block = ir3_block_create(ir);
2324 list_addtail(&new_end_block->node, &ir->block_list);
2325
2326 orig_end_block->successors[0] = stream_out_block;
2327 orig_end_block->successors[1] = new_end_block;
2328 stream_out_block->successors[0] = new_end_block;
2329
2330 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2331 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2332 cond->regs[0]->num = regid(REG_P0, 0);
2333 cond->cat2.condition = IR3_COND_LT;
2334
2335 /* condition goes on previous block to the conditional,
2336 * since it is used to pick which of the two successor
2337 * paths to take:
2338 */
2339 orig_end_block->condition = cond;
2340
2341 /* switch to stream_out_block to generate the stream-out
2342 * instructions:
2343 */
2344 ctx->block = stream_out_block;
2345
2346 /* Calculate base addresses based on vtxcnt. Instructions
2347 * generated for bases not used in following loop will be
2348 * stripped out in the backend.
2349 */
2350 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2351 unsigned stride = strmout->stride[i];
2352 struct ir3_instruction *base, *off;
2353
2354 base = create_uniform(ctx->block, regid(v->constbase.tfbo, i));
2355
2356 /* 24-bit should be enough: */
2357 off = ir3_MUL_U(ctx->block, vtxcnt, 0,
2358 create_immed(ctx->block, stride * 4), 0);
2359
2360 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2361 }
2362
2363 /* Generate the per-output store instructions: */
2364 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2365 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2366 unsigned c = j + strmout->output[i].start_component;
2367 struct ir3_instruction *base, *out, *stg;
2368
2369 base = bases[strmout->output[i].output_buffer];
2370 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2371
2372 stg = ir3_STG(ctx->block, base, 0, out, 0,
2373 create_immed(ctx->block, 1), 0);
2374 stg->cat6.type = TYPE_U32;
2375 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2376
2377 array_insert(ctx->block, ctx->block->keeps, stg);
2378 }
2379 }
2380
2381 /* and finally switch to the new_end_block: */
2382 ctx->block = new_end_block;
2383 }
2384
2385 static void
2386 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2387 {
2388 nir_metadata_require(impl, nir_metadata_block_index);
2389
2390 compile_assert(ctx, ctx->stack == 0);
2391
2392 emit_cf_list(ctx, &impl->body);
2393 emit_block(ctx, impl->end_block);
2394
2395 compile_assert(ctx, ctx->stack == 0);
2396
2397 /* at this point, we should have a single empty block,
2398 * into which we emit the 'end' instruction.
2399 */
2400 compile_assert(ctx, list_empty(&ctx->block->instr_list));
2401
2402 /* If stream-out (aka transform-feedback) enabled, emit the
2403 * stream-out instructions, followed by a new empty block (into
2404 * which the 'end' instruction lands).
2405 *
2406 * NOTE: it is done in this order, rather than inserting before
2407 * we emit end_block, because NIR guarantees that all blocks
2408 * flow into end_block, and that end_block has no successors.
2409 * So by re-purposing end_block as the first block of stream-
2410 * out, we guarantee that all exit paths flow into the stream-
2411 * out instructions.
2412 */
2413 if ((ctx->compiler->gpu_id < 500) &&
2414 (ctx->so->shader->stream_output.num_outputs > 0) &&
2415 !ctx->so->binning_pass) {
2416 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2417 emit_stream_out(ctx);
2418 }
2419
2420 ir3_END(ctx->block);
2421 }
2422
2423 static struct ir3_instruction *
2424 create_frag_coord(struct ir3_context *ctx, unsigned comp)
2425 {
2426 struct ir3_block *block = ctx->block;
2427 struct ir3_instruction *instr;
2428
2429 if (!ctx->frag_coord) {
2430 ctx->frag_coord = create_input_compmask(ctx, 0, 0xf);
2431 /* defer add_sysval_input() until after all inputs created */
2432 }
2433
2434 ir3_split_dest(block, &instr, ctx->frag_coord, comp, 1);
2435
2436 switch (comp) {
2437 case 0: /* .x */
2438 case 1: /* .y */
2439 /* for frag_coord, we get unsigned values.. we need
2440 * to subtract (integer) 8 and divide by 16 (right-
2441 * shift by 4) then convert to float:
2442 *
2443 * sub.s tmp, src, 8
2444 * shr.b tmp, tmp, 4
2445 * mov.u32f32 dst, tmp
2446 *
2447 */
2448 instr = ir3_SUB_S(block, instr, 0,
2449 create_immed(block, 8), 0);
2450 instr = ir3_SHR_B(block, instr, 0,
2451 create_immed(block, 4), 0);
2452 instr = ir3_COV(block, instr, TYPE_U32, TYPE_F32);
2453
2454 return instr;
2455 case 2: /* .z */
2456 case 3: /* .w */
2457 default:
2458 /* seems that we can use these as-is: */
2459 return instr;
2460 }
2461 }
2462
2463 static void
2464 setup_input(struct ir3_context *ctx, nir_variable *in)
2465 {
2466 struct ir3_shader_variant *so = ctx->so;
2467 unsigned ncomp = glsl_get_components(in->type);
2468 unsigned n = in->data.driver_location;
2469 unsigned frac = in->data.location_frac;
2470 unsigned slot = in->data.location;
2471
2472 /* skip unread inputs, we could end up with (for example), unsplit
2473 * matrix/etc inputs in the case they are not read, so just silently
2474 * skip these.
2475 */
2476 if (ncomp > 4)
2477 return;
2478
2479 so->inputs[n].slot = slot;
2480 so->inputs[n].compmask = (1 << (ncomp + frac)) - 1;
2481 so->inputs_count = MAX2(so->inputs_count, n + 1);
2482 so->inputs[n].interpolate = in->data.interpolation;
2483
2484 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2485 for (int i = 0; i < ncomp; i++) {
2486 struct ir3_instruction *instr = NULL;
2487 unsigned idx = (n * 4) + i + frac;
2488
2489 if (slot == VARYING_SLOT_POS) {
2490 so->inputs[n].bary = false;
2491 so->frag_coord = true;
2492 instr = create_frag_coord(ctx, i);
2493 } else if (slot == VARYING_SLOT_PNTC) {
2494 /* see for example st_nir_fixup_varying_slots().. this is
2495 * maybe a bit mesa/st specific. But we need things to line
2496 * up for this in fdN_program:
2497 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2498 * if (emit->sprite_coord_enable & texmask) {
2499 * ...
2500 * }
2501 */
2502 so->inputs[n].slot = VARYING_SLOT_VAR8;
2503 so->inputs[n].bary = true;
2504 instr = create_frag_input(ctx, false);
2505 } else {
2506 bool use_ldlv = false;
2507
2508 /* detect the special case for front/back colors where
2509 * we need to do flat vs smooth shading depending on
2510 * rast state:
2511 */
2512 if (in->data.interpolation == INTERP_MODE_NONE) {
2513 switch (slot) {
2514 case VARYING_SLOT_COL0:
2515 case VARYING_SLOT_COL1:
2516 case VARYING_SLOT_BFC0:
2517 case VARYING_SLOT_BFC1:
2518 so->inputs[n].rasterflat = true;
2519 break;
2520 default:
2521 break;
2522 }
2523 }
2524
2525 if (ctx->compiler->flat_bypass) {
2526 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2527 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2528 use_ldlv = true;
2529 }
2530
2531 so->inputs[n].bary = true;
2532
2533 instr = create_frag_input(ctx, use_ldlv);
2534 }
2535
2536 compile_assert(ctx, idx < ctx->ir->ninputs);
2537
2538 ctx->ir->inputs[idx] = instr;
2539 }
2540 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2541 for (int i = 0; i < ncomp; i++) {
2542 unsigned idx = (n * 4) + i + frac;
2543 compile_assert(ctx, idx < ctx->ir->ninputs);
2544 ctx->ir->inputs[idx] = create_input(ctx, idx);
2545 }
2546 } else {
2547 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2548 }
2549
2550 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2551 so->total_in += ncomp;
2552 }
2553 }
2554
2555 static void
2556 setup_output(struct ir3_context *ctx, nir_variable *out)
2557 {
2558 struct ir3_shader_variant *so = ctx->so;
2559 unsigned ncomp = glsl_get_components(out->type);
2560 unsigned n = out->data.driver_location;
2561 unsigned frac = out->data.location_frac;
2562 unsigned slot = out->data.location;
2563 unsigned comp = 0;
2564
2565 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2566 switch (slot) {
2567 case FRAG_RESULT_DEPTH:
2568 comp = 2; /* tgsi will write to .z component */
2569 so->writes_pos = true;
2570 break;
2571 case FRAG_RESULT_COLOR:
2572 so->color0_mrt = 1;
2573 break;
2574 default:
2575 if (slot >= FRAG_RESULT_DATA0)
2576 break;
2577 ir3_context_error(ctx, "unknown FS output name: %s\n",
2578 gl_frag_result_name(slot));
2579 }
2580 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2581 switch (slot) {
2582 case VARYING_SLOT_POS:
2583 so->writes_pos = true;
2584 break;
2585 case VARYING_SLOT_PSIZ:
2586 so->writes_psize = true;
2587 break;
2588 case VARYING_SLOT_COL0:
2589 case VARYING_SLOT_COL1:
2590 case VARYING_SLOT_BFC0:
2591 case VARYING_SLOT_BFC1:
2592 case VARYING_SLOT_FOGC:
2593 case VARYING_SLOT_CLIP_DIST0:
2594 case VARYING_SLOT_CLIP_DIST1:
2595 case VARYING_SLOT_CLIP_VERTEX:
2596 break;
2597 default:
2598 if (slot >= VARYING_SLOT_VAR0)
2599 break;
2600 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2601 break;
2602 ir3_context_error(ctx, "unknown VS output name: %s\n",
2603 gl_varying_slot_name(slot));
2604 }
2605 } else {
2606 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2607 }
2608
2609 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2610
2611 so->outputs[n].slot = slot;
2612 so->outputs[n].regid = regid(n, comp);
2613 so->outputs_count = MAX2(so->outputs_count, n + 1);
2614
2615 for (int i = 0; i < ncomp; i++) {
2616 unsigned idx = (n * 4) + i + frac;
2617 compile_assert(ctx, idx < ctx->ir->noutputs);
2618 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2619 }
2620
2621 /* if varying packing doesn't happen, we could end up in a situation
2622 * with "holes" in the output, and since the per-generation code that
2623 * sets up varying linkage registers doesn't expect to have more than
2624 * one varying per vec4 slot, pad the holes.
2625 *
2626 * Note that this should probably generate a performance warning of
2627 * some sort.
2628 */
2629 for (int i = 0; i < frac; i++) {
2630 unsigned idx = (n * 4) + i;
2631 if (!ctx->ir->outputs[idx]) {
2632 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2633 }
2634 }
2635 }
2636
2637 static int
2638 max_drvloc(struct exec_list *vars)
2639 {
2640 int drvloc = -1;
2641 nir_foreach_variable(var, vars) {
2642 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2643 }
2644 return drvloc;
2645 }
2646
2647 static const unsigned max_sysvals[] = {
2648 [MESA_SHADER_FRAGMENT] = 24, // TODO
2649 [MESA_SHADER_VERTEX] = 16,
2650 [MESA_SHADER_COMPUTE] = 16, // TODO how many do we actually need?
2651 [MESA_SHADER_KERNEL] = 16, // TODO how many do we actually need?
2652 };
2653
2654 static void
2655 emit_instructions(struct ir3_context *ctx)
2656 {
2657 unsigned ninputs, noutputs;
2658 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
2659
2660 ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
2661 noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
2662
2663 /* we need to leave room for sysvals:
2664 */
2665 ninputs += max_sysvals[ctx->so->type];
2666
2667 ctx->ir = ir3_create(ctx->compiler, ninputs, noutputs);
2668
2669 /* Create inputs in first block: */
2670 ctx->block = get_block(ctx, nir_start_block(fxn));
2671 ctx->in_block = ctx->block;
2672 list_addtail(&ctx->block->node, &ctx->ir->block_list);
2673
2674 ninputs -= max_sysvals[ctx->so->type];
2675
2676 /* for fragment shader, the vcoord input register is used as the
2677 * base for bary.f varying fetch instrs:
2678 */
2679 struct ir3_instruction *vcoord = NULL;
2680 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2681 struct ir3_instruction *xy[2];
2682
2683 vcoord = create_input_compmask(ctx, 0, 0x3);
2684 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
2685
2686 ctx->frag_vcoord = ir3_create_collect(ctx, xy, 2);
2687 }
2688
2689 /* Setup inputs: */
2690 nir_foreach_variable(var, &ctx->s->inputs) {
2691 setup_input(ctx, var);
2692 }
2693
2694 /* Defer add_sysval_input() stuff until after setup_inputs(),
2695 * because sysvals need to be appended after varyings:
2696 */
2697 if (vcoord) {
2698 add_sysval_input_compmask(ctx, SYSTEM_VALUE_VARYING_COORD,
2699 0x3, vcoord);
2700 }
2701
2702 if (ctx->frag_coord) {
2703 add_sysval_input_compmask(ctx, SYSTEM_VALUE_FRAG_COORD,
2704 0xf, ctx->frag_coord);
2705 }
2706
2707 /* Setup outputs: */
2708 nir_foreach_variable(var, &ctx->s->outputs) {
2709 setup_output(ctx, var);
2710 }
2711
2712 /* Setup registers (which should only be arrays): */
2713 nir_foreach_register(reg, &ctx->s->registers) {
2714 ir3_declare_array(ctx, reg);
2715 }
2716
2717 /* NOTE: need to do something more clever when we support >1 fxn */
2718 nir_foreach_register(reg, &fxn->registers) {
2719 ir3_declare_array(ctx, reg);
2720 }
2721 /* And emit the body: */
2722 ctx->impl = fxn;
2723 emit_function(ctx, fxn);
2724 }
2725
2726 /* from NIR perspective, we actually have varying inputs. But the varying
2727 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
2728 * only actual inputs are the sysvals.
2729 */
2730 static void
2731 fixup_frag_inputs(struct ir3_context *ctx)
2732 {
2733 struct ir3_shader_variant *so = ctx->so;
2734 struct ir3 *ir = ctx->ir;
2735 unsigned i = 0;
2736
2737 /* sysvals should appear at the end of the inputs, drop everything else: */
2738 while ((i < so->inputs_count) && !so->inputs[i].sysval)
2739 i++;
2740
2741 /* at IR level, inputs are always blocks of 4 scalars: */
2742 i *= 4;
2743
2744 ir->inputs = &ir->inputs[i];
2745 ir->ninputs -= i;
2746 }
2747
2748 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2749 * need to assign the tex state indexes for these after we know the
2750 * max tex index.
2751 */
2752 static void
2753 fixup_astc_srgb(struct ir3_context *ctx)
2754 {
2755 struct ir3_shader_variant *so = ctx->so;
2756 /* indexed by original tex idx, value is newly assigned alpha sampler
2757 * state tex idx. Zero is invalid since there is at least one sampler
2758 * if we get here.
2759 */
2760 unsigned alt_tex_state[16] = {0};
2761 unsigned tex_idx = ctx->max_texture_index + 1;
2762 unsigned idx = 0;
2763
2764 so->astc_srgb.base = tex_idx;
2765
2766 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
2767 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
2768
2769 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
2770
2771 if (alt_tex_state[sam->cat5.tex] == 0) {
2772 /* assign new alternate/alpha tex state slot: */
2773 alt_tex_state[sam->cat5.tex] = tex_idx++;
2774 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
2775 so->astc_srgb.count++;
2776 }
2777
2778 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
2779 }
2780 }
2781
2782 static void
2783 fixup_binning_pass(struct ir3_context *ctx)
2784 {
2785 struct ir3_shader_variant *so = ctx->so;
2786 struct ir3 *ir = ctx->ir;
2787 unsigned i, j;
2788
2789 for (i = 0, j = 0; i < so->outputs_count; i++) {
2790 unsigned slot = so->outputs[i].slot;
2791
2792 /* throw away everything but first position/psize */
2793 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
2794 if (i != j) {
2795 so->outputs[j] = so->outputs[i];
2796 ir->outputs[(j*4)+0] = ir->outputs[(i*4)+0];
2797 ir->outputs[(j*4)+1] = ir->outputs[(i*4)+1];
2798 ir->outputs[(j*4)+2] = ir->outputs[(i*4)+2];
2799 ir->outputs[(j*4)+3] = ir->outputs[(i*4)+3];
2800 }
2801 j++;
2802 }
2803 }
2804 so->outputs_count = j;
2805 ir->noutputs = j * 4;
2806 }
2807
2808 int
2809 ir3_compile_shader_nir(struct ir3_compiler *compiler,
2810 struct ir3_shader_variant *so)
2811 {
2812 struct ir3_context *ctx;
2813 struct ir3 *ir;
2814 struct ir3_instruction **inputs;
2815 unsigned i, actual_in, inloc;
2816 int ret = 0, max_bary;
2817
2818 assert(!so->ir);
2819
2820 ctx = ir3_context_init(compiler, so);
2821 if (!ctx) {
2822 DBG("INIT failed!");
2823 ret = -1;
2824 goto out;
2825 }
2826
2827 emit_instructions(ctx);
2828
2829 if (ctx->error) {
2830 DBG("EMIT failed!");
2831 ret = -1;
2832 goto out;
2833 }
2834
2835 ir = so->ir = ctx->ir;
2836
2837 /* keep track of the inputs from TGSI perspective.. */
2838 inputs = ir->inputs;
2839
2840 /* but fixup actual inputs for frag shader: */
2841 if (so->type == MESA_SHADER_FRAGMENT)
2842 fixup_frag_inputs(ctx);
2843
2844 /* at this point, for binning pass, throw away unneeded outputs: */
2845 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
2846 fixup_binning_pass(ctx);
2847
2848 /* if we want half-precision outputs, mark the output registers
2849 * as half:
2850 */
2851 if (so->key.half_precision) {
2852 for (i = 0; i < ir->noutputs; i++) {
2853 struct ir3_instruction *out = ir->outputs[i];
2854
2855 if (!out)
2856 continue;
2857
2858 /* if frag shader writes z, that needs to be full precision: */
2859 if (so->outputs[i/4].slot == FRAG_RESULT_DEPTH)
2860 continue;
2861
2862 out->regs[0]->flags |= IR3_REG_HALF;
2863 /* output could be a fanout (ie. texture fetch output)
2864 * in which case we need to propagate the half-reg flag
2865 * up to the definer so that RA sees it:
2866 */
2867 if (out->opc == OPC_META_FO) {
2868 out = out->regs[1]->instr;
2869 out->regs[0]->flags |= IR3_REG_HALF;
2870 }
2871
2872 if (out->opc == OPC_MOV) {
2873 out->cat1.dst_type = half_type(out->cat1.dst_type);
2874 }
2875 }
2876 }
2877
2878 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2879 printf("BEFORE CP:\n");
2880 ir3_print(ir);
2881 }
2882
2883 ir3_cp(ir, so);
2884
2885 /* at this point, for binning pass, throw away unneeded outputs:
2886 * Note that for a6xx and later, we do this after ir3_cp to ensure
2887 * that the uniform/constant layout for BS and VS matches, so that
2888 * we can re-use same VS_CONST state group.
2889 */
2890 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
2891 fixup_binning_pass(ctx);
2892
2893 /* Insert mov if there's same instruction for each output.
2894 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
2895 */
2896 for (int i = ir->noutputs - 1; i >= 0; i--) {
2897 if (!ir->outputs[i])
2898 continue;
2899 for (unsigned j = 0; j < i; j++) {
2900 if (ir->outputs[i] == ir->outputs[j]) {
2901 ir->outputs[i] =
2902 ir3_MOV(ir->outputs[i]->block, ir->outputs[i], TYPE_F32);
2903 }
2904 }
2905 }
2906
2907 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2908 printf("BEFORE GROUPING:\n");
2909 ir3_print(ir);
2910 }
2911
2912 ir3_sched_add_deps(ir);
2913
2914 /* Group left/right neighbors, inserting mov's where needed to
2915 * solve conflicts:
2916 */
2917 ir3_group(ir);
2918
2919 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2920 printf("AFTER GROUPING:\n");
2921 ir3_print(ir);
2922 }
2923
2924 ir3_depth(ir);
2925
2926 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2927 printf("AFTER DEPTH:\n");
2928 ir3_print(ir);
2929 }
2930
2931 ret = ir3_sched(ir);
2932 if (ret) {
2933 DBG("SCHED failed!");
2934 goto out;
2935 }
2936
2937 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2938 printf("AFTER SCHED:\n");
2939 ir3_print(ir);
2940 }
2941
2942 ret = ir3_ra(ir, so->type, so->frag_coord, so->frag_face);
2943 if (ret) {
2944 DBG("RA failed!");
2945 goto out;
2946 }
2947
2948 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2949 printf("AFTER RA:\n");
2950 ir3_print(ir);
2951 }
2952
2953 /* fixup input/outputs: */
2954 for (i = 0; i < so->outputs_count; i++) {
2955 /* sometimes we get outputs that don't write the .x coord, like:
2956 *
2957 * decl_var shader_out INTERP_MODE_NONE float Color (VARYING_SLOT_VAR9.z, 1, 0)
2958 *
2959 * Presumably the result of varying packing and then eliminating
2960 * some unneeded varyings? Just skip head to the first valid
2961 * component of the output.
2962 */
2963 for (unsigned j = 0; j < 4; j++) {
2964 struct ir3_instruction *instr = ir->outputs[(i*4) + j];
2965 if (instr) {
2966 so->outputs[i].regid = instr->regs[0]->num;
2967 break;
2968 }
2969 }
2970 }
2971
2972 /* Note that some or all channels of an input may be unused: */
2973 actual_in = 0;
2974 inloc = 0;
2975 for (i = 0; i < so->inputs_count; i++) {
2976 unsigned j, reg = regid(63,0), compmask = 0, maxcomp = 0;
2977 so->inputs[i].ncomp = 0;
2978 so->inputs[i].inloc = inloc;
2979 for (j = 0; j < 4; j++) {
2980 struct ir3_instruction *in = inputs[(i*4) + j];
2981 if (in && !(in->flags & IR3_INSTR_UNUSED)) {
2982 compmask |= (1 << j);
2983 reg = in->regs[0]->num - j;
2984 actual_in++;
2985 so->inputs[i].ncomp++;
2986 if ((so->type == MESA_SHADER_FRAGMENT) && so->inputs[i].bary) {
2987 /* assign inloc: */
2988 assert(in->regs[1]->flags & IR3_REG_IMMED);
2989 in->regs[1]->iim_val = inloc + j;
2990 maxcomp = j + 1;
2991 }
2992 }
2993 }
2994 if ((so->type == MESA_SHADER_FRAGMENT) && compmask && so->inputs[i].bary) {
2995 so->varying_in++;
2996 so->inputs[i].compmask = (1 << maxcomp) - 1;
2997 inloc += maxcomp;
2998 } else if (!so->inputs[i].sysval) {
2999 so->inputs[i].compmask = compmask;
3000 }
3001 so->inputs[i].regid = reg;
3002 }
3003
3004 if (ctx->astc_srgb)
3005 fixup_astc_srgb(ctx);
3006
3007 /* We need to do legalize after (for frag shader's) the "bary.f"
3008 * offsets (inloc) have been assigned.
3009 */
3010 ir3_legalize(ir, &so->num_samp, &so->has_ssbo, &max_bary);
3011
3012 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3013 printf("AFTER LEGALIZE:\n");
3014 ir3_print(ir);
3015 }
3016
3017 so->branchstack = ctx->max_stack;
3018
3019 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3020 if (so->type == MESA_SHADER_VERTEX)
3021 so->total_in = actual_in;
3022 else
3023 so->total_in = max_bary + 1;
3024
3025 out:
3026 if (ret) {
3027 if (so->ir)
3028 ir3_destroy(so->ir);
3029 so->ir = NULL;
3030 }
3031 ir3_context_free(ctx);
3032
3033 return ret;
3034 }