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freedreno/ir3: add meta instruction for pre-fs texture fetch
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 ir3_reg_create(mov, 0, 0);
55 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
56 src->instr = collect;
57 src->size = arrsz;
58 src->array.offset = n;
59
60 ir3_instr_set_address(mov, address);
61
62 return mov;
63 }
64
65 static struct ir3_instruction *
66 create_input_compmask(struct ir3_context *ctx, unsigned n, unsigned compmask)
67 {
68 struct ir3_instruction *in;
69
70 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
71 in->input.sysval = ~0;
72 ir3_reg_create(in, n, 0);
73
74 in->regs[0]->wrmask = compmask;
75
76 return in;
77 }
78
79 static struct ir3_instruction *
80 create_input(struct ir3_context *ctx, unsigned n)
81 {
82 return create_input_compmask(ctx, n, 0x1);
83 }
84
85 static struct ir3_instruction *
86 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
87 {
88 struct ir3_block *block = ctx->block;
89 struct ir3_instruction *instr;
90 /* packed inloc is fixed up later: */
91 struct ir3_instruction *inloc = create_immed(block, n);
92
93 if (use_ldlv) {
94 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
95 instr->cat6.type = TYPE_U32;
96 instr->cat6.iim_val = 1;
97 } else {
98 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
99 instr->regs[2]->wrmask = 0x3;
100 }
101
102 return instr;
103 }
104
105 static struct ir3_instruction *
106 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
107 {
108 /* first four vec4 sysval's reserved for UBOs: */
109 /* NOTE: dp is in scalar, but there can be >4 dp components: */
110 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
111 unsigned n = const_state->offsets.driver_param;
112 unsigned r = regid(n + dp / 4, dp % 4);
113 return create_uniform(ctx->block, r);
114 }
115
116 /*
117 * Adreno uses uint rather than having dedicated bool type,
118 * which (potentially) requires some conversion, in particular
119 * when using output of an bool instr to int input, or visa
120 * versa.
121 *
122 * | Adreno | NIR |
123 * -------+---------+-------+-
124 * true | 1 | ~0 |
125 * false | 0 | 0 |
126 *
127 * To convert from an adreno bool (uint) to nir, use:
128 *
129 * absneg.s dst, (neg)src
130 *
131 * To convert back in the other direction:
132 *
133 * absneg.s dst, (abs)arc
134 *
135 * The CP step can clean up the absneg.s that cancel each other
136 * out, and with a slight bit of extra cleverness (to recognize
137 * the instructions which produce either a 0 or 1) can eliminate
138 * the absneg.s's completely when an instruction that wants
139 * 0/1 consumes the result. For example, when a nir 'bcsel'
140 * consumes the result of 'feq'. So we should be able to get by
141 * without a boolean resolve step, and without incuring any
142 * extra penalty in instruction count.
143 */
144
145 /* NIR bool -> native (adreno): */
146 static struct ir3_instruction *
147 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
148 {
149 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
150 }
151
152 /* native (adreno) -> NIR bool: */
153 static struct ir3_instruction *
154 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
155 {
156 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
157 }
158
159 /*
160 * alu/sfu instructions:
161 */
162
163 static struct ir3_instruction *
164 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
165 unsigned src_bitsize, nir_op op)
166 {
167 type_t src_type, dst_type;
168
169 switch (op) {
170 case nir_op_f2f32:
171 case nir_op_f2f16_rtne:
172 case nir_op_f2f16_rtz:
173 case nir_op_f2f16:
174 case nir_op_f2i32:
175 case nir_op_f2i16:
176 case nir_op_f2i8:
177 case nir_op_f2u32:
178 case nir_op_f2u16:
179 case nir_op_f2u8:
180 switch (src_bitsize) {
181 case 32:
182 src_type = TYPE_F32;
183 break;
184 case 16:
185 src_type = TYPE_F16;
186 break;
187 default:
188 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
189 }
190 break;
191
192 case nir_op_i2f32:
193 case nir_op_i2f16:
194 case nir_op_i2i32:
195 case nir_op_i2i16:
196 case nir_op_i2i8:
197 switch (src_bitsize) {
198 case 32:
199 src_type = TYPE_S32;
200 break;
201 case 16:
202 src_type = TYPE_S16;
203 break;
204 case 8:
205 src_type = TYPE_S8;
206 break;
207 default:
208 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
209 }
210 break;
211
212 case nir_op_u2f32:
213 case nir_op_u2f16:
214 case nir_op_u2u32:
215 case nir_op_u2u16:
216 case nir_op_u2u8:
217 switch (src_bitsize) {
218 case 32:
219 src_type = TYPE_U32;
220 break;
221 case 16:
222 src_type = TYPE_U16;
223 break;
224 case 8:
225 src_type = TYPE_U8;
226 break;
227 default:
228 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
229 }
230 break;
231
232 default:
233 ir3_context_error(ctx, "invalid conversion op: %u", op);
234 }
235
236 switch (op) {
237 case nir_op_f2f32:
238 case nir_op_i2f32:
239 case nir_op_u2f32:
240 dst_type = TYPE_F32;
241 break;
242
243 case nir_op_f2f16_rtne:
244 case nir_op_f2f16_rtz:
245 case nir_op_f2f16:
246 /* TODO how to handle rounding mode? */
247 case nir_op_i2f16:
248 case nir_op_u2f16:
249 dst_type = TYPE_F16;
250 break;
251
252 case nir_op_f2i32:
253 case nir_op_i2i32:
254 dst_type = TYPE_S32;
255 break;
256
257 case nir_op_f2i16:
258 case nir_op_i2i16:
259 dst_type = TYPE_S16;
260 break;
261
262 case nir_op_f2i8:
263 case nir_op_i2i8:
264 dst_type = TYPE_S8;
265 break;
266
267 case nir_op_f2u32:
268 case nir_op_u2u32:
269 dst_type = TYPE_U32;
270 break;
271
272 case nir_op_f2u16:
273 case nir_op_u2u16:
274 dst_type = TYPE_U16;
275 break;
276
277 case nir_op_f2u8:
278 case nir_op_u2u8:
279 dst_type = TYPE_U8;
280 break;
281
282 default:
283 ir3_context_error(ctx, "invalid conversion op: %u", op);
284 }
285
286 return ir3_COV(ctx->block, src, src_type, dst_type);
287 }
288
289 static void
290 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
291 {
292 const nir_op_info *info = &nir_op_infos[alu->op];
293 struct ir3_instruction **dst, *src[info->num_inputs];
294 unsigned bs[info->num_inputs]; /* bit size */
295 struct ir3_block *b = ctx->block;
296 unsigned dst_sz, wrmask;
297 type_t dst_type = nir_dest_bit_size(alu->dest.dest) < 32 ?
298 TYPE_U16 : TYPE_U32;
299
300 if (alu->dest.dest.is_ssa) {
301 dst_sz = alu->dest.dest.ssa.num_components;
302 wrmask = (1 << dst_sz) - 1;
303 } else {
304 dst_sz = alu->dest.dest.reg.reg->num_components;
305 wrmask = alu->dest.write_mask;
306 }
307
308 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
309
310 /* Vectors are special in that they have non-scalarized writemasks,
311 * and just take the first swizzle channel for each argument in
312 * order into each writemask channel.
313 */
314 if ((alu->op == nir_op_vec2) ||
315 (alu->op == nir_op_vec3) ||
316 (alu->op == nir_op_vec4)) {
317
318 for (int i = 0; i < info->num_inputs; i++) {
319 nir_alu_src *asrc = &alu->src[i];
320
321 compile_assert(ctx, !asrc->abs);
322 compile_assert(ctx, !asrc->negate);
323
324 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
325 if (!src[i])
326 src[i] = create_immed_typed(ctx->block, 0, dst_type);
327 dst[i] = ir3_MOV(b, src[i], dst_type);
328 }
329
330 ir3_put_dst(ctx, &alu->dest.dest);
331 return;
332 }
333
334 /* We also get mov's with more than one component for mov's so
335 * handle those specially:
336 */
337 if (alu->op == nir_op_mov) {
338 nir_alu_src *asrc = &alu->src[0];
339 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
340
341 for (unsigned i = 0; i < dst_sz; i++) {
342 if (wrmask & (1 << i)) {
343 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
344 } else {
345 dst[i] = NULL;
346 }
347 }
348
349 ir3_put_dst(ctx, &alu->dest.dest);
350 return;
351 }
352
353 /* General case: We can just grab the one used channel per src. */
354 for (int i = 0; i < info->num_inputs; i++) {
355 unsigned chan = ffs(alu->dest.write_mask) - 1;
356 nir_alu_src *asrc = &alu->src[i];
357
358 compile_assert(ctx, !asrc->abs);
359 compile_assert(ctx, !asrc->negate);
360
361 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
362 bs[i] = nir_src_bit_size(asrc->src);
363
364 compile_assert(ctx, src[i]);
365 }
366
367 switch (alu->op) {
368 case nir_op_f2f32:
369 case nir_op_f2f16_rtne:
370 case nir_op_f2f16_rtz:
371 case nir_op_f2f16:
372 case nir_op_f2i32:
373 case nir_op_f2i16:
374 case nir_op_f2i8:
375 case nir_op_f2u32:
376 case nir_op_f2u16:
377 case nir_op_f2u8:
378 case nir_op_i2f32:
379 case nir_op_i2f16:
380 case nir_op_i2i32:
381 case nir_op_i2i16:
382 case nir_op_i2i8:
383 case nir_op_u2f32:
384 case nir_op_u2f16:
385 case nir_op_u2u32:
386 case nir_op_u2u16:
387 case nir_op_u2u8:
388 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
389 break;
390 case nir_op_fquantize2f16:
391 dst[0] = create_cov(ctx,
392 create_cov(ctx, src[0], 32, nir_op_f2f16),
393 16, nir_op_f2f32);
394 break;
395 case nir_op_f2b32:
396 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
397 dst[0]->cat2.condition = IR3_COND_NE;
398 dst[0] = ir3_n2b(b, dst[0]);
399 break;
400 case nir_op_b2f16:
401 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F16);
402 break;
403 case nir_op_b2f32:
404 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
405 break;
406 case nir_op_b2i8:
407 case nir_op_b2i16:
408 case nir_op_b2i32:
409 dst[0] = ir3_b2n(b, src[0]);
410 break;
411 case nir_op_i2b32:
412 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
413 dst[0]->cat2.condition = IR3_COND_NE;
414 dst[0] = ir3_n2b(b, dst[0]);
415 break;
416
417 case nir_op_fneg:
418 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
419 break;
420 case nir_op_fabs:
421 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
422 break;
423 case nir_op_fmax:
424 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
425 break;
426 case nir_op_fmin:
427 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
428 break;
429 case nir_op_fsat:
430 /* if there is just a single use of the src, and it supports
431 * (sat) bit, we can just fold the (sat) flag back to the
432 * src instruction and create a mov. This is easier for cp
433 * to eliminate.
434 *
435 * TODO probably opc_cat==4 is ok too
436 */
437 if (alu->src[0].src.is_ssa &&
438 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
439 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
440 src[0]->flags |= IR3_INSTR_SAT;
441 dst[0] = ir3_MOV(b, src[0], dst_type);
442 } else {
443 /* otherwise generate a max.f that saturates.. blob does
444 * similar (generating a cat2 mov using max.f)
445 */
446 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
447 dst[0]->flags |= IR3_INSTR_SAT;
448 }
449 break;
450 case nir_op_fmul:
451 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
452 break;
453 case nir_op_fadd:
454 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
455 break;
456 case nir_op_fsub:
457 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
458 break;
459 case nir_op_ffma:
460 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
461 break;
462 case nir_op_fddx:
463 case nir_op_fddx_coarse:
464 dst[0] = ir3_DSX(b, src[0], 0);
465 dst[0]->cat5.type = TYPE_F32;
466 break;
467 case nir_op_fddy:
468 case nir_op_fddy_coarse:
469 dst[0] = ir3_DSY(b, src[0], 0);
470 dst[0]->cat5.type = TYPE_F32;
471 break;
472 break;
473 case nir_op_flt32:
474 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
475 dst[0]->cat2.condition = IR3_COND_LT;
476 dst[0] = ir3_n2b(b, dst[0]);
477 break;
478 case nir_op_fge32:
479 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
480 dst[0]->cat2.condition = IR3_COND_GE;
481 dst[0] = ir3_n2b(b, dst[0]);
482 break;
483 case nir_op_feq32:
484 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
485 dst[0]->cat2.condition = IR3_COND_EQ;
486 dst[0] = ir3_n2b(b, dst[0]);
487 break;
488 case nir_op_fne32:
489 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
490 dst[0]->cat2.condition = IR3_COND_NE;
491 dst[0] = ir3_n2b(b, dst[0]);
492 break;
493 case nir_op_fceil:
494 dst[0] = ir3_CEIL_F(b, src[0], 0);
495 break;
496 case nir_op_ffloor:
497 dst[0] = ir3_FLOOR_F(b, src[0], 0);
498 break;
499 case nir_op_ftrunc:
500 dst[0] = ir3_TRUNC_F(b, src[0], 0);
501 break;
502 case nir_op_fround_even:
503 dst[0] = ir3_RNDNE_F(b, src[0], 0);
504 break;
505 case nir_op_fsign:
506 dst[0] = ir3_SIGN_F(b, src[0], 0);
507 break;
508
509 case nir_op_fsin:
510 dst[0] = ir3_SIN(b, src[0], 0);
511 break;
512 case nir_op_fcos:
513 dst[0] = ir3_COS(b, src[0], 0);
514 break;
515 case nir_op_frsq:
516 dst[0] = ir3_RSQ(b, src[0], 0);
517 break;
518 case nir_op_frcp:
519 dst[0] = ir3_RCP(b, src[0], 0);
520 break;
521 case nir_op_flog2:
522 dst[0] = ir3_LOG2(b, src[0], 0);
523 break;
524 case nir_op_fexp2:
525 dst[0] = ir3_EXP2(b, src[0], 0);
526 break;
527 case nir_op_fsqrt:
528 dst[0] = ir3_SQRT(b, src[0], 0);
529 break;
530
531 case nir_op_iabs:
532 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
533 break;
534 case nir_op_iadd:
535 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
536 break;
537 case nir_op_iand:
538 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
539 break;
540 case nir_op_imax:
541 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
542 break;
543 case nir_op_umax:
544 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
545 break;
546 case nir_op_imin:
547 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
548 break;
549 case nir_op_umin:
550 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
551 break;
552 case nir_op_umul_low:
553 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
554 break;
555 case nir_op_imadsh_mix16:
556 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
557 break;
558 case nir_op_ineg:
559 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
560 break;
561 case nir_op_inot:
562 dst[0] = ir3_NOT_B(b, src[0], 0);
563 break;
564 case nir_op_ior:
565 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
566 break;
567 case nir_op_ishl:
568 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
569 break;
570 case nir_op_ishr:
571 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
572 break;
573 case nir_op_isub:
574 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
575 break;
576 case nir_op_ixor:
577 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
578 break;
579 case nir_op_ushr:
580 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
581 break;
582 case nir_op_ilt32:
583 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
584 dst[0]->cat2.condition = IR3_COND_LT;
585 dst[0] = ir3_n2b(b, dst[0]);
586 break;
587 case nir_op_ige32:
588 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
589 dst[0]->cat2.condition = IR3_COND_GE;
590 dst[0] = ir3_n2b(b, dst[0]);
591 break;
592 case nir_op_ieq32:
593 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
594 dst[0]->cat2.condition = IR3_COND_EQ;
595 dst[0] = ir3_n2b(b, dst[0]);
596 break;
597 case nir_op_ine32:
598 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
599 dst[0]->cat2.condition = IR3_COND_NE;
600 dst[0] = ir3_n2b(b, dst[0]);
601 break;
602 case nir_op_ult32:
603 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
604 dst[0]->cat2.condition = IR3_COND_LT;
605 dst[0] = ir3_n2b(b, dst[0]);
606 break;
607 case nir_op_uge32:
608 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
609 dst[0]->cat2.condition = IR3_COND_GE;
610 dst[0] = ir3_n2b(b, dst[0]);
611 break;
612
613 case nir_op_b32csel: {
614 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
615 compile_assert(ctx, bs[1] == bs[2]);
616 /* the boolean condition is 32b even if src[1] and src[2] are
617 * half-precision, but sel.b16 wants all three src's to be the
618 * same type.
619 */
620 if (bs[1] < 32)
621 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
622 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
623 break;
624 }
625 case nir_op_bit_count: {
626 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
627 // double check on earlier gen's. Once half-precision support is
628 // in place, this should probably move to a NIR lowering pass:
629 struct ir3_instruction *hi, *lo;
630
631 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
632 TYPE_U32, TYPE_U16);
633 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
634
635 hi = ir3_CBITS_B(b, hi, 0);
636 lo = ir3_CBITS_B(b, lo, 0);
637
638 // TODO maybe the builders should default to making dst half-precision
639 // if the src's were half precision, to make this less awkward.. otoh
640 // we should probably just do this lowering in NIR.
641 hi->regs[0]->flags |= IR3_REG_HALF;
642 lo->regs[0]->flags |= IR3_REG_HALF;
643
644 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
645 dst[0]->regs[0]->flags |= IR3_REG_HALF;
646 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
647 break;
648 }
649 case nir_op_ifind_msb: {
650 struct ir3_instruction *cmp;
651 dst[0] = ir3_CLZ_S(b, src[0], 0);
652 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
653 cmp->cat2.condition = IR3_COND_GE;
654 dst[0] = ir3_SEL_B32(b,
655 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
656 cmp, 0, dst[0], 0);
657 break;
658 }
659 case nir_op_ufind_msb:
660 dst[0] = ir3_CLZ_B(b, src[0], 0);
661 dst[0] = ir3_SEL_B32(b,
662 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
663 src[0], 0, dst[0], 0);
664 break;
665 case nir_op_find_lsb:
666 dst[0] = ir3_BFREV_B(b, src[0], 0);
667 dst[0] = ir3_CLZ_B(b, dst[0], 0);
668 break;
669 case nir_op_bitfield_reverse:
670 dst[0] = ir3_BFREV_B(b, src[0], 0);
671 break;
672
673 default:
674 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
675 nir_op_infos[alu->op].name);
676 break;
677 }
678
679 ir3_put_dst(ctx, &alu->dest.dest);
680 }
681
682 /* handles direct/indirect UBO reads: */
683 static void
684 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
685 struct ir3_instruction **dst)
686 {
687 struct ir3_block *b = ctx->block;
688 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
689 /* UBO addresses are the first driver params, but subtract 2 here to
690 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
691 * is the uniforms: */
692 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
693 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
694 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
695
696 int off = 0;
697
698 /* First src is ubo index, which could either be an immed or not: */
699 src0 = ir3_get_src(ctx, &intr->src[0])[0];
700 if (is_same_type_mov(src0) &&
701 (src0->regs[1]->flags & IR3_REG_IMMED)) {
702 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
703 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
704 } else {
705 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
706 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
707
708 /* NOTE: since relative addressing is used, make sure constlen is
709 * at least big enough to cover all the UBO addresses, since the
710 * assembler won't know what the max address reg is.
711 */
712 ctx->so->constlen = MAX2(ctx->so->constlen,
713 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
714 }
715
716 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
717 addr = base_lo;
718
719 if (nir_src_is_const(intr->src[1])) {
720 off += nir_src_as_uint(intr->src[1]);
721 } else {
722 /* For load_ubo_indirect, second src is indirect offset: */
723 src1 = ir3_get_src(ctx, &intr->src[1])[0];
724
725 /* and add offset to addr: */
726 addr = ir3_ADD_S(b, addr, 0, src1, 0);
727 }
728
729 /* if offset is to large to encode in the ldg, split it out: */
730 if ((off + (intr->num_components * 4)) > 1024) {
731 /* split out the minimal amount to improve the odds that
732 * cp can fit the immediate in the add.s instruction:
733 */
734 unsigned off2 = off + (intr->num_components * 4) - 1024;
735 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
736 off -= off2;
737 }
738
739 if (ptrsz == 2) {
740 struct ir3_instruction *carry;
741
742 /* handle 32b rollover, ie:
743 * if (addr < base_lo)
744 * base_hi++
745 */
746 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
747 carry->cat2.condition = IR3_COND_LT;
748 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
749
750 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
751 }
752
753 for (int i = 0; i < intr->num_components; i++) {
754 struct ir3_instruction *load =
755 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
756 create_immed(b, off + i * 4), 0);
757 load->cat6.type = TYPE_U32;
758 dst[i] = load;
759 }
760 }
761
762 /* src[] = { block_index } */
763 static void
764 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
765 struct ir3_instruction **dst)
766 {
767 /* SSBO size stored as a const starting at ssbo_sizes: */
768 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
769 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
770 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
771 const_state->ssbo_size.off[blk_idx];
772
773 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
774
775 dst[0] = create_uniform(ctx->block, idx);
776 }
777
778 /* src[] = { offset }. const_index[] = { base } */
779 static void
780 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
781 struct ir3_instruction **dst)
782 {
783 struct ir3_block *b = ctx->block;
784 struct ir3_instruction *ldl, *offset;
785 unsigned base;
786
787 offset = ir3_get_src(ctx, &intr->src[0])[0];
788 base = nir_intrinsic_base(intr);
789
790 ldl = ir3_LDL(b, offset, 0,
791 create_immed(b, intr->num_components), 0,
792 create_immed(b, base), 0);
793
794 ldl->cat6.type = utype_dst(intr->dest);
795 ldl->regs[0]->wrmask = MASK(intr->num_components);
796
797 ldl->barrier_class = IR3_BARRIER_SHARED_R;
798 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
799
800 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
801 }
802
803 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
804 static void
805 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
806 {
807 struct ir3_block *b = ctx->block;
808 struct ir3_instruction *stl, *offset;
809 struct ir3_instruction * const *value;
810 unsigned base, wrmask;
811
812 value = ir3_get_src(ctx, &intr->src[0]);
813 offset = ir3_get_src(ctx, &intr->src[1])[0];
814
815 base = nir_intrinsic_base(intr);
816 wrmask = nir_intrinsic_write_mask(intr);
817
818 /* Combine groups of consecutive enabled channels in one write
819 * message. We use ffs to find the first enabled channel and then ffs on
820 * the bit-inverse, down-shifted writemask to determine the length of
821 * the block of enabled bits.
822 *
823 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
824 */
825 while (wrmask) {
826 unsigned first_component = ffs(wrmask) - 1;
827 unsigned length = ffs(~(wrmask >> first_component)) - 1;
828
829 stl = ir3_STL(b, offset, 0,
830 ir3_create_collect(ctx, &value[first_component], length), 0,
831 create_immed(b, length), 0);
832 stl->cat6.dst_offset = first_component + base;
833 stl->cat6.type = utype_src(intr->src[0]);
834 stl->barrier_class = IR3_BARRIER_SHARED_W;
835 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
836
837 array_insert(b, b->keeps, stl);
838
839 /* Clear the bits in the writemask that we just wrote, then try
840 * again to see if more channels are left.
841 */
842 wrmask &= (15 << (first_component + length));
843 }
844 }
845
846 /* src[] = { offset }. const_index[] = { base } */
847 static void
848 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
849 struct ir3_instruction **dst)
850 {
851 struct ir3_block *b = ctx->block;
852 struct ir3_instruction *load, *offset;
853 unsigned base;
854
855 offset = ir3_get_src(ctx, &intr->src[0])[0];
856 base = nir_intrinsic_base(intr);
857
858 load = ir3_LDLW(b, offset, 0,
859 create_immed(b, intr->num_components), 0,
860 create_immed(b, base), 0);
861
862 load->cat6.type = utype_dst(intr->dest);
863 load->regs[0]->wrmask = MASK(intr->num_components);
864
865 load->barrier_class = IR3_BARRIER_SHARED_R;
866 load->barrier_conflict = IR3_BARRIER_SHARED_W;
867
868 ir3_split_dest(b, dst, load, 0, intr->num_components);
869 }
870
871 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
872 static void
873 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
874 {
875 struct ir3_block *b = ctx->block;
876 struct ir3_instruction *store, *offset;
877 struct ir3_instruction * const *value;
878 unsigned base, wrmask;
879
880 value = ir3_get_src(ctx, &intr->src[0]);
881 offset = ir3_get_src(ctx, &intr->src[1])[0];
882
883 base = nir_intrinsic_base(intr);
884 wrmask = nir_intrinsic_write_mask(intr);
885
886 /* Combine groups of consecutive enabled channels in one write
887 * message. We use ffs to find the first enabled channel and then ffs on
888 * the bit-inverse, down-shifted writemask to determine the length of
889 * the block of enabled bits.
890 *
891 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
892 */
893 while (wrmask) {
894 unsigned first_component = ffs(wrmask) - 1;
895 unsigned length = ffs(~(wrmask >> first_component)) - 1;
896
897 store = ir3_STLW(b, offset, 0,
898 ir3_create_collect(ctx, &value[first_component], length), 0,
899 create_immed(b, length), 0);
900
901 store->cat6.dst_offset = first_component + base;
902 store->cat6.type = utype_src(intr->src[0]);
903 store->barrier_class = IR3_BARRIER_SHARED_W;
904 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
905
906 array_insert(b, b->keeps, store);
907
908 /* Clear the bits in the writemask that we just wrote, then try
909 * again to see if more channels are left.
910 */
911 wrmask &= (15 << (first_component + length));
912 }
913 }
914
915 /*
916 * CS shared variable atomic intrinsics
917 *
918 * All of the shared variable atomic memory operations read a value from
919 * memory, compute a new value using one of the operations below, write the
920 * new value to memory, and return the original value read.
921 *
922 * All operations take 2 sources except CompSwap that takes 3. These
923 * sources represent:
924 *
925 * 0: The offset into the shared variable storage region that the atomic
926 * operation will operate on.
927 * 1: The data parameter to the atomic function (i.e. the value to add
928 * in shared_atomic_add, etc).
929 * 2: For CompSwap only: the second data parameter.
930 */
931 static struct ir3_instruction *
932 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
933 {
934 struct ir3_block *b = ctx->block;
935 struct ir3_instruction *atomic, *src0, *src1;
936 type_t type = TYPE_U32;
937
938 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
939 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
940
941 switch (intr->intrinsic) {
942 case nir_intrinsic_shared_atomic_add:
943 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
944 break;
945 case nir_intrinsic_shared_atomic_imin:
946 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
947 type = TYPE_S32;
948 break;
949 case nir_intrinsic_shared_atomic_umin:
950 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
951 break;
952 case nir_intrinsic_shared_atomic_imax:
953 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
954 type = TYPE_S32;
955 break;
956 case nir_intrinsic_shared_atomic_umax:
957 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
958 break;
959 case nir_intrinsic_shared_atomic_and:
960 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
961 break;
962 case nir_intrinsic_shared_atomic_or:
963 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
964 break;
965 case nir_intrinsic_shared_atomic_xor:
966 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
967 break;
968 case nir_intrinsic_shared_atomic_exchange:
969 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
970 break;
971 case nir_intrinsic_shared_atomic_comp_swap:
972 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
973 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
974 ir3_get_src(ctx, &intr->src[2])[0],
975 src1,
976 }, 2);
977 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
978 break;
979 default:
980 unreachable("boo");
981 }
982
983 atomic->cat6.iim_val = 1;
984 atomic->cat6.d = 1;
985 atomic->cat6.type = type;
986 atomic->barrier_class = IR3_BARRIER_SHARED_W;
987 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
988
989 /* even if nothing consume the result, we can't DCE the instruction: */
990 array_insert(b, b->keeps, atomic);
991
992 return atomic;
993 }
994
995 /* TODO handle actual indirect/dynamic case.. which is going to be weird
996 * to handle with the image_mapping table..
997 */
998 static struct ir3_instruction *
999 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1000 {
1001 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
1002 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1003 struct ir3_instruction *texture, *sampler;
1004
1005 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1006 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1007
1008 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1009 sampler,
1010 texture,
1011 }, 2);
1012 }
1013
1014 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1015 static void
1016 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1017 struct ir3_instruction **dst)
1018 {
1019 struct ir3_block *b = ctx->block;
1020 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1021 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1022 struct ir3_instruction *sam;
1023 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1024 struct ir3_instruction *coords[4];
1025 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1026 type_t type = ir3_get_image_type(var);
1027
1028 /* hmm, this seems a bit odd, but it is what blob does and (at least
1029 * a5xx) just faults on bogus addresses otherwise:
1030 */
1031 if (flags & IR3_INSTR_3D) {
1032 flags &= ~IR3_INSTR_3D;
1033 flags |= IR3_INSTR_A;
1034 }
1035
1036 for (unsigned i = 0; i < ncoords; i++)
1037 coords[i] = src0[i];
1038
1039 if (ncoords == 1)
1040 coords[ncoords++] = create_immed(b, 0);
1041
1042 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
1043 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
1044
1045 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1046 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1047
1048 ir3_split_dest(b, dst, sam, 0, 4);
1049 }
1050
1051 static void
1052 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1053 struct ir3_instruction **dst)
1054 {
1055 struct ir3_block *b = ctx->block;
1056 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1057 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1058 struct ir3_instruction *sam, *lod;
1059 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1060
1061 lod = create_immed(b, 0);
1062 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
1063 samp_tex, lod, NULL);
1064
1065 /* Array size actually ends up in .w rather than .z. This doesn't
1066 * matter for miplevel 0, but for higher mips the value in z is
1067 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1068 * returned, which means that we have to add 1 to it for arrays for
1069 * a3xx.
1070 *
1071 * Note use a temporary dst and then copy, since the size of the dst
1072 * array that is passed in is based on nir's understanding of the
1073 * result size, not the hardware's
1074 */
1075 struct ir3_instruction *tmp[4];
1076
1077 ir3_split_dest(b, tmp, sam, 0, 4);
1078
1079 /* get_size instruction returns size in bytes instead of texels
1080 * for imageBuffer, so we need to divide it by the pixel size
1081 * of the image format.
1082 *
1083 * TODO: This is at least true on a5xx. Check other gens.
1084 */
1085 enum glsl_sampler_dim dim =
1086 glsl_get_sampler_dim(glsl_without_array(var->type));
1087 if (dim == GLSL_SAMPLER_DIM_BUF) {
1088 /* Since all the possible values the divisor can take are
1089 * power-of-two (4, 8, or 16), the division is implemented
1090 * as a shift-right.
1091 * During shader setup, the log2 of the image format's
1092 * bytes-per-pixel should have been emitted in 2nd slot of
1093 * image_dims. See ir3_shader::emit_image_dims().
1094 */
1095 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1096 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1097 const_state->image_dims.off[var->data.driver_location];
1098 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1099
1100 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1101 }
1102
1103 for (unsigned i = 0; i < ncoords; i++)
1104 dst[i] = tmp[i];
1105
1106 if (flags & IR3_INSTR_A) {
1107 if (ctx->compiler->levels_add_one) {
1108 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1109 } else {
1110 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1111 }
1112 }
1113 }
1114
1115 static void
1116 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1117 {
1118 struct ir3_block *b = ctx->block;
1119 struct ir3_instruction *barrier;
1120
1121 switch (intr->intrinsic) {
1122 case nir_intrinsic_barrier:
1123 barrier = ir3_BAR(b);
1124 barrier->cat7.g = true;
1125 barrier->cat7.l = true;
1126 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1127 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1128 break;
1129 case nir_intrinsic_memory_barrier:
1130 barrier = ir3_FENCE(b);
1131 barrier->cat7.g = true;
1132 barrier->cat7.r = true;
1133 barrier->cat7.w = true;
1134 barrier->cat7.l = true;
1135 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1136 IR3_BARRIER_BUFFER_W;
1137 barrier->barrier_conflict =
1138 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1139 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1140 break;
1141 case nir_intrinsic_memory_barrier_atomic_counter:
1142 case nir_intrinsic_memory_barrier_buffer:
1143 barrier = ir3_FENCE(b);
1144 barrier->cat7.g = true;
1145 barrier->cat7.r = true;
1146 barrier->cat7.w = true;
1147 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1148 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1149 IR3_BARRIER_BUFFER_W;
1150 break;
1151 case nir_intrinsic_memory_barrier_image:
1152 // TODO double check if this should have .g set
1153 barrier = ir3_FENCE(b);
1154 barrier->cat7.g = true;
1155 barrier->cat7.r = true;
1156 barrier->cat7.w = true;
1157 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1158 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1159 IR3_BARRIER_IMAGE_W;
1160 break;
1161 case nir_intrinsic_memory_barrier_shared:
1162 barrier = ir3_FENCE(b);
1163 barrier->cat7.g = true;
1164 barrier->cat7.l = true;
1165 barrier->cat7.r = true;
1166 barrier->cat7.w = true;
1167 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1168 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1169 IR3_BARRIER_SHARED_W;
1170 break;
1171 case nir_intrinsic_group_memory_barrier:
1172 barrier = ir3_FENCE(b);
1173 barrier->cat7.g = true;
1174 barrier->cat7.l = true;
1175 barrier->cat7.r = true;
1176 barrier->cat7.w = true;
1177 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1178 IR3_BARRIER_IMAGE_W |
1179 IR3_BARRIER_BUFFER_W;
1180 barrier->barrier_conflict =
1181 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1182 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1183 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1184 break;
1185 default:
1186 unreachable("boo");
1187 }
1188
1189 /* make sure barrier doesn't get DCE'd */
1190 array_insert(b, b->keeps, barrier);
1191 }
1192
1193 static void add_sysval_input_compmask(struct ir3_context *ctx,
1194 gl_system_value slot, unsigned compmask,
1195 struct ir3_instruction *instr)
1196 {
1197 struct ir3_shader_variant *so = ctx->so;
1198 unsigned r = regid(so->inputs_count, 0);
1199 unsigned n = so->inputs_count++;
1200
1201 assert(instr->opc == OPC_META_INPUT);
1202 instr->input.sysval = slot;
1203
1204 so->inputs[n].sysval = true;
1205 so->inputs[n].slot = slot;
1206 so->inputs[n].compmask = compmask;
1207 so->inputs[n].regid = r;
1208 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1209 so->total_in++;
1210
1211 ctx->ir->ninputs = MAX2(ctx->ir->ninputs, r + 1);
1212 ctx->ir->inputs[r] = instr;
1213 }
1214
1215 static void add_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1216 struct ir3_instruction *instr)
1217 {
1218 add_sysval_input_compmask(ctx, slot, 0x1, instr);
1219 }
1220
1221 static struct ir3_instruction *
1222 get_barycentric_centroid(struct ir3_context *ctx)
1223 {
1224 if (!ctx->ij_centroid) {
1225 struct ir3_instruction *xy[2];
1226 struct ir3_instruction *ij;
1227
1228 ij = create_input_compmask(ctx, 0, 0x3);
1229 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1230
1231 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1232
1233 add_sysval_input_compmask(ctx,
1234 SYSTEM_VALUE_BARYCENTRIC_CENTROID,
1235 0x3, ij);
1236 }
1237
1238 return ctx->ij_centroid;
1239 }
1240
1241 static struct ir3_instruction *
1242 get_barycentric_sample(struct ir3_context *ctx)
1243 {
1244 if (!ctx->ij_sample) {
1245 struct ir3_instruction *xy[2];
1246 struct ir3_instruction *ij;
1247
1248 ij = create_input_compmask(ctx, 0, 0x3);
1249 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1250
1251 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1252
1253 add_sysval_input_compmask(ctx,
1254 SYSTEM_VALUE_BARYCENTRIC_SAMPLE,
1255 0x3, ij);
1256 }
1257
1258 return ctx->ij_sample;
1259 }
1260
1261 static struct ir3_instruction *
1262 get_barycentric_pixel(struct ir3_context *ctx)
1263 {
1264 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1265 * this to create ij_pixel only on demand:
1266 */
1267 return ctx->ij_pixel;
1268 }
1269
1270 static struct ir3_instruction *
1271 get_frag_coord(struct ir3_context *ctx)
1272 {
1273 if (!ctx->frag_coord) {
1274 struct ir3_block *b = ctx->block;
1275 struct ir3_instruction *xyzw[4];
1276 struct ir3_instruction *hw_frag_coord;
1277
1278 hw_frag_coord = create_input_compmask(ctx, 0, 0xf);
1279 ir3_split_dest(ctx->block, xyzw, hw_frag_coord, 0, 4);
1280
1281 /* for frag_coord.xy, we get unsigned values.. we need
1282 * to subtract (integer) 8 and divide by 16 (right-
1283 * shift by 4) then convert to float:
1284 *
1285 * sub.s tmp, src, 8
1286 * shr.b tmp, tmp, 4
1287 * mov.u32f32 dst, tmp
1288 *
1289 */
1290 for (int i = 0; i < 2; i++) {
1291 xyzw[i] = ir3_SUB_S(b, xyzw[i], 0,
1292 create_immed(b, 8), 0);
1293 xyzw[i] = ir3_SHR_B(b, xyzw[i], 0,
1294 create_immed(b, 4), 0);
1295 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1296 }
1297
1298 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1299
1300 add_sysval_input_compmask(ctx,
1301 SYSTEM_VALUE_FRAG_COORD,
1302 0xf, hw_frag_coord);
1303
1304 ctx->so->frag_coord = true;
1305 }
1306
1307 return ctx->frag_coord;
1308 }
1309
1310 static void
1311 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1312 {
1313 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1314 struct ir3_instruction **dst;
1315 struct ir3_instruction * const *src;
1316 struct ir3_block *b = ctx->block;
1317 int idx, comp;
1318
1319 if (info->has_dest) {
1320 unsigned n = nir_intrinsic_dest_components(intr);
1321 dst = ir3_get_dst(ctx, &intr->dest, n);
1322 } else {
1323 dst = NULL;
1324 }
1325
1326 const unsigned primitive_param = ctx->so->shader->const_state.offsets.primitive_param * 4;
1327 const unsigned primitive_map = ctx->so->shader->const_state.offsets.primitive_map * 4;
1328
1329 switch (intr->intrinsic) {
1330 case nir_intrinsic_load_uniform:
1331 idx = nir_intrinsic_base(intr);
1332 if (nir_src_is_const(intr->src[0])) {
1333 idx += nir_src_as_uint(intr->src[0]);
1334 for (int i = 0; i < intr->num_components; i++) {
1335 dst[i] = create_uniform_typed(b, idx + i,
1336 nir_dest_bit_size(intr->dest) < 32 ? TYPE_F16 : TYPE_F32);
1337 }
1338 } else {
1339 src = ir3_get_src(ctx, &intr->src[0]);
1340 for (int i = 0; i < intr->num_components; i++) {
1341 dst[i] = create_uniform_indirect(b, idx + i,
1342 ir3_get_addr(ctx, src[0], 1));
1343 }
1344 /* NOTE: if relative addressing is used, we set
1345 * constlen in the compiler (to worst-case value)
1346 * since we don't know in the assembler what the max
1347 * addr reg value can be:
1348 */
1349 ctx->so->constlen = MAX2(ctx->so->constlen,
1350 ctx->so->shader->ubo_state.size / 16);
1351 }
1352 break;
1353
1354 case nir_intrinsic_load_vs_primitive_stride_ir3:
1355 dst[0] = create_uniform(b, primitive_param + 0);
1356 break;
1357 case nir_intrinsic_load_vs_vertex_stride_ir3:
1358 dst[0] = create_uniform(b, primitive_param + 1);
1359 break;
1360 case nir_intrinsic_load_primitive_location_ir3:
1361 idx = nir_intrinsic_driver_location(intr);
1362 dst[0] = create_uniform(b, primitive_map + idx);
1363 break;
1364
1365 case nir_intrinsic_load_gs_header_ir3:
1366 dst[0] = ctx->gs_header;
1367 break;
1368
1369 case nir_intrinsic_load_primitive_id:
1370 dst[0] = ctx->primitive_id;
1371 break;
1372
1373 case nir_intrinsic_load_ubo:
1374 emit_intrinsic_load_ubo(ctx, intr, dst);
1375 break;
1376 case nir_intrinsic_load_frag_coord:
1377 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1378 break;
1379 case nir_intrinsic_load_sample_pos_from_id: {
1380 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1381 * but that doesn't seem necessary.
1382 */
1383 struct ir3_instruction *offset =
1384 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1385 offset->regs[0]->wrmask = 0x3;
1386 offset->cat5.type = TYPE_F32;
1387
1388 ir3_split_dest(b, dst, offset, 0, 2);
1389
1390 break;
1391 }
1392 case nir_intrinsic_load_size_ir3:
1393 if (!ctx->ij_size) {
1394 ctx->ij_size = create_input(ctx, 0);
1395
1396 add_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SIZE,
1397 ctx->ij_size);
1398 }
1399 dst[0] = ctx->ij_size;
1400 break;
1401 case nir_intrinsic_load_barycentric_centroid:
1402 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1403 break;
1404 case nir_intrinsic_load_barycentric_sample:
1405 if (ctx->so->key.msaa) {
1406 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1407 } else {
1408 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1409 }
1410 break;
1411 case nir_intrinsic_load_barycentric_pixel:
1412 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1413 break;
1414 case nir_intrinsic_load_interpolated_input:
1415 idx = nir_intrinsic_base(intr);
1416 comp = nir_intrinsic_component(intr);
1417 src = ir3_get_src(ctx, &intr->src[0]);
1418 if (nir_src_is_const(intr->src[1])) {
1419 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1420 idx += nir_src_as_uint(intr->src[1]);
1421 for (int i = 0; i < intr->num_components; i++) {
1422 unsigned inloc = idx * 4 + i + comp;
1423 if (ctx->so->inputs[idx].bary &&
1424 !ctx->so->inputs[idx].use_ldlv) {
1425 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1426 } else {
1427 /* for non-varyings use the pre-setup input, since
1428 * that is easier than mapping things back to a
1429 * nir_variable to figure out what it is.
1430 */
1431 dst[i] = ctx->ir->inputs[inloc];
1432 }
1433 }
1434 } else {
1435 ir3_context_error(ctx, "unhandled");
1436 }
1437 break;
1438 case nir_intrinsic_load_input:
1439 idx = nir_intrinsic_base(intr);
1440 comp = nir_intrinsic_component(intr);
1441 if (nir_src_is_const(intr->src[0])) {
1442 idx += nir_src_as_uint(intr->src[0]);
1443 for (int i = 0; i < intr->num_components; i++) {
1444 unsigned n = idx * 4 + i + comp;
1445 dst[i] = ctx->ir->inputs[n];
1446 compile_assert(ctx, ctx->ir->inputs[n]);
1447 }
1448 } else {
1449 src = ir3_get_src(ctx, &intr->src[0]);
1450 struct ir3_instruction *collect =
1451 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ir->ninputs);
1452 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1453 for (int i = 0; i < intr->num_components; i++) {
1454 unsigned n = idx * 4 + i + comp;
1455 dst[i] = create_indirect_load(ctx, ctx->ir->ninputs,
1456 n, addr, collect);
1457 }
1458 }
1459 break;
1460 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1461 * pass and replaced by an ir3-specifc version that adds the
1462 * dword-offset in the last source.
1463 */
1464 case nir_intrinsic_load_ssbo_ir3:
1465 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1466 break;
1467 case nir_intrinsic_store_ssbo_ir3:
1468 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1469 !ctx->s->info.fs.early_fragment_tests)
1470 ctx->so->no_earlyz = true;
1471 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1472 break;
1473 case nir_intrinsic_get_buffer_size:
1474 emit_intrinsic_ssbo_size(ctx, intr, dst);
1475 break;
1476 case nir_intrinsic_ssbo_atomic_add_ir3:
1477 case nir_intrinsic_ssbo_atomic_imin_ir3:
1478 case nir_intrinsic_ssbo_atomic_umin_ir3:
1479 case nir_intrinsic_ssbo_atomic_imax_ir3:
1480 case nir_intrinsic_ssbo_atomic_umax_ir3:
1481 case nir_intrinsic_ssbo_atomic_and_ir3:
1482 case nir_intrinsic_ssbo_atomic_or_ir3:
1483 case nir_intrinsic_ssbo_atomic_xor_ir3:
1484 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1485 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1486 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1487 !ctx->s->info.fs.early_fragment_tests)
1488 ctx->so->no_earlyz = true;
1489 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1490 break;
1491 case nir_intrinsic_load_shared:
1492 emit_intrinsic_load_shared(ctx, intr, dst);
1493 break;
1494 case nir_intrinsic_store_shared:
1495 emit_intrinsic_store_shared(ctx, intr);
1496 break;
1497 case nir_intrinsic_shared_atomic_add:
1498 case nir_intrinsic_shared_atomic_imin:
1499 case nir_intrinsic_shared_atomic_umin:
1500 case nir_intrinsic_shared_atomic_imax:
1501 case nir_intrinsic_shared_atomic_umax:
1502 case nir_intrinsic_shared_atomic_and:
1503 case nir_intrinsic_shared_atomic_or:
1504 case nir_intrinsic_shared_atomic_xor:
1505 case nir_intrinsic_shared_atomic_exchange:
1506 case nir_intrinsic_shared_atomic_comp_swap:
1507 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1508 break;
1509 case nir_intrinsic_image_deref_load:
1510 emit_intrinsic_load_image(ctx, intr, dst);
1511 break;
1512 case nir_intrinsic_image_deref_store:
1513 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1514 !ctx->s->info.fs.early_fragment_tests)
1515 ctx->so->no_earlyz = true;
1516 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1517 break;
1518 case nir_intrinsic_image_deref_size:
1519 emit_intrinsic_image_size(ctx, intr, dst);
1520 break;
1521 case nir_intrinsic_image_deref_atomic_add:
1522 case nir_intrinsic_image_deref_atomic_imin:
1523 case nir_intrinsic_image_deref_atomic_umin:
1524 case nir_intrinsic_image_deref_atomic_imax:
1525 case nir_intrinsic_image_deref_atomic_umax:
1526 case nir_intrinsic_image_deref_atomic_and:
1527 case nir_intrinsic_image_deref_atomic_or:
1528 case nir_intrinsic_image_deref_atomic_xor:
1529 case nir_intrinsic_image_deref_atomic_exchange:
1530 case nir_intrinsic_image_deref_atomic_comp_swap:
1531 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1532 !ctx->s->info.fs.early_fragment_tests)
1533 ctx->so->no_earlyz = true;
1534 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1535 break;
1536 case nir_intrinsic_barrier:
1537 case nir_intrinsic_memory_barrier:
1538 case nir_intrinsic_group_memory_barrier:
1539 case nir_intrinsic_memory_barrier_atomic_counter:
1540 case nir_intrinsic_memory_barrier_buffer:
1541 case nir_intrinsic_memory_barrier_image:
1542 case nir_intrinsic_memory_barrier_shared:
1543 emit_intrinsic_barrier(ctx, intr);
1544 /* note that blk ptr no longer valid, make that obvious: */
1545 b = NULL;
1546 break;
1547 case nir_intrinsic_store_output:
1548 idx = nir_intrinsic_base(intr);
1549 comp = nir_intrinsic_component(intr);
1550 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1551 idx += nir_src_as_uint(intr->src[1]);
1552
1553 src = ir3_get_src(ctx, &intr->src[0]);
1554 for (int i = 0; i < intr->num_components; i++) {
1555 unsigned n = idx * 4 + i + comp;
1556 ctx->ir->outputs[n] = src[i];
1557 }
1558 break;
1559 case nir_intrinsic_load_base_vertex:
1560 case nir_intrinsic_load_first_vertex:
1561 if (!ctx->basevertex) {
1562 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1563 add_sysval_input(ctx, SYSTEM_VALUE_FIRST_VERTEX, ctx->basevertex);
1564 }
1565 dst[0] = ctx->basevertex;
1566 break;
1567 case nir_intrinsic_load_vertex_id_zero_base:
1568 case nir_intrinsic_load_vertex_id:
1569 if (!ctx->vertex_id) {
1570 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1571 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1572 ctx->vertex_id = create_input(ctx, 0);
1573 add_sysval_input(ctx, sv, ctx->vertex_id);
1574 }
1575 dst[0] = ctx->vertex_id;
1576 break;
1577 case nir_intrinsic_load_instance_id:
1578 if (!ctx->instance_id) {
1579 ctx->instance_id = create_input(ctx, 0);
1580 add_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID,
1581 ctx->instance_id);
1582 }
1583 dst[0] = ctx->instance_id;
1584 break;
1585 case nir_intrinsic_load_sample_id:
1586 ctx->so->per_samp = true;
1587 /* fall-thru */
1588 case nir_intrinsic_load_sample_id_no_per_sample:
1589 if (!ctx->samp_id) {
1590 ctx->samp_id = create_input(ctx, 0);
1591 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1592 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID,
1593 ctx->samp_id);
1594 }
1595 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1596 break;
1597 case nir_intrinsic_load_sample_mask_in:
1598 if (!ctx->samp_mask_in) {
1599 ctx->samp_mask_in = create_input(ctx, 0);
1600 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN,
1601 ctx->samp_mask_in);
1602 }
1603 dst[0] = ctx->samp_mask_in;
1604 break;
1605 case nir_intrinsic_load_user_clip_plane:
1606 idx = nir_intrinsic_ucp_id(intr);
1607 for (int i = 0; i < intr->num_components; i++) {
1608 unsigned n = idx * 4 + i;
1609 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1610 }
1611 break;
1612 case nir_intrinsic_load_front_face:
1613 if (!ctx->frag_face) {
1614 ctx->so->frag_face = true;
1615 ctx->frag_face = create_input(ctx, 0);
1616 add_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, ctx->frag_face);
1617 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1618 }
1619 /* for fragface, we get -1 for back and 0 for front. However this is
1620 * the inverse of what nir expects (where ~0 is true).
1621 */
1622 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1623 dst[0] = ir3_NOT_B(b, dst[0], 0);
1624 break;
1625 case nir_intrinsic_load_local_invocation_id:
1626 if (!ctx->local_invocation_id) {
1627 ctx->local_invocation_id = create_input_compmask(ctx, 0, 0x7);
1628 add_sysval_input_compmask(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID,
1629 0x7, ctx->local_invocation_id);
1630 }
1631 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1632 break;
1633 case nir_intrinsic_load_work_group_id:
1634 if (!ctx->work_group_id) {
1635 ctx->work_group_id = create_input_compmask(ctx, 0, 0x7);
1636 add_sysval_input_compmask(ctx, SYSTEM_VALUE_WORK_GROUP_ID,
1637 0x7, ctx->work_group_id);
1638 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1639 }
1640 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1641 break;
1642 case nir_intrinsic_load_num_work_groups:
1643 for (int i = 0; i < intr->num_components; i++) {
1644 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1645 }
1646 break;
1647 case nir_intrinsic_load_local_group_size:
1648 for (int i = 0; i < intr->num_components; i++) {
1649 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1650 }
1651 break;
1652 case nir_intrinsic_discard_if:
1653 case nir_intrinsic_discard: {
1654 struct ir3_instruction *cond, *kill;
1655
1656 if (intr->intrinsic == nir_intrinsic_discard_if) {
1657 /* conditional discard: */
1658 src = ir3_get_src(ctx, &intr->src[0]);
1659 cond = ir3_b2n(b, src[0]);
1660 } else {
1661 /* unconditional discard: */
1662 cond = create_immed(b, 1);
1663 }
1664
1665 /* NOTE: only cmps.*.* can write p0.x: */
1666 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1667 cond->cat2.condition = IR3_COND_NE;
1668
1669 /* condition always goes in predicate register: */
1670 cond->regs[0]->num = regid(REG_P0, 0);
1671
1672 kill = ir3_KILL(b, cond, 0);
1673 array_insert(ctx->ir, ctx->ir->predicates, kill);
1674
1675 array_insert(b, b->keeps, kill);
1676 ctx->so->no_earlyz = true;
1677
1678 break;
1679 }
1680 case nir_intrinsic_load_shared_ir3:
1681 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1682 break;
1683 case nir_intrinsic_store_shared_ir3:
1684 emit_intrinsic_store_shared_ir3(ctx, intr);
1685 break;
1686 default:
1687 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1688 nir_intrinsic_infos[intr->intrinsic].name);
1689 break;
1690 }
1691
1692 if (info->has_dest)
1693 ir3_put_dst(ctx, &intr->dest);
1694 }
1695
1696 static void
1697 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1698 {
1699 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1700 instr->def.num_components);
1701
1702 if (instr->def.bit_size < 32) {
1703 for (int i = 0; i < instr->def.num_components; i++)
1704 dst[i] = create_immed_typed(ctx->block,
1705 instr->value[i].u16,
1706 TYPE_U16);
1707 } else {
1708 for (int i = 0; i < instr->def.num_components; i++)
1709 dst[i] = create_immed_typed(ctx->block,
1710 instr->value[i].u32,
1711 TYPE_U32);
1712 }
1713
1714 }
1715
1716 static void
1717 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1718 {
1719 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1720 undef->def.num_components);
1721 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1722
1723 /* backend doesn't want undefined instructions, so just plug
1724 * in 0.0..
1725 */
1726 for (int i = 0; i < undef->def.num_components; i++)
1727 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1728 }
1729
1730 /*
1731 * texture fetch/sample instructions:
1732 */
1733
1734 static void
1735 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1736 {
1737 unsigned coords, flags = 0;
1738
1739 /* note: would use tex->coord_components.. except txs.. also,
1740 * since array index goes after shadow ref, we don't want to
1741 * count it:
1742 */
1743 switch (tex->sampler_dim) {
1744 case GLSL_SAMPLER_DIM_1D:
1745 case GLSL_SAMPLER_DIM_BUF:
1746 coords = 1;
1747 break;
1748 case GLSL_SAMPLER_DIM_2D:
1749 case GLSL_SAMPLER_DIM_RECT:
1750 case GLSL_SAMPLER_DIM_EXTERNAL:
1751 case GLSL_SAMPLER_DIM_MS:
1752 coords = 2;
1753 break;
1754 case GLSL_SAMPLER_DIM_3D:
1755 case GLSL_SAMPLER_DIM_CUBE:
1756 coords = 3;
1757 flags |= IR3_INSTR_3D;
1758 break;
1759 default:
1760 unreachable("bad sampler_dim");
1761 }
1762
1763 if (tex->is_shadow && tex->op != nir_texop_lod)
1764 flags |= IR3_INSTR_S;
1765
1766 if (tex->is_array && tex->op != nir_texop_lod)
1767 flags |= IR3_INSTR_A;
1768
1769 *flagsp = flags;
1770 *coordsp = coords;
1771 }
1772
1773 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1774 * or immediate (in which case it will get lowered later to a non .s2en
1775 * version of the tex instruction which encode tex/samp as immediates:
1776 */
1777 static struct ir3_instruction *
1778 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1779 {
1780 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1781 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1782 struct ir3_instruction *texture, *sampler;
1783
1784 if (texture_idx >= 0) {
1785 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1786 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1787 } else {
1788 /* TODO what to do for dynamic case? I guess we only need the
1789 * max index for astc srgb workaround so maybe not a problem
1790 * to worry about if we don't enable indirect samplers for
1791 * a4xx?
1792 */
1793 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1794 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1795 }
1796
1797 if (sampler_idx >= 0) {
1798 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1799 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1800 } else {
1801 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1802 }
1803
1804 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1805 sampler,
1806 texture,
1807 }, 2);
1808 }
1809
1810 static void
1811 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1812 {
1813 struct ir3_block *b = ctx->block;
1814 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1815 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1816 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1817 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1818 unsigned i, coords, flags, ncomp;
1819 unsigned nsrc0 = 0, nsrc1 = 0;
1820 type_t type;
1821 opc_t opc = 0;
1822
1823 ncomp = nir_dest_num_components(tex->dest);
1824
1825 coord = off = ddx = ddy = NULL;
1826 lod = proj = compare = sample_index = NULL;
1827
1828 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1829
1830 for (unsigned i = 0; i < tex->num_srcs; i++) {
1831 switch (tex->src[i].src_type) {
1832 case nir_tex_src_coord:
1833 coord = ir3_get_src(ctx, &tex->src[i].src);
1834 break;
1835 case nir_tex_src_bias:
1836 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1837 has_bias = true;
1838 break;
1839 case nir_tex_src_lod:
1840 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1841 has_lod = true;
1842 break;
1843 case nir_tex_src_comparator: /* shadow comparator */
1844 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1845 break;
1846 case nir_tex_src_projector:
1847 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1848 has_proj = true;
1849 break;
1850 case nir_tex_src_offset:
1851 off = ir3_get_src(ctx, &tex->src[i].src);
1852 has_off = true;
1853 break;
1854 case nir_tex_src_ddx:
1855 ddx = ir3_get_src(ctx, &tex->src[i].src);
1856 break;
1857 case nir_tex_src_ddy:
1858 ddy = ir3_get_src(ctx, &tex->src[i].src);
1859 break;
1860 case nir_tex_src_ms_index:
1861 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
1862 break;
1863 case nir_tex_src_texture_offset:
1864 case nir_tex_src_sampler_offset:
1865 /* handled in get_tex_samp_src() */
1866 break;
1867 default:
1868 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
1869 tex->src[i].src_type);
1870 return;
1871 }
1872 }
1873
1874 switch (tex->op) {
1875 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
1876 case nir_texop_txb: opc = OPC_SAMB; break;
1877 case nir_texop_txl: opc = OPC_SAML; break;
1878 case nir_texop_txd: opc = OPC_SAMGQ; break;
1879 case nir_texop_txf: opc = OPC_ISAML; break;
1880 case nir_texop_lod: opc = OPC_GETLOD; break;
1881 case nir_texop_tg4:
1882 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1883 * what blob does, seems gather is broken?), and a3xx did
1884 * not support it (but probably could also emulate).
1885 */
1886 switch (tex->component) {
1887 case 0: opc = OPC_GATHER4R; break;
1888 case 1: opc = OPC_GATHER4G; break;
1889 case 2: opc = OPC_GATHER4B; break;
1890 case 3: opc = OPC_GATHER4A; break;
1891 }
1892 break;
1893 case nir_texop_txf_ms_fb:
1894 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
1895 default:
1896 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
1897 return;
1898 }
1899
1900 tex_info(tex, &flags, &coords);
1901
1902 /*
1903 * lay out the first argument in the proper order:
1904 * - actual coordinates first
1905 * - shadow reference
1906 * - array index
1907 * - projection w
1908 * - starting at offset 4, dpdx.xy, dpdy.xy
1909 *
1910 * bias/lod go into the second arg
1911 */
1912
1913 /* insert tex coords: */
1914 for (i = 0; i < coords; i++)
1915 src0[i] = coord[i];
1916
1917 nsrc0 = i;
1918
1919 /* scale up integer coords for TXF based on the LOD */
1920 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
1921 assert(has_lod);
1922 for (i = 0; i < coords; i++)
1923 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
1924 }
1925
1926 if (coords == 1) {
1927 /* hw doesn't do 1d, so we treat it as 2d with
1928 * height of 1, and patch up the y coord.
1929 */
1930 if (is_isam(opc)) {
1931 src0[nsrc0++] = create_immed(b, 0);
1932 } else {
1933 src0[nsrc0++] = create_immed(b, fui(0.5));
1934 }
1935 }
1936
1937 if (tex->is_shadow && tex->op != nir_texop_lod)
1938 src0[nsrc0++] = compare;
1939
1940 if (tex->is_array && tex->op != nir_texop_lod) {
1941 struct ir3_instruction *idx = coord[coords];
1942
1943 /* the array coord for cube arrays needs 0.5 added to it */
1944 if (ctx->compiler->array_index_add_half && !is_isam(opc))
1945 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
1946
1947 src0[nsrc0++] = idx;
1948 }
1949
1950 if (has_proj) {
1951 src0[nsrc0++] = proj;
1952 flags |= IR3_INSTR_P;
1953 }
1954
1955 /* pad to 4, then ddx/ddy: */
1956 if (tex->op == nir_texop_txd) {
1957 while (nsrc0 < 4)
1958 src0[nsrc0++] = create_immed(b, fui(0.0));
1959 for (i = 0; i < coords; i++)
1960 src0[nsrc0++] = ddx[i];
1961 if (coords < 2)
1962 src0[nsrc0++] = create_immed(b, fui(0.0));
1963 for (i = 0; i < coords; i++)
1964 src0[nsrc0++] = ddy[i];
1965 if (coords < 2)
1966 src0[nsrc0++] = create_immed(b, fui(0.0));
1967 }
1968
1969 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
1970 * with scaled x coord according to requested sample:
1971 */
1972 if (opc == OPC_ISAMM) {
1973 if (ctx->compiler->txf_ms_with_isaml) {
1974 /* the samples are laid out in x dimension as
1975 * 0 1 2 3
1976 * x_ms = (x << ms) + sample_index;
1977 */
1978 struct ir3_instruction *ms;
1979 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
1980
1981 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
1982 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
1983
1984 opc = OPC_ISAML;
1985 } else {
1986 src0[nsrc0++] = sample_index;
1987 }
1988 }
1989
1990 /*
1991 * second argument (if applicable):
1992 * - offsets
1993 * - lod
1994 * - bias
1995 */
1996 if (has_off | has_lod | has_bias) {
1997 if (has_off) {
1998 unsigned off_coords = coords;
1999 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2000 off_coords--;
2001 for (i = 0; i < off_coords; i++)
2002 src1[nsrc1++] = off[i];
2003 if (off_coords < 2)
2004 src1[nsrc1++] = create_immed(b, fui(0.0));
2005 flags |= IR3_INSTR_O;
2006 }
2007
2008 if (has_lod | has_bias)
2009 src1[nsrc1++] = lod;
2010 }
2011
2012 switch (tex->dest_type) {
2013 case nir_type_invalid:
2014 case nir_type_float:
2015 type = TYPE_F32;
2016 break;
2017 case nir_type_int:
2018 type = TYPE_S32;
2019 break;
2020 case nir_type_uint:
2021 case nir_type_bool:
2022 type = TYPE_U32;
2023 break;
2024 default:
2025 unreachable("bad dest_type");
2026 }
2027
2028 if (opc == OPC_GETLOD)
2029 type = TYPE_S32;
2030
2031 struct ir3_instruction *samp_tex;
2032
2033 if (tex->op == nir_texop_txf_ms_fb) {
2034 /* only expect a single txf_ms_fb per shader: */
2035 compile_assert(ctx, !ctx->so->fb_read);
2036 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2037
2038 ctx->so->fb_read = true;
2039 samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2040 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2041 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2042 }, 2);
2043
2044 ctx->so->num_samp++;
2045 } else {
2046 samp_tex = get_tex_samp_tex_src(ctx, tex);
2047 }
2048
2049 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2050 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2051
2052 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
2053 samp_tex, col0, col1);
2054
2055 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2056 /* only need first 3 components: */
2057 sam->regs[0]->wrmask = 0x7;
2058 ir3_split_dest(b, dst, sam, 0, 3);
2059
2060 /* we need to sample the alpha separately with a non-ASTC
2061 * texture state:
2062 */
2063 sam = ir3_SAM(b, opc, type, 0b1000, flags,
2064 samp_tex, col0, col1);
2065
2066 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2067
2068 /* fixup .w component: */
2069 ir3_split_dest(b, &dst[3], sam, 3, 1);
2070 } else {
2071 /* normal (non-workaround) case: */
2072 ir3_split_dest(b, dst, sam, 0, ncomp);
2073 }
2074
2075 /* GETLOD returns results in 4.8 fixed point */
2076 if (opc == OPC_GETLOD) {
2077 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2078
2079 compile_assert(ctx, tex->dest_type == nir_type_float);
2080 for (i = 0; i < 2; i++) {
2081 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2082 factor, 0);
2083 }
2084 }
2085
2086 ir3_put_dst(ctx, &tex->dest);
2087 }
2088
2089 static void
2090 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2091 {
2092 struct ir3_block *b = ctx->block;
2093 struct ir3_instruction **dst, *sam;
2094
2095 dst = ir3_get_dst(ctx, &tex->dest, 1);
2096
2097 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, 1 << idx, 0,
2098 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
2099
2100 /* even though there is only one component, since it ends
2101 * up in .y/.z/.w rather than .x, we need a split_dest()
2102 */
2103 if (idx)
2104 ir3_split_dest(b, dst, sam, 0, idx + 1);
2105
2106 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2107 * the value in TEX_CONST_0 is zero-based.
2108 */
2109 if (ctx->compiler->levels_add_one)
2110 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2111
2112 ir3_put_dst(ctx, &tex->dest);
2113 }
2114
2115 static void
2116 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2117 {
2118 struct ir3_block *b = ctx->block;
2119 struct ir3_instruction **dst, *sam;
2120 struct ir3_instruction *lod;
2121 unsigned flags, coords;
2122
2123 tex_info(tex, &flags, &coords);
2124
2125 /* Actually we want the number of dimensions, not coordinates. This
2126 * distinction only matters for cubes.
2127 */
2128 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2129 coords = 2;
2130
2131 dst = ir3_get_dst(ctx, &tex->dest, 4);
2132
2133 compile_assert(ctx, tex->num_srcs == 1);
2134 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2135
2136 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2137
2138 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
2139 get_tex_samp_tex_src(ctx, tex), lod, NULL);
2140
2141 ir3_split_dest(b, dst, sam, 0, 4);
2142
2143 /* Array size actually ends up in .w rather than .z. This doesn't
2144 * matter for miplevel 0, but for higher mips the value in z is
2145 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2146 * returned, which means that we have to add 1 to it for arrays.
2147 */
2148 if (tex->is_array) {
2149 if (ctx->compiler->levels_add_one) {
2150 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2151 } else {
2152 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2153 }
2154 }
2155
2156 ir3_put_dst(ctx, &tex->dest);
2157 }
2158
2159 static void
2160 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2161 {
2162 switch (jump->type) {
2163 case nir_jump_break:
2164 case nir_jump_continue:
2165 case nir_jump_return:
2166 /* I *think* we can simply just ignore this, and use the
2167 * successor block link to figure out where we need to
2168 * jump to for break/continue
2169 */
2170 break;
2171 default:
2172 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2173 break;
2174 }
2175 }
2176
2177 static void
2178 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2179 {
2180 switch (instr->type) {
2181 case nir_instr_type_alu:
2182 emit_alu(ctx, nir_instr_as_alu(instr));
2183 break;
2184 case nir_instr_type_deref:
2185 /* ignored, handled as part of the intrinsic they are src to */
2186 break;
2187 case nir_instr_type_intrinsic:
2188 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2189 break;
2190 case nir_instr_type_load_const:
2191 emit_load_const(ctx, nir_instr_as_load_const(instr));
2192 break;
2193 case nir_instr_type_ssa_undef:
2194 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2195 break;
2196 case nir_instr_type_tex: {
2197 nir_tex_instr *tex = nir_instr_as_tex(instr);
2198 /* couple tex instructions get special-cased:
2199 */
2200 switch (tex->op) {
2201 case nir_texop_txs:
2202 emit_tex_txs(ctx, tex);
2203 break;
2204 case nir_texop_query_levels:
2205 emit_tex_info(ctx, tex, 2);
2206 break;
2207 case nir_texop_texture_samples:
2208 emit_tex_info(ctx, tex, 3);
2209 break;
2210 default:
2211 emit_tex(ctx, tex);
2212 break;
2213 }
2214 break;
2215 }
2216 case nir_instr_type_jump:
2217 emit_jump(ctx, nir_instr_as_jump(instr));
2218 break;
2219 case nir_instr_type_phi:
2220 /* we have converted phi webs to regs in NIR by now */
2221 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2222 break;
2223 case nir_instr_type_call:
2224 case nir_instr_type_parallel_copy:
2225 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2226 break;
2227 }
2228 }
2229
2230 static struct ir3_block *
2231 get_block(struct ir3_context *ctx, const nir_block *nblock)
2232 {
2233 struct ir3_block *block;
2234 struct hash_entry *hentry;
2235
2236 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2237 if (hentry)
2238 return hentry->data;
2239
2240 block = ir3_block_create(ctx->ir);
2241 block->nblock = nblock;
2242 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2243
2244 block->predecessors = _mesa_pointer_set_create(block);
2245 set_foreach(nblock->predecessors, sentry) {
2246 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2247 }
2248
2249 return block;
2250 }
2251
2252 static void
2253 emit_block(struct ir3_context *ctx, nir_block *nblock)
2254 {
2255 struct ir3_block *block = get_block(ctx, nblock);
2256
2257 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2258 if (nblock->successors[i]) {
2259 block->successors[i] =
2260 get_block(ctx, nblock->successors[i]);
2261 }
2262 }
2263
2264 ctx->block = block;
2265 list_addtail(&block->node, &ctx->ir->block_list);
2266
2267 /* re-emit addr register in each block if needed: */
2268 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2269 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2270 ctx->addr_ht[i] = NULL;
2271 }
2272
2273 nir_foreach_instr(instr, nblock) {
2274 ctx->cur_instr = instr;
2275 emit_instr(ctx, instr);
2276 ctx->cur_instr = NULL;
2277 if (ctx->error)
2278 return;
2279 }
2280 }
2281
2282 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2283
2284 static void
2285 emit_if(struct ir3_context *ctx, nir_if *nif)
2286 {
2287 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2288
2289 ctx->block->condition =
2290 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2291
2292 emit_cf_list(ctx, &nif->then_list);
2293 emit_cf_list(ctx, &nif->else_list);
2294 }
2295
2296 static void
2297 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2298 {
2299 emit_cf_list(ctx, &nloop->body);
2300 ctx->so->loops++;
2301 }
2302
2303 static void
2304 stack_push(struct ir3_context *ctx)
2305 {
2306 ctx->stack++;
2307 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2308 }
2309
2310 static void
2311 stack_pop(struct ir3_context *ctx)
2312 {
2313 compile_assert(ctx, ctx->stack > 0);
2314 ctx->stack--;
2315 }
2316
2317 static void
2318 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2319 {
2320 foreach_list_typed(nir_cf_node, node, node, list) {
2321 switch (node->type) {
2322 case nir_cf_node_block:
2323 emit_block(ctx, nir_cf_node_as_block(node));
2324 break;
2325 case nir_cf_node_if:
2326 stack_push(ctx);
2327 emit_if(ctx, nir_cf_node_as_if(node));
2328 stack_pop(ctx);
2329 break;
2330 case nir_cf_node_loop:
2331 stack_push(ctx);
2332 emit_loop(ctx, nir_cf_node_as_loop(node));
2333 stack_pop(ctx);
2334 break;
2335 case nir_cf_node_function:
2336 ir3_context_error(ctx, "TODO\n");
2337 break;
2338 }
2339 }
2340 }
2341
2342 /* emit stream-out code. At this point, the current block is the original
2343 * (nir) end block, and nir ensures that all flow control paths terminate
2344 * into the end block. We re-purpose the original end block to generate
2345 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2346 * block holding stream-out write instructions, followed by the new end
2347 * block:
2348 *
2349 * blockOrigEnd {
2350 * p0.x = (vtxcnt < maxvtxcnt)
2351 * // succs: blockStreamOut, blockNewEnd
2352 * }
2353 * blockStreamOut {
2354 * ... stream-out instructions ...
2355 * // succs: blockNewEnd
2356 * }
2357 * blockNewEnd {
2358 * }
2359 */
2360 static void
2361 emit_stream_out(struct ir3_context *ctx)
2362 {
2363 struct ir3 *ir = ctx->ir;
2364 struct ir3_stream_output_info *strmout =
2365 &ctx->so->shader->stream_output;
2366 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2367 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2368 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2369
2370 /* create vtxcnt input in input block at top of shader,
2371 * so that it is seen as live over the entire duration
2372 * of the shader:
2373 */
2374 vtxcnt = create_input(ctx, 0);
2375 add_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, vtxcnt);
2376
2377 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2378
2379 /* at this point, we are at the original 'end' block,
2380 * re-purpose this block to stream-out condition, then
2381 * append stream-out block and new-end block
2382 */
2383 orig_end_block = ctx->block;
2384
2385 // TODO these blocks need to update predecessors..
2386 // maybe w/ store_global intrinsic, we could do this
2387 // stuff in nir->nir pass
2388
2389 stream_out_block = ir3_block_create(ir);
2390 list_addtail(&stream_out_block->node, &ir->block_list);
2391
2392 new_end_block = ir3_block_create(ir);
2393 list_addtail(&new_end_block->node, &ir->block_list);
2394
2395 orig_end_block->successors[0] = stream_out_block;
2396 orig_end_block->successors[1] = new_end_block;
2397 stream_out_block->successors[0] = new_end_block;
2398
2399 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2400 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2401 cond->regs[0]->num = regid(REG_P0, 0);
2402 cond->cat2.condition = IR3_COND_LT;
2403
2404 /* condition goes on previous block to the conditional,
2405 * since it is used to pick which of the two successor
2406 * paths to take:
2407 */
2408 orig_end_block->condition = cond;
2409
2410 /* switch to stream_out_block to generate the stream-out
2411 * instructions:
2412 */
2413 ctx->block = stream_out_block;
2414
2415 /* Calculate base addresses based on vtxcnt. Instructions
2416 * generated for bases not used in following loop will be
2417 * stripped out in the backend.
2418 */
2419 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2420 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2421 unsigned stride = strmout->stride[i];
2422 struct ir3_instruction *base, *off;
2423
2424 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2425
2426 /* 24-bit should be enough: */
2427 off = ir3_MUL_U(ctx->block, vtxcnt, 0,
2428 create_immed(ctx->block, stride * 4), 0);
2429
2430 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2431 }
2432
2433 /* Generate the per-output store instructions: */
2434 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2435 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2436 unsigned c = j + strmout->output[i].start_component;
2437 struct ir3_instruction *base, *out, *stg;
2438
2439 base = bases[strmout->output[i].output_buffer];
2440 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2441
2442 stg = ir3_STG(ctx->block, base, 0, out, 0,
2443 create_immed(ctx->block, 1), 0);
2444 stg->cat6.type = TYPE_U32;
2445 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2446
2447 array_insert(ctx->block, ctx->block->keeps, stg);
2448 }
2449 }
2450
2451 /* and finally switch to the new_end_block: */
2452 ctx->block = new_end_block;
2453 }
2454
2455 static void
2456 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2457 {
2458 nir_metadata_require(impl, nir_metadata_block_index);
2459
2460 compile_assert(ctx, ctx->stack == 0);
2461
2462 emit_cf_list(ctx, &impl->body);
2463 emit_block(ctx, impl->end_block);
2464
2465 compile_assert(ctx, ctx->stack == 0);
2466
2467 /* at this point, we should have a single empty block,
2468 * into which we emit the 'end' instruction.
2469 */
2470 compile_assert(ctx, list_empty(&ctx->block->instr_list));
2471
2472 /* If stream-out (aka transform-feedback) enabled, emit the
2473 * stream-out instructions, followed by a new empty block (into
2474 * which the 'end' instruction lands).
2475 *
2476 * NOTE: it is done in this order, rather than inserting before
2477 * we emit end_block, because NIR guarantees that all blocks
2478 * flow into end_block, and that end_block has no successors.
2479 * So by re-purposing end_block as the first block of stream-
2480 * out, we guarantee that all exit paths flow into the stream-
2481 * out instructions.
2482 */
2483 if ((ctx->compiler->gpu_id < 500) &&
2484 (ctx->so->shader->stream_output.num_outputs > 0) &&
2485 !ctx->so->binning_pass) {
2486 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2487 emit_stream_out(ctx);
2488 }
2489
2490 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2491 * NOP and has an epilogue that writes the VS outputs to local storage, to
2492 * be read by the HS. Then it resets execution mask (chmask) and chains
2493 * to the next shader (chsh).
2494 */
2495 if (ctx->so->type == MESA_SHADER_VERTEX && ctx->so->key.has_gs) {
2496 struct ir3_instruction *chmask =
2497 ir3_CHMASK(ctx->block);
2498 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2499 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2500
2501 struct ir3_instruction *chsh =
2502 ir3_CHSH(ctx->block);
2503 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2504 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2505 } else {
2506 ir3_END(ctx->block);
2507 }
2508 }
2509
2510 static void
2511 setup_input(struct ir3_context *ctx, nir_variable *in)
2512 {
2513 struct ir3_shader_variant *so = ctx->so;
2514 unsigned ncomp = glsl_get_components(in->type);
2515 unsigned n = in->data.driver_location;
2516 unsigned frac = in->data.location_frac;
2517 unsigned slot = in->data.location;
2518
2519 /* Inputs are loaded using ldlw or ldg for these stages. */
2520 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2521 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2522 ctx->so->type == MESA_SHADER_GEOMETRY)
2523 return;
2524
2525 /* skip unread inputs, we could end up with (for example), unsplit
2526 * matrix/etc inputs in the case they are not read, so just silently
2527 * skip these.
2528 */
2529 if (ncomp > 4)
2530 return;
2531
2532 so->inputs[n].slot = slot;
2533 so->inputs[n].compmask = (1 << (ncomp + frac)) - 1;
2534 so->inputs_count = MAX2(so->inputs_count, n + 1);
2535 so->inputs[n].interpolate = in->data.interpolation;
2536
2537 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2538
2539 /* if any varyings have 'sample' qualifer, that triggers us
2540 * to run in per-sample mode:
2541 */
2542 so->per_samp |= in->data.sample;
2543
2544 for (int i = 0; i < ncomp; i++) {
2545 struct ir3_instruction *instr = NULL;
2546 unsigned idx = (n * 4) + i + frac;
2547
2548 if (slot == VARYING_SLOT_POS) {
2549 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2550 } else if (slot == VARYING_SLOT_PNTC) {
2551 /* see for example st_nir_fixup_varying_slots().. this is
2552 * maybe a bit mesa/st specific. But we need things to line
2553 * up for this in fdN_program:
2554 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2555 * if (emit->sprite_coord_enable & texmask) {
2556 * ...
2557 * }
2558 */
2559 so->inputs[n].slot = VARYING_SLOT_VAR8;
2560 so->inputs[n].bary = true;
2561 instr = create_frag_input(ctx, false, idx);
2562 } else {
2563 /* detect the special case for front/back colors where
2564 * we need to do flat vs smooth shading depending on
2565 * rast state:
2566 */
2567 if (in->data.interpolation == INTERP_MODE_NONE) {
2568 switch (slot) {
2569 case VARYING_SLOT_COL0:
2570 case VARYING_SLOT_COL1:
2571 case VARYING_SLOT_BFC0:
2572 case VARYING_SLOT_BFC1:
2573 so->inputs[n].rasterflat = true;
2574 break;
2575 default:
2576 break;
2577 }
2578 }
2579
2580 if (ctx->compiler->flat_bypass) {
2581 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2582 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2583 so->inputs[n].use_ldlv = true;
2584 }
2585
2586 so->inputs[n].bary = true;
2587
2588 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2589 }
2590
2591 compile_assert(ctx, idx < ctx->ir->ninputs);
2592
2593 ctx->ir->inputs[idx] = instr;
2594 }
2595 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2596 for (int i = 0; i < ncomp; i++) {
2597 unsigned idx = (n * 4) + i + frac;
2598 compile_assert(ctx, idx < ctx->ir->ninputs);
2599 ctx->ir->inputs[idx] = create_input(ctx, idx);
2600 }
2601 } else {
2602 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2603 }
2604
2605 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2606 so->total_in += ncomp;
2607 }
2608 }
2609
2610 /* Initially we assign non-packed inloc's for varyings, as we don't really
2611 * know up-front which components will be unused. After all the compilation
2612 * stages we scan the shader to see which components are actually used, and
2613 * re-pack the inlocs to eliminate unneeded varyings.
2614 */
2615 static void
2616 pack_inlocs(struct ir3_context *ctx)
2617 {
2618 struct ir3_shader_variant *so = ctx->so;
2619 uint8_t used_components[so->inputs_count];
2620
2621 memset(used_components, 0, sizeof(used_components));
2622
2623 /*
2624 * First Step: scan shader to find which bary.f/ldlv remain:
2625 */
2626
2627 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2628 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2629 if (is_input(instr)) {
2630 unsigned inloc = instr->regs[1]->iim_val;
2631 unsigned i = inloc / 4;
2632 unsigned j = inloc % 4;
2633
2634 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
2635 compile_assert(ctx, i < so->inputs_count);
2636
2637 used_components[i] |= 1 << j;
2638 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
2639 for (int n = 0; n < 2; n++) {
2640 unsigned inloc = instr->prefetch.input_offset + n;
2641 unsigned i = inloc / 4;
2642 unsigned j = inloc % 4;
2643
2644 compile_assert(ctx, i < so->inputs_count);
2645
2646 used_components[i] |= 1 << j;
2647 }
2648 }
2649 }
2650 }
2651
2652 /*
2653 * Second Step: reassign varying inloc/slots:
2654 */
2655
2656 unsigned actual_in = 0;
2657 unsigned inloc = 0;
2658
2659 for (unsigned i = 0; i < so->inputs_count; i++) {
2660 unsigned compmask = 0, maxcomp = 0;
2661
2662 so->inputs[i].inloc = inloc;
2663 so->inputs[i].bary = false;
2664
2665 for (unsigned j = 0; j < 4; j++) {
2666 if (!(used_components[i] & (1 << j)))
2667 continue;
2668
2669 compmask |= (1 << j);
2670 actual_in++;
2671 maxcomp = j + 1;
2672
2673 /* at this point, since used_components[i] mask is only
2674 * considering varyings (ie. not sysvals) we know this
2675 * is a varying:
2676 */
2677 so->inputs[i].bary = true;
2678 }
2679
2680 if (so->inputs[i].bary) {
2681 so->varying_in++;
2682 so->inputs[i].compmask = (1 << maxcomp) - 1;
2683 inloc += maxcomp;
2684 }
2685 }
2686
2687 /*
2688 * Third Step: reassign packed inloc's:
2689 */
2690
2691 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2692 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2693 if (is_input(instr)) {
2694 unsigned inloc = instr->regs[1]->iim_val;
2695 unsigned i = inloc / 4;
2696 unsigned j = inloc % 4;
2697
2698 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
2699 }
2700 }
2701 }
2702 }
2703
2704 static void
2705 setup_output(struct ir3_context *ctx, nir_variable *out)
2706 {
2707 struct ir3_shader_variant *so = ctx->so;
2708 unsigned ncomp = glsl_get_components(out->type);
2709 unsigned n = out->data.driver_location;
2710 unsigned frac = out->data.location_frac;
2711 unsigned slot = out->data.location;
2712 unsigned comp = 0;
2713
2714 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2715 switch (slot) {
2716 case FRAG_RESULT_DEPTH:
2717 comp = 2; /* tgsi will write to .z component */
2718 so->writes_pos = true;
2719 break;
2720 case FRAG_RESULT_COLOR:
2721 so->color0_mrt = 1;
2722 break;
2723 case FRAG_RESULT_SAMPLE_MASK:
2724 so->writes_smask = true;
2725 break;
2726 default:
2727 if (slot >= FRAG_RESULT_DATA0)
2728 break;
2729 ir3_context_error(ctx, "unknown FS output name: %s\n",
2730 gl_frag_result_name(slot));
2731 }
2732 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
2733 ctx->so->type == MESA_SHADER_GEOMETRY) {
2734 switch (slot) {
2735 case VARYING_SLOT_POS:
2736 so->writes_pos = true;
2737 break;
2738 case VARYING_SLOT_PSIZ:
2739 so->writes_psize = true;
2740 break;
2741 case VARYING_SLOT_PRIMITIVE_ID:
2742 case VARYING_SLOT_LAYER:
2743 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
2744 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
2745 /* fall through */
2746 case VARYING_SLOT_COL0:
2747 case VARYING_SLOT_COL1:
2748 case VARYING_SLOT_BFC0:
2749 case VARYING_SLOT_BFC1:
2750 case VARYING_SLOT_FOGC:
2751 case VARYING_SLOT_CLIP_DIST0:
2752 case VARYING_SLOT_CLIP_DIST1:
2753 case VARYING_SLOT_CLIP_VERTEX:
2754 break;
2755 default:
2756 if (slot >= VARYING_SLOT_VAR0)
2757 break;
2758 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2759 break;
2760 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
2761 _mesa_shader_stage_to_string(ctx->so->type),
2762 gl_varying_slot_name(slot));
2763 }
2764 } else {
2765 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2766 }
2767
2768 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2769
2770 so->outputs[n].slot = slot;
2771 so->outputs[n].regid = regid(n, comp);
2772 so->outputs_count = MAX2(so->outputs_count, n + 1);
2773
2774 for (int i = 0; i < ncomp; i++) {
2775 unsigned idx = (n * 4) + i + frac;
2776 compile_assert(ctx, idx < ctx->ir->noutputs);
2777 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2778 }
2779
2780 /* if varying packing doesn't happen, we could end up in a situation
2781 * with "holes" in the output, and since the per-generation code that
2782 * sets up varying linkage registers doesn't expect to have more than
2783 * one varying per vec4 slot, pad the holes.
2784 *
2785 * Note that this should probably generate a performance warning of
2786 * some sort.
2787 */
2788 for (int i = 0; i < frac; i++) {
2789 unsigned idx = (n * 4) + i;
2790 if (!ctx->ir->outputs[idx]) {
2791 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2792 }
2793 }
2794 }
2795
2796 static int
2797 max_drvloc(struct exec_list *vars)
2798 {
2799 int drvloc = -1;
2800 nir_foreach_variable(var, vars) {
2801 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2802 }
2803 return drvloc;
2804 }
2805
2806 static const unsigned max_sysvals[] = {
2807 [MESA_SHADER_VERTEX] = 16,
2808 [MESA_SHADER_GEOMETRY] = 16,
2809 [MESA_SHADER_FRAGMENT] = 24, // TODO
2810 [MESA_SHADER_COMPUTE] = 16, // TODO how many do we actually need?
2811 [MESA_SHADER_KERNEL] = 16, // TODO how many do we actually need?
2812 };
2813
2814 static void
2815 emit_instructions(struct ir3_context *ctx)
2816 {
2817 unsigned ninputs, noutputs;
2818 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
2819
2820 ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
2821 noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
2822
2823 /* we need to leave room for sysvals:
2824 */
2825 ninputs += max_sysvals[ctx->so->type];
2826 if (ctx->so->type == MESA_SHADER_VERTEX)
2827 noutputs += 8; /* gs or tess header + primitive_id */
2828
2829 ctx->ir = ir3_create(ctx->compiler, ctx->so->type, ninputs, noutputs);
2830
2831 /* Create inputs in first block: */
2832 ctx->block = get_block(ctx, nir_start_block(fxn));
2833 ctx->in_block = ctx->block;
2834 list_addtail(&ctx->block->node, &ctx->ir->block_list);
2835
2836 ninputs -= max_sysvals[ctx->so->type];
2837
2838 if (ctx->so->key.has_gs) {
2839 if (ctx->so->type == MESA_SHADER_VERTEX ||
2840 ctx->so->type == MESA_SHADER_GEOMETRY) {
2841 ctx->gs_header = create_input(ctx, 0);
2842 ctx->primitive_id = create_input(ctx, 0);
2843 }
2844 }
2845
2846 /* for fragment shader, the vcoord input register is used as the
2847 * base for bary.f varying fetch instrs:
2848 *
2849 * TODO defer creating ctx->ij_pixel and corresponding sysvals
2850 * until emit_intrinsic when we know they are actually needed.
2851 * For now, we defer creating ctx->ij_centroid, etc, since we
2852 * only need ij_pixel for "old style" varying inputs (ie.
2853 * tgsi_to_nir)
2854 */
2855 struct ir3_instruction *vcoord = NULL;
2856 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2857 struct ir3_instruction *xy[2];
2858
2859 vcoord = create_input_compmask(ctx, 0, 0x3);
2860 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
2861
2862 ctx->ij_pixel = ir3_create_collect(ctx, xy, 2);
2863 }
2864
2865 /* Setup inputs: */
2866 nir_foreach_variable(var, &ctx->s->inputs) {
2867 setup_input(ctx, var);
2868 }
2869
2870 /* Defer add_sysval_input() stuff until after setup_inputs(),
2871 * because sysvals need to be appended after varyings:
2872 */
2873 if (vcoord) {
2874 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PIXEL,
2875 0x3, vcoord);
2876 }
2877
2878 if (ctx->primitive_id)
2879 add_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, ctx->primitive_id);
2880 if (ctx->gs_header)
2881 add_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, ctx->gs_header);
2882
2883 /* Setup outputs: */
2884 nir_foreach_variable(var, &ctx->s->outputs) {
2885 setup_output(ctx, var);
2886 }
2887
2888 /* Set up the gs header as an output for the vertex shader so it won't
2889 * clobber it for the tess ctrl shader. */
2890 if (ctx->so->type == MESA_SHADER_VERTEX) {
2891 struct ir3_shader_variant *so = ctx->so;
2892 if (ctx->primitive_id) {
2893 unsigned n = so->outputs_count++;
2894 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
2895 so->outputs[n].regid = regid(n, 0);
2896 ctx->ir->outputs[n * 4] = ctx->primitive_id;
2897
2898 compile_assert(ctx, n * 4 < ctx->ir->noutputs);
2899 }
2900
2901 if (ctx->gs_header) {
2902 unsigned n = so->outputs_count++;
2903 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
2904 so->outputs[n].regid = regid(n, 0);
2905 ctx->ir->outputs[n * 4] = ctx->gs_header;
2906
2907 compile_assert(ctx, n * 4 < ctx->ir->noutputs);
2908 }
2909
2910 }
2911
2912 /* Find # of samplers: */
2913 nir_foreach_variable(var, &ctx->s->uniforms) {
2914 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
2915 /* just assume that we'll be reading from images.. if it
2916 * is write-only we don't have to count it, but not sure
2917 * if there is a good way to know?
2918 */
2919 ctx->so->num_samp += glsl_type_get_image_count(var->type);
2920 }
2921
2922 /* NOTE: need to do something more clever when we support >1 fxn */
2923 nir_foreach_register(reg, &fxn->registers) {
2924 ir3_declare_array(ctx, reg);
2925 }
2926 /* And emit the body: */
2927 ctx->impl = fxn;
2928 emit_function(ctx, fxn);
2929 }
2930
2931 /* from NIR perspective, we actually have varying inputs. But the varying
2932 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
2933 * only actual inputs are the sysvals.
2934 */
2935 static void
2936 fixup_frag_inputs(struct ir3_context *ctx)
2937 {
2938 struct ir3_shader_variant *so = ctx->so;
2939 struct ir3 *ir = ctx->ir;
2940 unsigned i = 0;
2941
2942 /* sysvals should appear at the end of the inputs, drop everything else: */
2943 while ((i < so->inputs_count) && !so->inputs[i].sysval)
2944 i++;
2945
2946 /* at IR level, inputs are always blocks of 4 scalars: */
2947 i *= 4;
2948
2949 ir->inputs = &ir->inputs[i];
2950 ir->ninputs -= i;
2951 }
2952
2953 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2954 * need to assign the tex state indexes for these after we know the
2955 * max tex index.
2956 */
2957 static void
2958 fixup_astc_srgb(struct ir3_context *ctx)
2959 {
2960 struct ir3_shader_variant *so = ctx->so;
2961 /* indexed by original tex idx, value is newly assigned alpha sampler
2962 * state tex idx. Zero is invalid since there is at least one sampler
2963 * if we get here.
2964 */
2965 unsigned alt_tex_state[16] = {0};
2966 unsigned tex_idx = ctx->max_texture_index + 1;
2967 unsigned idx = 0;
2968
2969 so->astc_srgb.base = tex_idx;
2970
2971 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
2972 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
2973
2974 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
2975
2976 if (alt_tex_state[sam->cat5.tex] == 0) {
2977 /* assign new alternate/alpha tex state slot: */
2978 alt_tex_state[sam->cat5.tex] = tex_idx++;
2979 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
2980 so->astc_srgb.count++;
2981 }
2982
2983 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
2984 }
2985 }
2986
2987 static void
2988 fixup_binning_pass(struct ir3_context *ctx)
2989 {
2990 struct ir3_shader_variant *so = ctx->so;
2991 struct ir3 *ir = ctx->ir;
2992 unsigned i, j;
2993
2994 for (i = 0, j = 0; i < so->outputs_count; i++) {
2995 unsigned slot = so->outputs[i].slot;
2996
2997 /* throw away everything but first position/psize */
2998 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
2999 if (i != j) {
3000 so->outputs[j] = so->outputs[i];
3001 ir->outputs[(j*4)+0] = ir->outputs[(i*4)+0];
3002 ir->outputs[(j*4)+1] = ir->outputs[(i*4)+1];
3003 ir->outputs[(j*4)+2] = ir->outputs[(i*4)+2];
3004 ir->outputs[(j*4)+3] = ir->outputs[(i*4)+3];
3005 }
3006 j++;
3007 }
3008 }
3009 so->outputs_count = j;
3010 ir->noutputs = j * 4;
3011 }
3012
3013 int
3014 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3015 struct ir3_shader_variant *so)
3016 {
3017 struct ir3_context *ctx;
3018 struct ir3 *ir;
3019 struct ir3_instruction **inputs;
3020 unsigned i;
3021 int ret = 0, max_bary;
3022
3023 assert(!so->ir);
3024
3025 ctx = ir3_context_init(compiler, so);
3026 if (!ctx) {
3027 DBG("INIT failed!");
3028 ret = -1;
3029 goto out;
3030 }
3031
3032 emit_instructions(ctx);
3033
3034 if (ctx->error) {
3035 DBG("EMIT failed!");
3036 ret = -1;
3037 goto out;
3038 }
3039
3040 ir = so->ir = ctx->ir;
3041
3042 /* keep track of the inputs from TGSI perspective.. */
3043 inputs = ir->inputs;
3044
3045 /* but fixup actual inputs for frag shader: */
3046 if (so->type == MESA_SHADER_FRAGMENT)
3047 fixup_frag_inputs(ctx);
3048
3049 /* at this point, for binning pass, throw away unneeded outputs: */
3050 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3051 fixup_binning_pass(ctx);
3052
3053 /* if we want half-precision outputs, mark the output registers
3054 * as half:
3055 */
3056 if (so->key.half_precision) {
3057 for (i = 0; i < ir->noutputs; i++) {
3058 struct ir3_instruction *out = ir->outputs[i];
3059
3060 if (!out)
3061 continue;
3062
3063 /* if frag shader writes z, that needs to be full precision: */
3064 if (so->outputs[i/4].slot == FRAG_RESULT_DEPTH)
3065 continue;
3066
3067 out->regs[0]->flags |= IR3_REG_HALF;
3068 /* output could be a fanout (ie. texture fetch output)
3069 * in which case we need to propagate the half-reg flag
3070 * up to the definer so that RA sees it:
3071 */
3072 if (out->opc == OPC_META_FO) {
3073 out = out->regs[1]->instr;
3074 out->regs[0]->flags |= IR3_REG_HALF;
3075 }
3076
3077 if (out->opc == OPC_MOV) {
3078 out->cat1.dst_type = half_type(out->cat1.dst_type);
3079 }
3080 }
3081 }
3082
3083 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3084 printf("BEFORE CP:\n");
3085 ir3_print(ir);
3086 }
3087
3088 ir3_cp(ir, so);
3089
3090 /* at this point, for binning pass, throw away unneeded outputs:
3091 * Note that for a6xx and later, we do this after ir3_cp to ensure
3092 * that the uniform/constant layout for BS and VS matches, so that
3093 * we can re-use same VS_CONST state group.
3094 */
3095 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
3096 fixup_binning_pass(ctx);
3097
3098 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3099 * need to make sure not to remove any inputs that are used by
3100 * the nonbinning VS.
3101 */
3102 if (ctx->compiler->gpu_id >= 600 && so->binning_pass) {
3103 debug_assert(so->type == MESA_SHADER_VERTEX);
3104 for (int i = 0; i < ir->ninputs; i++) {
3105 struct ir3_instruction *in = ir->inputs[i];
3106
3107 if (!in)
3108 continue;
3109
3110 unsigned n = i / 4;
3111 unsigned c = i % 4;
3112
3113 debug_assert(n < so->nonbinning->inputs_count);
3114
3115 if (so->nonbinning->inputs[n].sysval)
3116 continue;
3117
3118 /* be sure to keep inputs, even if only used in VS */
3119 if (so->nonbinning->inputs[n].compmask & (1 << c))
3120 array_insert(in->block, in->block->keeps, in);
3121 }
3122 }
3123
3124 /* Insert mov if there's same instruction for each output.
3125 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
3126 */
3127 for (int i = ir->noutputs - 1; i >= 0; i--) {
3128 if (!ir->outputs[i])
3129 continue;
3130 for (unsigned j = 0; j < i; j++) {
3131 if (ir->outputs[i] == ir->outputs[j]) {
3132 ir->outputs[i] =
3133 ir3_MOV(ir->outputs[i]->block, ir->outputs[i], TYPE_F32);
3134 }
3135 }
3136 }
3137
3138 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3139 printf("BEFORE GROUPING:\n");
3140 ir3_print(ir);
3141 }
3142
3143 ir3_sched_add_deps(ir);
3144
3145 /* Group left/right neighbors, inserting mov's where needed to
3146 * solve conflicts:
3147 */
3148 ir3_group(ir);
3149
3150 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3151 printf("AFTER GROUPING:\n");
3152 ir3_print(ir);
3153 }
3154
3155 ir3_depth(ir, so);
3156
3157 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3158 printf("AFTER DEPTH:\n");
3159 ir3_print(ir);
3160 }
3161
3162 /* do Sethi–Ullman numbering before scheduling: */
3163 ir3_sun(ir);
3164
3165 ret = ir3_sched(ir);
3166 if (ret) {
3167 DBG("SCHED failed!");
3168 goto out;
3169 }
3170
3171 if (compiler->gpu_id >= 600) {
3172 ir3_a6xx_fixup_atomic_dests(ir, so);
3173 }
3174
3175 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3176 printf("AFTER SCHED:\n");
3177 ir3_print(ir);
3178 }
3179
3180 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3181 * with draw pass VS, so binning and draw pass can both use the
3182 * same VBO state.
3183 *
3184 * Note that VS inputs are expected to be full precision.
3185 */
3186 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3187 (ir->type == MESA_SHADER_VERTEX) &&
3188 so->binning_pass;
3189
3190 if (pre_assign_inputs) {
3191 for (unsigned i = 0; i < ir->ninputs; i++) {
3192 struct ir3_instruction *instr = ir->inputs[i];
3193
3194 if (!instr)
3195 continue;
3196
3197 unsigned n = i / 4;
3198 unsigned c = i % 4;
3199 unsigned regid = so->nonbinning->inputs[n].regid + c;
3200
3201 instr->regs[0]->num = regid;
3202 }
3203
3204 ret = ir3_ra(so, ir->inputs, ir->ninputs);
3205 } else if (ctx->gs_header) {
3206 /* We need to have these values in the same registers between VS and GS
3207 * since the VS chains to GS and doesn't get the sysvals redelivered.
3208 */
3209
3210 ctx->gs_header->regs[0]->num = 0;
3211 ctx->primitive_id->regs[0]->num = 1;
3212 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3213 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3214 } else {
3215 ret = ir3_ra(so, NULL, 0);
3216 }
3217
3218 if (ret) {
3219 DBG("RA failed!");
3220 goto out;
3221 }
3222
3223 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3224 printf("AFTER RA:\n");
3225 ir3_print(ir);
3226 }
3227
3228 if (so->type == MESA_SHADER_FRAGMENT)
3229 pack_inlocs(ctx);
3230
3231 /* fixup input/outputs: */
3232 for (i = 0; i < so->outputs_count; i++) {
3233 /* sometimes we get outputs that don't write the .x coord, like:
3234 *
3235 * decl_var shader_out INTERP_MODE_NONE float Color (VARYING_SLOT_VAR9.z, 1, 0)
3236 *
3237 * Presumably the result of varying packing and then eliminating
3238 * some unneeded varyings? Just skip head to the first valid
3239 * component of the output.
3240 */
3241 for (unsigned j = 0; j < 4; j++) {
3242 struct ir3_instruction *instr = ir->outputs[(i*4) + j];
3243 if (instr) {
3244 so->outputs[i].regid = instr->regs[0]->num;
3245 so->outputs[i].half = !!(instr->regs[0]->flags & IR3_REG_HALF);
3246 break;
3247 }
3248 }
3249 }
3250
3251 /* Note that some or all channels of an input may be unused: */
3252 for (i = 0; i < so->inputs_count; i++) {
3253 unsigned j, reg = regid(63,0);
3254 bool half = false;
3255 for (j = 0; j < 4; j++) {
3256 struct ir3_instruction *in = inputs[(i*4) + j];
3257
3258 if (!in)
3259 continue;
3260
3261 if (in->flags & IR3_INSTR_UNUSED)
3262 continue;
3263
3264 reg = in->regs[0]->num - j;
3265 if (half) {
3266 compile_assert(ctx, in->regs[0]->flags & IR3_REG_HALF);
3267 } else {
3268 half = !!(in->regs[0]->flags & IR3_REG_HALF);
3269 }
3270 }
3271 so->inputs[i].regid = reg;
3272 so->inputs[i].half = half;
3273 }
3274
3275 if (ctx->astc_srgb)
3276 fixup_astc_srgb(ctx);
3277
3278 /* We need to do legalize after (for frag shader's) the "bary.f"
3279 * offsets (inloc) have been assigned.
3280 */
3281 ir3_legalize(ir, &so->has_ssbo, &so->need_pixlod, &max_bary);
3282
3283 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3284 printf("AFTER LEGALIZE:\n");
3285 ir3_print(ir);
3286 }
3287
3288 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3289 * know what we might have to wait on when coming in from VS chsh.
3290 */
3291 if (so->type == MESA_SHADER_TESS_CTRL ||
3292 so->type == MESA_SHADER_GEOMETRY ) {
3293 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
3294 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
3295 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3296 break;
3297 }
3298 }
3299 }
3300
3301 so->branchstack = ctx->max_stack;
3302
3303 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3304 if (so->type == MESA_SHADER_FRAGMENT)
3305 so->total_in = max_bary + 1;
3306
3307 so->max_sun = ir->max_sun;
3308
3309 out:
3310 if (ret) {
3311 if (so->ir)
3312 ir3_destroy(so->ir);
3313 so->ir = NULL;
3314 }
3315 ir3_context_free(ctx);
3316
3317 return ret;
3318 }