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compiler: rename SYSTEM_VALUE_VARYING_COORD
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 ir3_reg_create(mov, 0, 0);
55 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
56 src->instr = collect;
57 src->size = arrsz;
58 src->array.offset = n;
59
60 ir3_instr_set_address(mov, address);
61
62 return mov;
63 }
64
65 static struct ir3_instruction *
66 create_input_compmask(struct ir3_context *ctx, unsigned n, unsigned compmask)
67 {
68 struct ir3_instruction *in;
69
70 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
71 in->inout.block = ctx->in_block;
72 ir3_reg_create(in, n, 0);
73
74 in->regs[0]->wrmask = compmask;
75
76 return in;
77 }
78
79 static struct ir3_instruction *
80 create_input(struct ir3_context *ctx, unsigned n)
81 {
82 return create_input_compmask(ctx, n, 0x1);
83 }
84
85 static struct ir3_instruction *
86 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
87 {
88 struct ir3_block *block = ctx->block;
89 struct ir3_instruction *instr;
90 /* packed inloc is fixed up later: */
91 struct ir3_instruction *inloc = create_immed(block, n);
92
93 if (use_ldlv) {
94 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
95 instr->cat6.type = TYPE_U32;
96 instr->cat6.iim_val = 1;
97 } else {
98 instr = ir3_BARY_F(block, inloc, 0, ctx->frag_vcoord, 0);
99 instr->regs[2]->wrmask = 0x3;
100 }
101
102 return instr;
103 }
104
105 static struct ir3_instruction *
106 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
107 {
108 /* first four vec4 sysval's reserved for UBOs: */
109 /* NOTE: dp is in scalar, but there can be >4 dp components: */
110 unsigned n = ctx->so->constbase.driver_param;
111 unsigned r = regid(n + dp / 4, dp % 4);
112 return create_uniform(ctx->block, r);
113 }
114
115 /*
116 * Adreno uses uint rather than having dedicated bool type,
117 * which (potentially) requires some conversion, in particular
118 * when using output of an bool instr to int input, or visa
119 * versa.
120 *
121 * | Adreno | NIR |
122 * -------+---------+-------+-
123 * true | 1 | ~0 |
124 * false | 0 | 0 |
125 *
126 * To convert from an adreno bool (uint) to nir, use:
127 *
128 * absneg.s dst, (neg)src
129 *
130 * To convert back in the other direction:
131 *
132 * absneg.s dst, (abs)arc
133 *
134 * The CP step can clean up the absneg.s that cancel each other
135 * out, and with a slight bit of extra cleverness (to recognize
136 * the instructions which produce either a 0 or 1) can eliminate
137 * the absneg.s's completely when an instruction that wants
138 * 0/1 consumes the result. For example, when a nir 'bcsel'
139 * consumes the result of 'feq'. So we should be able to get by
140 * without a boolean resolve step, and without incuring any
141 * extra penalty in instruction count.
142 */
143
144 /* NIR bool -> native (adreno): */
145 static struct ir3_instruction *
146 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
147 {
148 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
149 }
150
151 /* native (adreno) -> NIR bool: */
152 static struct ir3_instruction *
153 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
154 {
155 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
156 }
157
158 /*
159 * alu/sfu instructions:
160 */
161
162 static struct ir3_instruction *
163 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
164 unsigned src_bitsize, nir_op op)
165 {
166 type_t src_type, dst_type;
167
168 switch (op) {
169 case nir_op_f2f32:
170 case nir_op_f2f16_rtne:
171 case nir_op_f2f16_rtz:
172 case nir_op_f2f16:
173 case nir_op_f2i32:
174 case nir_op_f2i16:
175 case nir_op_f2i8:
176 case nir_op_f2u32:
177 case nir_op_f2u16:
178 case nir_op_f2u8:
179 switch (src_bitsize) {
180 case 32:
181 src_type = TYPE_F32;
182 break;
183 case 16:
184 src_type = TYPE_F16;
185 break;
186 default:
187 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
188 }
189 break;
190
191 case nir_op_i2f32:
192 case nir_op_i2f16:
193 case nir_op_i2i32:
194 case nir_op_i2i16:
195 case nir_op_i2i8:
196 switch (src_bitsize) {
197 case 32:
198 src_type = TYPE_S32;
199 break;
200 case 16:
201 src_type = TYPE_S16;
202 break;
203 case 8:
204 src_type = TYPE_S8;
205 break;
206 default:
207 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
208 }
209 break;
210
211 case nir_op_u2f32:
212 case nir_op_u2f16:
213 case nir_op_u2u32:
214 case nir_op_u2u16:
215 case nir_op_u2u8:
216 switch (src_bitsize) {
217 case 32:
218 src_type = TYPE_U32;
219 break;
220 case 16:
221 src_type = TYPE_U16;
222 break;
223 case 8:
224 src_type = TYPE_U8;
225 break;
226 default:
227 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
228 }
229 break;
230
231 default:
232 ir3_context_error(ctx, "invalid conversion op: %u", op);
233 }
234
235 switch (op) {
236 case nir_op_f2f32:
237 case nir_op_i2f32:
238 case nir_op_u2f32:
239 dst_type = TYPE_F32;
240 break;
241
242 case nir_op_f2f16_rtne:
243 case nir_op_f2f16_rtz:
244 case nir_op_f2f16:
245 /* TODO how to handle rounding mode? */
246 case nir_op_i2f16:
247 case nir_op_u2f16:
248 dst_type = TYPE_F16;
249 break;
250
251 case nir_op_f2i32:
252 case nir_op_i2i32:
253 dst_type = TYPE_S32;
254 break;
255
256 case nir_op_f2i16:
257 case nir_op_i2i16:
258 dst_type = TYPE_S16;
259 break;
260
261 case nir_op_f2i8:
262 case nir_op_i2i8:
263 dst_type = TYPE_S8;
264 break;
265
266 case nir_op_f2u32:
267 case nir_op_u2u32:
268 dst_type = TYPE_U32;
269 break;
270
271 case nir_op_f2u16:
272 case nir_op_u2u16:
273 dst_type = TYPE_U16;
274 break;
275
276 case nir_op_f2u8:
277 case nir_op_u2u8:
278 dst_type = TYPE_U8;
279 break;
280
281 default:
282 ir3_context_error(ctx, "invalid conversion op: %u", op);
283 }
284
285 return ir3_COV(ctx->block, src, src_type, dst_type);
286 }
287
288 static void
289 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
290 {
291 const nir_op_info *info = &nir_op_infos[alu->op];
292 struct ir3_instruction **dst, *src[info->num_inputs];
293 unsigned bs[info->num_inputs]; /* bit size */
294 struct ir3_block *b = ctx->block;
295 unsigned dst_sz, wrmask;
296
297 if (alu->dest.dest.is_ssa) {
298 dst_sz = alu->dest.dest.ssa.num_components;
299 wrmask = (1 << dst_sz) - 1;
300 } else {
301 dst_sz = alu->dest.dest.reg.reg->num_components;
302 wrmask = alu->dest.write_mask;
303 }
304
305 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
306
307 /* Vectors are special in that they have non-scalarized writemasks,
308 * and just take the first swizzle channel for each argument in
309 * order into each writemask channel.
310 */
311 if ((alu->op == nir_op_vec2) ||
312 (alu->op == nir_op_vec3) ||
313 (alu->op == nir_op_vec4)) {
314
315 for (int i = 0; i < info->num_inputs; i++) {
316 nir_alu_src *asrc = &alu->src[i];
317
318 compile_assert(ctx, !asrc->abs);
319 compile_assert(ctx, !asrc->negate);
320
321 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
322 if (!src[i])
323 src[i] = create_immed(ctx->block, 0);
324 dst[i] = ir3_MOV(b, src[i], TYPE_U32);
325 }
326
327 ir3_put_dst(ctx, &alu->dest.dest);
328 return;
329 }
330
331 /* We also get mov's with more than one component for mov's so
332 * handle those specially:
333 */
334 if ((alu->op == nir_op_imov) || (alu->op == nir_op_fmov)) {
335 type_t type = (alu->op == nir_op_imov) ? TYPE_U32 : TYPE_F32;
336 nir_alu_src *asrc = &alu->src[0];
337 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
338
339 for (unsigned i = 0; i < dst_sz; i++) {
340 if (wrmask & (1 << i)) {
341 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], type);
342 } else {
343 dst[i] = NULL;
344 }
345 }
346
347 ir3_put_dst(ctx, &alu->dest.dest);
348 return;
349 }
350
351 /* General case: We can just grab the one used channel per src. */
352 for (int i = 0; i < info->num_inputs; i++) {
353 unsigned chan = ffs(alu->dest.write_mask) - 1;
354 nir_alu_src *asrc = &alu->src[i];
355
356 compile_assert(ctx, !asrc->abs);
357 compile_assert(ctx, !asrc->negate);
358
359 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
360 bs[i] = nir_src_bit_size(asrc->src);
361
362 compile_assert(ctx, src[i]);
363 }
364
365 switch (alu->op) {
366 case nir_op_f2f32:
367 case nir_op_f2f16_rtne:
368 case nir_op_f2f16_rtz:
369 case nir_op_f2f16:
370 case nir_op_f2i32:
371 case nir_op_f2i16:
372 case nir_op_f2i8:
373 case nir_op_f2u32:
374 case nir_op_f2u16:
375 case nir_op_f2u8:
376 case nir_op_i2f32:
377 case nir_op_i2f16:
378 case nir_op_i2i32:
379 case nir_op_i2i16:
380 case nir_op_i2i8:
381 case nir_op_u2f32:
382 case nir_op_u2f16:
383 case nir_op_u2u32:
384 case nir_op_u2u16:
385 case nir_op_u2u8:
386 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
387 break;
388 case nir_op_f2b32:
389 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
390 dst[0]->cat2.condition = IR3_COND_NE;
391 dst[0] = ir3_n2b(b, dst[0]);
392 break;
393 case nir_op_b2f16:
394 case nir_op_b2f32:
395 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
396 break;
397 case nir_op_b2i8:
398 case nir_op_b2i16:
399 case nir_op_b2i32:
400 dst[0] = ir3_b2n(b, src[0]);
401 break;
402 case nir_op_i2b32:
403 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
404 dst[0]->cat2.condition = IR3_COND_NE;
405 dst[0] = ir3_n2b(b, dst[0]);
406 break;
407
408 case nir_op_fneg:
409 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
410 break;
411 case nir_op_fabs:
412 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
413 break;
414 case nir_op_fmax:
415 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
416 break;
417 case nir_op_fmin:
418 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
419 break;
420 case nir_op_fsat:
421 /* if there is just a single use of the src, and it supports
422 * (sat) bit, we can just fold the (sat) flag back to the
423 * src instruction and create a mov. This is easier for cp
424 * to eliminate.
425 *
426 * TODO probably opc_cat==4 is ok too
427 */
428 if (alu->src[0].src.is_ssa &&
429 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
430 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
431 src[0]->flags |= IR3_INSTR_SAT;
432 dst[0] = ir3_MOV(b, src[0], TYPE_U32);
433 } else {
434 /* otherwise generate a max.f that saturates.. blob does
435 * similar (generating a cat2 mov using max.f)
436 */
437 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
438 dst[0]->flags |= IR3_INSTR_SAT;
439 }
440 break;
441 case nir_op_fmul:
442 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
443 break;
444 case nir_op_fadd:
445 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
446 break;
447 case nir_op_fsub:
448 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
449 break;
450 case nir_op_ffma:
451 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
452 break;
453 case nir_op_fddx:
454 dst[0] = ir3_DSX(b, src[0], 0);
455 dst[0]->cat5.type = TYPE_F32;
456 break;
457 case nir_op_fddy:
458 dst[0] = ir3_DSY(b, src[0], 0);
459 dst[0]->cat5.type = TYPE_F32;
460 break;
461 break;
462 case nir_op_flt32:
463 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
464 dst[0]->cat2.condition = IR3_COND_LT;
465 dst[0] = ir3_n2b(b, dst[0]);
466 break;
467 case nir_op_fge32:
468 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
469 dst[0]->cat2.condition = IR3_COND_GE;
470 dst[0] = ir3_n2b(b, dst[0]);
471 break;
472 case nir_op_feq32:
473 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
474 dst[0]->cat2.condition = IR3_COND_EQ;
475 dst[0] = ir3_n2b(b, dst[0]);
476 break;
477 case nir_op_fne32:
478 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
479 dst[0]->cat2.condition = IR3_COND_NE;
480 dst[0] = ir3_n2b(b, dst[0]);
481 break;
482 case nir_op_fceil:
483 dst[0] = ir3_CEIL_F(b, src[0], 0);
484 break;
485 case nir_op_ffloor:
486 dst[0] = ir3_FLOOR_F(b, src[0], 0);
487 break;
488 case nir_op_ftrunc:
489 dst[0] = ir3_TRUNC_F(b, src[0], 0);
490 break;
491 case nir_op_fround_even:
492 dst[0] = ir3_RNDNE_F(b, src[0], 0);
493 break;
494 case nir_op_fsign:
495 dst[0] = ir3_SIGN_F(b, src[0], 0);
496 break;
497
498 case nir_op_fsin:
499 dst[0] = ir3_SIN(b, src[0], 0);
500 break;
501 case nir_op_fcos:
502 dst[0] = ir3_COS(b, src[0], 0);
503 break;
504 case nir_op_frsq:
505 dst[0] = ir3_RSQ(b, src[0], 0);
506 break;
507 case nir_op_frcp:
508 dst[0] = ir3_RCP(b, src[0], 0);
509 break;
510 case nir_op_flog2:
511 dst[0] = ir3_LOG2(b, src[0], 0);
512 break;
513 case nir_op_fexp2:
514 dst[0] = ir3_EXP2(b, src[0], 0);
515 break;
516 case nir_op_fsqrt:
517 dst[0] = ir3_SQRT(b, src[0], 0);
518 break;
519
520 case nir_op_iabs:
521 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
522 break;
523 case nir_op_iadd:
524 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
525 break;
526 case nir_op_iand:
527 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
528 break;
529 case nir_op_imax:
530 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
531 break;
532 case nir_op_umax:
533 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
534 break;
535 case nir_op_imin:
536 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
537 break;
538 case nir_op_umin:
539 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
540 break;
541 case nir_op_imul:
542 /*
543 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
544 * mull.u tmp0, a, b ; mul low, i.e. al * bl
545 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
546 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
547 */
548 dst[0] = ir3_MADSH_M16(b, src[1], 0, src[0], 0,
549 ir3_MADSH_M16(b, src[0], 0, src[1], 0,
550 ir3_MULL_U(b, src[0], 0, src[1], 0), 0), 0);
551 break;
552 case nir_op_ineg:
553 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
554 break;
555 case nir_op_inot:
556 dst[0] = ir3_NOT_B(b, src[0], 0);
557 break;
558 case nir_op_ior:
559 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
560 break;
561 case nir_op_ishl:
562 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
563 break;
564 case nir_op_ishr:
565 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
566 break;
567 case nir_op_isub:
568 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
569 break;
570 case nir_op_ixor:
571 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
572 break;
573 case nir_op_ushr:
574 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
575 break;
576 case nir_op_ilt32:
577 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
578 dst[0]->cat2.condition = IR3_COND_LT;
579 dst[0] = ir3_n2b(b, dst[0]);
580 break;
581 case nir_op_ige32:
582 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
583 dst[0]->cat2.condition = IR3_COND_GE;
584 dst[0] = ir3_n2b(b, dst[0]);
585 break;
586 case nir_op_ieq32:
587 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
588 dst[0]->cat2.condition = IR3_COND_EQ;
589 dst[0] = ir3_n2b(b, dst[0]);
590 break;
591 case nir_op_ine32:
592 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
593 dst[0]->cat2.condition = IR3_COND_NE;
594 dst[0] = ir3_n2b(b, dst[0]);
595 break;
596 case nir_op_ult32:
597 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
598 dst[0]->cat2.condition = IR3_COND_LT;
599 dst[0] = ir3_n2b(b, dst[0]);
600 break;
601 case nir_op_uge32:
602 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
603 dst[0]->cat2.condition = IR3_COND_GE;
604 dst[0] = ir3_n2b(b, dst[0]);
605 break;
606
607 case nir_op_b32csel: {
608 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
609 compile_assert(ctx, bs[1] == bs[2]);
610 /* the boolean condition is 32b even if src[1] and src[2] are
611 * half-precision, but sel.b16 wants all three src's to be the
612 * same type.
613 */
614 if (bs[1] < 32)
615 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
616 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
617 break;
618 }
619 case nir_op_bit_count: {
620 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
621 // double check on earlier gen's. Once half-precision support is
622 // in place, this should probably move to a NIR lowering pass:
623 struct ir3_instruction *hi, *lo;
624
625 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
626 TYPE_U32, TYPE_U16);
627 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
628
629 hi = ir3_CBITS_B(b, hi, 0);
630 lo = ir3_CBITS_B(b, lo, 0);
631
632 // TODO maybe the builders should default to making dst half-precision
633 // if the src's were half precision, to make this less awkward.. otoh
634 // we should probably just do this lowering in NIR.
635 hi->regs[0]->flags |= IR3_REG_HALF;
636 lo->regs[0]->flags |= IR3_REG_HALF;
637
638 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
639 dst[0]->regs[0]->flags |= IR3_REG_HALF;
640 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
641 break;
642 }
643 case nir_op_ifind_msb: {
644 struct ir3_instruction *cmp;
645 dst[0] = ir3_CLZ_S(b, src[0], 0);
646 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
647 cmp->cat2.condition = IR3_COND_GE;
648 dst[0] = ir3_SEL_B32(b,
649 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
650 cmp, 0, dst[0], 0);
651 break;
652 }
653 case nir_op_ufind_msb:
654 dst[0] = ir3_CLZ_B(b, src[0], 0);
655 dst[0] = ir3_SEL_B32(b,
656 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
657 src[0], 0, dst[0], 0);
658 break;
659 case nir_op_find_lsb:
660 dst[0] = ir3_BFREV_B(b, src[0], 0);
661 dst[0] = ir3_CLZ_B(b, dst[0], 0);
662 break;
663 case nir_op_bitfield_reverse:
664 dst[0] = ir3_BFREV_B(b, src[0], 0);
665 break;
666
667 default:
668 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
669 nir_op_infos[alu->op].name);
670 break;
671 }
672
673 ir3_put_dst(ctx, &alu->dest.dest);
674 }
675
676 /* handles direct/indirect UBO reads: */
677 static void
678 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
679 struct ir3_instruction **dst)
680 {
681 struct ir3_block *b = ctx->block;
682 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
683 /* UBO addresses are the first driver params, but subtract 2 here to
684 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
685 * is the uniforms: */
686 unsigned ubo = regid(ctx->so->constbase.ubo, 0) - 2;
687 const unsigned ptrsz = ir3_pointer_size(ctx);
688
689 int off = 0;
690
691 /* First src is ubo index, which could either be an immed or not: */
692 src0 = ir3_get_src(ctx, &intr->src[0])[0];
693 if (is_same_type_mov(src0) &&
694 (src0->regs[1]->flags & IR3_REG_IMMED)) {
695 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
696 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
697 } else {
698 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
699 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
700 }
701
702 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
703 addr = base_lo;
704
705 if (nir_src_is_const(intr->src[1])) {
706 off += nir_src_as_uint(intr->src[1]);
707 } else {
708 /* For load_ubo_indirect, second src is indirect offset: */
709 src1 = ir3_get_src(ctx, &intr->src[1])[0];
710
711 /* and add offset to addr: */
712 addr = ir3_ADD_S(b, addr, 0, src1, 0);
713 }
714
715 /* if offset is to large to encode in the ldg, split it out: */
716 if ((off + (intr->num_components * 4)) > 1024) {
717 /* split out the minimal amount to improve the odds that
718 * cp can fit the immediate in the add.s instruction:
719 */
720 unsigned off2 = off + (intr->num_components * 4) - 1024;
721 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
722 off -= off2;
723 }
724
725 if (ptrsz == 2) {
726 struct ir3_instruction *carry;
727
728 /* handle 32b rollover, ie:
729 * if (addr < base_lo)
730 * base_hi++
731 */
732 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
733 carry->cat2.condition = IR3_COND_LT;
734 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
735
736 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
737 }
738
739 for (int i = 0; i < intr->num_components; i++) {
740 struct ir3_instruction *load =
741 ir3_LDG(b, addr, 0, create_immed(b, 1), 0);
742 load->cat6.type = TYPE_U32;
743 load->cat6.src_offset = off + i * 4; /* byte offset */
744 dst[i] = load;
745 }
746 }
747
748 /* src[] = { block_index } */
749 static void
750 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
751 struct ir3_instruction **dst)
752 {
753 /* SSBO size stored as a const starting at ssbo_sizes: */
754 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
755 unsigned idx = regid(ctx->so->constbase.ssbo_sizes, 0) +
756 ctx->so->const_layout.ssbo_size.off[blk_idx];
757
758 debug_assert(ctx->so->const_layout.ssbo_size.mask & (1 << blk_idx));
759
760 dst[0] = create_uniform(ctx->block, idx);
761 }
762
763 /* src[] = { offset }. const_index[] = { base } */
764 static void
765 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
766 struct ir3_instruction **dst)
767 {
768 struct ir3_block *b = ctx->block;
769 struct ir3_instruction *ldl, *offset;
770 unsigned base;
771
772 offset = ir3_get_src(ctx, &intr->src[0])[0];
773 base = nir_intrinsic_base(intr);
774
775 ldl = ir3_LDL(b, offset, 0, create_immed(b, intr->num_components), 0);
776 ldl->cat6.src_offset = base;
777 ldl->cat6.type = utype_dst(intr->dest);
778 ldl->regs[0]->wrmask = MASK(intr->num_components);
779
780 ldl->barrier_class = IR3_BARRIER_SHARED_R;
781 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
782
783 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
784 }
785
786 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
787 static void
788 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
789 {
790 struct ir3_block *b = ctx->block;
791 struct ir3_instruction *stl, *offset;
792 struct ir3_instruction * const *value;
793 unsigned base, wrmask;
794
795 value = ir3_get_src(ctx, &intr->src[0]);
796 offset = ir3_get_src(ctx, &intr->src[1])[0];
797
798 base = nir_intrinsic_base(intr);
799 wrmask = nir_intrinsic_write_mask(intr);
800
801 /* Combine groups of consecutive enabled channels in one write
802 * message. We use ffs to find the first enabled channel and then ffs on
803 * the bit-inverse, down-shifted writemask to determine the length of
804 * the block of enabled bits.
805 *
806 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
807 */
808 while (wrmask) {
809 unsigned first_component = ffs(wrmask) - 1;
810 unsigned length = ffs(~(wrmask >> first_component)) - 1;
811
812 stl = ir3_STL(b, offset, 0,
813 ir3_create_collect(ctx, &value[first_component], length), 0,
814 create_immed(b, length), 0);
815 stl->cat6.dst_offset = first_component + base;
816 stl->cat6.type = utype_src(intr->src[0]);
817 stl->barrier_class = IR3_BARRIER_SHARED_W;
818 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
819
820 array_insert(b, b->keeps, stl);
821
822 /* Clear the bits in the writemask that we just wrote, then try
823 * again to see if more channels are left.
824 */
825 wrmask &= (15 << (first_component + length));
826 }
827 }
828
829 /*
830 * CS shared variable atomic intrinsics
831 *
832 * All of the shared variable atomic memory operations read a value from
833 * memory, compute a new value using one of the operations below, write the
834 * new value to memory, and return the original value read.
835 *
836 * All operations take 2 sources except CompSwap that takes 3. These
837 * sources represent:
838 *
839 * 0: The offset into the shared variable storage region that the atomic
840 * operation will operate on.
841 * 1: The data parameter to the atomic function (i.e. the value to add
842 * in shared_atomic_add, etc).
843 * 2: For CompSwap only: the second data parameter.
844 */
845 static struct ir3_instruction *
846 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
847 {
848 struct ir3_block *b = ctx->block;
849 struct ir3_instruction *atomic, *src0, *src1;
850 type_t type = TYPE_U32;
851
852 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
853 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
854
855 switch (intr->intrinsic) {
856 case nir_intrinsic_shared_atomic_add:
857 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
858 break;
859 case nir_intrinsic_shared_atomic_imin:
860 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
861 type = TYPE_S32;
862 break;
863 case nir_intrinsic_shared_atomic_umin:
864 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
865 break;
866 case nir_intrinsic_shared_atomic_imax:
867 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
868 type = TYPE_S32;
869 break;
870 case nir_intrinsic_shared_atomic_umax:
871 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
872 break;
873 case nir_intrinsic_shared_atomic_and:
874 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
875 break;
876 case nir_intrinsic_shared_atomic_or:
877 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
878 break;
879 case nir_intrinsic_shared_atomic_xor:
880 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
881 break;
882 case nir_intrinsic_shared_atomic_exchange:
883 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
884 break;
885 case nir_intrinsic_shared_atomic_comp_swap:
886 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
887 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
888 ir3_get_src(ctx, &intr->src[2])[0],
889 src1,
890 }, 2);
891 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
892 break;
893 default:
894 unreachable("boo");
895 }
896
897 atomic->cat6.iim_val = 1;
898 atomic->cat6.d = 1;
899 atomic->cat6.type = type;
900 atomic->barrier_class = IR3_BARRIER_SHARED_W;
901 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
902
903 /* even if nothing consume the result, we can't DCE the instruction: */
904 array_insert(b, b->keeps, atomic);
905
906 return atomic;
907 }
908
909 /* TODO handle actual indirect/dynamic case.. which is going to be weird
910 * to handle with the image_mapping table..
911 */
912 static struct ir3_instruction *
913 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
914 {
915 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
916 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
917 struct ir3_instruction *texture, *sampler;
918
919 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
920 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
921
922 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
923 sampler,
924 texture,
925 }, 2);
926 }
927
928 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
929 static void
930 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
931 struct ir3_instruction **dst)
932 {
933 struct ir3_block *b = ctx->block;
934 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
935 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
936 struct ir3_instruction *sam;
937 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
938 struct ir3_instruction *coords[4];
939 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
940 type_t type = ir3_get_image_type(var);
941
942 /* hmm, this seems a bit odd, but it is what blob does and (at least
943 * a5xx) just faults on bogus addresses otherwise:
944 */
945 if (flags & IR3_INSTR_3D) {
946 flags &= ~IR3_INSTR_3D;
947 flags |= IR3_INSTR_A;
948 }
949
950 for (unsigned i = 0; i < ncoords; i++)
951 coords[i] = src0[i];
952
953 if (ncoords == 1)
954 coords[ncoords++] = create_immed(b, 0);
955
956 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
957 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
958
959 sam->barrier_class = IR3_BARRIER_IMAGE_R;
960 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
961
962 ir3_split_dest(b, dst, sam, 0, 4);
963 }
964
965 static void
966 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
967 struct ir3_instruction **dst)
968 {
969 struct ir3_block *b = ctx->block;
970 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
971 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
972 struct ir3_instruction *sam, *lod;
973 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
974
975 lod = create_immed(b, 0);
976 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
977 samp_tex, lod, NULL);
978
979 /* Array size actually ends up in .w rather than .z. This doesn't
980 * matter for miplevel 0, but for higher mips the value in z is
981 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
982 * returned, which means that we have to add 1 to it for arrays for
983 * a3xx.
984 *
985 * Note use a temporary dst and then copy, since the size of the dst
986 * array that is passed in is based on nir's understanding of the
987 * result size, not the hardware's
988 */
989 struct ir3_instruction *tmp[4];
990
991 ir3_split_dest(b, tmp, sam, 0, 4);
992
993 /* get_size instruction returns size in bytes instead of texels
994 * for imageBuffer, so we need to divide it by the pixel size
995 * of the image format.
996 *
997 * TODO: This is at least true on a5xx. Check other gens.
998 */
999 enum glsl_sampler_dim dim =
1000 glsl_get_sampler_dim(glsl_without_array(var->type));
1001 if (dim == GLSL_SAMPLER_DIM_BUF) {
1002 /* Since all the possible values the divisor can take are
1003 * power-of-two (4, 8, or 16), the division is implemented
1004 * as a shift-right.
1005 * During shader setup, the log2 of the image format's
1006 * bytes-per-pixel should have been emitted in 2nd slot of
1007 * image_dims. See ir3_shader::emit_image_dims().
1008 */
1009 unsigned cb = regid(ctx->so->constbase.image_dims, 0) +
1010 ctx->so->const_layout.image_dims.off[var->data.driver_location];
1011 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1012
1013 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1014 }
1015
1016 for (unsigned i = 0; i < ncoords; i++)
1017 dst[i] = tmp[i];
1018
1019 if (flags & IR3_INSTR_A) {
1020 if (ctx->compiler->levels_add_one) {
1021 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1022 } else {
1023 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1024 }
1025 }
1026 }
1027
1028 static void
1029 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1030 {
1031 struct ir3_block *b = ctx->block;
1032 struct ir3_instruction *barrier;
1033
1034 switch (intr->intrinsic) {
1035 case nir_intrinsic_barrier:
1036 barrier = ir3_BAR(b);
1037 barrier->cat7.g = true;
1038 barrier->cat7.l = true;
1039 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1040 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1041 break;
1042 case nir_intrinsic_memory_barrier:
1043 barrier = ir3_FENCE(b);
1044 barrier->cat7.g = true;
1045 barrier->cat7.r = true;
1046 barrier->cat7.w = true;
1047 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1048 IR3_BARRIER_BUFFER_W;
1049 barrier->barrier_conflict =
1050 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1051 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1052 break;
1053 case nir_intrinsic_memory_barrier_atomic_counter:
1054 case nir_intrinsic_memory_barrier_buffer:
1055 barrier = ir3_FENCE(b);
1056 barrier->cat7.g = true;
1057 barrier->cat7.r = true;
1058 barrier->cat7.w = true;
1059 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1060 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1061 IR3_BARRIER_BUFFER_W;
1062 break;
1063 case nir_intrinsic_memory_barrier_image:
1064 // TODO double check if this should have .g set
1065 barrier = ir3_FENCE(b);
1066 barrier->cat7.g = true;
1067 barrier->cat7.r = true;
1068 barrier->cat7.w = true;
1069 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1070 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1071 IR3_BARRIER_IMAGE_W;
1072 break;
1073 case nir_intrinsic_memory_barrier_shared:
1074 barrier = ir3_FENCE(b);
1075 barrier->cat7.g = true;
1076 barrier->cat7.l = true;
1077 barrier->cat7.r = true;
1078 barrier->cat7.w = true;
1079 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1080 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1081 IR3_BARRIER_SHARED_W;
1082 break;
1083 case nir_intrinsic_group_memory_barrier:
1084 barrier = ir3_FENCE(b);
1085 barrier->cat7.g = true;
1086 barrier->cat7.l = true;
1087 barrier->cat7.r = true;
1088 barrier->cat7.w = true;
1089 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1090 IR3_BARRIER_IMAGE_W |
1091 IR3_BARRIER_BUFFER_W;
1092 barrier->barrier_conflict =
1093 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1094 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1095 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1096 break;
1097 default:
1098 unreachable("boo");
1099 }
1100
1101 /* make sure barrier doesn't get DCE'd */
1102 array_insert(b, b->keeps, barrier);
1103 }
1104
1105 static void add_sysval_input_compmask(struct ir3_context *ctx,
1106 gl_system_value slot, unsigned compmask,
1107 struct ir3_instruction *instr)
1108 {
1109 struct ir3_shader_variant *so = ctx->so;
1110 unsigned r = regid(so->inputs_count, 0);
1111 unsigned n = so->inputs_count++;
1112
1113 so->inputs[n].sysval = true;
1114 so->inputs[n].slot = slot;
1115 so->inputs[n].compmask = compmask;
1116 so->inputs[n].regid = r;
1117 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1118 so->total_in++;
1119
1120 ctx->ir->ninputs = MAX2(ctx->ir->ninputs, r + 1);
1121 ctx->ir->inputs[r] = instr;
1122 }
1123
1124 static void add_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1125 struct ir3_instruction *instr)
1126 {
1127 add_sysval_input_compmask(ctx, slot, 0x1, instr);
1128 }
1129
1130 static void
1131 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1132 {
1133 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1134 struct ir3_instruction **dst;
1135 struct ir3_instruction * const *src;
1136 struct ir3_block *b = ctx->block;
1137 int idx, comp;
1138
1139 if (info->has_dest) {
1140 unsigned n = nir_intrinsic_dest_components(intr);
1141 dst = ir3_get_dst(ctx, &intr->dest, n);
1142 } else {
1143 dst = NULL;
1144 }
1145
1146 switch (intr->intrinsic) {
1147 case nir_intrinsic_load_uniform:
1148 idx = nir_intrinsic_base(intr);
1149 if (nir_src_is_const(intr->src[0])) {
1150 idx += nir_src_as_uint(intr->src[0]);
1151 for (int i = 0; i < intr->num_components; i++) {
1152 dst[i] = create_uniform(b, idx + i);
1153 }
1154 } else {
1155 src = ir3_get_src(ctx, &intr->src[0]);
1156 for (int i = 0; i < intr->num_components; i++) {
1157 dst[i] = create_uniform_indirect(b, idx + i,
1158 ir3_get_addr(ctx, src[0], 1));
1159 }
1160 /* NOTE: if relative addressing is used, we set
1161 * constlen in the compiler (to worst-case value)
1162 * since we don't know in the assembler what the max
1163 * addr reg value can be:
1164 */
1165 ctx->so->constlen = ctx->s->num_uniforms;
1166 }
1167 break;
1168 case nir_intrinsic_load_ubo:
1169 emit_intrinsic_load_ubo(ctx, intr, dst);
1170 break;
1171 case nir_intrinsic_load_barycentric_centroid:
1172 case nir_intrinsic_load_barycentric_pixel:
1173 ir3_split_dest(b, dst, ctx->frag_vcoord, 0, 2);
1174 break;
1175 case nir_intrinsic_load_interpolated_input:
1176 idx = nir_intrinsic_base(intr);
1177 comp = nir_intrinsic_component(intr);
1178 src = ir3_get_src(ctx, &intr->src[0]);
1179 if (nir_src_is_const(intr->src[1])) {
1180 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1181 idx += nir_src_as_uint(intr->src[1]);
1182 for (int i = 0; i < intr->num_components; i++) {
1183 unsigned inloc = idx * 4 + i + comp;
1184 if (ctx->so->inputs[idx * 4].bary) {
1185 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1186 } else {
1187 /* for non-varyings use the pre-setup input, since
1188 * that is easier than mapping things back to a
1189 * nir_variable to figure out what it is.
1190 */
1191 dst[i] = ctx->ir->inputs[inloc];
1192 }
1193 }
1194 } else {
1195 ir3_context_error(ctx, "unhandled");
1196 }
1197 break;
1198 case nir_intrinsic_load_input:
1199 idx = nir_intrinsic_base(intr);
1200 comp = nir_intrinsic_component(intr);
1201 if (nir_src_is_const(intr->src[0])) {
1202 idx += nir_src_as_uint(intr->src[0]);
1203 for (int i = 0; i < intr->num_components; i++) {
1204 unsigned n = idx * 4 + i + comp;
1205 dst[i] = ctx->ir->inputs[n];
1206 compile_assert(ctx, ctx->ir->inputs[n]);
1207 }
1208 } else {
1209 src = ir3_get_src(ctx, &intr->src[0]);
1210 struct ir3_instruction *collect =
1211 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ir->ninputs);
1212 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1213 for (int i = 0; i < intr->num_components; i++) {
1214 unsigned n = idx * 4 + i + comp;
1215 dst[i] = create_indirect_load(ctx, ctx->ir->ninputs,
1216 n, addr, collect);
1217 }
1218 }
1219 break;
1220 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1221 * pass and replaced by an ir3-specifc version that adds the
1222 * dword-offset in the last source.
1223 */
1224 case nir_intrinsic_load_ssbo_ir3:
1225 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1226 break;
1227 case nir_intrinsic_store_ssbo_ir3:
1228 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1229 !ctx->s->info.fs.early_fragment_tests)
1230 ctx->so->no_earlyz = true;
1231 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1232 break;
1233 case nir_intrinsic_get_buffer_size:
1234 emit_intrinsic_ssbo_size(ctx, intr, dst);
1235 break;
1236 case nir_intrinsic_ssbo_atomic_add_ir3:
1237 case nir_intrinsic_ssbo_atomic_imin_ir3:
1238 case nir_intrinsic_ssbo_atomic_umin_ir3:
1239 case nir_intrinsic_ssbo_atomic_imax_ir3:
1240 case nir_intrinsic_ssbo_atomic_umax_ir3:
1241 case nir_intrinsic_ssbo_atomic_and_ir3:
1242 case nir_intrinsic_ssbo_atomic_or_ir3:
1243 case nir_intrinsic_ssbo_atomic_xor_ir3:
1244 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1245 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1246 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1247 !ctx->s->info.fs.early_fragment_tests)
1248 ctx->so->no_earlyz = true;
1249 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1250 break;
1251 case nir_intrinsic_load_shared:
1252 emit_intrinsic_load_shared(ctx, intr, dst);
1253 break;
1254 case nir_intrinsic_store_shared:
1255 emit_intrinsic_store_shared(ctx, intr);
1256 break;
1257 case nir_intrinsic_shared_atomic_add:
1258 case nir_intrinsic_shared_atomic_imin:
1259 case nir_intrinsic_shared_atomic_umin:
1260 case nir_intrinsic_shared_atomic_imax:
1261 case nir_intrinsic_shared_atomic_umax:
1262 case nir_intrinsic_shared_atomic_and:
1263 case nir_intrinsic_shared_atomic_or:
1264 case nir_intrinsic_shared_atomic_xor:
1265 case nir_intrinsic_shared_atomic_exchange:
1266 case nir_intrinsic_shared_atomic_comp_swap:
1267 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1268 break;
1269 case nir_intrinsic_image_deref_load:
1270 emit_intrinsic_load_image(ctx, intr, dst);
1271 break;
1272 case nir_intrinsic_image_deref_store:
1273 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1274 !ctx->s->info.fs.early_fragment_tests)
1275 ctx->so->no_earlyz = true;
1276 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1277 break;
1278 case nir_intrinsic_image_deref_size:
1279 emit_intrinsic_image_size(ctx, intr, dst);
1280 break;
1281 case nir_intrinsic_image_deref_atomic_add:
1282 case nir_intrinsic_image_deref_atomic_min:
1283 case nir_intrinsic_image_deref_atomic_max:
1284 case nir_intrinsic_image_deref_atomic_and:
1285 case nir_intrinsic_image_deref_atomic_or:
1286 case nir_intrinsic_image_deref_atomic_xor:
1287 case nir_intrinsic_image_deref_atomic_exchange:
1288 case nir_intrinsic_image_deref_atomic_comp_swap:
1289 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1290 !ctx->s->info.fs.early_fragment_tests)
1291 ctx->so->no_earlyz = true;
1292 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1293 break;
1294 case nir_intrinsic_barrier:
1295 case nir_intrinsic_memory_barrier:
1296 case nir_intrinsic_group_memory_barrier:
1297 case nir_intrinsic_memory_barrier_atomic_counter:
1298 case nir_intrinsic_memory_barrier_buffer:
1299 case nir_intrinsic_memory_barrier_image:
1300 case nir_intrinsic_memory_barrier_shared:
1301 emit_intrinsic_barrier(ctx, intr);
1302 /* note that blk ptr no longer valid, make that obvious: */
1303 b = NULL;
1304 break;
1305 case nir_intrinsic_store_output:
1306 idx = nir_intrinsic_base(intr);
1307 comp = nir_intrinsic_component(intr);
1308 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1309 idx += nir_src_as_uint(intr->src[1]);
1310
1311 src = ir3_get_src(ctx, &intr->src[0]);
1312 for (int i = 0; i < intr->num_components; i++) {
1313 unsigned n = idx * 4 + i + comp;
1314 ctx->ir->outputs[n] = src[i];
1315 }
1316 break;
1317 case nir_intrinsic_load_base_vertex:
1318 case nir_intrinsic_load_first_vertex:
1319 if (!ctx->basevertex) {
1320 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1321 add_sysval_input(ctx, SYSTEM_VALUE_FIRST_VERTEX, ctx->basevertex);
1322 }
1323 dst[0] = ctx->basevertex;
1324 break;
1325 case nir_intrinsic_load_vertex_id_zero_base:
1326 case nir_intrinsic_load_vertex_id:
1327 if (!ctx->vertex_id) {
1328 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1329 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1330 ctx->vertex_id = create_input(ctx, 0);
1331 add_sysval_input(ctx, sv, ctx->vertex_id);
1332 }
1333 dst[0] = ctx->vertex_id;
1334 break;
1335 case nir_intrinsic_load_instance_id:
1336 if (!ctx->instance_id) {
1337 ctx->instance_id = create_input(ctx, 0);
1338 add_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID,
1339 ctx->instance_id);
1340 }
1341 dst[0] = ctx->instance_id;
1342 break;
1343 case nir_intrinsic_load_sample_id:
1344 case nir_intrinsic_load_sample_id_no_per_sample:
1345 if (!ctx->samp_id) {
1346 ctx->samp_id = create_input(ctx, 0);
1347 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1348 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID,
1349 ctx->samp_id);
1350 }
1351 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1352 break;
1353 case nir_intrinsic_load_sample_mask_in:
1354 if (!ctx->samp_mask_in) {
1355 ctx->samp_mask_in = create_input(ctx, 0);
1356 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN,
1357 ctx->samp_mask_in);
1358 }
1359 dst[0] = ctx->samp_mask_in;
1360 break;
1361 case nir_intrinsic_load_user_clip_plane:
1362 idx = nir_intrinsic_ucp_id(intr);
1363 for (int i = 0; i < intr->num_components; i++) {
1364 unsigned n = idx * 4 + i;
1365 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1366 }
1367 break;
1368 case nir_intrinsic_load_front_face:
1369 if (!ctx->frag_face) {
1370 ctx->so->frag_face = true;
1371 ctx->frag_face = create_input(ctx, 0);
1372 add_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, ctx->frag_face);
1373 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1374 }
1375 /* for fragface, we get -1 for back and 0 for front. However this is
1376 * the inverse of what nir expects (where ~0 is true).
1377 */
1378 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1379 dst[0] = ir3_NOT_B(b, dst[0], 0);
1380 break;
1381 case nir_intrinsic_load_local_invocation_id:
1382 if (!ctx->local_invocation_id) {
1383 ctx->local_invocation_id = create_input_compmask(ctx, 0, 0x7);
1384 add_sysval_input_compmask(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID,
1385 0x7, ctx->local_invocation_id);
1386 }
1387 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1388 break;
1389 case nir_intrinsic_load_work_group_id:
1390 if (!ctx->work_group_id) {
1391 ctx->work_group_id = create_input_compmask(ctx, 0, 0x7);
1392 add_sysval_input_compmask(ctx, SYSTEM_VALUE_WORK_GROUP_ID,
1393 0x7, ctx->work_group_id);
1394 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1395 }
1396 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1397 break;
1398 case nir_intrinsic_load_num_work_groups:
1399 for (int i = 0; i < intr->num_components; i++) {
1400 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1401 }
1402 break;
1403 case nir_intrinsic_load_local_group_size:
1404 for (int i = 0; i < intr->num_components; i++) {
1405 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1406 }
1407 break;
1408 case nir_intrinsic_discard_if:
1409 case nir_intrinsic_discard: {
1410 struct ir3_instruction *cond, *kill;
1411
1412 if (intr->intrinsic == nir_intrinsic_discard_if) {
1413 /* conditional discard: */
1414 src = ir3_get_src(ctx, &intr->src[0]);
1415 cond = ir3_b2n(b, src[0]);
1416 } else {
1417 /* unconditional discard: */
1418 cond = create_immed(b, 1);
1419 }
1420
1421 /* NOTE: only cmps.*.* can write p0.x: */
1422 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1423 cond->cat2.condition = IR3_COND_NE;
1424
1425 /* condition always goes in predicate register: */
1426 cond->regs[0]->num = regid(REG_P0, 0);
1427
1428 kill = ir3_KILL(b, cond, 0);
1429 array_insert(ctx->ir, ctx->ir->predicates, kill);
1430
1431 array_insert(b, b->keeps, kill);
1432 ctx->so->no_earlyz = true;
1433
1434 break;
1435 }
1436 default:
1437 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1438 nir_intrinsic_infos[intr->intrinsic].name);
1439 break;
1440 }
1441
1442 if (info->has_dest)
1443 ir3_put_dst(ctx, &intr->dest);
1444 }
1445
1446 static void
1447 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1448 {
1449 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1450 instr->def.num_components);
1451 type_t type = (instr->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1452
1453 for (int i = 0; i < instr->def.num_components; i++)
1454 dst[i] = create_immed_typed(ctx->block, instr->value[i].u32, type);
1455 }
1456
1457 static void
1458 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1459 {
1460 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1461 undef->def.num_components);
1462 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1463
1464 /* backend doesn't want undefined instructions, so just plug
1465 * in 0.0..
1466 */
1467 for (int i = 0; i < undef->def.num_components; i++)
1468 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1469 }
1470
1471 /*
1472 * texture fetch/sample instructions:
1473 */
1474
1475 static void
1476 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1477 {
1478 unsigned coords, flags = 0;
1479
1480 /* note: would use tex->coord_components.. except txs.. also,
1481 * since array index goes after shadow ref, we don't want to
1482 * count it:
1483 */
1484 switch (tex->sampler_dim) {
1485 case GLSL_SAMPLER_DIM_1D:
1486 case GLSL_SAMPLER_DIM_BUF:
1487 coords = 1;
1488 break;
1489 case GLSL_SAMPLER_DIM_2D:
1490 case GLSL_SAMPLER_DIM_RECT:
1491 case GLSL_SAMPLER_DIM_EXTERNAL:
1492 case GLSL_SAMPLER_DIM_MS:
1493 coords = 2;
1494 break;
1495 case GLSL_SAMPLER_DIM_3D:
1496 case GLSL_SAMPLER_DIM_CUBE:
1497 coords = 3;
1498 flags |= IR3_INSTR_3D;
1499 break;
1500 default:
1501 unreachable("bad sampler_dim");
1502 }
1503
1504 if (tex->is_shadow && tex->op != nir_texop_lod)
1505 flags |= IR3_INSTR_S;
1506
1507 if (tex->is_array && tex->op != nir_texop_lod)
1508 flags |= IR3_INSTR_A;
1509
1510 *flagsp = flags;
1511 *coordsp = coords;
1512 }
1513
1514 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1515 * or immediate (in which case it will get lowered later to a non .s2en
1516 * version of the tex instruction which encode tex/samp as immediates:
1517 */
1518 static struct ir3_instruction *
1519 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1520 {
1521 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1522 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1523 struct ir3_instruction *texture, *sampler;
1524
1525 if (texture_idx >= 0) {
1526 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1527 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1528 } else {
1529 /* TODO what to do for dynamic case? I guess we only need the
1530 * max index for astc srgb workaround so maybe not a problem
1531 * to worry about if we don't enable indirect samplers for
1532 * a4xx?
1533 */
1534 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1535 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1536 }
1537
1538 if (sampler_idx >= 0) {
1539 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1540 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1541 } else {
1542 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1543 }
1544
1545 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1546 sampler,
1547 texture,
1548 }, 2);
1549 }
1550
1551 static void
1552 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1553 {
1554 struct ir3_block *b = ctx->block;
1555 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1556 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1557 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1558 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1559 unsigned i, coords, flags, ncomp;
1560 unsigned nsrc0 = 0, nsrc1 = 0;
1561 type_t type;
1562 opc_t opc = 0;
1563
1564 ncomp = nir_dest_num_components(tex->dest);
1565
1566 coord = off = ddx = ddy = NULL;
1567 lod = proj = compare = sample_index = NULL;
1568
1569 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1570
1571 for (unsigned i = 0; i < tex->num_srcs; i++) {
1572 switch (tex->src[i].src_type) {
1573 case nir_tex_src_coord:
1574 coord = ir3_get_src(ctx, &tex->src[i].src);
1575 break;
1576 case nir_tex_src_bias:
1577 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1578 has_bias = true;
1579 break;
1580 case nir_tex_src_lod:
1581 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1582 has_lod = true;
1583 break;
1584 case nir_tex_src_comparator: /* shadow comparator */
1585 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1586 break;
1587 case nir_tex_src_projector:
1588 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1589 has_proj = true;
1590 break;
1591 case nir_tex_src_offset:
1592 off = ir3_get_src(ctx, &tex->src[i].src);
1593 has_off = true;
1594 break;
1595 case nir_tex_src_ddx:
1596 ddx = ir3_get_src(ctx, &tex->src[i].src);
1597 break;
1598 case nir_tex_src_ddy:
1599 ddy = ir3_get_src(ctx, &tex->src[i].src);
1600 break;
1601 case nir_tex_src_ms_index:
1602 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
1603 break;
1604 case nir_tex_src_texture_offset:
1605 case nir_tex_src_sampler_offset:
1606 /* handled in get_tex_samp_src() */
1607 break;
1608 default:
1609 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
1610 tex->src[i].src_type);
1611 return;
1612 }
1613 }
1614
1615 switch (tex->op) {
1616 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
1617 case nir_texop_txb: opc = OPC_SAMB; break;
1618 case nir_texop_txl: opc = OPC_SAML; break;
1619 case nir_texop_txd: opc = OPC_SAMGQ; break;
1620 case nir_texop_txf: opc = OPC_ISAML; break;
1621 case nir_texop_lod: opc = OPC_GETLOD; break;
1622 case nir_texop_tg4:
1623 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1624 * what blob does, seems gather is broken?), and a3xx did
1625 * not support it (but probably could also emulate).
1626 */
1627 switch (tex->component) {
1628 case 0: opc = OPC_GATHER4R; break;
1629 case 1: opc = OPC_GATHER4G; break;
1630 case 2: opc = OPC_GATHER4B; break;
1631 case 3: opc = OPC_GATHER4A; break;
1632 }
1633 break;
1634 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
1635 case nir_texop_txs:
1636 case nir_texop_query_levels:
1637 case nir_texop_texture_samples:
1638 case nir_texop_samples_identical:
1639 case nir_texop_txf_ms_mcs:
1640 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
1641 return;
1642 }
1643
1644 tex_info(tex, &flags, &coords);
1645
1646 /*
1647 * lay out the first argument in the proper order:
1648 * - actual coordinates first
1649 * - shadow reference
1650 * - array index
1651 * - projection w
1652 * - starting at offset 4, dpdx.xy, dpdy.xy
1653 *
1654 * bias/lod go into the second arg
1655 */
1656
1657 /* insert tex coords: */
1658 for (i = 0; i < coords; i++)
1659 src0[i] = coord[i];
1660
1661 nsrc0 = i;
1662
1663 /* scale up integer coords for TXF based on the LOD */
1664 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
1665 assert(has_lod);
1666 for (i = 0; i < coords; i++)
1667 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
1668 }
1669
1670 if (coords == 1) {
1671 /* hw doesn't do 1d, so we treat it as 2d with
1672 * height of 1, and patch up the y coord.
1673 */
1674 if (is_isam(opc)) {
1675 src0[nsrc0++] = create_immed(b, 0);
1676 } else {
1677 src0[nsrc0++] = create_immed(b, fui(0.5));
1678 }
1679 }
1680
1681 if (tex->is_shadow && tex->op != nir_texop_lod)
1682 src0[nsrc0++] = compare;
1683
1684 if (tex->is_array && tex->op != nir_texop_lod) {
1685 struct ir3_instruction *idx = coord[coords];
1686
1687 /* the array coord for cube arrays needs 0.5 added to it */
1688 if (ctx->compiler->array_index_add_half && !is_isam(opc))
1689 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
1690
1691 src0[nsrc0++] = idx;
1692 }
1693
1694 if (has_proj) {
1695 src0[nsrc0++] = proj;
1696 flags |= IR3_INSTR_P;
1697 }
1698
1699 /* pad to 4, then ddx/ddy: */
1700 if (tex->op == nir_texop_txd) {
1701 while (nsrc0 < 4)
1702 src0[nsrc0++] = create_immed(b, fui(0.0));
1703 for (i = 0; i < coords; i++)
1704 src0[nsrc0++] = ddx[i];
1705 if (coords < 2)
1706 src0[nsrc0++] = create_immed(b, fui(0.0));
1707 for (i = 0; i < coords; i++)
1708 src0[nsrc0++] = ddy[i];
1709 if (coords < 2)
1710 src0[nsrc0++] = create_immed(b, fui(0.0));
1711 }
1712
1713 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
1714 * with scaled x coord according to requested sample:
1715 */
1716 if (tex->op == nir_texop_txf_ms) {
1717 if (ctx->compiler->txf_ms_with_isaml) {
1718 /* the samples are laid out in x dimension as
1719 * 0 1 2 3
1720 * x_ms = (x << ms) + sample_index;
1721 */
1722 struct ir3_instruction *ms;
1723 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
1724
1725 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
1726 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
1727
1728 opc = OPC_ISAML;
1729 } else {
1730 src0[nsrc0++] = sample_index;
1731 }
1732 }
1733
1734 /*
1735 * second argument (if applicable):
1736 * - offsets
1737 * - lod
1738 * - bias
1739 */
1740 if (has_off | has_lod | has_bias) {
1741 if (has_off) {
1742 unsigned off_coords = coords;
1743 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
1744 off_coords--;
1745 for (i = 0; i < off_coords; i++)
1746 src1[nsrc1++] = off[i];
1747 if (off_coords < 2)
1748 src1[nsrc1++] = create_immed(b, fui(0.0));
1749 flags |= IR3_INSTR_O;
1750 }
1751
1752 if (has_lod | has_bias)
1753 src1[nsrc1++] = lod;
1754 }
1755
1756 switch (tex->dest_type) {
1757 case nir_type_invalid:
1758 case nir_type_float:
1759 type = TYPE_F32;
1760 break;
1761 case nir_type_int:
1762 type = TYPE_S32;
1763 break;
1764 case nir_type_uint:
1765 case nir_type_bool:
1766 type = TYPE_U32;
1767 break;
1768 default:
1769 unreachable("bad dest_type");
1770 }
1771
1772 if (opc == OPC_GETLOD)
1773 type = TYPE_U32;
1774
1775 struct ir3_instruction *samp_tex = get_tex_samp_tex_src(ctx, tex);
1776 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
1777 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
1778
1779 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
1780 samp_tex, col0, col1);
1781
1782 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
1783 /* only need first 3 components: */
1784 sam->regs[0]->wrmask = 0x7;
1785 ir3_split_dest(b, dst, sam, 0, 3);
1786
1787 /* we need to sample the alpha separately with a non-ASTC
1788 * texture state:
1789 */
1790 sam = ir3_SAM(b, opc, type, 0b1000, flags,
1791 samp_tex, col0, col1);
1792
1793 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
1794
1795 /* fixup .w component: */
1796 ir3_split_dest(b, &dst[3], sam, 3, 1);
1797 } else {
1798 /* normal (non-workaround) case: */
1799 ir3_split_dest(b, dst, sam, 0, ncomp);
1800 }
1801
1802 /* GETLOD returns results in 4.8 fixed point */
1803 if (opc == OPC_GETLOD) {
1804 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
1805
1806 compile_assert(ctx, tex->dest_type == nir_type_float);
1807 for (i = 0; i < 2; i++) {
1808 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_U32, TYPE_F32), 0,
1809 factor, 0);
1810 }
1811 }
1812
1813 ir3_put_dst(ctx, &tex->dest);
1814 }
1815
1816 static void
1817 emit_tex_query_levels(struct ir3_context *ctx, nir_tex_instr *tex)
1818 {
1819 struct ir3_block *b = ctx->block;
1820 struct ir3_instruction **dst, *sam;
1821
1822 dst = ir3_get_dst(ctx, &tex->dest, 1);
1823
1824 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, 0b0100, 0,
1825 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
1826
1827 /* even though there is only one component, since it ends
1828 * up in .z rather than .x, we need a split_dest()
1829 */
1830 ir3_split_dest(b, dst, sam, 0, 3);
1831
1832 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1833 * the value in TEX_CONST_0 is zero-based.
1834 */
1835 if (ctx->compiler->levels_add_one)
1836 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
1837
1838 ir3_put_dst(ctx, &tex->dest);
1839 }
1840
1841 static void
1842 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
1843 {
1844 struct ir3_block *b = ctx->block;
1845 struct ir3_instruction **dst, *sam;
1846 struct ir3_instruction *lod;
1847 unsigned flags, coords;
1848
1849 tex_info(tex, &flags, &coords);
1850
1851 /* Actually we want the number of dimensions, not coordinates. This
1852 * distinction only matters for cubes.
1853 */
1854 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
1855 coords = 2;
1856
1857 dst = ir3_get_dst(ctx, &tex->dest, 4);
1858
1859 compile_assert(ctx, tex->num_srcs == 1);
1860 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
1861
1862 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
1863
1864 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
1865 get_tex_samp_tex_src(ctx, tex), lod, NULL);
1866
1867 ir3_split_dest(b, dst, sam, 0, 4);
1868
1869 /* Array size actually ends up in .w rather than .z. This doesn't
1870 * matter for miplevel 0, but for higher mips the value in z is
1871 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1872 * returned, which means that we have to add 1 to it for arrays.
1873 */
1874 if (tex->is_array) {
1875 if (ctx->compiler->levels_add_one) {
1876 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
1877 } else {
1878 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
1879 }
1880 }
1881
1882 ir3_put_dst(ctx, &tex->dest);
1883 }
1884
1885 static void
1886 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
1887 {
1888 switch (jump->type) {
1889 case nir_jump_break:
1890 case nir_jump_continue:
1891 case nir_jump_return:
1892 /* I *think* we can simply just ignore this, and use the
1893 * successor block link to figure out where we need to
1894 * jump to for break/continue
1895 */
1896 break;
1897 default:
1898 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
1899 break;
1900 }
1901 }
1902
1903 static void
1904 emit_instr(struct ir3_context *ctx, nir_instr *instr)
1905 {
1906 switch (instr->type) {
1907 case nir_instr_type_alu:
1908 emit_alu(ctx, nir_instr_as_alu(instr));
1909 break;
1910 case nir_instr_type_deref:
1911 /* ignored, handled as part of the intrinsic they are src to */
1912 break;
1913 case nir_instr_type_intrinsic:
1914 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1915 break;
1916 case nir_instr_type_load_const:
1917 emit_load_const(ctx, nir_instr_as_load_const(instr));
1918 break;
1919 case nir_instr_type_ssa_undef:
1920 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
1921 break;
1922 case nir_instr_type_tex: {
1923 nir_tex_instr *tex = nir_instr_as_tex(instr);
1924 /* couple tex instructions get special-cased:
1925 */
1926 switch (tex->op) {
1927 case nir_texop_txs:
1928 emit_tex_txs(ctx, tex);
1929 break;
1930 case nir_texop_query_levels:
1931 emit_tex_query_levels(ctx, tex);
1932 break;
1933 default:
1934 emit_tex(ctx, tex);
1935 break;
1936 }
1937 break;
1938 }
1939 case nir_instr_type_jump:
1940 emit_jump(ctx, nir_instr_as_jump(instr));
1941 break;
1942 case nir_instr_type_phi:
1943 /* we have converted phi webs to regs in NIR by now */
1944 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
1945 break;
1946 case nir_instr_type_call:
1947 case nir_instr_type_parallel_copy:
1948 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
1949 break;
1950 }
1951 }
1952
1953 static struct ir3_block *
1954 get_block(struct ir3_context *ctx, const nir_block *nblock)
1955 {
1956 struct ir3_block *block;
1957 struct hash_entry *hentry;
1958 unsigned i;
1959
1960 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
1961 if (hentry)
1962 return hentry->data;
1963
1964 block = ir3_block_create(ctx->ir);
1965 block->nblock = nblock;
1966 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
1967
1968 block->predecessors_count = nblock->predecessors->entries;
1969 block->predecessors = ralloc_array_size(block,
1970 sizeof(block->predecessors[0]), block->predecessors_count);
1971 i = 0;
1972 set_foreach(nblock->predecessors, sentry) {
1973 block->predecessors[i++] = get_block(ctx, sentry->key);
1974 }
1975
1976 return block;
1977 }
1978
1979 static void
1980 emit_block(struct ir3_context *ctx, nir_block *nblock)
1981 {
1982 struct ir3_block *block = get_block(ctx, nblock);
1983
1984 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
1985 if (nblock->successors[i]) {
1986 block->successors[i] =
1987 get_block(ctx, nblock->successors[i]);
1988 }
1989 }
1990
1991 ctx->block = block;
1992 list_addtail(&block->node, &ctx->ir->block_list);
1993
1994 /* re-emit addr register in each block if needed: */
1995 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
1996 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
1997 ctx->addr_ht[i] = NULL;
1998 }
1999
2000 nir_foreach_instr(instr, nblock) {
2001 ctx->cur_instr = instr;
2002 emit_instr(ctx, instr);
2003 ctx->cur_instr = NULL;
2004 if (ctx->error)
2005 return;
2006 }
2007 }
2008
2009 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2010
2011 static void
2012 emit_if(struct ir3_context *ctx, nir_if *nif)
2013 {
2014 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2015
2016 ctx->block->condition =
2017 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2018
2019 emit_cf_list(ctx, &nif->then_list);
2020 emit_cf_list(ctx, &nif->else_list);
2021 }
2022
2023 static void
2024 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2025 {
2026 emit_cf_list(ctx, &nloop->body);
2027 }
2028
2029 static void
2030 stack_push(struct ir3_context *ctx)
2031 {
2032 ctx->stack++;
2033 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2034 }
2035
2036 static void
2037 stack_pop(struct ir3_context *ctx)
2038 {
2039 compile_assert(ctx, ctx->stack > 0);
2040 ctx->stack--;
2041 }
2042
2043 static void
2044 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2045 {
2046 foreach_list_typed(nir_cf_node, node, node, list) {
2047 switch (node->type) {
2048 case nir_cf_node_block:
2049 emit_block(ctx, nir_cf_node_as_block(node));
2050 break;
2051 case nir_cf_node_if:
2052 stack_push(ctx);
2053 emit_if(ctx, nir_cf_node_as_if(node));
2054 stack_pop(ctx);
2055 break;
2056 case nir_cf_node_loop:
2057 stack_push(ctx);
2058 emit_loop(ctx, nir_cf_node_as_loop(node));
2059 stack_pop(ctx);
2060 break;
2061 case nir_cf_node_function:
2062 ir3_context_error(ctx, "TODO\n");
2063 break;
2064 }
2065 }
2066 }
2067
2068 /* emit stream-out code. At this point, the current block is the original
2069 * (nir) end block, and nir ensures that all flow control paths terminate
2070 * into the end block. We re-purpose the original end block to generate
2071 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2072 * block holding stream-out write instructions, followed by the new end
2073 * block:
2074 *
2075 * blockOrigEnd {
2076 * p0.x = (vtxcnt < maxvtxcnt)
2077 * // succs: blockStreamOut, blockNewEnd
2078 * }
2079 * blockStreamOut {
2080 * ... stream-out instructions ...
2081 * // succs: blockNewEnd
2082 * }
2083 * blockNewEnd {
2084 * }
2085 */
2086 static void
2087 emit_stream_out(struct ir3_context *ctx)
2088 {
2089 struct ir3_shader_variant *v = ctx->so;
2090 struct ir3 *ir = ctx->ir;
2091 struct ir3_stream_output_info *strmout =
2092 &ctx->so->shader->stream_output;
2093 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2094 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2095 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2096
2097 /* create vtxcnt input in input block at top of shader,
2098 * so that it is seen as live over the entire duration
2099 * of the shader:
2100 */
2101 vtxcnt = create_input(ctx, 0);
2102 add_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, vtxcnt);
2103
2104 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2105
2106 /* at this point, we are at the original 'end' block,
2107 * re-purpose this block to stream-out condition, then
2108 * append stream-out block and new-end block
2109 */
2110 orig_end_block = ctx->block;
2111
2112 // TODO these blocks need to update predecessors..
2113 // maybe w/ store_global intrinsic, we could do this
2114 // stuff in nir->nir pass
2115
2116 stream_out_block = ir3_block_create(ir);
2117 list_addtail(&stream_out_block->node, &ir->block_list);
2118
2119 new_end_block = ir3_block_create(ir);
2120 list_addtail(&new_end_block->node, &ir->block_list);
2121
2122 orig_end_block->successors[0] = stream_out_block;
2123 orig_end_block->successors[1] = new_end_block;
2124 stream_out_block->successors[0] = new_end_block;
2125
2126 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2127 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2128 cond->regs[0]->num = regid(REG_P0, 0);
2129 cond->cat2.condition = IR3_COND_LT;
2130
2131 /* condition goes on previous block to the conditional,
2132 * since it is used to pick which of the two successor
2133 * paths to take:
2134 */
2135 orig_end_block->condition = cond;
2136
2137 /* switch to stream_out_block to generate the stream-out
2138 * instructions:
2139 */
2140 ctx->block = stream_out_block;
2141
2142 /* Calculate base addresses based on vtxcnt. Instructions
2143 * generated for bases not used in following loop will be
2144 * stripped out in the backend.
2145 */
2146 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2147 unsigned stride = strmout->stride[i];
2148 struct ir3_instruction *base, *off;
2149
2150 base = create_uniform(ctx->block, regid(v->constbase.tfbo, i));
2151
2152 /* 24-bit should be enough: */
2153 off = ir3_MUL_U(ctx->block, vtxcnt, 0,
2154 create_immed(ctx->block, stride * 4), 0);
2155
2156 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2157 }
2158
2159 /* Generate the per-output store instructions: */
2160 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2161 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2162 unsigned c = j + strmout->output[i].start_component;
2163 struct ir3_instruction *base, *out, *stg;
2164
2165 base = bases[strmout->output[i].output_buffer];
2166 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2167
2168 stg = ir3_STG(ctx->block, base, 0, out, 0,
2169 create_immed(ctx->block, 1), 0);
2170 stg->cat6.type = TYPE_U32;
2171 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2172
2173 array_insert(ctx->block, ctx->block->keeps, stg);
2174 }
2175 }
2176
2177 /* and finally switch to the new_end_block: */
2178 ctx->block = new_end_block;
2179 }
2180
2181 static void
2182 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2183 {
2184 nir_metadata_require(impl, nir_metadata_block_index);
2185
2186 compile_assert(ctx, ctx->stack == 0);
2187
2188 emit_cf_list(ctx, &impl->body);
2189 emit_block(ctx, impl->end_block);
2190
2191 compile_assert(ctx, ctx->stack == 0);
2192
2193 /* at this point, we should have a single empty block,
2194 * into which we emit the 'end' instruction.
2195 */
2196 compile_assert(ctx, list_empty(&ctx->block->instr_list));
2197
2198 /* If stream-out (aka transform-feedback) enabled, emit the
2199 * stream-out instructions, followed by a new empty block (into
2200 * which the 'end' instruction lands).
2201 *
2202 * NOTE: it is done in this order, rather than inserting before
2203 * we emit end_block, because NIR guarantees that all blocks
2204 * flow into end_block, and that end_block has no successors.
2205 * So by re-purposing end_block as the first block of stream-
2206 * out, we guarantee that all exit paths flow into the stream-
2207 * out instructions.
2208 */
2209 if ((ctx->compiler->gpu_id < 500) &&
2210 (ctx->so->shader->stream_output.num_outputs > 0) &&
2211 !ctx->so->binning_pass) {
2212 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2213 emit_stream_out(ctx);
2214 }
2215
2216 ir3_END(ctx->block);
2217 }
2218
2219 static struct ir3_instruction *
2220 create_frag_coord(struct ir3_context *ctx, unsigned comp)
2221 {
2222 struct ir3_block *block = ctx->block;
2223 struct ir3_instruction *instr;
2224
2225 if (!ctx->frag_coord) {
2226 ctx->frag_coord = create_input_compmask(ctx, 0, 0xf);
2227 /* defer add_sysval_input() until after all inputs created */
2228 }
2229
2230 ir3_split_dest(block, &instr, ctx->frag_coord, comp, 1);
2231
2232 switch (comp) {
2233 case 0: /* .x */
2234 case 1: /* .y */
2235 /* for frag_coord, we get unsigned values.. we need
2236 * to subtract (integer) 8 and divide by 16 (right-
2237 * shift by 4) then convert to float:
2238 *
2239 * sub.s tmp, src, 8
2240 * shr.b tmp, tmp, 4
2241 * mov.u32f32 dst, tmp
2242 *
2243 */
2244 instr = ir3_SUB_S(block, instr, 0,
2245 create_immed(block, 8), 0);
2246 instr = ir3_SHR_B(block, instr, 0,
2247 create_immed(block, 4), 0);
2248 instr = ir3_COV(block, instr, TYPE_U32, TYPE_F32);
2249
2250 return instr;
2251 case 2: /* .z */
2252 case 3: /* .w */
2253 default:
2254 /* seems that we can use these as-is: */
2255 return instr;
2256 }
2257 }
2258
2259 static void
2260 setup_input(struct ir3_context *ctx, nir_variable *in)
2261 {
2262 struct ir3_shader_variant *so = ctx->so;
2263 unsigned ncomp = glsl_get_components(in->type);
2264 unsigned n = in->data.driver_location;
2265 unsigned frac = in->data.location_frac;
2266 unsigned slot = in->data.location;
2267
2268 /* skip unread inputs, we could end up with (for example), unsplit
2269 * matrix/etc inputs in the case they are not read, so just silently
2270 * skip these.
2271 */
2272 if (ncomp > 4)
2273 return;
2274
2275 so->inputs[n].slot = slot;
2276 so->inputs[n].compmask = (1 << (ncomp + frac)) - 1;
2277 so->inputs_count = MAX2(so->inputs_count, n + 1);
2278 so->inputs[n].interpolate = in->data.interpolation;
2279
2280 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2281 for (int i = 0; i < ncomp; i++) {
2282 struct ir3_instruction *instr = NULL;
2283 unsigned idx = (n * 4) + i + frac;
2284
2285 if (slot == VARYING_SLOT_POS) {
2286 so->inputs[n].bary = false;
2287 so->frag_coord = true;
2288 instr = create_frag_coord(ctx, i);
2289 } else if (slot == VARYING_SLOT_PNTC) {
2290 /* see for example st_nir_fixup_varying_slots().. this is
2291 * maybe a bit mesa/st specific. But we need things to line
2292 * up for this in fdN_program:
2293 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2294 * if (emit->sprite_coord_enable & texmask) {
2295 * ...
2296 * }
2297 */
2298 so->inputs[n].slot = VARYING_SLOT_VAR8;
2299 so->inputs[n].bary = true;
2300 instr = create_frag_input(ctx, false, idx);
2301 } else {
2302 bool use_ldlv = false;
2303
2304 /* detect the special case for front/back colors where
2305 * we need to do flat vs smooth shading depending on
2306 * rast state:
2307 */
2308 if (in->data.interpolation == INTERP_MODE_NONE) {
2309 switch (slot) {
2310 case VARYING_SLOT_COL0:
2311 case VARYING_SLOT_COL1:
2312 case VARYING_SLOT_BFC0:
2313 case VARYING_SLOT_BFC1:
2314 so->inputs[n].rasterflat = true;
2315 break;
2316 default:
2317 break;
2318 }
2319 }
2320
2321 if (ctx->compiler->flat_bypass) {
2322 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2323 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2324 use_ldlv = true;
2325 }
2326
2327 so->inputs[n].bary = true;
2328
2329 instr = create_frag_input(ctx, use_ldlv, idx);
2330 }
2331
2332 compile_assert(ctx, idx < ctx->ir->ninputs);
2333
2334 ctx->ir->inputs[idx] = instr;
2335 }
2336 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2337 for (int i = 0; i < ncomp; i++) {
2338 unsigned idx = (n * 4) + i + frac;
2339 compile_assert(ctx, idx < ctx->ir->ninputs);
2340 ctx->ir->inputs[idx] = create_input(ctx, idx);
2341 }
2342 } else {
2343 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2344 }
2345
2346 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2347 so->total_in += ncomp;
2348 }
2349 }
2350
2351 /* Initially we assign non-packed inloc's for varyings, as we don't really
2352 * know up-front which components will be unused. After all the compilation
2353 * stages we scan the shader to see which components are actually used, and
2354 * re-pack the inlocs to eliminate unneeded varyings.
2355 */
2356 static void
2357 pack_inlocs(struct ir3_context *ctx)
2358 {
2359 struct ir3_shader_variant *so = ctx->so;
2360 uint8_t used_components[so->inputs_count];
2361
2362 memset(used_components, 0, sizeof(used_components));
2363
2364 /*
2365 * First Step: scan shader to find which bary.f/ldlv remain:
2366 */
2367
2368 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2369 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2370 if (is_input(instr)) {
2371 unsigned inloc = instr->regs[1]->iim_val;
2372 unsigned i = inloc / 4;
2373 unsigned j = inloc % 4;
2374
2375 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
2376 compile_assert(ctx, i < so->inputs_count);
2377
2378 used_components[i] |= 1 << j;
2379 }
2380 }
2381 }
2382
2383 /*
2384 * Second Step: reassign varying inloc/slots:
2385 */
2386
2387 unsigned actual_in = 0;
2388 unsigned inloc = 0;
2389
2390 for (unsigned i = 0; i < so->inputs_count; i++) {
2391 unsigned compmask = 0, maxcomp = 0;
2392
2393 so->inputs[i].ncomp = 0;
2394 so->inputs[i].inloc = inloc;
2395 so->inputs[i].bary = false;
2396
2397 for (unsigned j = 0; j < 4; j++) {
2398 if (!(used_components[i] & (1 << j)))
2399 continue;
2400
2401 compmask |= (1 << j);
2402 actual_in++;
2403 so->inputs[i].ncomp++;
2404 maxcomp = j + 1;
2405
2406 /* at this point, since used_components[i] mask is only
2407 * considering varyings (ie. not sysvals) we know this
2408 * is a varying:
2409 */
2410 so->inputs[i].bary = true;
2411 }
2412
2413 if (so->inputs[i].bary) {
2414 so->varying_in++;
2415 so->inputs[i].compmask = (1 << maxcomp) - 1;
2416 inloc += maxcomp;
2417 }
2418 }
2419
2420 /*
2421 * Third Step: reassign packed inloc's:
2422 */
2423
2424 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2425 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2426 if (is_input(instr)) {
2427 unsigned inloc = instr->regs[1]->iim_val;
2428 unsigned i = inloc / 4;
2429 unsigned j = inloc % 4;
2430
2431 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
2432 }
2433 }
2434 }
2435 }
2436
2437 static void
2438 setup_output(struct ir3_context *ctx, nir_variable *out)
2439 {
2440 struct ir3_shader_variant *so = ctx->so;
2441 unsigned ncomp = glsl_get_components(out->type);
2442 unsigned n = out->data.driver_location;
2443 unsigned frac = out->data.location_frac;
2444 unsigned slot = out->data.location;
2445 unsigned comp = 0;
2446
2447 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2448 switch (slot) {
2449 case FRAG_RESULT_DEPTH:
2450 comp = 2; /* tgsi will write to .z component */
2451 so->writes_pos = true;
2452 break;
2453 case FRAG_RESULT_COLOR:
2454 so->color0_mrt = 1;
2455 break;
2456 default:
2457 if (slot >= FRAG_RESULT_DATA0)
2458 break;
2459 ir3_context_error(ctx, "unknown FS output name: %s\n",
2460 gl_frag_result_name(slot));
2461 }
2462 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2463 switch (slot) {
2464 case VARYING_SLOT_POS:
2465 so->writes_pos = true;
2466 break;
2467 case VARYING_SLOT_PSIZ:
2468 so->writes_psize = true;
2469 break;
2470 case VARYING_SLOT_COL0:
2471 case VARYING_SLOT_COL1:
2472 case VARYING_SLOT_BFC0:
2473 case VARYING_SLOT_BFC1:
2474 case VARYING_SLOT_FOGC:
2475 case VARYING_SLOT_CLIP_DIST0:
2476 case VARYING_SLOT_CLIP_DIST1:
2477 case VARYING_SLOT_CLIP_VERTEX:
2478 break;
2479 default:
2480 if (slot >= VARYING_SLOT_VAR0)
2481 break;
2482 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2483 break;
2484 ir3_context_error(ctx, "unknown VS output name: %s\n",
2485 gl_varying_slot_name(slot));
2486 }
2487 } else {
2488 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2489 }
2490
2491 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2492
2493 so->outputs[n].slot = slot;
2494 so->outputs[n].regid = regid(n, comp);
2495 so->outputs_count = MAX2(so->outputs_count, n + 1);
2496
2497 for (int i = 0; i < ncomp; i++) {
2498 unsigned idx = (n * 4) + i + frac;
2499 compile_assert(ctx, idx < ctx->ir->noutputs);
2500 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2501 }
2502
2503 /* if varying packing doesn't happen, we could end up in a situation
2504 * with "holes" in the output, and since the per-generation code that
2505 * sets up varying linkage registers doesn't expect to have more than
2506 * one varying per vec4 slot, pad the holes.
2507 *
2508 * Note that this should probably generate a performance warning of
2509 * some sort.
2510 */
2511 for (int i = 0; i < frac; i++) {
2512 unsigned idx = (n * 4) + i;
2513 if (!ctx->ir->outputs[idx]) {
2514 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2515 }
2516 }
2517 }
2518
2519 static int
2520 max_drvloc(struct exec_list *vars)
2521 {
2522 int drvloc = -1;
2523 nir_foreach_variable(var, vars) {
2524 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2525 }
2526 return drvloc;
2527 }
2528
2529 static const unsigned max_sysvals[] = {
2530 [MESA_SHADER_FRAGMENT] = 24, // TODO
2531 [MESA_SHADER_VERTEX] = 16,
2532 [MESA_SHADER_COMPUTE] = 16, // TODO how many do we actually need?
2533 [MESA_SHADER_KERNEL] = 16, // TODO how many do we actually need?
2534 };
2535
2536 static void
2537 emit_instructions(struct ir3_context *ctx)
2538 {
2539 unsigned ninputs, noutputs;
2540 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
2541
2542 ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
2543 noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
2544
2545 /* we need to leave room for sysvals:
2546 */
2547 ninputs += max_sysvals[ctx->so->type];
2548
2549 ctx->ir = ir3_create(ctx->compiler, ctx->so->type, ninputs, noutputs);
2550
2551 /* Create inputs in first block: */
2552 ctx->block = get_block(ctx, nir_start_block(fxn));
2553 ctx->in_block = ctx->block;
2554 list_addtail(&ctx->block->node, &ctx->ir->block_list);
2555
2556 ninputs -= max_sysvals[ctx->so->type];
2557
2558 /* for fragment shader, the vcoord input register is used as the
2559 * base for bary.f varying fetch instrs:
2560 */
2561 struct ir3_instruction *vcoord = NULL;
2562 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2563 struct ir3_instruction *xy[2];
2564
2565 vcoord = create_input_compmask(ctx, 0, 0x3);
2566 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
2567
2568 ctx->frag_vcoord = ir3_create_collect(ctx, xy, 2);
2569 }
2570
2571 /* Setup inputs: */
2572 nir_foreach_variable(var, &ctx->s->inputs) {
2573 setup_input(ctx, var);
2574 }
2575
2576 /* Defer add_sysval_input() stuff until after setup_inputs(),
2577 * because sysvals need to be appended after varyings:
2578 */
2579 if (vcoord) {
2580 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PIXEL,
2581 0x3, vcoord);
2582 }
2583
2584 if (ctx->frag_coord) {
2585 add_sysval_input_compmask(ctx, SYSTEM_VALUE_FRAG_COORD,
2586 0xf, ctx->frag_coord);
2587 }
2588
2589 /* Setup outputs: */
2590 nir_foreach_variable(var, &ctx->s->outputs) {
2591 setup_output(ctx, var);
2592 }
2593
2594 /* Find # of samplers: */
2595 nir_foreach_variable(var, &ctx->s->uniforms) {
2596 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
2597 /* just assume that we'll be reading from images.. if it
2598 * is write-only we don't have to count it, but not sure
2599 * if there is a good way to know?
2600 */
2601 ctx->so->num_samp += glsl_type_get_image_count(var->type);
2602 }
2603
2604 /* NOTE: need to do something more clever when we support >1 fxn */
2605 nir_foreach_register(reg, &fxn->registers) {
2606 ir3_declare_array(ctx, reg);
2607 }
2608 /* And emit the body: */
2609 ctx->impl = fxn;
2610 emit_function(ctx, fxn);
2611 }
2612
2613 /* from NIR perspective, we actually have varying inputs. But the varying
2614 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
2615 * only actual inputs are the sysvals.
2616 */
2617 static void
2618 fixup_frag_inputs(struct ir3_context *ctx)
2619 {
2620 struct ir3_shader_variant *so = ctx->so;
2621 struct ir3 *ir = ctx->ir;
2622 unsigned i = 0;
2623
2624 /* sysvals should appear at the end of the inputs, drop everything else: */
2625 while ((i < so->inputs_count) && !so->inputs[i].sysval)
2626 i++;
2627
2628 /* at IR level, inputs are always blocks of 4 scalars: */
2629 i *= 4;
2630
2631 ir->inputs = &ir->inputs[i];
2632 ir->ninputs -= i;
2633 }
2634
2635 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2636 * need to assign the tex state indexes for these after we know the
2637 * max tex index.
2638 */
2639 static void
2640 fixup_astc_srgb(struct ir3_context *ctx)
2641 {
2642 struct ir3_shader_variant *so = ctx->so;
2643 /* indexed by original tex idx, value is newly assigned alpha sampler
2644 * state tex idx. Zero is invalid since there is at least one sampler
2645 * if we get here.
2646 */
2647 unsigned alt_tex_state[16] = {0};
2648 unsigned tex_idx = ctx->max_texture_index + 1;
2649 unsigned idx = 0;
2650
2651 so->astc_srgb.base = tex_idx;
2652
2653 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
2654 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
2655
2656 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
2657
2658 if (alt_tex_state[sam->cat5.tex] == 0) {
2659 /* assign new alternate/alpha tex state slot: */
2660 alt_tex_state[sam->cat5.tex] = tex_idx++;
2661 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
2662 so->astc_srgb.count++;
2663 }
2664
2665 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
2666 }
2667 }
2668
2669 static void
2670 fixup_binning_pass(struct ir3_context *ctx)
2671 {
2672 struct ir3_shader_variant *so = ctx->so;
2673 struct ir3 *ir = ctx->ir;
2674 unsigned i, j;
2675
2676 for (i = 0, j = 0; i < so->outputs_count; i++) {
2677 unsigned slot = so->outputs[i].slot;
2678
2679 /* throw away everything but first position/psize */
2680 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
2681 if (i != j) {
2682 so->outputs[j] = so->outputs[i];
2683 ir->outputs[(j*4)+0] = ir->outputs[(i*4)+0];
2684 ir->outputs[(j*4)+1] = ir->outputs[(i*4)+1];
2685 ir->outputs[(j*4)+2] = ir->outputs[(i*4)+2];
2686 ir->outputs[(j*4)+3] = ir->outputs[(i*4)+3];
2687 }
2688 j++;
2689 }
2690 }
2691 so->outputs_count = j;
2692 ir->noutputs = j * 4;
2693 }
2694
2695 int
2696 ir3_compile_shader_nir(struct ir3_compiler *compiler,
2697 struct ir3_shader_variant *so)
2698 {
2699 struct ir3_context *ctx;
2700 struct ir3 *ir;
2701 struct ir3_instruction **inputs;
2702 unsigned i;
2703 int ret = 0, max_bary;
2704
2705 assert(!so->ir);
2706
2707 ctx = ir3_context_init(compiler, so);
2708 if (!ctx) {
2709 DBG("INIT failed!");
2710 ret = -1;
2711 goto out;
2712 }
2713
2714 emit_instructions(ctx);
2715
2716 if (ctx->error) {
2717 DBG("EMIT failed!");
2718 ret = -1;
2719 goto out;
2720 }
2721
2722 ir = so->ir = ctx->ir;
2723
2724 /* keep track of the inputs from TGSI perspective.. */
2725 inputs = ir->inputs;
2726
2727 /* but fixup actual inputs for frag shader: */
2728 if (so->type == MESA_SHADER_FRAGMENT)
2729 fixup_frag_inputs(ctx);
2730
2731 /* at this point, for binning pass, throw away unneeded outputs: */
2732 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
2733 fixup_binning_pass(ctx);
2734
2735 /* if we want half-precision outputs, mark the output registers
2736 * as half:
2737 */
2738 if (so->key.half_precision) {
2739 for (i = 0; i < ir->noutputs; i++) {
2740 struct ir3_instruction *out = ir->outputs[i];
2741
2742 if (!out)
2743 continue;
2744
2745 /* if frag shader writes z, that needs to be full precision: */
2746 if (so->outputs[i/4].slot == FRAG_RESULT_DEPTH)
2747 continue;
2748
2749 out->regs[0]->flags |= IR3_REG_HALF;
2750 /* output could be a fanout (ie. texture fetch output)
2751 * in which case we need to propagate the half-reg flag
2752 * up to the definer so that RA sees it:
2753 */
2754 if (out->opc == OPC_META_FO) {
2755 out = out->regs[1]->instr;
2756 out->regs[0]->flags |= IR3_REG_HALF;
2757 }
2758
2759 if (out->opc == OPC_MOV) {
2760 out->cat1.dst_type = half_type(out->cat1.dst_type);
2761 }
2762 }
2763 }
2764
2765 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2766 printf("BEFORE CP:\n");
2767 ir3_print(ir);
2768 }
2769
2770 ir3_cp(ir, so);
2771
2772 /* at this point, for binning pass, throw away unneeded outputs:
2773 * Note that for a6xx and later, we do this after ir3_cp to ensure
2774 * that the uniform/constant layout for BS and VS matches, so that
2775 * we can re-use same VS_CONST state group.
2776 */
2777 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
2778 fixup_binning_pass(ctx);
2779
2780 /* Insert mov if there's same instruction for each output.
2781 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
2782 */
2783 for (int i = ir->noutputs - 1; i >= 0; i--) {
2784 if (!ir->outputs[i])
2785 continue;
2786 for (unsigned j = 0; j < i; j++) {
2787 if (ir->outputs[i] == ir->outputs[j]) {
2788 ir->outputs[i] =
2789 ir3_MOV(ir->outputs[i]->block, ir->outputs[i], TYPE_F32);
2790 }
2791 }
2792 }
2793
2794 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2795 printf("BEFORE GROUPING:\n");
2796 ir3_print(ir);
2797 }
2798
2799 ir3_sched_add_deps(ir);
2800
2801 /* Group left/right neighbors, inserting mov's where needed to
2802 * solve conflicts:
2803 */
2804 ir3_group(ir);
2805
2806 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2807 printf("AFTER GROUPING:\n");
2808 ir3_print(ir);
2809 }
2810
2811 ir3_depth(ir);
2812
2813 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2814 printf("AFTER DEPTH:\n");
2815 ir3_print(ir);
2816 }
2817
2818 /* do Sethi–Ullman numbering before scheduling: */
2819 ir3_sun(ir);
2820
2821 ret = ir3_sched(ir);
2822 if (ret) {
2823 DBG("SCHED failed!");
2824 goto out;
2825 }
2826
2827 if (compiler->gpu_id >= 600) {
2828 ir3_a6xx_fixup_atomic_dests(ir, so);
2829 }
2830
2831 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2832 printf("AFTER SCHED:\n");
2833 ir3_print(ir);
2834 }
2835
2836 ret = ir3_ra(ir, so->type, so->frag_coord, so->frag_face);
2837 if (ret) {
2838 DBG("RA failed!");
2839 goto out;
2840 }
2841
2842 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2843 printf("AFTER RA:\n");
2844 ir3_print(ir);
2845 }
2846
2847 if (so->type == MESA_SHADER_FRAGMENT)
2848 pack_inlocs(ctx);
2849
2850 /* fixup input/outputs: */
2851 for (i = 0; i < so->outputs_count; i++) {
2852 /* sometimes we get outputs that don't write the .x coord, like:
2853 *
2854 * decl_var shader_out INTERP_MODE_NONE float Color (VARYING_SLOT_VAR9.z, 1, 0)
2855 *
2856 * Presumably the result of varying packing and then eliminating
2857 * some unneeded varyings? Just skip head to the first valid
2858 * component of the output.
2859 */
2860 for (unsigned j = 0; j < 4; j++) {
2861 struct ir3_instruction *instr = ir->outputs[(i*4) + j];
2862 if (instr) {
2863 so->outputs[i].regid = instr->regs[0]->num;
2864 break;
2865 }
2866 }
2867 }
2868
2869 /* Note that some or all channels of an input may be unused: */
2870 for (i = 0; i < so->inputs_count; i++) {
2871 unsigned j, reg = regid(63,0);
2872 for (j = 0; j < 4; j++) {
2873 struct ir3_instruction *in = inputs[(i*4) + j];
2874
2875 if (in && !(in->flags & IR3_INSTR_UNUSED)) {
2876 reg = in->regs[0]->num - j;
2877 }
2878 }
2879 so->inputs[i].regid = reg;
2880 }
2881
2882 if (ctx->astc_srgb)
2883 fixup_astc_srgb(ctx);
2884
2885 /* We need to do legalize after (for frag shader's) the "bary.f"
2886 * offsets (inloc) have been assigned.
2887 */
2888 ir3_legalize(ir, &so->has_ssbo, &so->need_pixlod, &max_bary);
2889
2890 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2891 printf("AFTER LEGALIZE:\n");
2892 ir3_print(ir);
2893 }
2894
2895 so->branchstack = ctx->max_stack;
2896
2897 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
2898 if (so->type == MESA_SHADER_FRAGMENT)
2899 so->total_in = max_bary + 1;
2900
2901 so->max_sun = ir->max_sun;
2902
2903 out:
2904 if (ret) {
2905 if (so->ir)
2906 ir3_destroy(so->ir);
2907 so->ir = NULL;
2908 }
2909 ir3_context_free(ctx);
2910
2911 return ret;
2912 }