2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
38 #include "instr-a3xx.h"
40 #include "ir3_context.h"
43 static struct ir3_instruction
*
44 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
45 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
47 struct ir3_block
*block
= ctx
->block
;
48 struct ir3_instruction
*mov
;
49 struct ir3_register
*src
;
51 mov
= ir3_instr_create(block
, OPC_MOV
);
52 mov
->cat1
.src_type
= TYPE_U32
;
53 mov
->cat1
.dst_type
= TYPE_U32
;
55 src
= __ssa_src(mov
, collect
, IR3_REG_RELATIV
);
57 src
->array
.offset
= n
;
59 ir3_instr_set_address(mov
, address
);
64 static struct ir3_instruction
*
65 create_input(struct ir3_context
*ctx
, unsigned compmask
)
67 struct ir3_instruction
*in
;
69 in
= ir3_instr_create(ctx
->in_block
, OPC_META_INPUT
);
70 in
->input
.sysval
= ~0;
71 __ssa_dst(in
)->wrmask
= compmask
;
73 array_insert(ctx
->ir
, ctx
->ir
->inputs
, in
);
78 static struct ir3_instruction
*
79 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
, unsigned n
)
81 struct ir3_block
*block
= ctx
->block
;
82 struct ir3_instruction
*instr
;
83 /* packed inloc is fixed up later: */
84 struct ir3_instruction
*inloc
= create_immed(block
, n
);
87 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
88 instr
->cat6
.type
= TYPE_U32
;
89 instr
->cat6
.iim_val
= 1;
91 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->ij_pixel
, 0);
92 instr
->regs
[2]->wrmask
= 0x3;
98 static struct ir3_instruction
*
99 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
101 /* first four vec4 sysval's reserved for UBOs: */
102 /* NOTE: dp is in scalar, but there can be >4 dp components: */
103 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
104 unsigned n
= const_state
->offsets
.driver_param
;
105 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
106 return create_uniform(ctx
->block
, r
);
110 * Adreno's comparisons produce a 1 for true and 0 for false, in either 16 or
111 * 32-bit registers. We use NIR's 1-bit integers to represent bools, and
112 * trust that we will only see and/or/xor on those 1-bit values, so we can
113 * safely store NIR i1s in a 32-bit reg while always containing either a 1 or
118 * alu/sfu instructions:
121 static struct ir3_instruction
*
122 create_cov(struct ir3_context
*ctx
, struct ir3_instruction
*src
,
123 unsigned src_bitsize
, nir_op op
)
125 type_t src_type
, dst_type
;
129 case nir_op_f2f16_rtne
:
130 case nir_op_f2f16_rtz
:
138 switch (src_bitsize
) {
146 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
155 switch (src_bitsize
) {
166 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
175 switch (src_bitsize
) {
186 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
199 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
210 case nir_op_f2f16_rtne
:
211 case nir_op_f2f16_rtz
:
253 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
256 if (src_type
== dst_type
)
259 struct ir3_instruction
*cov
=
260 ir3_COV(ctx
->block
, src
, src_type
, dst_type
);
262 if (op
== nir_op_f2f16_rtne
)
263 cov
->regs
[0]->flags
|= IR3_REG_EVEN
;
269 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
271 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
272 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
273 unsigned bs
[info
->num_inputs
]; /* bit size */
274 struct ir3_block
*b
= ctx
->block
;
275 unsigned dst_sz
, wrmask
;
276 type_t dst_type
= nir_dest_bit_size(alu
->dest
.dest
) == 16 ?
279 if (alu
->dest
.dest
.is_ssa
) {
280 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
281 wrmask
= (1 << dst_sz
) - 1;
283 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
284 wrmask
= alu
->dest
.write_mask
;
287 dst
= ir3_get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
289 /* Vectors are special in that they have non-scalarized writemasks,
290 * and just take the first swizzle channel for each argument in
291 * order into each writemask channel.
293 if ((alu
->op
== nir_op_vec2
) ||
294 (alu
->op
== nir_op_vec3
) ||
295 (alu
->op
== nir_op_vec4
)) {
297 for (int i
= 0; i
< info
->num_inputs
; i
++) {
298 nir_alu_src
*asrc
= &alu
->src
[i
];
300 compile_assert(ctx
, !asrc
->abs
);
301 compile_assert(ctx
, !asrc
->negate
);
303 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
305 src
[i
] = create_immed_typed(ctx
->block
, 0, dst_type
);
306 dst
[i
] = ir3_MOV(b
, src
[i
], dst_type
);
309 ir3_put_dst(ctx
, &alu
->dest
.dest
);
313 /* We also get mov's with more than one component for mov's so
314 * handle those specially:
316 if (alu
->op
== nir_op_mov
) {
317 nir_alu_src
*asrc
= &alu
->src
[0];
318 struct ir3_instruction
*const *src0
= ir3_get_src(ctx
, &asrc
->src
);
320 for (unsigned i
= 0; i
< dst_sz
; i
++) {
321 if (wrmask
& (1 << i
)) {
322 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], dst_type
);
328 ir3_put_dst(ctx
, &alu
->dest
.dest
);
332 /* General case: We can just grab the one used channel per src. */
333 for (int i
= 0; i
< info
->num_inputs
; i
++) {
334 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
335 nir_alu_src
*asrc
= &alu
->src
[i
];
337 compile_assert(ctx
, !asrc
->abs
);
338 compile_assert(ctx
, !asrc
->negate
);
340 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
341 bs
[i
] = nir_src_bit_size(asrc
->src
);
343 compile_assert(ctx
, src
[i
]);
348 case nir_op_f2f16_rtne
:
349 case nir_op_f2f16_rtz
:
372 dst
[0] = create_cov(ctx
, src
[0], bs
[0], alu
->op
);
375 case nir_op_fquantize2f16
:
376 dst
[0] = create_cov(ctx
,
377 create_cov(ctx
, src
[0], 32, nir_op_f2f16
),
381 dst
[0] = ir3_CMPS_F(b
,
383 create_immed_typed(b
, 0, bs
[0] == 16 ? TYPE_F16
: TYPE_F32
), 0);
384 dst
[0]->cat2
.condition
= IR3_COND_NE
;
388 /* i2b1 will appear when translating from nir_load_ubo or
389 * nir_intrinsic_load_ssbo, where any non-zero value is true.
391 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
392 dst
[0]->cat2
.condition
= IR3_COND_NE
;
396 /* b2b1 will appear when translating from
398 * - nir_intrinsic_load_shared of a 32-bit 0/~0 value.
399 * - nir_intrinsic_load_constant of a 32-bit 0/~0 value
401 * A negate can turn those into a 1 or 0 for us.
403 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
407 /* b2b32 will appear when converting our 1-bit bools to a store_shared
410 * A negate can turn those into a ~0 for us.
412 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
416 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
419 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
422 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
425 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
428 /* if there is just a single use of the src, and it supports
429 * (sat) bit, we can just fold the (sat) flag back to the
430 * src instruction and create a mov. This is easier for cp
433 * TODO probably opc_cat==4 is ok too
435 if (alu
->src
[0].src
.is_ssa
&&
436 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
437 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
438 src
[0]->flags
|= IR3_INSTR_SAT
;
439 dst
[0] = ir3_MOV(b
, src
[0], dst_type
);
441 /* otherwise generate a max.f that saturates.. blob does
442 * similar (generating a cat2 mov using max.f)
444 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
445 dst
[0]->flags
|= IR3_INSTR_SAT
;
449 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
452 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
455 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
458 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
461 case nir_op_fddx_coarse
:
462 dst
[0] = ir3_DSX(b
, src
[0], 0);
463 dst
[0]->cat5
.type
= TYPE_F32
;
465 case nir_op_fddx_fine
:
466 dst
[0] = ir3_DSXPP_1(b
, src
[0], 0);
467 dst
[0]->cat5
.type
= TYPE_F32
;
470 case nir_op_fddy_coarse
:
471 dst
[0] = ir3_DSY(b
, src
[0], 0);
472 dst
[0]->cat5
.type
= TYPE_F32
;
475 case nir_op_fddy_fine
:
476 dst
[0] = ir3_DSYPP_1(b
, src
[0], 0);
477 dst
[0]->cat5
.type
= TYPE_F32
;
480 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
481 dst
[0]->cat2
.condition
= IR3_COND_LT
;
484 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
485 dst
[0]->cat2
.condition
= IR3_COND_GE
;
488 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
489 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
492 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
493 dst
[0]->cat2
.condition
= IR3_COND_NE
;
496 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
499 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
502 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
504 case nir_op_fround_even
:
505 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
508 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
512 dst
[0] = ir3_SIN(b
, src
[0], 0);
515 dst
[0] = ir3_COS(b
, src
[0], 0);
518 dst
[0] = ir3_RSQ(b
, src
[0], 0);
521 dst
[0] = ir3_RCP(b
, src
[0], 0);
524 dst
[0] = ir3_LOG2(b
, src
[0], 0);
527 dst
[0] = ir3_EXP2(b
, src
[0], 0);
530 dst
[0] = ir3_SQRT(b
, src
[0], 0);
534 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
537 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
540 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
543 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
546 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
549 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
552 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
554 case nir_op_umul_low
:
555 dst
[0] = ir3_MULL_U(b
, src
[0], 0, src
[1], 0);
557 case nir_op_imadsh_mix16
:
558 dst
[0] = ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0, src
[2], 0);
560 case nir_op_imad24_ir3
:
561 dst
[0] = ir3_MAD_S24(b
, src
[0], 0, src
[1], 0, src
[2], 0);
564 dst
[0] = ir3_MUL_S24(b
, src
[0], 0, src
[1], 0);
567 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
571 dst
[0] = ir3_SUB_U(b
, create_immed(ctx
->block
, 1), 0, src
[0], 0);
573 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
577 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
580 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
583 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
586 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
589 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
592 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
595 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
596 dst
[0]->cat2
.condition
= IR3_COND_LT
;
599 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
600 dst
[0]->cat2
.condition
= IR3_COND_GE
;
603 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
604 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
607 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
608 dst
[0]->cat2
.condition
= IR3_COND_NE
;
611 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
612 dst
[0]->cat2
.condition
= IR3_COND_LT
;
615 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
616 dst
[0]->cat2
.condition
= IR3_COND_GE
;
620 struct ir3_instruction
*cond
= src
[0];
622 /* If src[0] is a negation (likely as a result of an ir3_b2n(cond)),
623 * we can ignore that and use original cond, since the nonzero-ness of
624 * cond stays the same.
626 if (cond
->opc
== OPC_ABSNEG_S
&&
628 (cond
->regs
[1]->flags
& (IR3_REG_SNEG
| IR3_REG_SABS
)) == IR3_REG_SNEG
) {
629 cond
= cond
->regs
[1]->instr
;
632 compile_assert(ctx
, bs
[1] == bs
[2]);
633 /* The condition's size has to match the other two arguments' size, so
634 * convert down if necessary.
637 struct hash_entry
*prev_entry
=
638 _mesa_hash_table_search(ctx
->sel_cond_conversions
, src
[0]);
640 cond
= prev_entry
->data
;
642 cond
= ir3_COV(b
, cond
, TYPE_U32
, TYPE_U16
);
643 _mesa_hash_table_insert(ctx
->sel_cond_conversions
, src
[0], cond
);
648 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, cond
, 0, src
[2], 0);
650 dst
[0] = ir3_SEL_B16(b
, src
[1], 0, cond
, 0, src
[2], 0);
653 case nir_op_bit_count
: {
654 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
655 // double check on earlier gen's. Once half-precision support is
656 // in place, this should probably move to a NIR lowering pass:
657 struct ir3_instruction
*hi
, *lo
;
659 hi
= ir3_COV(b
, ir3_SHR_B(b
, src
[0], 0, create_immed(b
, 16), 0),
661 lo
= ir3_COV(b
, src
[0], TYPE_U32
, TYPE_U16
);
663 hi
= ir3_CBITS_B(b
, hi
, 0);
664 lo
= ir3_CBITS_B(b
, lo
, 0);
666 // TODO maybe the builders should default to making dst half-precision
667 // if the src's were half precision, to make this less awkward.. otoh
668 // we should probably just do this lowering in NIR.
669 hi
->regs
[0]->flags
|= IR3_REG_HALF
;
670 lo
->regs
[0]->flags
|= IR3_REG_HALF
;
672 dst
[0] = ir3_ADD_S(b
, hi
, 0, lo
, 0);
673 dst
[0]->regs
[0]->flags
|= IR3_REG_HALF
;
674 dst
[0] = ir3_COV(b
, dst
[0], TYPE_U16
, TYPE_U32
);
677 case nir_op_ifind_msb
: {
678 struct ir3_instruction
*cmp
;
679 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
680 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
681 cmp
->cat2
.condition
= IR3_COND_GE
;
682 dst
[0] = ir3_SEL_B32(b
,
683 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
687 case nir_op_ufind_msb
:
688 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
689 dst
[0] = ir3_SEL_B32(b
,
690 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
691 src
[0], 0, dst
[0], 0);
693 case nir_op_find_lsb
:
694 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
695 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
697 case nir_op_bitfield_reverse
:
698 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
702 ir3_context_error(ctx
, "Unhandled ALU op: %s\n",
703 nir_op_infos
[alu
->op
].name
);
707 if (nir_alu_type_get_base_type(info
->output_type
) == nir_type_bool
) {
708 assert(nir_dest_bit_size(alu
->dest
.dest
) == 1 ||
709 alu
->op
== nir_op_b2b32
);
712 /* 1-bit values stored in 32-bit registers are only valid for certain
723 compile_assert(ctx
, nir_dest_bit_size(alu
->dest
.dest
) != 1);
727 ir3_put_dst(ctx
, &alu
->dest
.dest
);
731 emit_intrinsic_load_ubo_ldc(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
732 struct ir3_instruction
**dst
)
734 struct ir3_block
*b
= ctx
->block
;
736 unsigned ncomp
= intr
->num_components
;
737 struct ir3_instruction
*offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
738 struct ir3_instruction
*idx
= ir3_get_src(ctx
, &intr
->src
[0])[0];
739 struct ir3_instruction
*ldc
= ir3_LDC(b
, idx
, 0, offset
, 0);
740 ldc
->regs
[0]->wrmask
= MASK(ncomp
);
741 ldc
->cat6
.iim_val
= ncomp
;
742 ldc
->cat6
.d
= nir_intrinsic_base(intr
);
743 ldc
->cat6
.type
= TYPE_U32
;
745 nir_intrinsic_instr
*bindless
= ir3_bindless_resource(intr
->src
[0]);
747 ldc
->flags
|= IR3_INSTR_B
;
748 ldc
->cat6
.base
= nir_intrinsic_desc_set(bindless
);
749 ctx
->so
->bindless_ubo
= true;
752 ir3_split_dest(b
, dst
, ldc
, 0, ncomp
);
756 /* handles direct/indirect UBO reads: */
758 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
759 struct ir3_instruction
**dst
)
761 struct ir3_block
*b
= ctx
->block
;
762 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
763 /* UBO addresses are the first driver params, but subtract 2 here to
764 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
765 * is the uniforms: */
766 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
767 unsigned ubo
= regid(const_state
->offsets
.ubo
, 0) - 2;
768 const unsigned ptrsz
= ir3_pointer_size(ctx
->compiler
);
772 /* First src is ubo index, which could either be an immed or not: */
773 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0];
774 if (is_same_type_mov(src0
) &&
775 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
776 base_lo
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
777 base_hi
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
779 base_lo
= create_uniform_indirect(b
, ubo
, ir3_get_addr0(ctx
, src0
, ptrsz
));
780 base_hi
= create_uniform_indirect(b
, ubo
+ 1, ir3_get_addr0(ctx
, src0
, ptrsz
));
782 /* NOTE: since relative addressing is used, make sure constlen is
783 * at least big enough to cover all the UBO addresses, since the
784 * assembler won't know what the max address reg is.
786 ctx
->so
->constlen
= MAX2(ctx
->so
->constlen
,
787 const_state
->offsets
.ubo
+ (ctx
->s
->info
.num_ubos
* ptrsz
));
790 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
793 if (nir_src_is_const(intr
->src
[1])) {
794 off
+= nir_src_as_uint(intr
->src
[1]);
796 /* For load_ubo_indirect, second src is indirect offset: */
797 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0];
799 /* and add offset to addr: */
800 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
803 /* if offset is to large to encode in the ldg, split it out: */
804 if ((off
+ (intr
->num_components
* 4)) > 1024) {
805 /* split out the minimal amount to improve the odds that
806 * cp can fit the immediate in the add.s instruction:
808 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
809 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
814 struct ir3_instruction
*carry
;
816 /* handle 32b rollover, ie:
817 * if (addr < base_lo)
820 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
821 carry
->cat2
.condition
= IR3_COND_LT
;
822 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
824 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
827 for (int i
= 0; i
< intr
->num_components
; i
++) {
828 struct ir3_instruction
*load
=
829 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0, /* num components */
830 create_immed(b
, off
+ i
* 4), 0);
831 load
->cat6
.type
= TYPE_U32
;
836 /* src[] = { block_index } */
838 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
839 struct ir3_instruction
**dst
)
841 /* SSBO size stored as a const starting at ssbo_sizes: */
842 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
843 unsigned blk_idx
= nir_src_as_uint(intr
->src
[0]);
844 unsigned idx
= regid(const_state
->offsets
.ssbo_sizes
, 0) +
845 const_state
->ssbo_size
.off
[blk_idx
];
847 debug_assert(const_state
->ssbo_size
.mask
& (1 << blk_idx
));
849 dst
[0] = create_uniform(ctx
->block
, idx
);
852 /* src[] = { offset }. const_index[] = { base } */
854 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
855 struct ir3_instruction
**dst
)
857 struct ir3_block
*b
= ctx
->block
;
858 struct ir3_instruction
*ldl
, *offset
;
861 offset
= ir3_get_src(ctx
, &intr
->src
[0])[0];
862 base
= nir_intrinsic_base(intr
);
864 ldl
= ir3_LDL(b
, offset
, 0,
865 create_immed(b
, intr
->num_components
), 0,
866 create_immed(b
, base
), 0);
868 ldl
->cat6
.type
= utype_dst(intr
->dest
);
869 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
871 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
872 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
874 ir3_split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
877 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
879 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
881 struct ir3_block
*b
= ctx
->block
;
882 struct ir3_instruction
*stl
, *offset
;
883 struct ir3_instruction
* const *value
;
884 unsigned base
, wrmask
;
886 value
= ir3_get_src(ctx
, &intr
->src
[0]);
887 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
889 base
= nir_intrinsic_base(intr
);
890 wrmask
= nir_intrinsic_write_mask(intr
);
892 /* Combine groups of consecutive enabled channels in one write
893 * message. We use ffs to find the first enabled channel and then ffs on
894 * the bit-inverse, down-shifted writemask to determine the length of
895 * the block of enabled bits.
897 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
900 unsigned first_component
= ffs(wrmask
) - 1;
901 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
903 stl
= ir3_STL(b
, offset
, 0,
904 ir3_create_collect(ctx
, &value
[first_component
], length
), 0,
905 create_immed(b
, length
), 0);
906 stl
->cat6
.dst_offset
= first_component
+ base
;
907 stl
->cat6
.type
= utype_src(intr
->src
[0]);
908 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
909 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
911 array_insert(b
, b
->keeps
, stl
);
913 /* Clear the bits in the writemask that we just wrote, then try
914 * again to see if more channels are left.
916 wrmask
&= (15 << (first_component
+ length
));
920 /* src[] = { offset }. const_index[] = { base } */
922 emit_intrinsic_load_shared_ir3(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
923 struct ir3_instruction
**dst
)
925 struct ir3_block
*b
= ctx
->block
;
926 struct ir3_instruction
*load
, *offset
;
929 offset
= ir3_get_src(ctx
, &intr
->src
[0])[0];
930 base
= nir_intrinsic_base(intr
);
932 load
= ir3_LDLW(b
, offset
, 0,
933 create_immed(b
, intr
->num_components
), 0,
934 create_immed(b
, base
), 0);
936 load
->cat6
.type
= utype_dst(intr
->dest
);
937 load
->regs
[0]->wrmask
= MASK(intr
->num_components
);
939 load
->barrier_class
= IR3_BARRIER_SHARED_R
;
940 load
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
942 ir3_split_dest(b
, dst
, load
, 0, intr
->num_components
);
945 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
947 emit_intrinsic_store_shared_ir3(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
949 struct ir3_block
*b
= ctx
->block
;
950 struct ir3_instruction
*store
, *offset
;
951 struct ir3_instruction
* const *value
;
952 unsigned base
, wrmask
;
954 value
= ir3_get_src(ctx
, &intr
->src
[0]);
955 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
957 base
= nir_intrinsic_base(intr
);
958 wrmask
= nir_intrinsic_write_mask(intr
);
960 /* Combine groups of consecutive enabled channels in one write
961 * message. We use ffs to find the first enabled channel and then ffs on
962 * the bit-inverse, down-shifted writemask to determine the length of
963 * the block of enabled bits.
965 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
968 unsigned first_component
= ffs(wrmask
) - 1;
969 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
971 store
= ir3_STLW(b
, offset
, 0,
972 ir3_create_collect(ctx
, &value
[first_component
], length
), 0,
973 create_immed(b
, length
), 0);
975 store
->cat6
.dst_offset
= first_component
+ base
;
976 store
->cat6
.type
= utype_src(intr
->src
[0]);
977 store
->barrier_class
= IR3_BARRIER_SHARED_W
;
978 store
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
980 array_insert(b
, b
->keeps
, store
);
982 /* Clear the bits in the writemask that we just wrote, then try
983 * again to see if more channels are left.
985 wrmask
&= (15 << (first_component
+ length
));
990 * CS shared variable atomic intrinsics
992 * All of the shared variable atomic memory operations read a value from
993 * memory, compute a new value using one of the operations below, write the
994 * new value to memory, and return the original value read.
996 * All operations take 2 sources except CompSwap that takes 3. These
999 * 0: The offset into the shared variable storage region that the atomic
1000 * operation will operate on.
1001 * 1: The data parameter to the atomic function (i.e. the value to add
1002 * in shared_atomic_add, etc).
1003 * 2: For CompSwap only: the second data parameter.
1005 static struct ir3_instruction
*
1006 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1008 struct ir3_block
*b
= ctx
->block
;
1009 struct ir3_instruction
*atomic
, *src0
, *src1
;
1010 type_t type
= TYPE_U32
;
1012 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0]; /* offset */
1013 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0]; /* value */
1015 switch (intr
->intrinsic
) {
1016 case nir_intrinsic_shared_atomic_add
:
1017 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
1019 case nir_intrinsic_shared_atomic_imin
:
1020 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1023 case nir_intrinsic_shared_atomic_umin
:
1024 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1026 case nir_intrinsic_shared_atomic_imax
:
1027 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1030 case nir_intrinsic_shared_atomic_umax
:
1031 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1033 case nir_intrinsic_shared_atomic_and
:
1034 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
1036 case nir_intrinsic_shared_atomic_or
:
1037 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
1039 case nir_intrinsic_shared_atomic_xor
:
1040 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1042 case nir_intrinsic_shared_atomic_exchange
:
1043 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1045 case nir_intrinsic_shared_atomic_comp_swap
:
1046 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1047 src1
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1048 ir3_get_src(ctx
, &intr
->src
[2])[0],
1051 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1057 atomic
->cat6
.iim_val
= 1;
1059 atomic
->cat6
.type
= type
;
1060 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1061 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1063 /* even if nothing consume the result, we can't DCE the instruction: */
1064 array_insert(b
, b
->keeps
, atomic
);
1069 struct tex_src_info
{
1071 unsigned tex_base
, samp_base
, tex_idx
, samp_idx
;
1072 /* For normal tex instructions */
1073 unsigned base
, combined_idx
, a1_val
, flags
;
1074 struct ir3_instruction
*samp_tex
;
1077 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1078 * to handle with the image_mapping table..
1080 static struct tex_src_info
1081 get_image_samp_tex_src(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1083 struct ir3_block
*b
= ctx
->block
;
1084 struct tex_src_info info
= { 0 };
1085 nir_intrinsic_instr
*bindless_tex
= ir3_bindless_resource(intr
->src
[0]);
1086 ctx
->so
->bindless_tex
= true;
1090 info
.flags
|= IR3_INSTR_B
;
1092 /* Gather information required to determine which encoding to
1093 * choose as well as for prefetch.
1095 info
.tex_base
= nir_intrinsic_desc_set(bindless_tex
);
1096 bool tex_const
= nir_src_is_const(bindless_tex
->src
[0]);
1098 info
.tex_idx
= nir_src_as_uint(bindless_tex
->src
[0]);
1101 /* Choose encoding. */
1102 if (tex_const
&& info
.tex_idx
< 256) {
1103 if (info
.tex_idx
< 16) {
1104 /* Everything fits within the instruction */
1105 info
.base
= info
.tex_base
;
1106 info
.combined_idx
= info
.samp_idx
| (info
.tex_idx
<< 4);
1108 info
.base
= info
.tex_base
;
1109 info
.a1_val
= info
.tex_idx
<< 3;
1110 info
.combined_idx
= 0;
1111 info
.flags
|= IR3_INSTR_A1EN
;
1113 info
.samp_tex
= NULL
;
1115 info
.flags
|= IR3_INSTR_S2EN
;
1116 info
.base
= info
.tex_base
;
1118 /* Note: the indirect source is now a vec2 instead of hvec2 */
1119 struct ir3_instruction
*texture
, *sampler
;
1121 texture
= ir3_get_src(ctx
, &intr
->src
[0])[0];
1122 sampler
= create_immed(b
, 0);
1123 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1129 info
.flags
|= IR3_INSTR_S2EN
;
1130 unsigned slot
= nir_src_as_uint(intr
->src
[0]);
1131 unsigned tex_idx
= ir3_image_to_tex(&ctx
->so
->image_mapping
, slot
);
1132 struct ir3_instruction
*texture
, *sampler
;
1134 texture
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
1135 sampler
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
1137 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1146 static struct ir3_instruction
*
1147 emit_sam(struct ir3_context
*ctx
, opc_t opc
, struct tex_src_info info
,
1148 type_t type
, unsigned wrmask
, struct ir3_instruction
*src0
,
1149 struct ir3_instruction
*src1
)
1151 struct ir3_instruction
*sam
, *addr
;
1152 if (info
.flags
& IR3_INSTR_A1EN
) {
1153 addr
= ir3_get_addr1(ctx
, info
.a1_val
);
1155 sam
= ir3_SAM(ctx
->block
, opc
, type
, 0b1111, info
.flags
,
1156 info
.samp_tex
, src0
, src1
);
1157 if (info
.flags
& IR3_INSTR_A1EN
) {
1158 ir3_instr_set_address(sam
, addr
);
1160 if (info
.flags
& IR3_INSTR_B
) {
1161 sam
->cat5
.tex_base
= info
.base
;
1162 sam
->cat5
.samp
= info
.combined_idx
;
1167 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1169 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1170 struct ir3_instruction
**dst
)
1172 struct ir3_block
*b
= ctx
->block
;
1173 struct tex_src_info info
= get_image_samp_tex_src(ctx
, intr
);
1174 struct ir3_instruction
*sam
;
1175 struct ir3_instruction
* const *src0
= ir3_get_src(ctx
, &intr
->src
[1]);
1176 struct ir3_instruction
*coords
[4];
1177 unsigned flags
, ncoords
= ir3_get_image_coords(intr
, &flags
);
1178 type_t type
= ir3_get_type_for_image_intrinsic(intr
);
1180 /* hmm, this seems a bit odd, but it is what blob does and (at least
1181 * a5xx) just faults on bogus addresses otherwise:
1183 if (flags
& IR3_INSTR_3D
) {
1184 flags
&= ~IR3_INSTR_3D
;
1185 flags
|= IR3_INSTR_A
;
1187 info
.flags
|= flags
;
1189 for (unsigned i
= 0; i
< ncoords
; i
++)
1190 coords
[i
] = src0
[i
];
1193 coords
[ncoords
++] = create_immed(b
, 0);
1195 sam
= emit_sam(ctx
, OPC_ISAM
, info
, type
, 0b1111,
1196 ir3_create_collect(ctx
, coords
, ncoords
), NULL
);
1198 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
1199 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
1201 ir3_split_dest(b
, dst
, sam
, 0, 4);
1205 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1206 struct ir3_instruction
**dst
)
1208 struct ir3_block
*b
= ctx
->block
;
1209 struct tex_src_info info
= get_image_samp_tex_src(ctx
, intr
);
1210 struct ir3_instruction
*sam
, *lod
;
1211 unsigned flags
, ncoords
= ir3_get_image_coords(intr
, &flags
);
1212 type_t dst_type
= nir_dest_bit_size(intr
->dest
) == 16 ?
1213 TYPE_U16
: TYPE_U32
;
1215 info
.flags
|= flags
;
1216 lod
= create_immed(b
, 0);
1217 sam
= emit_sam(ctx
, OPC_GETSIZE
, info
, dst_type
, 0b1111, lod
, NULL
);
1219 /* Array size actually ends up in .w rather than .z. This doesn't
1220 * matter for miplevel 0, but for higher mips the value in z is
1221 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1222 * returned, which means that we have to add 1 to it for arrays for
1225 * Note use a temporary dst and then copy, since the size of the dst
1226 * array that is passed in is based on nir's understanding of the
1227 * result size, not the hardware's
1229 struct ir3_instruction
*tmp
[4];
1231 ir3_split_dest(b
, tmp
, sam
, 0, 4);
1233 /* get_size instruction returns size in bytes instead of texels
1234 * for imageBuffer, so we need to divide it by the pixel size
1235 * of the image format.
1237 * TODO: This is at least true on a5xx. Check other gens.
1239 if (nir_intrinsic_image_dim(intr
) == GLSL_SAMPLER_DIM_BUF
) {
1240 /* Since all the possible values the divisor can take are
1241 * power-of-two (4, 8, or 16), the division is implemented
1243 * During shader setup, the log2 of the image format's
1244 * bytes-per-pixel should have been emitted in 2nd slot of
1245 * image_dims. See ir3_shader::emit_image_dims().
1247 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
1248 unsigned cb
= regid(const_state
->offsets
.image_dims
, 0) +
1249 const_state
->image_dims
.off
[nir_src_as_uint(intr
->src
[0])];
1250 struct ir3_instruction
*aux
= create_uniform(b
, cb
+ 1);
1252 tmp
[0] = ir3_SHR_B(b
, tmp
[0], 0, aux
, 0);
1255 for (unsigned i
= 0; i
< ncoords
; i
++)
1258 if (flags
& IR3_INSTR_A
) {
1259 if (ctx
->compiler
->levels_add_one
) {
1260 dst
[ncoords
-1] = ir3_ADD_U(b
, tmp
[3], 0, create_immed(b
, 1), 0);
1262 dst
[ncoords
-1] = ir3_MOV(b
, tmp
[3], TYPE_U32
);
1268 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1270 struct ir3_block
*b
= ctx
->block
;
1271 struct ir3_instruction
*barrier
;
1273 switch (intr
->intrinsic
) {
1274 case nir_intrinsic_control_barrier
:
1275 barrier
= ir3_BAR(b
);
1276 barrier
->cat7
.g
= true;
1277 barrier
->cat7
.l
= true;
1278 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
1279 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1281 case nir_intrinsic_memory_barrier
:
1282 barrier
= ir3_FENCE(b
);
1283 barrier
->cat7
.g
= true;
1284 barrier
->cat7
.r
= true;
1285 barrier
->cat7
.w
= true;
1286 barrier
->cat7
.l
= true;
1287 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
1288 IR3_BARRIER_BUFFER_W
;
1289 barrier
->barrier_conflict
=
1290 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1291 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1293 case nir_intrinsic_memory_barrier_buffer
:
1294 barrier
= ir3_FENCE(b
);
1295 barrier
->cat7
.g
= true;
1296 barrier
->cat7
.r
= true;
1297 barrier
->cat7
.w
= true;
1298 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1299 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
1300 IR3_BARRIER_BUFFER_W
;
1302 case nir_intrinsic_memory_barrier_image
:
1303 // TODO double check if this should have .g set
1304 barrier
= ir3_FENCE(b
);
1305 barrier
->cat7
.g
= true;
1306 barrier
->cat7
.r
= true;
1307 barrier
->cat7
.w
= true;
1308 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1309 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
1310 IR3_BARRIER_IMAGE_W
;
1312 case nir_intrinsic_memory_barrier_shared
:
1313 barrier
= ir3_FENCE(b
);
1314 barrier
->cat7
.g
= true;
1315 barrier
->cat7
.l
= true;
1316 barrier
->cat7
.r
= true;
1317 barrier
->cat7
.w
= true;
1318 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
1319 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
1320 IR3_BARRIER_SHARED_W
;
1322 case nir_intrinsic_group_memory_barrier
:
1323 barrier
= ir3_FENCE(b
);
1324 barrier
->cat7
.g
= true;
1325 barrier
->cat7
.l
= true;
1326 barrier
->cat7
.r
= true;
1327 barrier
->cat7
.w
= true;
1328 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
1329 IR3_BARRIER_IMAGE_W
|
1330 IR3_BARRIER_BUFFER_W
;
1331 barrier
->barrier_conflict
=
1332 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
1333 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1334 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1340 /* make sure barrier doesn't get DCE'd */
1341 array_insert(b
, b
->keeps
, barrier
);
1344 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
1345 gl_system_value slot
, unsigned compmask
,
1346 struct ir3_instruction
*instr
)
1348 struct ir3_shader_variant
*so
= ctx
->so
;
1349 unsigned n
= so
->inputs_count
++;
1351 assert(instr
->opc
== OPC_META_INPUT
);
1352 instr
->input
.inidx
= n
;
1353 instr
->input
.sysval
= slot
;
1355 so
->inputs
[n
].sysval
= true;
1356 so
->inputs
[n
].slot
= slot
;
1357 so
->inputs
[n
].compmask
= compmask
;
1358 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1362 static struct ir3_instruction
*
1363 create_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
1367 struct ir3_instruction
*sysval
= create_input(ctx
, compmask
);
1368 add_sysval_input_compmask(ctx
, slot
, compmask
, sysval
);
1372 static struct ir3_instruction
*
1373 get_barycentric_centroid(struct ir3_context
*ctx
)
1375 if (!ctx
->ij_centroid
) {
1376 struct ir3_instruction
*xy
[2];
1377 struct ir3_instruction
*ij
;
1379 ij
= create_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
, 0x3);
1380 ir3_split_dest(ctx
->block
, xy
, ij
, 0, 2);
1382 ctx
->ij_centroid
= ir3_create_collect(ctx
, xy
, 2);
1385 return ctx
->ij_centroid
;
1388 static struct ir3_instruction
*
1389 get_barycentric_sample(struct ir3_context
*ctx
)
1391 if (!ctx
->ij_sample
) {
1392 struct ir3_instruction
*xy
[2];
1393 struct ir3_instruction
*ij
;
1395 ij
= create_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE
, 0x3);
1396 ir3_split_dest(ctx
->block
, xy
, ij
, 0, 2);
1398 ctx
->ij_sample
= ir3_create_collect(ctx
, xy
, 2);
1401 return ctx
->ij_sample
;
1404 static struct ir3_instruction
*
1405 get_barycentric_pixel(struct ir3_context
*ctx
)
1407 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1408 * this to create ij_pixel only on demand:
1410 return ctx
->ij_pixel
;
1413 static struct ir3_instruction
*
1414 get_frag_coord(struct ir3_context
*ctx
)
1416 if (!ctx
->frag_coord
) {
1417 struct ir3_block
*b
= ctx
->in_block
;
1418 struct ir3_instruction
*xyzw
[4];
1419 struct ir3_instruction
*hw_frag_coord
;
1421 hw_frag_coord
= create_sysval_input(ctx
, SYSTEM_VALUE_FRAG_COORD
, 0xf);
1422 ir3_split_dest(b
, xyzw
, hw_frag_coord
, 0, 4);
1424 /* for frag_coord.xy, we get unsigned values.. we need
1425 * to subtract (integer) 8 and divide by 16 (right-
1426 * shift by 4) then convert to float:
1430 * mov.u32f32 dst, tmp
1433 for (int i
= 0; i
< 2; i
++) {
1434 xyzw
[i
] = ir3_COV(b
, xyzw
[i
], TYPE_U32
, TYPE_F32
);
1435 xyzw
[i
] = ir3_MUL_F(b
, xyzw
[i
], 0, create_immed(b
, fui(1.0 / 16.0)), 0);
1438 ctx
->frag_coord
= ir3_create_collect(ctx
, xyzw
, 4);
1439 ctx
->so
->frag_coord
= true;
1442 return ctx
->frag_coord
;
1446 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1448 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1449 struct ir3_instruction
**dst
;
1450 struct ir3_instruction
* const *src
;
1451 struct ir3_block
*b
= ctx
->block
;
1454 if (info
->has_dest
) {
1455 unsigned n
= nir_intrinsic_dest_components(intr
);
1456 dst
= ir3_get_dst(ctx
, &intr
->dest
, n
);
1461 const unsigned primitive_param
= ctx
->so
->shader
->const_state
.offsets
.primitive_param
* 4;
1462 const unsigned primitive_map
= ctx
->so
->shader
->const_state
.offsets
.primitive_map
* 4;
1464 switch (intr
->intrinsic
) {
1465 case nir_intrinsic_load_uniform
:
1466 idx
= nir_intrinsic_base(intr
);
1467 if (nir_src_is_const(intr
->src
[0])) {
1468 idx
+= nir_src_as_uint(intr
->src
[0]);
1469 for (int i
= 0; i
< intr
->num_components
; i
++) {
1470 dst
[i
] = create_uniform_typed(b
, idx
+ i
,
1471 nir_dest_bit_size(intr
->dest
) == 16 ? TYPE_F16
: TYPE_F32
);
1474 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1475 for (int i
= 0; i
< intr
->num_components
; i
++) {
1476 dst
[i
] = create_uniform_indirect(b
, idx
+ i
,
1477 ir3_get_addr0(ctx
, src
[0], 1));
1479 /* NOTE: if relative addressing is used, we set
1480 * constlen in the compiler (to worst-case value)
1481 * since we don't know in the assembler what the max
1482 * addr reg value can be:
1484 ctx
->so
->constlen
= MAX2(ctx
->so
->constlen
,
1485 ctx
->so
->shader
->ubo_state
.size
/ 16);
1489 case nir_intrinsic_load_vs_primitive_stride_ir3
:
1490 dst
[0] = create_uniform(b
, primitive_param
+ 0);
1492 case nir_intrinsic_load_vs_vertex_stride_ir3
:
1493 dst
[0] = create_uniform(b
, primitive_param
+ 1);
1495 case nir_intrinsic_load_hs_patch_stride_ir3
:
1496 dst
[0] = create_uniform(b
, primitive_param
+ 2);
1498 case nir_intrinsic_load_patch_vertices_in
:
1499 dst
[0] = create_uniform(b
, primitive_param
+ 3);
1501 case nir_intrinsic_load_tess_param_base_ir3
:
1502 dst
[0] = create_uniform(b
, primitive_param
+ 4);
1503 dst
[1] = create_uniform(b
, primitive_param
+ 5);
1505 case nir_intrinsic_load_tess_factor_base_ir3
:
1506 dst
[0] = create_uniform(b
, primitive_param
+ 6);
1507 dst
[1] = create_uniform(b
, primitive_param
+ 7);
1510 case nir_intrinsic_load_primitive_location_ir3
:
1511 idx
= nir_intrinsic_driver_location(intr
);
1512 dst
[0] = create_uniform(b
, primitive_map
+ idx
);
1515 case nir_intrinsic_load_gs_header_ir3
:
1516 dst
[0] = ctx
->gs_header
;
1518 case nir_intrinsic_load_tcs_header_ir3
:
1519 dst
[0] = ctx
->tcs_header
;
1522 case nir_intrinsic_load_primitive_id
:
1523 dst
[0] = ctx
->primitive_id
;
1526 case nir_intrinsic_load_tess_coord
:
1527 if (!ctx
->tess_coord
) {
1529 create_sysval_input(ctx
, SYSTEM_VALUE_TESS_COORD
, 0x3);
1531 ir3_split_dest(b
, dst
, ctx
->tess_coord
, 0, 2);
1533 /* Unused, but ir3_put_dst() below wants to free something */
1534 dst
[2] = create_immed(b
, 0);
1537 case nir_intrinsic_end_patch_ir3
:
1538 assert(ctx
->so
->type
== MESA_SHADER_TESS_CTRL
);
1539 struct ir3_instruction
*end
= ir3_ENDIF(b
);
1540 array_insert(b
, b
->keeps
, end
);
1542 end
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1543 end
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
1546 case nir_intrinsic_store_global_ir3
: {
1547 struct ir3_instruction
*value
, *addr
, *offset
;
1549 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1550 ir3_get_src(ctx
, &intr
->src
[1])[0],
1551 ir3_get_src(ctx
, &intr
->src
[1])[1]
1554 offset
= ir3_get_src(ctx
, &intr
->src
[2])[0];
1556 value
= ir3_create_collect(ctx
, ir3_get_src(ctx
, &intr
->src
[0]),
1557 intr
->num_components
);
1559 struct ir3_instruction
*stg
=
1560 ir3_STG_G(ctx
->block
, addr
, 0, value
, 0,
1561 create_immed(ctx
->block
, intr
->num_components
), 0, offset
, 0);
1562 stg
->cat6
.type
= TYPE_U32
;
1563 stg
->cat6
.iim_val
= 1;
1565 array_insert(b
, b
->keeps
, stg
);
1567 stg
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1568 stg
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1572 case nir_intrinsic_load_global_ir3
: {
1573 struct ir3_instruction
*addr
, *offset
;
1575 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1576 ir3_get_src(ctx
, &intr
->src
[0])[0],
1577 ir3_get_src(ctx
, &intr
->src
[0])[1]
1580 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
1582 struct ir3_instruction
*load
=
1583 ir3_LDG(b
, addr
, 0, create_immed(ctx
->block
, intr
->num_components
),
1585 load
->cat6
.type
= TYPE_U32
;
1586 load
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1588 load
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1589 load
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1591 ir3_split_dest(b
, dst
, load
, 0, intr
->num_components
);
1595 case nir_intrinsic_load_ubo
:
1596 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1598 case nir_intrinsic_load_ubo_ir3
:
1599 emit_intrinsic_load_ubo_ldc(ctx
, intr
, dst
);
1601 case nir_intrinsic_load_frag_coord
:
1602 ir3_split_dest(b
, dst
, get_frag_coord(ctx
), 0, 4);
1604 case nir_intrinsic_load_sample_pos_from_id
: {
1605 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1606 * but that doesn't seem necessary.
1608 struct ir3_instruction
*offset
=
1609 ir3_RGETPOS(b
, ir3_get_src(ctx
, &intr
->src
[0])[0], 0);
1610 offset
->regs
[0]->wrmask
= 0x3;
1611 offset
->cat5
.type
= TYPE_F32
;
1613 ir3_split_dest(b
, dst
, offset
, 0, 2);
1617 case nir_intrinsic_load_size_ir3
:
1618 if (!ctx
->ij_size
) {
1620 create_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE
, 0x1);
1622 dst
[0] = ctx
->ij_size
;
1624 case nir_intrinsic_load_barycentric_centroid
:
1625 ir3_split_dest(b
, dst
, get_barycentric_centroid(ctx
), 0, 2);
1627 case nir_intrinsic_load_barycentric_sample
:
1628 if (ctx
->so
->key
.msaa
) {
1629 ir3_split_dest(b
, dst
, get_barycentric_sample(ctx
), 0, 2);
1631 ir3_split_dest(b
, dst
, get_barycentric_pixel(ctx
), 0, 2);
1634 case nir_intrinsic_load_barycentric_pixel
:
1635 ir3_split_dest(b
, dst
, get_barycentric_pixel(ctx
), 0, 2);
1637 case nir_intrinsic_load_interpolated_input
:
1638 idx
= nir_intrinsic_base(intr
);
1639 comp
= nir_intrinsic_component(intr
);
1640 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1641 if (nir_src_is_const(intr
->src
[1])) {
1642 struct ir3_instruction
*coord
= ir3_create_collect(ctx
, src
, 2);
1643 idx
+= nir_src_as_uint(intr
->src
[1]);
1644 for (int i
= 0; i
< intr
->num_components
; i
++) {
1645 unsigned inloc
= idx
* 4 + i
+ comp
;
1646 if (ctx
->so
->inputs
[idx
].bary
&&
1647 !ctx
->so
->inputs
[idx
].use_ldlv
) {
1648 dst
[i
] = ir3_BARY_F(b
, create_immed(b
, inloc
), 0, coord
, 0);
1650 /* for non-varyings use the pre-setup input, since
1651 * that is easier than mapping things back to a
1652 * nir_variable to figure out what it is.
1654 dst
[i
] = ctx
->inputs
[inloc
];
1655 compile_assert(ctx
, dst
[i
]);
1659 ir3_context_error(ctx
, "unhandled");
1662 case nir_intrinsic_load_input
:
1663 idx
= nir_intrinsic_base(intr
);
1664 comp
= nir_intrinsic_component(intr
);
1665 if (nir_src_is_const(intr
->src
[0])) {
1666 idx
+= nir_src_as_uint(intr
->src
[0]);
1667 for (int i
= 0; i
< intr
->num_components
; i
++) {
1668 unsigned n
= idx
* 4 + i
+ comp
;
1669 dst
[i
] = ctx
->inputs
[n
];
1670 compile_assert(ctx
, ctx
->inputs
[n
]);
1673 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1674 struct ir3_instruction
*collect
=
1675 ir3_create_collect(ctx
, ctx
->ir
->inputs
, ctx
->ninputs
);
1676 struct ir3_instruction
*addr
= ir3_get_addr0(ctx
, src
[0], 4);
1677 for (int i
= 0; i
< intr
->num_components
; i
++) {
1678 unsigned n
= idx
* 4 + i
+ comp
;
1679 dst
[i
] = create_indirect_load(ctx
, ctx
->ninputs
,
1684 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1685 * pass and replaced by an ir3-specifc version that adds the
1686 * dword-offset in the last source.
1688 case nir_intrinsic_load_ssbo_ir3
:
1689 ctx
->funcs
->emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
1691 case nir_intrinsic_store_ssbo_ir3
:
1692 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1693 !ctx
->s
->info
.fs
.early_fragment_tests
)
1694 ctx
->so
->no_earlyz
= true;
1695 ctx
->funcs
->emit_intrinsic_store_ssbo(ctx
, intr
);
1697 case nir_intrinsic_get_buffer_size
:
1698 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
1700 case nir_intrinsic_ssbo_atomic_add_ir3
:
1701 case nir_intrinsic_ssbo_atomic_imin_ir3
:
1702 case nir_intrinsic_ssbo_atomic_umin_ir3
:
1703 case nir_intrinsic_ssbo_atomic_imax_ir3
:
1704 case nir_intrinsic_ssbo_atomic_umax_ir3
:
1705 case nir_intrinsic_ssbo_atomic_and_ir3
:
1706 case nir_intrinsic_ssbo_atomic_or_ir3
:
1707 case nir_intrinsic_ssbo_atomic_xor_ir3
:
1708 case nir_intrinsic_ssbo_atomic_exchange_ir3
:
1709 case nir_intrinsic_ssbo_atomic_comp_swap_ir3
:
1710 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1711 !ctx
->s
->info
.fs
.early_fragment_tests
)
1712 ctx
->so
->no_earlyz
= true;
1713 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_ssbo(ctx
, intr
);
1715 case nir_intrinsic_load_shared
:
1716 emit_intrinsic_load_shared(ctx
, intr
, dst
);
1718 case nir_intrinsic_store_shared
:
1719 emit_intrinsic_store_shared(ctx
, intr
);
1721 case nir_intrinsic_shared_atomic_add
:
1722 case nir_intrinsic_shared_atomic_imin
:
1723 case nir_intrinsic_shared_atomic_umin
:
1724 case nir_intrinsic_shared_atomic_imax
:
1725 case nir_intrinsic_shared_atomic_umax
:
1726 case nir_intrinsic_shared_atomic_and
:
1727 case nir_intrinsic_shared_atomic_or
:
1728 case nir_intrinsic_shared_atomic_xor
:
1729 case nir_intrinsic_shared_atomic_exchange
:
1730 case nir_intrinsic_shared_atomic_comp_swap
:
1731 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
1733 case nir_intrinsic_image_load
:
1734 emit_intrinsic_load_image(ctx
, intr
, dst
);
1736 case nir_intrinsic_bindless_image_load
:
1737 /* Bindless uses the IBO state, which doesn't have swizzle filled out,
1738 * so using isam doesn't work.
1740 * TODO: can we use isam if we fill out more fields?
1742 ctx
->funcs
->emit_intrinsic_load_image(ctx
, intr
, dst
);
1744 case nir_intrinsic_image_store
:
1745 case nir_intrinsic_bindless_image_store
:
1746 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1747 !ctx
->s
->info
.fs
.early_fragment_tests
)
1748 ctx
->so
->no_earlyz
= true;
1749 ctx
->funcs
->emit_intrinsic_store_image(ctx
, intr
);
1751 case nir_intrinsic_image_size
:
1752 case nir_intrinsic_bindless_image_size
:
1753 emit_intrinsic_image_size(ctx
, intr
, dst
);
1755 case nir_intrinsic_image_atomic_add
:
1756 case nir_intrinsic_bindless_image_atomic_add
:
1757 case nir_intrinsic_image_atomic_imin
:
1758 case nir_intrinsic_bindless_image_atomic_imin
:
1759 case nir_intrinsic_image_atomic_umin
:
1760 case nir_intrinsic_bindless_image_atomic_umin
:
1761 case nir_intrinsic_image_atomic_imax
:
1762 case nir_intrinsic_bindless_image_atomic_imax
:
1763 case nir_intrinsic_image_atomic_umax
:
1764 case nir_intrinsic_bindless_image_atomic_umax
:
1765 case nir_intrinsic_image_atomic_and
:
1766 case nir_intrinsic_bindless_image_atomic_and
:
1767 case nir_intrinsic_image_atomic_or
:
1768 case nir_intrinsic_bindless_image_atomic_or
:
1769 case nir_intrinsic_image_atomic_xor
:
1770 case nir_intrinsic_bindless_image_atomic_xor
:
1771 case nir_intrinsic_image_atomic_exchange
:
1772 case nir_intrinsic_bindless_image_atomic_exchange
:
1773 case nir_intrinsic_image_atomic_comp_swap
:
1774 case nir_intrinsic_bindless_image_atomic_comp_swap
:
1775 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1776 !ctx
->s
->info
.fs
.early_fragment_tests
)
1777 ctx
->so
->no_earlyz
= true;
1778 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_image(ctx
, intr
);
1780 case nir_intrinsic_control_barrier
:
1781 case nir_intrinsic_memory_barrier
:
1782 case nir_intrinsic_group_memory_barrier
:
1783 case nir_intrinsic_memory_barrier_buffer
:
1784 case nir_intrinsic_memory_barrier_image
:
1785 case nir_intrinsic_memory_barrier_shared
:
1786 emit_intrinsic_barrier(ctx
, intr
);
1787 /* note that blk ptr no longer valid, make that obvious: */
1790 case nir_intrinsic_store_output
:
1791 idx
= nir_intrinsic_base(intr
);
1792 comp
= nir_intrinsic_component(intr
);
1793 compile_assert(ctx
, nir_src_is_const(intr
->src
[1]));
1794 idx
+= nir_src_as_uint(intr
->src
[1]);
1796 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1797 for (int i
= 0; i
< intr
->num_components
; i
++) {
1798 unsigned n
= idx
* 4 + i
+ comp
;
1799 ctx
->outputs
[n
] = src
[i
];
1802 case nir_intrinsic_load_base_vertex
:
1803 case nir_intrinsic_load_first_vertex
:
1804 if (!ctx
->basevertex
) {
1805 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1807 dst
[0] = ctx
->basevertex
;
1809 case nir_intrinsic_load_base_instance
:
1810 if (!ctx
->base_instance
) {
1811 ctx
->base_instance
= create_driver_param(ctx
, IR3_DP_INSTID_BASE
);
1813 dst
[0] = ctx
->base_instance
;
1815 case nir_intrinsic_load_vertex_id_zero_base
:
1816 case nir_intrinsic_load_vertex_id
:
1817 if (!ctx
->vertex_id
) {
1818 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
1819 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
1820 ctx
->vertex_id
= create_sysval_input(ctx
, sv
, 0x1);
1822 dst
[0] = ctx
->vertex_id
;
1824 case nir_intrinsic_load_instance_id
:
1825 if (!ctx
->instance_id
) {
1826 ctx
->instance_id
= create_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
, 0x1);
1828 dst
[0] = ctx
->instance_id
;
1830 case nir_intrinsic_load_sample_id
:
1831 ctx
->so
->per_samp
= true;
1833 case nir_intrinsic_load_sample_id_no_per_sample
:
1834 if (!ctx
->samp_id
) {
1835 ctx
->samp_id
= create_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_ID
, 0x1);
1836 ctx
->samp_id
->regs
[0]->flags
|= IR3_REG_HALF
;
1838 dst
[0] = ir3_COV(b
, ctx
->samp_id
, TYPE_U16
, TYPE_U32
);
1840 case nir_intrinsic_load_sample_mask_in
:
1841 if (!ctx
->samp_mask_in
) {
1842 ctx
->samp_mask_in
= create_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_MASK_IN
, 0x1);
1844 dst
[0] = ctx
->samp_mask_in
;
1846 case nir_intrinsic_load_user_clip_plane
:
1847 idx
= nir_intrinsic_ucp_id(intr
);
1848 for (int i
= 0; i
< intr
->num_components
; i
++) {
1849 unsigned n
= idx
* 4 + i
;
1850 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1853 case nir_intrinsic_load_front_face
:
1854 if (!ctx
->frag_face
) {
1855 ctx
->so
->frag_face
= true;
1856 ctx
->frag_face
= create_sysval_input(ctx
, SYSTEM_VALUE_FRONT_FACE
, 0x1);
1857 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
1859 /* for fragface, we get -1 for back and 0 for front. However this is
1860 * the inverse of what nir expects (where ~0 is true).
1862 dst
[0] = ir3_CMPS_S(b
,
1864 create_immed_typed(b
, 0, TYPE_U16
), 0);
1865 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1867 case nir_intrinsic_load_local_invocation_id
:
1868 if (!ctx
->local_invocation_id
) {
1869 ctx
->local_invocation_id
=
1870 create_sysval_input(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
, 0x7);
1872 ir3_split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
1874 case nir_intrinsic_load_work_group_id
:
1875 if (!ctx
->work_group_id
) {
1876 ctx
->work_group_id
=
1877 create_sysval_input(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
, 0x7);
1878 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
1880 ir3_split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
1882 case nir_intrinsic_load_num_work_groups
:
1883 for (int i
= 0; i
< intr
->num_components
; i
++) {
1884 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
1887 case nir_intrinsic_load_local_group_size
:
1888 for (int i
= 0; i
< intr
->num_components
; i
++) {
1889 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
1892 case nir_intrinsic_discard_if
:
1893 case nir_intrinsic_discard
: {
1894 struct ir3_instruction
*cond
, *kill
;
1896 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1897 /* conditional discard: */
1898 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1901 /* unconditional discard: */
1902 cond
= create_immed(b
, 1);
1905 /* NOTE: only cmps.*.* can write p0.x: */
1906 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1907 cond
->cat2
.condition
= IR3_COND_NE
;
1909 /* condition always goes in predicate register: */
1910 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1911 cond
->regs
[0]->flags
&= ~IR3_REG_SSA
;
1913 kill
= ir3_KILL(b
, cond
, 0);
1914 kill
->regs
[1]->num
= regid(REG_P0
, 0);
1915 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1917 array_insert(b
, b
->keeps
, kill
);
1918 ctx
->so
->no_earlyz
= true;
1923 case nir_intrinsic_cond_end_ir3
: {
1924 struct ir3_instruction
*cond
, *kill
;
1926 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1929 /* NOTE: only cmps.*.* can write p0.x: */
1930 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1931 cond
->cat2
.condition
= IR3_COND_NE
;
1933 /* condition always goes in predicate register: */
1934 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1936 kill
= ir3_IF(b
, cond
, 0);
1938 kill
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1939 kill
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
1941 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1942 array_insert(b
, b
->keeps
, kill
);
1946 case nir_intrinsic_load_shared_ir3
:
1947 emit_intrinsic_load_shared_ir3(ctx
, intr
, dst
);
1949 case nir_intrinsic_store_shared_ir3
:
1950 emit_intrinsic_store_shared_ir3(ctx
, intr
);
1952 case nir_intrinsic_bindless_resource_ir3
:
1953 dst
[0] = ir3_get_src(ctx
, &intr
->src
[0])[0];
1956 ir3_context_error(ctx
, "Unhandled intrinsic type: %s\n",
1957 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1962 ir3_put_dst(ctx
, &intr
->dest
);
1966 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
1968 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &instr
->def
,
1969 instr
->def
.num_components
);
1971 if (instr
->def
.bit_size
== 16) {
1972 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1973 dst
[i
] = create_immed_typed(ctx
->block
,
1974 instr
->value
[i
].u16
,
1977 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1978 dst
[i
] = create_immed_typed(ctx
->block
,
1979 instr
->value
[i
].u32
,
1986 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
1988 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &undef
->def
,
1989 undef
->def
.num_components
);
1990 type_t type
= (undef
->def
.bit_size
== 16) ? TYPE_U16
: TYPE_U32
;
1992 /* backend doesn't want undefined instructions, so just plug
1995 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1996 dst
[i
] = create_immed_typed(ctx
->block
, fui(0.0), type
);
2000 * texture fetch/sample instructions:
2004 get_tex_dest_type(nir_tex_instr
*tex
)
2008 switch (nir_alu_type_get_base_type(tex
->dest_type
)) {
2009 case nir_type_invalid
:
2010 case nir_type_float
:
2011 type
= nir_dest_bit_size(tex
->dest
) == 16 ? TYPE_F16
: TYPE_F32
;
2014 type
= nir_dest_bit_size(tex
->dest
) == 16 ? TYPE_S16
: TYPE_S32
;
2018 type
= nir_dest_bit_size(tex
->dest
) == 16 ? TYPE_U16
: TYPE_U32
;
2021 unreachable("bad dest_type");
2028 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
2030 unsigned coords
= glsl_get_sampler_dim_coordinate_components(tex
->sampler_dim
);
2033 /* note: would use tex->coord_components.. except txs.. also,
2034 * since array index goes after shadow ref, we don't want to
2038 flags
|= IR3_INSTR_3D
;
2040 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2041 flags
|= IR3_INSTR_S
;
2043 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
2044 flags
|= IR3_INSTR_A
;
2050 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
2051 * or immediate (in which case it will get lowered later to a non .s2en
2052 * version of the tex instruction which encode tex/samp as immediates:
2054 static struct tex_src_info
2055 get_tex_samp_tex_src(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2057 struct ir3_block
*b
= ctx
->block
;
2058 struct tex_src_info info
= { 0 };
2059 int texture_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_texture_handle
);
2060 int sampler_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_sampler_handle
);
2061 struct ir3_instruction
*texture
, *sampler
;
2063 if (texture_idx
>= 0 || sampler_idx
>= 0) {
2065 info
.flags
|= IR3_INSTR_B
;
2067 /* Gather information required to determine which encoding to
2068 * choose as well as for prefetch.
2070 nir_intrinsic_instr
*bindless_tex
= NULL
;
2072 if (texture_idx
>= 0) {
2073 ctx
->so
->bindless_tex
= true;
2074 bindless_tex
= ir3_bindless_resource(tex
->src
[texture_idx
].src
);
2075 assert(bindless_tex
);
2076 info
.tex_base
= nir_intrinsic_desc_set(bindless_tex
);
2077 tex_const
= nir_src_is_const(bindless_tex
->src
[0]);
2079 info
.tex_idx
= nir_src_as_uint(bindless_tex
->src
[0]);
2081 /* To simplify some of the logic below, assume the index is
2082 * constant 0 when it's not enabled.
2087 nir_intrinsic_instr
*bindless_samp
= NULL
;
2089 if (sampler_idx
>= 0) {
2090 ctx
->so
->bindless_samp
= true;
2091 bindless_samp
= ir3_bindless_resource(tex
->src
[sampler_idx
].src
);
2092 assert(bindless_samp
);
2093 info
.samp_base
= nir_intrinsic_desc_set(bindless_samp
);
2094 samp_const
= nir_src_is_const(bindless_samp
->src
[0]);
2096 info
.samp_idx
= nir_src_as_uint(bindless_samp
->src
[0]);
2102 /* Choose encoding. */
2103 if (tex_const
&& samp_const
&& info
.tex_idx
< 256 && info
.samp_idx
< 256) {
2104 if (info
.tex_idx
< 16 && info
.samp_idx
< 16 &&
2105 (!bindless_tex
|| !bindless_samp
|| info
.tex_base
== info
.samp_base
)) {
2106 /* Everything fits within the instruction */
2107 info
.base
= info
.tex_base
;
2108 info
.combined_idx
= info
.samp_idx
| (info
.tex_idx
<< 4);
2110 info
.base
= info
.tex_base
;
2111 info
.a1_val
= info
.tex_idx
<< 3 | info
.samp_base
;
2112 info
.combined_idx
= info
.samp_idx
;
2113 info
.flags
|= IR3_INSTR_A1EN
;
2115 info
.samp_tex
= NULL
;
2117 info
.flags
|= IR3_INSTR_S2EN
;
2118 /* In the indirect case, we only use a1.x to store the sampler
2119 * base if it differs from the texture base.
2121 if (!bindless_tex
|| !bindless_samp
|| info
.tex_base
== info
.samp_base
) {
2122 info
.base
= info
.tex_base
;
2124 info
.base
= info
.tex_base
;
2125 info
.a1_val
= info
.samp_base
;
2126 info
.flags
|= IR3_INSTR_A1EN
;
2129 /* Note: the indirect source is now a vec2 instead of hvec2, and
2130 * for some reason the texture and sampler are swapped.
2132 struct ir3_instruction
*texture
, *sampler
;
2135 texture
= ir3_get_src(ctx
, &tex
->src
[texture_idx
].src
)[0];
2137 texture
= create_immed(b
, 0);
2140 if (bindless_samp
) {
2141 sampler
= ir3_get_src(ctx
, &tex
->src
[sampler_idx
].src
)[0];
2143 sampler
= create_immed(b
, 0);
2145 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2151 info
.flags
|= IR3_INSTR_S2EN
;
2152 texture_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_texture_offset
);
2153 sampler_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_sampler_offset
);
2154 if (texture_idx
>= 0) {
2155 texture
= ir3_get_src(ctx
, &tex
->src
[texture_idx
].src
)[0];
2156 texture
= ir3_COV(ctx
->block
, texture
, TYPE_U32
, TYPE_U16
);
2158 /* TODO what to do for dynamic case? I guess we only need the
2159 * max index for astc srgb workaround so maybe not a problem
2160 * to worry about if we don't enable indirect samplers for
2163 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex
->texture_index
);
2164 texture
= create_immed_typed(ctx
->block
, tex
->texture_index
, TYPE_U16
);
2165 info
.tex_idx
= tex
->texture_index
;
2168 if (sampler_idx
>= 0) {
2169 sampler
= ir3_get_src(ctx
, &tex
->src
[sampler_idx
].src
)[0];
2170 sampler
= ir3_COV(ctx
->block
, sampler
, TYPE_U32
, TYPE_U16
);
2172 sampler
= create_immed_typed(ctx
->block
, tex
->sampler_index
, TYPE_U16
);
2173 info
.samp_idx
= tex
->texture_index
;
2176 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2186 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2188 struct ir3_block
*b
= ctx
->block
;
2189 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
2190 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
2191 struct ir3_instruction
*lod
, *compare
, *proj
, *sample_index
;
2192 struct tex_src_info info
= { 0 };
2193 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
2194 unsigned i
, coords
, flags
, ncomp
;
2195 unsigned nsrc0
= 0, nsrc1
= 0;
2199 ncomp
= nir_dest_num_components(tex
->dest
);
2201 coord
= off
= ddx
= ddy
= NULL
;
2202 lod
= proj
= compare
= sample_index
= NULL
;
2204 dst
= ir3_get_dst(ctx
, &tex
->dest
, ncomp
);
2206 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
2207 switch (tex
->src
[i
].src_type
) {
2208 case nir_tex_src_coord
:
2209 coord
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2211 case nir_tex_src_bias
:
2212 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2215 case nir_tex_src_lod
:
2216 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2219 case nir_tex_src_comparator
: /* shadow comparator */
2220 compare
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2222 case nir_tex_src_projector
:
2223 proj
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2226 case nir_tex_src_offset
:
2227 off
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2230 case nir_tex_src_ddx
:
2231 ddx
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2233 case nir_tex_src_ddy
:
2234 ddy
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2236 case nir_tex_src_ms_index
:
2237 sample_index
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2239 case nir_tex_src_texture_offset
:
2240 case nir_tex_src_sampler_offset
:
2241 case nir_tex_src_texture_handle
:
2242 case nir_tex_src_sampler_handle
:
2243 /* handled in get_tex_samp_src() */
2246 ir3_context_error(ctx
, "Unhandled NIR tex src type: %d\n",
2247 tex
->src
[i
].src_type
);
2253 case nir_texop_tex_prefetch
:
2254 compile_assert(ctx
, !has_bias
);
2255 compile_assert(ctx
, !has_lod
);
2256 compile_assert(ctx
, !compare
);
2257 compile_assert(ctx
, !has_proj
);
2258 compile_assert(ctx
, !has_off
);
2259 compile_assert(ctx
, !ddx
);
2260 compile_assert(ctx
, !ddy
);
2261 compile_assert(ctx
, !sample_index
);
2262 compile_assert(ctx
, nir_tex_instr_src_index(tex
, nir_tex_src_texture_offset
) < 0);
2263 compile_assert(ctx
, nir_tex_instr_src_index(tex
, nir_tex_src_sampler_offset
) < 0);
2265 if (ctx
->so
->num_sampler_prefetch
< IR3_MAX_SAMPLER_PREFETCH
) {
2266 opc
= OPC_META_TEX_PREFETCH
;
2267 ctx
->so
->num_sampler_prefetch
++;
2271 case nir_texop_tex
: opc
= has_lod
? OPC_SAML
: OPC_SAM
; break;
2272 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2273 case nir_texop_txl
: opc
= OPC_SAML
; break;
2274 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2275 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2276 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2278 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2279 * what blob does, seems gather is broken?), and a3xx did
2280 * not support it (but probably could also emulate).
2282 switch (tex
->component
) {
2283 case 0: opc
= OPC_GATHER4R
; break;
2284 case 1: opc
= OPC_GATHER4G
; break;
2285 case 2: opc
= OPC_GATHER4B
; break;
2286 case 3: opc
= OPC_GATHER4A
; break;
2289 case nir_texop_txf_ms_fb
:
2290 case nir_texop_txf_ms
: opc
= OPC_ISAMM
; break;
2292 ir3_context_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2296 tex_info(tex
, &flags
, &coords
);
2299 * lay out the first argument in the proper order:
2300 * - actual coordinates first
2301 * - shadow reference
2304 * - starting at offset 4, dpdx.xy, dpdy.xy
2306 * bias/lod go into the second arg
2309 /* insert tex coords: */
2310 for (i
= 0; i
< coords
; i
++)
2315 /* scale up integer coords for TXF based on the LOD */
2316 if (ctx
->compiler
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2318 for (i
= 0; i
< coords
; i
++)
2319 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2323 /* hw doesn't do 1d, so we treat it as 2d with
2324 * height of 1, and patch up the y coord.
2327 src0
[nsrc0
++] = create_immed(b
, 0);
2329 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2333 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2334 src0
[nsrc0
++] = compare
;
2336 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2337 struct ir3_instruction
*idx
= coord
[coords
];
2339 /* the array coord for cube arrays needs 0.5 added to it */
2340 if (ctx
->compiler
->array_index_add_half
&& !is_isam(opc
))
2341 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2343 src0
[nsrc0
++] = idx
;
2347 src0
[nsrc0
++] = proj
;
2348 flags
|= IR3_INSTR_P
;
2351 /* pad to 4, then ddx/ddy: */
2352 if (tex
->op
== nir_texop_txd
) {
2354 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2355 for (i
= 0; i
< coords
; i
++)
2356 src0
[nsrc0
++] = ddx
[i
];
2358 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2359 for (i
= 0; i
< coords
; i
++)
2360 src0
[nsrc0
++] = ddy
[i
];
2362 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2365 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2366 * with scaled x coord according to requested sample:
2368 if (opc
== OPC_ISAMM
) {
2369 if (ctx
->compiler
->txf_ms_with_isaml
) {
2370 /* the samples are laid out in x dimension as
2372 * x_ms = (x << ms) + sample_index;
2374 struct ir3_instruction
*ms
;
2375 ms
= create_immed(b
, (ctx
->samples
>> (2 * tex
->texture_index
)) & 3);
2377 src0
[0] = ir3_SHL_B(b
, src0
[0], 0, ms
, 0);
2378 src0
[0] = ir3_ADD_U(b
, src0
[0], 0, sample_index
, 0);
2382 src0
[nsrc0
++] = sample_index
;
2387 * second argument (if applicable):
2392 if (has_off
| has_lod
| has_bias
) {
2394 unsigned off_coords
= coords
;
2395 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2397 for (i
= 0; i
< off_coords
; i
++)
2398 src1
[nsrc1
++] = off
[i
];
2400 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2401 flags
|= IR3_INSTR_O
;
2404 if (has_lod
| has_bias
)
2405 src1
[nsrc1
++] = lod
;
2408 type
= get_tex_dest_type(tex
);
2410 if (opc
== OPC_GETLOD
)
2414 if (tex
->op
== nir_texop_txf_ms_fb
) {
2415 /* only expect a single txf_ms_fb per shader: */
2416 compile_assert(ctx
, !ctx
->so
->fb_read
);
2417 compile_assert(ctx
, ctx
->so
->type
== MESA_SHADER_FRAGMENT
);
2419 ctx
->so
->fb_read
= true;
2420 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2421 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
2422 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
2424 info
.flags
= IR3_INSTR_S2EN
;
2426 ctx
->so
->num_samp
++;
2428 info
= get_tex_samp_tex_src(ctx
, tex
);
2431 struct ir3_instruction
*col0
= ir3_create_collect(ctx
, src0
, nsrc0
);
2432 struct ir3_instruction
*col1
= ir3_create_collect(ctx
, src1
, nsrc1
);
2434 if (opc
== OPC_META_TEX_PREFETCH
) {
2435 int idx
= nir_tex_instr_src_index(tex
, nir_tex_src_coord
);
2437 compile_assert(ctx
, tex
->src
[idx
].src
.is_ssa
);
2439 sam
= ir3_META_TEX_PREFETCH(b
);
2440 __ssa_dst(sam
)->wrmask
= MASK(ncomp
); /* dst */
2441 __ssa_src(sam
, get_barycentric_pixel(ctx
), 0);
2442 sam
->prefetch
.input_offset
=
2443 ir3_nir_coord_offset(tex
->src
[idx
].src
.ssa
);
2444 /* make sure not to add irrelevant flags like S2EN */
2445 sam
->flags
= flags
| (info
.flags
& IR3_INSTR_B
);
2446 sam
->prefetch
.tex
= info
.tex_idx
;
2447 sam
->prefetch
.samp
= info
.samp_idx
;
2448 sam
->prefetch
.tex_base
= info
.tex_base
;
2449 sam
->prefetch
.samp_base
= info
.samp_base
;
2451 info
.flags
|= flags
;
2452 sam
= emit_sam(ctx
, opc
, info
, type
, MASK(ncomp
), col0
, col1
);
2455 if ((ctx
->astc_srgb
& (1 << tex
->texture_index
)) && !nir_tex_instr_is_query(tex
)) {
2456 assert(opc
!= OPC_META_TEX_PREFETCH
);
2458 /* only need first 3 components: */
2459 sam
->regs
[0]->wrmask
= 0x7;
2460 ir3_split_dest(b
, dst
, sam
, 0, 3);
2462 /* we need to sample the alpha separately with a non-ASTC
2465 sam
= ir3_SAM(b
, opc
, type
, 0b1000, flags
| info
.flags
,
2466 info
.samp_tex
, col0
, col1
);
2468 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2470 /* fixup .w component: */
2471 ir3_split_dest(b
, &dst
[3], sam
, 3, 1);
2473 /* normal (non-workaround) case: */
2474 ir3_split_dest(b
, dst
, sam
, 0, ncomp
);
2477 /* GETLOD returns results in 4.8 fixed point */
2478 if (opc
== OPC_GETLOD
) {
2479 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2481 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2482 for (i
= 0; i
< 2; i
++) {
2483 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_S32
, TYPE_F32
), 0,
2488 ir3_put_dst(ctx
, &tex
->dest
);
2492 emit_tex_info(struct ir3_context
*ctx
, nir_tex_instr
*tex
, unsigned idx
)
2494 struct ir3_block
*b
= ctx
->block
;
2495 struct ir3_instruction
**dst
, *sam
;
2496 type_t dst_type
= get_tex_dest_type(tex
);
2497 struct tex_src_info info
= get_tex_samp_tex_src(ctx
, tex
);
2499 dst
= ir3_get_dst(ctx
, &tex
->dest
, 1);
2501 sam
= emit_sam(ctx
, OPC_GETINFO
, info
, dst_type
, 1 << idx
, NULL
, NULL
);
2503 /* even though there is only one component, since it ends
2504 * up in .y/.z/.w rather than .x, we need a split_dest()
2506 ir3_split_dest(b
, dst
, sam
, idx
, 1);
2508 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2509 * the value in TEX_CONST_0 is zero-based.
2511 if (ctx
->compiler
->levels_add_one
)
2512 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2514 ir3_put_dst(ctx
, &tex
->dest
);
2518 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2520 struct ir3_block
*b
= ctx
->block
;
2521 struct ir3_instruction
**dst
, *sam
;
2522 struct ir3_instruction
*lod
;
2523 unsigned flags
, coords
;
2524 type_t dst_type
= get_tex_dest_type(tex
);
2525 struct tex_src_info info
= get_tex_samp_tex_src(ctx
, tex
);
2527 tex_info(tex
, &flags
, &coords
);
2528 info
.flags
|= flags
;
2530 /* Actually we want the number of dimensions, not coordinates. This
2531 * distinction only matters for cubes.
2533 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2536 dst
= ir3_get_dst(ctx
, &tex
->dest
, 4);
2538 int lod_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_lod
);
2539 compile_assert(ctx
, lod_idx
>= 0);
2541 lod
= ir3_get_src(ctx
, &tex
->src
[lod_idx
].src
)[0];
2543 sam
= emit_sam(ctx
, OPC_GETSIZE
, info
, dst_type
, 0b1111, lod
, NULL
);
2544 ir3_split_dest(b
, dst
, sam
, 0, 4);
2546 /* Array size actually ends up in .w rather than .z. This doesn't
2547 * matter for miplevel 0, but for higher mips the value in z is
2548 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2549 * returned, which means that we have to add 1 to it for arrays.
2551 if (tex
->is_array
) {
2552 if (ctx
->compiler
->levels_add_one
) {
2553 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2555 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2559 ir3_put_dst(ctx
, &tex
->dest
);
2563 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2565 switch (jump
->type
) {
2566 case nir_jump_break
:
2567 case nir_jump_continue
:
2568 case nir_jump_return
:
2569 /* I *think* we can simply just ignore this, and use the
2570 * successor block link to figure out where we need to
2571 * jump to for break/continue
2575 ir3_context_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2581 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2583 switch (instr
->type
) {
2584 case nir_instr_type_alu
:
2585 emit_alu(ctx
, nir_instr_as_alu(instr
));
2587 case nir_instr_type_deref
:
2588 /* ignored, handled as part of the intrinsic they are src to */
2590 case nir_instr_type_intrinsic
:
2591 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2593 case nir_instr_type_load_const
:
2594 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2596 case nir_instr_type_ssa_undef
:
2597 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2599 case nir_instr_type_tex
: {
2600 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2601 /* couple tex instructions get special-cased:
2605 emit_tex_txs(ctx
, tex
);
2607 case nir_texop_query_levels
:
2608 emit_tex_info(ctx
, tex
, 2);
2610 case nir_texop_texture_samples
:
2611 emit_tex_info(ctx
, tex
, 3);
2619 case nir_instr_type_jump
:
2620 emit_jump(ctx
, nir_instr_as_jump(instr
));
2622 case nir_instr_type_phi
:
2623 /* we have converted phi webs to regs in NIR by now */
2624 ir3_context_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
2626 case nir_instr_type_call
:
2627 case nir_instr_type_parallel_copy
:
2628 ir3_context_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2633 static struct ir3_block
*
2634 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
2636 struct ir3_block
*block
;
2637 struct hash_entry
*hentry
;
2639 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2641 return hentry
->data
;
2643 block
= ir3_block_create(ctx
->ir
);
2644 block
->nblock
= nblock
;
2645 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2647 set_foreach(nblock
->predecessors
, sentry
) {
2648 _mesa_set_add(block
->predecessors
, get_block(ctx
, sentry
->key
));
2655 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2657 struct ir3_block
*block
= get_block(ctx
, nblock
);
2659 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2660 if (nblock
->successors
[i
]) {
2661 block
->successors
[i
] =
2662 get_block(ctx
, nblock
->successors
[i
]);
2667 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2669 /* re-emit addr register in each block if needed: */
2670 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr0_ht
); i
++) {
2671 _mesa_hash_table_destroy(ctx
->addr0_ht
[i
], NULL
);
2672 ctx
->addr0_ht
[i
] = NULL
;
2675 _mesa_hash_table_u64_destroy(ctx
->addr1_ht
, NULL
);
2676 ctx
->addr1_ht
= NULL
;
2678 nir_foreach_instr (instr
, nblock
) {
2679 ctx
->cur_instr
= instr
;
2680 emit_instr(ctx
, instr
);
2681 ctx
->cur_instr
= NULL
;
2686 _mesa_hash_table_clear(ctx
->sel_cond_conversions
, NULL
);
2689 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
2692 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
2694 struct ir3_instruction
*condition
= ir3_get_src(ctx
, &nif
->condition
)[0];
2696 ctx
->block
->condition
= ir3_get_predicate(ctx
, condition
);
2698 emit_cf_list(ctx
, &nif
->then_list
);
2699 emit_cf_list(ctx
, &nif
->else_list
);
2703 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
2705 emit_cf_list(ctx
, &nloop
->body
);
2710 stack_push(struct ir3_context
*ctx
)
2713 ctx
->max_stack
= MAX2(ctx
->max_stack
, ctx
->stack
);
2717 stack_pop(struct ir3_context
*ctx
)
2719 compile_assert(ctx
, ctx
->stack
> 0);
2724 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
2726 foreach_list_typed (nir_cf_node
, node
, node
, list
) {
2727 switch (node
->type
) {
2728 case nir_cf_node_block
:
2729 emit_block(ctx
, nir_cf_node_as_block(node
));
2731 case nir_cf_node_if
:
2733 emit_if(ctx
, nir_cf_node_as_if(node
));
2736 case nir_cf_node_loop
:
2738 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2741 case nir_cf_node_function
:
2742 ir3_context_error(ctx
, "TODO\n");
2748 /* emit stream-out code. At this point, the current block is the original
2749 * (nir) end block, and nir ensures that all flow control paths terminate
2750 * into the end block. We re-purpose the original end block to generate
2751 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2752 * block holding stream-out write instructions, followed by the new end
2756 * p0.x = (vtxcnt < maxvtxcnt)
2757 * // succs: blockStreamOut, blockNewEnd
2760 * // preds: blockOrigEnd
2761 * ... stream-out instructions ...
2762 * // succs: blockNewEnd
2765 * // preds: blockOrigEnd, blockStreamOut
2769 emit_stream_out(struct ir3_context
*ctx
)
2771 struct ir3
*ir
= ctx
->ir
;
2772 struct ir3_stream_output_info
*strmout
=
2773 &ctx
->so
->shader
->stream_output
;
2774 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2775 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2776 struct ir3_instruction
*bases
[IR3_MAX_SO_BUFFERS
];
2778 /* create vtxcnt input in input block at top of shader,
2779 * so that it is seen as live over the entire duration
2782 vtxcnt
= create_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, 0x1);
2783 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2785 /* at this point, we are at the original 'end' block,
2786 * re-purpose this block to stream-out condition, then
2787 * append stream-out block and new-end block
2789 orig_end_block
= ctx
->block
;
2791 // maybe w/ store_global intrinsic, we could do this
2792 // stuff in nir->nir pass
2794 stream_out_block
= ir3_block_create(ir
);
2795 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2797 new_end_block
= ir3_block_create(ir
);
2798 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2800 orig_end_block
->successors
[0] = stream_out_block
;
2801 orig_end_block
->successors
[1] = new_end_block
;
2803 stream_out_block
->successors
[0] = new_end_block
;
2804 _mesa_set_add(stream_out_block
->predecessors
, orig_end_block
);
2806 _mesa_set_add(new_end_block
->predecessors
, orig_end_block
);
2807 _mesa_set_add(new_end_block
->predecessors
, stream_out_block
);
2809 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2810 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2811 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2812 cond
->regs
[0]->flags
&= ~IR3_REG_SSA
;
2813 cond
->cat2
.condition
= IR3_COND_LT
;
2815 /* condition goes on previous block to the conditional,
2816 * since it is used to pick which of the two successor
2819 orig_end_block
->condition
= cond
;
2821 /* switch to stream_out_block to generate the stream-out
2824 ctx
->block
= stream_out_block
;
2826 /* Calculate base addresses based on vtxcnt. Instructions
2827 * generated for bases not used in following loop will be
2828 * stripped out in the backend.
2830 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
2831 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
2832 unsigned stride
= strmout
->stride
[i
];
2833 struct ir3_instruction
*base
, *off
;
2835 base
= create_uniform(ctx
->block
, regid(const_state
->offsets
.tfbo
, i
));
2837 /* 24-bit should be enough: */
2838 off
= ir3_MUL_U24(ctx
->block
, vtxcnt
, 0,
2839 create_immed(ctx
->block
, stride
* 4), 0);
2841 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2844 /* Generate the per-output store instructions: */
2845 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2846 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2847 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2848 struct ir3_instruction
*base
, *out
, *stg
;
2850 base
= bases
[strmout
->output
[i
].output_buffer
];
2851 out
= ctx
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2853 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2854 create_immed(ctx
->block
, 1), 0);
2855 stg
->cat6
.type
= TYPE_U32
;
2856 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2858 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2862 /* and finally switch to the new_end_block: */
2863 ctx
->block
= new_end_block
;
2867 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
2869 nir_metadata_require(impl
, nir_metadata_block_index
);
2871 compile_assert(ctx
, ctx
->stack
== 0);
2873 emit_cf_list(ctx
, &impl
->body
);
2874 emit_block(ctx
, impl
->end_block
);
2876 compile_assert(ctx
, ctx
->stack
== 0);
2878 /* at this point, we should have a single empty block,
2879 * into which we emit the 'end' instruction.
2881 compile_assert(ctx
, list_is_empty(&ctx
->block
->instr_list
));
2883 /* If stream-out (aka transform-feedback) enabled, emit the
2884 * stream-out instructions, followed by a new empty block (into
2885 * which the 'end' instruction lands).
2887 * NOTE: it is done in this order, rather than inserting before
2888 * we emit end_block, because NIR guarantees that all blocks
2889 * flow into end_block, and that end_block has no successors.
2890 * So by re-purposing end_block as the first block of stream-
2891 * out, we guarantee that all exit paths flow into the stream-
2894 if ((ctx
->compiler
->gpu_id
< 500) &&
2895 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2896 !ctx
->so
->binning_pass
) {
2897 debug_assert(ctx
->so
->type
== MESA_SHADER_VERTEX
);
2898 emit_stream_out(ctx
);
2901 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2902 * NOP and has an epilogue that writes the VS outputs to local storage, to
2903 * be read by the HS. Then it resets execution mask (chmask) and chains
2904 * to the next shader (chsh).
2906 if ((ctx
->so
->type
== MESA_SHADER_VERTEX
&&
2907 (ctx
->so
->key
.has_gs
|| ctx
->so
->key
.tessellation
)) ||
2908 (ctx
->so
->type
== MESA_SHADER_TESS_EVAL
&& ctx
->so
->key
.has_gs
)) {
2909 struct ir3_instruction
*chmask
=
2910 ir3_CHMASK(ctx
->block
);
2911 chmask
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2912 chmask
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
2914 struct ir3_instruction
*chsh
=
2915 ir3_CHSH(ctx
->block
);
2916 chsh
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2917 chsh
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
2919 ir3_END(ctx
->block
);
2924 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
2926 struct ir3_shader_variant
*so
= ctx
->so
;
2927 unsigned ncomp
= glsl_get_components(in
->type
);
2928 unsigned n
= in
->data
.driver_location
;
2929 unsigned frac
= in
->data
.location_frac
;
2930 unsigned slot
= in
->data
.location
;
2932 /* Inputs are loaded using ldlw or ldg for these stages. */
2933 if (ctx
->so
->type
== MESA_SHADER_TESS_CTRL
||
2934 ctx
->so
->type
== MESA_SHADER_TESS_EVAL
||
2935 ctx
->so
->type
== MESA_SHADER_GEOMETRY
)
2938 /* skip unread inputs, we could end up with (for example), unsplit
2939 * matrix/etc inputs in the case they are not read, so just silently
2945 so
->inputs
[n
].slot
= slot
;
2946 so
->inputs
[n
].compmask
|= (1 << (ncomp
+ frac
)) - 1;
2947 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2948 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2950 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
2952 /* if any varyings have 'sample' qualifer, that triggers us
2953 * to run in per-sample mode:
2955 so
->per_samp
|= in
->data
.sample
;
2957 for (int i
= 0; i
< ncomp
; i
++) {
2958 struct ir3_instruction
*instr
= NULL
;
2959 unsigned idx
= (n
* 4) + i
+ frac
;
2961 if (slot
== VARYING_SLOT_POS
) {
2962 ir3_context_error(ctx
, "fragcoord should be a sysval!\n");
2964 /* detect the special case for front/back colors where
2965 * we need to do flat vs smooth shading depending on
2968 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
2970 case VARYING_SLOT_COL0
:
2971 case VARYING_SLOT_COL1
:
2972 case VARYING_SLOT_BFC0
:
2973 case VARYING_SLOT_BFC1
:
2974 so
->inputs
[n
].rasterflat
= true;
2981 if (ctx
->compiler
->flat_bypass
) {
2982 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
2983 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2984 so
->inputs
[n
].use_ldlv
= true;
2987 so
->inputs
[n
].bary
= true;
2989 instr
= create_frag_input(ctx
, so
->inputs
[n
].use_ldlv
, idx
);
2992 compile_assert(ctx
, idx
< ctx
->ninputs
);
2994 ctx
->inputs
[idx
] = instr
;
2996 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
) {
2997 struct ir3_instruction
*input
= NULL
, *in
;
2998 struct ir3_instruction
*components
[4];
2999 unsigned mask
= (1 << (ncomp
+ frac
)) - 1;
3001 foreach_input (in
, ctx
->ir
) {
3002 if (in
->input
.inidx
== n
) {
3009 input
= create_input(ctx
, mask
);
3010 input
->input
.inidx
= n
;
3012 input
->regs
[0]->wrmask
|= mask
;
3015 ir3_split_dest(ctx
->block
, components
, input
, frac
, ncomp
);
3017 for (int i
= 0; i
< ncomp
; i
++) {
3018 unsigned idx
= (n
* 4) + i
+ frac
;
3019 compile_assert(ctx
, idx
< ctx
->ninputs
);
3020 ctx
->inputs
[idx
] = components
[i
];
3023 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3026 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== MESA_SHADER_VERTEX
)) {
3027 so
->total_in
+= ncomp
;
3031 /* Initially we assign non-packed inloc's for varyings, as we don't really
3032 * know up-front which components will be unused. After all the compilation
3033 * stages we scan the shader to see which components are actually used, and
3034 * re-pack the inlocs to eliminate unneeded varyings.
3037 pack_inlocs(struct ir3_context
*ctx
)
3039 struct ir3_shader_variant
*so
= ctx
->so
;
3040 uint8_t used_components
[so
->inputs_count
];
3042 memset(used_components
, 0, sizeof(used_components
));
3045 * First Step: scan shader to find which bary.f/ldlv remain:
3048 foreach_block (block
, &ctx
->ir
->block_list
) {
3049 foreach_instr (instr
, &block
->instr_list
) {
3050 if (is_input(instr
)) {
3051 unsigned inloc
= instr
->regs
[1]->iim_val
;
3052 unsigned i
= inloc
/ 4;
3053 unsigned j
= inloc
% 4;
3055 compile_assert(ctx
, instr
->regs
[1]->flags
& IR3_REG_IMMED
);
3056 compile_assert(ctx
, i
< so
->inputs_count
);
3058 used_components
[i
] |= 1 << j
;
3059 } else if (instr
->opc
== OPC_META_TEX_PREFETCH
) {
3060 for (int n
= 0; n
< 2; n
++) {
3061 unsigned inloc
= instr
->prefetch
.input_offset
+ n
;
3062 unsigned i
= inloc
/ 4;
3063 unsigned j
= inloc
% 4;
3065 compile_assert(ctx
, i
< so
->inputs_count
);
3067 used_components
[i
] |= 1 << j
;
3074 * Second Step: reassign varying inloc/slots:
3077 unsigned actual_in
= 0;
3080 for (unsigned i
= 0; i
< so
->inputs_count
; i
++) {
3081 unsigned compmask
= 0, maxcomp
= 0;
3083 so
->inputs
[i
].inloc
= inloc
;
3084 so
->inputs
[i
].bary
= false;
3086 for (unsigned j
= 0; j
< 4; j
++) {
3087 if (!(used_components
[i
] & (1 << j
)))
3090 compmask
|= (1 << j
);
3094 /* at this point, since used_components[i] mask is only
3095 * considering varyings (ie. not sysvals) we know this
3098 so
->inputs
[i
].bary
= true;
3101 if (so
->inputs
[i
].bary
) {
3103 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
3109 * Third Step: reassign packed inloc's:
3112 foreach_block (block
, &ctx
->ir
->block_list
) {
3113 foreach_instr (instr
, &block
->instr_list
) {
3114 if (is_input(instr
)) {
3115 unsigned inloc
= instr
->regs
[1]->iim_val
;
3116 unsigned i
= inloc
/ 4;
3117 unsigned j
= inloc
% 4;
3119 instr
->regs
[1]->iim_val
= so
->inputs
[i
].inloc
+ j
;
3120 } else if (instr
->opc
== OPC_META_TEX_PREFETCH
) {
3121 unsigned i
= instr
->prefetch
.input_offset
/ 4;
3122 unsigned j
= instr
->prefetch
.input_offset
% 4;
3123 instr
->prefetch
.input_offset
= so
->inputs
[i
].inloc
+ j
;
3130 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
3132 struct ir3_shader_variant
*so
= ctx
->so
;
3133 unsigned ncomp
= glsl_get_components(out
->type
);
3134 unsigned n
= out
->data
.driver_location
;
3135 unsigned frac
= out
->data
.location_frac
;
3136 unsigned slot
= out
->data
.location
;
3138 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
3140 case FRAG_RESULT_DEPTH
:
3141 so
->writes_pos
= true;
3143 case FRAG_RESULT_COLOR
:
3146 case FRAG_RESULT_SAMPLE_MASK
:
3147 so
->writes_smask
= true;
3150 if (slot
>= FRAG_RESULT_DATA0
)
3152 ir3_context_error(ctx
, "unknown FS output name: %s\n",
3153 gl_frag_result_name(slot
));
3155 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
||
3156 ctx
->so
->type
== MESA_SHADER_TESS_EVAL
||
3157 ctx
->so
->type
== MESA_SHADER_GEOMETRY
) {
3159 case VARYING_SLOT_POS
:
3160 so
->writes_pos
= true;
3162 case VARYING_SLOT_PSIZ
:
3163 so
->writes_psize
= true;
3165 case VARYING_SLOT_PRIMITIVE_ID
:
3166 case VARYING_SLOT_LAYER
:
3167 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3
:
3168 debug_assert(ctx
->so
->type
== MESA_SHADER_GEOMETRY
);
3170 case VARYING_SLOT_COL0
:
3171 case VARYING_SLOT_COL1
:
3172 case VARYING_SLOT_BFC0
:
3173 case VARYING_SLOT_BFC1
:
3174 case VARYING_SLOT_FOGC
:
3175 case VARYING_SLOT_CLIP_DIST0
:
3176 case VARYING_SLOT_CLIP_DIST1
:
3177 case VARYING_SLOT_CLIP_VERTEX
:
3180 if (slot
>= VARYING_SLOT_VAR0
)
3182 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
3184 ir3_context_error(ctx
, "unknown %s shader output name: %s\n",
3185 _mesa_shader_stage_to_string(ctx
->so
->type
),
3186 gl_varying_slot_name(slot
));
3188 } else if (ctx
->so
->type
== MESA_SHADER_TESS_CTRL
) {
3189 /* output lowered to buffer writes. */
3192 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3195 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
3197 so
->outputs
[n
].slot
= slot
;
3198 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
3200 for (int i
= 0; i
< ncomp
; i
++) {
3201 unsigned idx
= (n
* 4) + i
+ frac
;
3202 compile_assert(ctx
, idx
< ctx
->noutputs
);
3203 ctx
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3206 /* if varying packing doesn't happen, we could end up in a situation
3207 * with "holes" in the output, and since the per-generation code that
3208 * sets up varying linkage registers doesn't expect to have more than
3209 * one varying per vec4 slot, pad the holes.
3211 * Note that this should probably generate a performance warning of
3214 for (int i
= 0; i
< frac
; i
++) {
3215 unsigned idx
= (n
* 4) + i
;
3216 if (!ctx
->outputs
[idx
]) {
3217 ctx
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3223 emit_instructions(struct ir3_context
*ctx
)
3225 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
3227 ctx
->ninputs
= ctx
->s
->num_inputs
* 4;
3228 ctx
->noutputs
= ctx
->s
->num_outputs
* 4;
3229 ctx
->inputs
= rzalloc_array(ctx
, struct ir3_instruction
*, ctx
->ninputs
);
3230 ctx
->outputs
= rzalloc_array(ctx
, struct ir3_instruction
*, ctx
->noutputs
);
3232 ctx
->ir
= ir3_create(ctx
->compiler
, ctx
->so
->type
);
3234 /* Create inputs in first block: */
3235 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3236 ctx
->in_block
= ctx
->block
;
3238 /* for fragment shader, the vcoord input register is used as the
3239 * base for bary.f varying fetch instrs:
3241 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3242 * until emit_intrinsic when we know they are actually needed.
3243 * For now, we defer creating ctx->ij_centroid, etc, since we
3244 * only need ij_pixel for "old style" varying inputs (ie.
3247 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
3248 ctx
->ij_pixel
= create_input(ctx
, 0x3);
3252 nir_foreach_variable (var
, &ctx
->s
->inputs
) {
3253 setup_input(ctx
, var
);
3256 /* Defer add_sysval_input() stuff until after setup_inputs(),
3257 * because sysvals need to be appended after varyings:
3259 if (ctx
->ij_pixel
) {
3260 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
,
3261 0x3, ctx
->ij_pixel
);
3265 /* Tesselation shaders always need primitive ID for indexing the
3266 * BO. Geometry shaders don't always need it but when they do it has be
3267 * delivered and unclobbered in the VS. To make things easy, we always
3268 * make room for it in VS/DS.
3270 bool has_tess
= ctx
->so
->key
.tessellation
!= IR3_TESS_NONE
;
3271 bool has_gs
= ctx
->so
->key
.has_gs
;
3272 switch (ctx
->so
->type
) {
3273 case MESA_SHADER_VERTEX
:
3275 ctx
->tcs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_TCS_HEADER_IR3
, 0x1);
3276 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3277 } else if (has_gs
) {
3278 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3279 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3282 case MESA_SHADER_TESS_CTRL
:
3283 ctx
->tcs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_TCS_HEADER_IR3
, 0x1);
3284 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3286 case MESA_SHADER_TESS_EVAL
:
3288 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3289 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3291 case MESA_SHADER_GEOMETRY
:
3292 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3293 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3299 /* Setup outputs: */
3300 nir_foreach_variable (var
, &ctx
->s
->outputs
) {
3301 setup_output(ctx
, var
);
3304 /* Find # of samplers: */
3305 nir_foreach_variable (var
, &ctx
->s
->uniforms
) {
3306 ctx
->so
->num_samp
+= glsl_type_get_sampler_count(var
->type
);
3307 /* just assume that we'll be reading from images.. if it
3308 * is write-only we don't have to count it, but not sure
3309 * if there is a good way to know?
3311 ctx
->so
->num_samp
+= glsl_type_get_image_count(var
->type
);
3314 /* NOTE: need to do something more clever when we support >1 fxn */
3315 nir_foreach_register (reg
, &fxn
->registers
) {
3316 ir3_declare_array(ctx
, reg
);
3318 /* And emit the body: */
3320 emit_function(ctx
, fxn
);
3323 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3324 * need to assign the tex state indexes for these after we know the
3328 fixup_astc_srgb(struct ir3_context
*ctx
)
3330 struct ir3_shader_variant
*so
= ctx
->so
;
3331 /* indexed by original tex idx, value is newly assigned alpha sampler
3332 * state tex idx. Zero is invalid since there is at least one sampler
3335 unsigned alt_tex_state
[16] = {0};
3336 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3339 so
->astc_srgb
.base
= tex_idx
;
3341 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3342 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3344 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3346 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3347 /* assign new alternate/alpha tex state slot: */
3348 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3349 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3350 so
->astc_srgb
.count
++;
3353 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3358 fixup_binning_pass(struct ir3_context
*ctx
)
3360 struct ir3_shader_variant
*so
= ctx
->so
;
3361 struct ir3
*ir
= ctx
->ir
;
3364 /* first pass, remove unused outputs from the IR level outputs: */
3365 for (i
= 0, j
= 0; i
< ir
->outputs_count
; i
++) {
3366 struct ir3_instruction
*out
= ir
->outputs
[i
];
3367 assert(out
->opc
== OPC_META_COLLECT
);
3368 unsigned outidx
= out
->collect
.outidx
;
3369 unsigned slot
= so
->outputs
[outidx
].slot
;
3371 /* throw away everything but first position/psize */
3372 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3373 ir
->outputs
[j
] = ir
->outputs
[i
];
3377 ir
->outputs_count
= j
;
3379 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3382 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3383 unsigned slot
= so
->outputs
[i
].slot
;
3385 /* throw away everything but first position/psize */
3386 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3387 so
->outputs
[j
] = so
->outputs
[i
];
3389 /* fixup outidx to point to new output table entry: */
3390 struct ir3_instruction
*out
;
3391 foreach_output (out
, ir
) {
3392 if (out
->collect
.outidx
== i
) {
3393 out
->collect
.outidx
= j
;
3401 so
->outputs_count
= j
;
3405 collect_tex_prefetches(struct ir3_context
*ctx
, struct ir3
*ir
)
3409 /* Collect sampling instructions eligible for pre-dispatch. */
3410 foreach_block (block
, &ir
->block_list
) {
3411 foreach_instr_safe (instr
, &block
->instr_list
) {
3412 if (instr
->opc
== OPC_META_TEX_PREFETCH
) {
3413 assert(idx
< ARRAY_SIZE(ctx
->so
->sampler_prefetch
));
3414 struct ir3_sampler_prefetch
*fetch
=
3415 &ctx
->so
->sampler_prefetch
[idx
];
3418 if (instr
->flags
& IR3_INSTR_B
) {
3419 fetch
->cmd
= IR3_SAMPLER_BINDLESS_PREFETCH_CMD
;
3420 /* In bindless mode, the index is actually the base */
3421 fetch
->tex_id
= instr
->prefetch
.tex_base
;
3422 fetch
->samp_id
= instr
->prefetch
.samp_base
;
3423 fetch
->tex_bindless_id
= instr
->prefetch
.tex
;
3424 fetch
->samp_bindless_id
= instr
->prefetch
.samp
;
3426 fetch
->cmd
= IR3_SAMPLER_PREFETCH_CMD
;
3427 fetch
->tex_id
= instr
->prefetch
.tex
;
3428 fetch
->samp_id
= instr
->prefetch
.samp
;
3430 fetch
->wrmask
= instr
->regs
[0]->wrmask
;
3431 fetch
->dst
= instr
->regs
[0]->num
;
3432 fetch
->src
= instr
->prefetch
.input_offset
;
3435 MAX2(ctx
->so
->total_in
, instr
->prefetch
.input_offset
+ 2);
3437 /* Disable half precision until supported. */
3438 fetch
->half_precision
= !!(instr
->regs
[0]->flags
& IR3_REG_HALF
);
3440 /* Remove the prefetch placeholder instruction: */
3441 list_delinit(&instr
->node
);
3448 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3449 struct ir3_shader_variant
*so
)
3451 struct ir3_context
*ctx
;
3453 int ret
= 0, max_bary
;
3457 ctx
= ir3_context_init(compiler
, so
);
3459 DBG("INIT failed!");
3464 emit_instructions(ctx
);
3467 DBG("EMIT failed!");
3472 ir
= so
->ir
= ctx
->ir
;
3474 assert((ctx
->noutputs
% 4) == 0);
3476 /* Setup IR level outputs, which are "collects" that gather
3477 * the scalar components of outputs.
3479 for (unsigned i
= 0; i
< ctx
->noutputs
; i
+= 4) {
3481 /* figure out the # of components written:
3483 * TODO do we need to handle holes, ie. if .x and .z
3484 * components written, but .y component not written?
3486 for (unsigned j
= 0; j
< 4; j
++) {
3487 if (!ctx
->outputs
[i
+ j
])
3492 /* Note that in some stages, like TCS, store_output is
3493 * lowered to memory writes, so no components of the
3494 * are "written" from the PoV of traditional store-
3495 * output instructions:
3500 struct ir3_instruction
*out
=
3501 ir3_create_collect(ctx
, &ctx
->outputs
[i
], ncomp
);
3504 assert(outidx
< so
->outputs_count
);
3506 /* stash index into so->outputs[] so we can map the
3507 * output back to slot/etc later:
3509 out
->collect
.outidx
= outidx
;
3511 array_insert(ir
, ir
->outputs
, out
);
3514 /* Set up the gs header as an output for the vertex shader so it won't
3515 * clobber it for the tess ctrl shader.
3517 * TODO this could probably be done more cleanly in a nir pass.
3519 if (ctx
->so
->type
== MESA_SHADER_VERTEX
||
3520 (ctx
->so
->key
.has_gs
&& ctx
->so
->type
== MESA_SHADER_TESS_EVAL
)) {
3521 if (ctx
->primitive_id
) {
3522 unsigned n
= so
->outputs_count
++;
3523 so
->outputs
[n
].slot
= VARYING_SLOT_PRIMITIVE_ID
;
3525 struct ir3_instruction
*out
=
3526 ir3_create_collect(ctx
, &ctx
->primitive_id
, 1);
3527 out
->collect
.outidx
= n
;
3528 array_insert(ir
, ir
->outputs
, out
);
3531 if (ctx
->gs_header
) {
3532 unsigned n
= so
->outputs_count
++;
3533 so
->outputs
[n
].slot
= VARYING_SLOT_GS_HEADER_IR3
;
3534 struct ir3_instruction
*out
=
3535 ir3_create_collect(ctx
, &ctx
->gs_header
, 1);
3536 out
->collect
.outidx
= n
;
3537 array_insert(ir
, ir
->outputs
, out
);
3540 if (ctx
->tcs_header
) {
3541 unsigned n
= so
->outputs_count
++;
3542 so
->outputs
[n
].slot
= VARYING_SLOT_TCS_HEADER_IR3
;
3543 struct ir3_instruction
*out
=
3544 ir3_create_collect(ctx
, &ctx
->tcs_header
, 1);
3545 out
->collect
.outidx
= n
;
3546 array_insert(ir
, ir
->outputs
, out
);
3550 /* at this point, for binning pass, throw away unneeded outputs: */
3551 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
< 600))
3552 fixup_binning_pass(ctx
);
3554 ir3_debug_print(ir
, "BEFORE CF");
3558 ir3_debug_print(ir
, "BEFORE CP");
3562 /* at this point, for binning pass, throw away unneeded outputs:
3563 * Note that for a6xx and later, we do this after ir3_cp to ensure
3564 * that the uniform/constant layout for BS and VS matches, so that
3565 * we can re-use same VS_CONST state group.
3567 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
>= 600))
3568 fixup_binning_pass(ctx
);
3570 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3571 * need to make sure not to remove any inputs that are used by
3572 * the nonbinning VS.
3574 if (ctx
->compiler
->gpu_id
>= 600 && so
->binning_pass
&&
3575 so
->type
== MESA_SHADER_VERTEX
) {
3576 for (int i
= 0; i
< ctx
->ninputs
; i
++) {
3577 struct ir3_instruction
*in
= ctx
->inputs
[i
];
3585 debug_assert(n
< so
->nonbinning
->inputs_count
);
3587 if (so
->nonbinning
->inputs
[n
].sysval
)
3590 /* be sure to keep inputs, even if only used in VS */
3591 if (so
->nonbinning
->inputs
[n
].compmask
& (1 << c
))
3592 array_insert(in
->block
, in
->block
->keeps
, in
);
3596 ir3_debug_print(ir
, "BEFORE GROUPING");
3598 ir3_sched_add_deps(ir
);
3600 /* Group left/right neighbors, inserting mov's where needed to
3605 ir3_debug_print(ir
, "AFTER GROUPING");
3609 ir3_debug_print(ir
, "AFTER DCE");
3611 /* do Sethi–Ullman numbering before scheduling: */
3614 ret
= ir3_sched(ir
);
3616 DBG("SCHED failed!");
3620 ir3_debug_print(ir
, "AFTER SCHED");
3622 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3623 * with draw pass VS, so binning and draw pass can both use the
3626 * Note that VS inputs are expected to be full precision.
3628 bool pre_assign_inputs
= (ir
->compiler
->gpu_id
>= 600) &&
3629 (ir
->type
== MESA_SHADER_VERTEX
) &&
3632 if (pre_assign_inputs
) {
3633 for (unsigned i
= 0; i
< ctx
->ninputs
; i
++) {
3634 struct ir3_instruction
*instr
= ctx
->inputs
[i
];
3641 unsigned regid
= so
->nonbinning
->inputs
[n
].regid
+ c
;
3643 instr
->regs
[0]->num
= regid
;
3646 ret
= ir3_ra(so
, ctx
->inputs
, ctx
->ninputs
);
3647 } else if (ctx
->tcs_header
) {
3648 /* We need to have these values in the same registers between VS and TCS
3649 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3652 ctx
->tcs_header
->regs
[0]->num
= regid(0, 0);
3653 ctx
->primitive_id
->regs
[0]->num
= regid(0, 1);
3654 struct ir3_instruction
*precolor
[] = { ctx
->tcs_header
, ctx
->primitive_id
};
3655 ret
= ir3_ra(so
, precolor
, ARRAY_SIZE(precolor
));
3656 } else if (ctx
->gs_header
) {
3657 /* We need to have these values in the same registers between producer
3658 * (VS or DS) and GS since the producer chains to GS and doesn't get
3659 * the sysvals redelivered.
3662 ctx
->gs_header
->regs
[0]->num
= regid(0, 0);
3663 ctx
->primitive_id
->regs
[0]->num
= regid(0, 1);
3664 struct ir3_instruction
*precolor
[] = { ctx
->gs_header
, ctx
->primitive_id
};
3665 ret
= ir3_ra(so
, precolor
, ARRAY_SIZE(precolor
));
3666 } else if (so
->num_sampler_prefetch
) {
3667 assert(so
->type
== MESA_SHADER_FRAGMENT
);
3668 struct ir3_instruction
*instr
, *precolor
[2];
3671 foreach_input (instr
, ir
) {
3672 if (instr
->input
.sysval
!= SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
)
3675 assert(idx
< ARRAY_SIZE(precolor
));
3677 precolor
[idx
] = instr
;
3678 instr
->regs
[0]->num
= idx
;
3682 ret
= ir3_ra(so
, precolor
, idx
);
3684 ret
= ir3_ra(so
, NULL
, 0);
3693 ir3_debug_print(ir
, "AFTER POSTSCHED");
3695 if (compiler
->gpu_id
>= 600) {
3696 if (ir3_a6xx_fixup_atomic_dests(ir
, so
)) {
3697 ir3_debug_print(ir
, "AFTER ATOMIC FIXUP");
3701 if (so
->type
== MESA_SHADER_FRAGMENT
)
3705 * Fixup inputs/outputs to point to the actual registers assigned:
3707 * 1) initialize to r63.x (invalid/unused)
3708 * 2) iterate IR level inputs/outputs and update the variants
3709 * inputs/outputs table based on the assigned registers for
3710 * the remaining inputs/outputs.
3713 for (unsigned i
= 0; i
< so
->inputs_count
; i
++)
3714 so
->inputs
[i
].regid
= INVALID_REG
;
3715 for (unsigned i
= 0; i
< so
->outputs_count
; i
++)
3716 so
->outputs
[i
].regid
= INVALID_REG
;
3718 struct ir3_instruction
*out
;
3719 foreach_output (out
, ir
) {
3720 assert(out
->opc
== OPC_META_COLLECT
);
3721 unsigned outidx
= out
->collect
.outidx
;
3723 so
->outputs
[outidx
].regid
= out
->regs
[0]->num
;
3724 so
->outputs
[outidx
].half
= !!(out
->regs
[0]->flags
& IR3_REG_HALF
);
3727 struct ir3_instruction
*in
;
3728 foreach_input (in
, ir
) {
3729 assert(in
->opc
== OPC_META_INPUT
);
3730 unsigned inidx
= in
->input
.inidx
;
3732 if (pre_assign_inputs
&& !so
->inputs
[inidx
].sysval
) {
3733 if (VALIDREG(so
->nonbinning
->inputs
[inidx
].regid
)) {
3734 compile_assert(ctx
, in
->regs
[0]->num
==
3735 so
->nonbinning
->inputs
[inidx
].regid
);
3736 compile_assert(ctx
, !!(in
->regs
[0]->flags
& IR3_REG_HALF
) ==
3737 so
->nonbinning
->inputs
[inidx
].half
);
3739 so
->inputs
[inidx
].regid
= so
->nonbinning
->inputs
[inidx
].regid
;
3740 so
->inputs
[inidx
].half
= so
->nonbinning
->inputs
[inidx
].half
;
3742 so
->inputs
[inidx
].regid
= in
->regs
[0]->num
;
3743 so
->inputs
[inidx
].half
= !!(in
->regs
[0]->flags
& IR3_REG_HALF
);
3748 fixup_astc_srgb(ctx
);
3750 /* We need to do legalize after (for frag shader's) the "bary.f"
3751 * offsets (inloc) have been assigned.
3753 ir3_legalize(ir
, so
, &max_bary
);
3755 ir3_debug_print(ir
, "AFTER LEGALIZE");
3757 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3758 * know what we might have to wait on when coming in from VS chsh.
3760 if (so
->type
== MESA_SHADER_TESS_CTRL
||
3761 so
->type
== MESA_SHADER_GEOMETRY
) {
3762 foreach_block (block
, &ir
->block_list
) {
3763 foreach_instr (instr
, &block
->instr_list
) {
3764 instr
->flags
|= IR3_INSTR_SS
| IR3_INSTR_SY
;
3770 so
->branchstack
= ctx
->max_stack
;
3772 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3773 if (so
->type
== MESA_SHADER_FRAGMENT
)
3774 so
->total_in
= max_bary
+ 1;
3776 so
->max_sun
= ir
->max_sun
;
3778 /* Collect sampling instructions eligible for pre-dispatch. */
3779 collect_tex_prefetches(ctx
, ir
);
3781 if (so
->type
== MESA_SHADER_FRAGMENT
&&
3782 ctx
->s
->info
.fs
.needs_helper_invocations
)
3783 so
->need_pixlod
= true;
3788 ir3_destroy(so
->ir
);
3791 ir3_context_free(ctx
);