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freedreno/ir3: Extend RA with mechanism for pre-coloring registers
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 ir3_reg_create(mov, 0, 0);
55 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
56 src->instr = collect;
57 src->size = arrsz;
58 src->array.offset = n;
59
60 ir3_instr_set_address(mov, address);
61
62 return mov;
63 }
64
65 static struct ir3_instruction *
66 create_input_compmask(struct ir3_context *ctx, unsigned n, unsigned compmask)
67 {
68 struct ir3_instruction *in;
69
70 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
71 in->inout.block = ctx->in_block;
72 ir3_reg_create(in, n, 0);
73
74 in->regs[0]->wrmask = compmask;
75
76 return in;
77 }
78
79 static struct ir3_instruction *
80 create_input(struct ir3_context *ctx, unsigned n)
81 {
82 return create_input_compmask(ctx, n, 0x1);
83 }
84
85 static struct ir3_instruction *
86 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
87 {
88 struct ir3_block *block = ctx->block;
89 struct ir3_instruction *instr;
90 /* packed inloc is fixed up later: */
91 struct ir3_instruction *inloc = create_immed(block, n);
92
93 if (use_ldlv) {
94 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
95 instr->cat6.type = TYPE_U32;
96 instr->cat6.iim_val = 1;
97 } else {
98 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
99 instr->regs[2]->wrmask = 0x3;
100 }
101
102 return instr;
103 }
104
105 static struct ir3_instruction *
106 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
107 {
108 /* first four vec4 sysval's reserved for UBOs: */
109 /* NOTE: dp is in scalar, but there can be >4 dp components: */
110 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
111 unsigned n = const_state->offsets.driver_param;
112 unsigned r = regid(n + dp / 4, dp % 4);
113 return create_uniform(ctx->block, r);
114 }
115
116 /*
117 * Adreno uses uint rather than having dedicated bool type,
118 * which (potentially) requires some conversion, in particular
119 * when using output of an bool instr to int input, or visa
120 * versa.
121 *
122 * | Adreno | NIR |
123 * -------+---------+-------+-
124 * true | 1 | ~0 |
125 * false | 0 | 0 |
126 *
127 * To convert from an adreno bool (uint) to nir, use:
128 *
129 * absneg.s dst, (neg)src
130 *
131 * To convert back in the other direction:
132 *
133 * absneg.s dst, (abs)arc
134 *
135 * The CP step can clean up the absneg.s that cancel each other
136 * out, and with a slight bit of extra cleverness (to recognize
137 * the instructions which produce either a 0 or 1) can eliminate
138 * the absneg.s's completely when an instruction that wants
139 * 0/1 consumes the result. For example, when a nir 'bcsel'
140 * consumes the result of 'feq'. So we should be able to get by
141 * without a boolean resolve step, and without incuring any
142 * extra penalty in instruction count.
143 */
144
145 /* NIR bool -> native (adreno): */
146 static struct ir3_instruction *
147 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
148 {
149 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
150 }
151
152 /* native (adreno) -> NIR bool: */
153 static struct ir3_instruction *
154 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
155 {
156 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
157 }
158
159 /*
160 * alu/sfu instructions:
161 */
162
163 static struct ir3_instruction *
164 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
165 unsigned src_bitsize, nir_op op)
166 {
167 type_t src_type, dst_type;
168
169 switch (op) {
170 case nir_op_f2f32:
171 case nir_op_f2f16_rtne:
172 case nir_op_f2f16_rtz:
173 case nir_op_f2f16:
174 case nir_op_f2i32:
175 case nir_op_f2i16:
176 case nir_op_f2i8:
177 case nir_op_f2u32:
178 case nir_op_f2u16:
179 case nir_op_f2u8:
180 switch (src_bitsize) {
181 case 32:
182 src_type = TYPE_F32;
183 break;
184 case 16:
185 src_type = TYPE_F16;
186 break;
187 default:
188 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
189 }
190 break;
191
192 case nir_op_i2f32:
193 case nir_op_i2f16:
194 case nir_op_i2i32:
195 case nir_op_i2i16:
196 case nir_op_i2i8:
197 switch (src_bitsize) {
198 case 32:
199 src_type = TYPE_S32;
200 break;
201 case 16:
202 src_type = TYPE_S16;
203 break;
204 case 8:
205 src_type = TYPE_S8;
206 break;
207 default:
208 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
209 }
210 break;
211
212 case nir_op_u2f32:
213 case nir_op_u2f16:
214 case nir_op_u2u32:
215 case nir_op_u2u16:
216 case nir_op_u2u8:
217 switch (src_bitsize) {
218 case 32:
219 src_type = TYPE_U32;
220 break;
221 case 16:
222 src_type = TYPE_U16;
223 break;
224 case 8:
225 src_type = TYPE_U8;
226 break;
227 default:
228 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
229 }
230 break;
231
232 default:
233 ir3_context_error(ctx, "invalid conversion op: %u", op);
234 }
235
236 switch (op) {
237 case nir_op_f2f32:
238 case nir_op_i2f32:
239 case nir_op_u2f32:
240 dst_type = TYPE_F32;
241 break;
242
243 case nir_op_f2f16_rtne:
244 case nir_op_f2f16_rtz:
245 case nir_op_f2f16:
246 /* TODO how to handle rounding mode? */
247 case nir_op_i2f16:
248 case nir_op_u2f16:
249 dst_type = TYPE_F16;
250 break;
251
252 case nir_op_f2i32:
253 case nir_op_i2i32:
254 dst_type = TYPE_S32;
255 break;
256
257 case nir_op_f2i16:
258 case nir_op_i2i16:
259 dst_type = TYPE_S16;
260 break;
261
262 case nir_op_f2i8:
263 case nir_op_i2i8:
264 dst_type = TYPE_S8;
265 break;
266
267 case nir_op_f2u32:
268 case nir_op_u2u32:
269 dst_type = TYPE_U32;
270 break;
271
272 case nir_op_f2u16:
273 case nir_op_u2u16:
274 dst_type = TYPE_U16;
275 break;
276
277 case nir_op_f2u8:
278 case nir_op_u2u8:
279 dst_type = TYPE_U8;
280 break;
281
282 default:
283 ir3_context_error(ctx, "invalid conversion op: %u", op);
284 }
285
286 return ir3_COV(ctx->block, src, src_type, dst_type);
287 }
288
289 static void
290 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
291 {
292 const nir_op_info *info = &nir_op_infos[alu->op];
293 struct ir3_instruction **dst, *src[info->num_inputs];
294 unsigned bs[info->num_inputs]; /* bit size */
295 struct ir3_block *b = ctx->block;
296 unsigned dst_sz, wrmask;
297 type_t dst_type = nir_dest_bit_size(alu->dest.dest) < 32 ?
298 TYPE_U16 : TYPE_U32;
299
300 if (alu->dest.dest.is_ssa) {
301 dst_sz = alu->dest.dest.ssa.num_components;
302 wrmask = (1 << dst_sz) - 1;
303 } else {
304 dst_sz = alu->dest.dest.reg.reg->num_components;
305 wrmask = alu->dest.write_mask;
306 }
307
308 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
309
310 /* Vectors are special in that they have non-scalarized writemasks,
311 * and just take the first swizzle channel for each argument in
312 * order into each writemask channel.
313 */
314 if ((alu->op == nir_op_vec2) ||
315 (alu->op == nir_op_vec3) ||
316 (alu->op == nir_op_vec4)) {
317
318 for (int i = 0; i < info->num_inputs; i++) {
319 nir_alu_src *asrc = &alu->src[i];
320
321 compile_assert(ctx, !asrc->abs);
322 compile_assert(ctx, !asrc->negate);
323
324 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
325 if (!src[i])
326 src[i] = create_immed_typed(ctx->block, 0, dst_type);
327 dst[i] = ir3_MOV(b, src[i], dst_type);
328 }
329
330 ir3_put_dst(ctx, &alu->dest.dest);
331 return;
332 }
333
334 /* We also get mov's with more than one component for mov's so
335 * handle those specially:
336 */
337 if (alu->op == nir_op_mov) {
338 nir_alu_src *asrc = &alu->src[0];
339 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
340
341 for (unsigned i = 0; i < dst_sz; i++) {
342 if (wrmask & (1 << i)) {
343 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
344 } else {
345 dst[i] = NULL;
346 }
347 }
348
349 ir3_put_dst(ctx, &alu->dest.dest);
350 return;
351 }
352
353 /* General case: We can just grab the one used channel per src. */
354 for (int i = 0; i < info->num_inputs; i++) {
355 unsigned chan = ffs(alu->dest.write_mask) - 1;
356 nir_alu_src *asrc = &alu->src[i];
357
358 compile_assert(ctx, !asrc->abs);
359 compile_assert(ctx, !asrc->negate);
360
361 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
362 bs[i] = nir_src_bit_size(asrc->src);
363
364 compile_assert(ctx, src[i]);
365 }
366
367 switch (alu->op) {
368 case nir_op_f2f32:
369 case nir_op_f2f16_rtne:
370 case nir_op_f2f16_rtz:
371 case nir_op_f2f16:
372 case nir_op_f2i32:
373 case nir_op_f2i16:
374 case nir_op_f2i8:
375 case nir_op_f2u32:
376 case nir_op_f2u16:
377 case nir_op_f2u8:
378 case nir_op_i2f32:
379 case nir_op_i2f16:
380 case nir_op_i2i32:
381 case nir_op_i2i16:
382 case nir_op_i2i8:
383 case nir_op_u2f32:
384 case nir_op_u2f16:
385 case nir_op_u2u32:
386 case nir_op_u2u16:
387 case nir_op_u2u8:
388 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
389 break;
390 case nir_op_fquantize2f16:
391 dst[0] = create_cov(ctx,
392 create_cov(ctx, src[0], 32, nir_op_f2f16),
393 16, nir_op_f2f32);
394 break;
395 case nir_op_f2b32:
396 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
397 dst[0]->cat2.condition = IR3_COND_NE;
398 dst[0] = ir3_n2b(b, dst[0]);
399 break;
400 case nir_op_b2f16:
401 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F16);
402 break;
403 case nir_op_b2f32:
404 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
405 break;
406 case nir_op_b2i8:
407 case nir_op_b2i16:
408 case nir_op_b2i32:
409 dst[0] = ir3_b2n(b, src[0]);
410 break;
411 case nir_op_i2b32:
412 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
413 dst[0]->cat2.condition = IR3_COND_NE;
414 dst[0] = ir3_n2b(b, dst[0]);
415 break;
416
417 case nir_op_fneg:
418 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
419 break;
420 case nir_op_fabs:
421 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
422 break;
423 case nir_op_fmax:
424 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
425 break;
426 case nir_op_fmin:
427 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
428 break;
429 case nir_op_fsat:
430 /* if there is just a single use of the src, and it supports
431 * (sat) bit, we can just fold the (sat) flag back to the
432 * src instruction and create a mov. This is easier for cp
433 * to eliminate.
434 *
435 * TODO probably opc_cat==4 is ok too
436 */
437 if (alu->src[0].src.is_ssa &&
438 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
439 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
440 src[0]->flags |= IR3_INSTR_SAT;
441 dst[0] = ir3_MOV(b, src[0], dst_type);
442 } else {
443 /* otherwise generate a max.f that saturates.. blob does
444 * similar (generating a cat2 mov using max.f)
445 */
446 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
447 dst[0]->flags |= IR3_INSTR_SAT;
448 }
449 break;
450 case nir_op_fmul:
451 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
452 break;
453 case nir_op_fadd:
454 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
455 break;
456 case nir_op_fsub:
457 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
458 break;
459 case nir_op_ffma:
460 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
461 break;
462 case nir_op_fddx:
463 case nir_op_fddx_coarse:
464 dst[0] = ir3_DSX(b, src[0], 0);
465 dst[0]->cat5.type = TYPE_F32;
466 break;
467 case nir_op_fddy:
468 case nir_op_fddy_coarse:
469 dst[0] = ir3_DSY(b, src[0], 0);
470 dst[0]->cat5.type = TYPE_F32;
471 break;
472 break;
473 case nir_op_flt32:
474 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
475 dst[0]->cat2.condition = IR3_COND_LT;
476 dst[0] = ir3_n2b(b, dst[0]);
477 break;
478 case nir_op_fge32:
479 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
480 dst[0]->cat2.condition = IR3_COND_GE;
481 dst[0] = ir3_n2b(b, dst[0]);
482 break;
483 case nir_op_feq32:
484 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
485 dst[0]->cat2.condition = IR3_COND_EQ;
486 dst[0] = ir3_n2b(b, dst[0]);
487 break;
488 case nir_op_fne32:
489 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
490 dst[0]->cat2.condition = IR3_COND_NE;
491 dst[0] = ir3_n2b(b, dst[0]);
492 break;
493 case nir_op_fceil:
494 dst[0] = ir3_CEIL_F(b, src[0], 0);
495 break;
496 case nir_op_ffloor:
497 dst[0] = ir3_FLOOR_F(b, src[0], 0);
498 break;
499 case nir_op_ftrunc:
500 dst[0] = ir3_TRUNC_F(b, src[0], 0);
501 break;
502 case nir_op_fround_even:
503 dst[0] = ir3_RNDNE_F(b, src[0], 0);
504 break;
505 case nir_op_fsign:
506 dst[0] = ir3_SIGN_F(b, src[0], 0);
507 break;
508
509 case nir_op_fsin:
510 dst[0] = ir3_SIN(b, src[0], 0);
511 break;
512 case nir_op_fcos:
513 dst[0] = ir3_COS(b, src[0], 0);
514 break;
515 case nir_op_frsq:
516 dst[0] = ir3_RSQ(b, src[0], 0);
517 break;
518 case nir_op_frcp:
519 dst[0] = ir3_RCP(b, src[0], 0);
520 break;
521 case nir_op_flog2:
522 dst[0] = ir3_LOG2(b, src[0], 0);
523 break;
524 case nir_op_fexp2:
525 dst[0] = ir3_EXP2(b, src[0], 0);
526 break;
527 case nir_op_fsqrt:
528 dst[0] = ir3_SQRT(b, src[0], 0);
529 break;
530
531 case nir_op_iabs:
532 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
533 break;
534 case nir_op_iadd:
535 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
536 break;
537 case nir_op_iand:
538 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
539 break;
540 case nir_op_imax:
541 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
542 break;
543 case nir_op_umax:
544 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
545 break;
546 case nir_op_imin:
547 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
548 break;
549 case nir_op_umin:
550 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
551 break;
552 case nir_op_umul_low:
553 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
554 break;
555 case nir_op_imadsh_mix16:
556 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
557 break;
558 case nir_op_ineg:
559 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
560 break;
561 case nir_op_inot:
562 dst[0] = ir3_NOT_B(b, src[0], 0);
563 break;
564 case nir_op_ior:
565 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
566 break;
567 case nir_op_ishl:
568 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
569 break;
570 case nir_op_ishr:
571 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
572 break;
573 case nir_op_isub:
574 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
575 break;
576 case nir_op_ixor:
577 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
578 break;
579 case nir_op_ushr:
580 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
581 break;
582 case nir_op_ilt32:
583 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
584 dst[0]->cat2.condition = IR3_COND_LT;
585 dst[0] = ir3_n2b(b, dst[0]);
586 break;
587 case nir_op_ige32:
588 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
589 dst[0]->cat2.condition = IR3_COND_GE;
590 dst[0] = ir3_n2b(b, dst[0]);
591 break;
592 case nir_op_ieq32:
593 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
594 dst[0]->cat2.condition = IR3_COND_EQ;
595 dst[0] = ir3_n2b(b, dst[0]);
596 break;
597 case nir_op_ine32:
598 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
599 dst[0]->cat2.condition = IR3_COND_NE;
600 dst[0] = ir3_n2b(b, dst[0]);
601 break;
602 case nir_op_ult32:
603 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
604 dst[0]->cat2.condition = IR3_COND_LT;
605 dst[0] = ir3_n2b(b, dst[0]);
606 break;
607 case nir_op_uge32:
608 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
609 dst[0]->cat2.condition = IR3_COND_GE;
610 dst[0] = ir3_n2b(b, dst[0]);
611 break;
612
613 case nir_op_b32csel: {
614 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
615 compile_assert(ctx, bs[1] == bs[2]);
616 /* the boolean condition is 32b even if src[1] and src[2] are
617 * half-precision, but sel.b16 wants all three src's to be the
618 * same type.
619 */
620 if (bs[1] < 32)
621 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
622 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
623 break;
624 }
625 case nir_op_bit_count: {
626 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
627 // double check on earlier gen's. Once half-precision support is
628 // in place, this should probably move to a NIR lowering pass:
629 struct ir3_instruction *hi, *lo;
630
631 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
632 TYPE_U32, TYPE_U16);
633 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
634
635 hi = ir3_CBITS_B(b, hi, 0);
636 lo = ir3_CBITS_B(b, lo, 0);
637
638 // TODO maybe the builders should default to making dst half-precision
639 // if the src's were half precision, to make this less awkward.. otoh
640 // we should probably just do this lowering in NIR.
641 hi->regs[0]->flags |= IR3_REG_HALF;
642 lo->regs[0]->flags |= IR3_REG_HALF;
643
644 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
645 dst[0]->regs[0]->flags |= IR3_REG_HALF;
646 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
647 break;
648 }
649 case nir_op_ifind_msb: {
650 struct ir3_instruction *cmp;
651 dst[0] = ir3_CLZ_S(b, src[0], 0);
652 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
653 cmp->cat2.condition = IR3_COND_GE;
654 dst[0] = ir3_SEL_B32(b,
655 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
656 cmp, 0, dst[0], 0);
657 break;
658 }
659 case nir_op_ufind_msb:
660 dst[0] = ir3_CLZ_B(b, src[0], 0);
661 dst[0] = ir3_SEL_B32(b,
662 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
663 src[0], 0, dst[0], 0);
664 break;
665 case nir_op_find_lsb:
666 dst[0] = ir3_BFREV_B(b, src[0], 0);
667 dst[0] = ir3_CLZ_B(b, dst[0], 0);
668 break;
669 case nir_op_bitfield_reverse:
670 dst[0] = ir3_BFREV_B(b, src[0], 0);
671 break;
672
673 default:
674 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
675 nir_op_infos[alu->op].name);
676 break;
677 }
678
679 ir3_put_dst(ctx, &alu->dest.dest);
680 }
681
682 /* handles direct/indirect UBO reads: */
683 static void
684 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
685 struct ir3_instruction **dst)
686 {
687 struct ir3_block *b = ctx->block;
688 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
689 /* UBO addresses are the first driver params, but subtract 2 here to
690 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
691 * is the uniforms: */
692 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
693 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
694 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
695
696 int off = 0;
697
698 /* First src is ubo index, which could either be an immed or not: */
699 src0 = ir3_get_src(ctx, &intr->src[0])[0];
700 if (is_same_type_mov(src0) &&
701 (src0->regs[1]->flags & IR3_REG_IMMED)) {
702 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
703 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
704 } else {
705 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
706 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
707
708 /* NOTE: since relative addressing is used, make sure constlen is
709 * at least big enough to cover all the UBO addresses, since the
710 * assembler won't know what the max address reg is.
711 */
712 ctx->so->constlen = MAX2(ctx->so->constlen,
713 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
714 }
715
716 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
717 addr = base_lo;
718
719 if (nir_src_is_const(intr->src[1])) {
720 off += nir_src_as_uint(intr->src[1]);
721 } else {
722 /* For load_ubo_indirect, second src is indirect offset: */
723 src1 = ir3_get_src(ctx, &intr->src[1])[0];
724
725 /* and add offset to addr: */
726 addr = ir3_ADD_S(b, addr, 0, src1, 0);
727 }
728
729 /* if offset is to large to encode in the ldg, split it out: */
730 if ((off + (intr->num_components * 4)) > 1024) {
731 /* split out the minimal amount to improve the odds that
732 * cp can fit the immediate in the add.s instruction:
733 */
734 unsigned off2 = off + (intr->num_components * 4) - 1024;
735 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
736 off -= off2;
737 }
738
739 if (ptrsz == 2) {
740 struct ir3_instruction *carry;
741
742 /* handle 32b rollover, ie:
743 * if (addr < base_lo)
744 * base_hi++
745 */
746 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
747 carry->cat2.condition = IR3_COND_LT;
748 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
749
750 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
751 }
752
753 for (int i = 0; i < intr->num_components; i++) {
754 struct ir3_instruction *load =
755 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
756 create_immed(b, off + i * 4), 0);
757 load->cat6.type = TYPE_U32;
758 dst[i] = load;
759 }
760 }
761
762 /* src[] = { block_index } */
763 static void
764 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
765 struct ir3_instruction **dst)
766 {
767 /* SSBO size stored as a const starting at ssbo_sizes: */
768 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
769 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
770 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
771 const_state->ssbo_size.off[blk_idx];
772
773 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
774
775 dst[0] = create_uniform(ctx->block, idx);
776 }
777
778 /* src[] = { offset }. const_index[] = { base } */
779 static void
780 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
781 struct ir3_instruction **dst)
782 {
783 struct ir3_block *b = ctx->block;
784 struct ir3_instruction *ldl, *offset;
785 unsigned base;
786
787 offset = ir3_get_src(ctx, &intr->src[0])[0];
788 base = nir_intrinsic_base(intr);
789
790 ldl = ir3_LDL(b, offset, 0,
791 create_immed(b, intr->num_components), 0,
792 create_immed(b, base), 0);
793
794 ldl->cat6.type = utype_dst(intr->dest);
795 ldl->regs[0]->wrmask = MASK(intr->num_components);
796
797 ldl->barrier_class = IR3_BARRIER_SHARED_R;
798 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
799
800 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
801 }
802
803 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
804 static void
805 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
806 {
807 struct ir3_block *b = ctx->block;
808 struct ir3_instruction *stl, *offset;
809 struct ir3_instruction * const *value;
810 unsigned base, wrmask;
811
812 value = ir3_get_src(ctx, &intr->src[0]);
813 offset = ir3_get_src(ctx, &intr->src[1])[0];
814
815 base = nir_intrinsic_base(intr);
816 wrmask = nir_intrinsic_write_mask(intr);
817
818 /* Combine groups of consecutive enabled channels in one write
819 * message. We use ffs to find the first enabled channel and then ffs on
820 * the bit-inverse, down-shifted writemask to determine the length of
821 * the block of enabled bits.
822 *
823 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
824 */
825 while (wrmask) {
826 unsigned first_component = ffs(wrmask) - 1;
827 unsigned length = ffs(~(wrmask >> first_component)) - 1;
828
829 stl = ir3_STL(b, offset, 0,
830 ir3_create_collect(ctx, &value[first_component], length), 0,
831 create_immed(b, length), 0);
832 stl->cat6.dst_offset = first_component + base;
833 stl->cat6.type = utype_src(intr->src[0]);
834 stl->barrier_class = IR3_BARRIER_SHARED_W;
835 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
836
837 array_insert(b, b->keeps, stl);
838
839 /* Clear the bits in the writemask that we just wrote, then try
840 * again to see if more channels are left.
841 */
842 wrmask &= (15 << (first_component + length));
843 }
844 }
845
846 /*
847 * CS shared variable atomic intrinsics
848 *
849 * All of the shared variable atomic memory operations read a value from
850 * memory, compute a new value using one of the operations below, write the
851 * new value to memory, and return the original value read.
852 *
853 * All operations take 2 sources except CompSwap that takes 3. These
854 * sources represent:
855 *
856 * 0: The offset into the shared variable storage region that the atomic
857 * operation will operate on.
858 * 1: The data parameter to the atomic function (i.e. the value to add
859 * in shared_atomic_add, etc).
860 * 2: For CompSwap only: the second data parameter.
861 */
862 static struct ir3_instruction *
863 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
864 {
865 struct ir3_block *b = ctx->block;
866 struct ir3_instruction *atomic, *src0, *src1;
867 type_t type = TYPE_U32;
868
869 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
870 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
871
872 switch (intr->intrinsic) {
873 case nir_intrinsic_shared_atomic_add:
874 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
875 break;
876 case nir_intrinsic_shared_atomic_imin:
877 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
878 type = TYPE_S32;
879 break;
880 case nir_intrinsic_shared_atomic_umin:
881 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
882 break;
883 case nir_intrinsic_shared_atomic_imax:
884 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
885 type = TYPE_S32;
886 break;
887 case nir_intrinsic_shared_atomic_umax:
888 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
889 break;
890 case nir_intrinsic_shared_atomic_and:
891 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
892 break;
893 case nir_intrinsic_shared_atomic_or:
894 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
895 break;
896 case nir_intrinsic_shared_atomic_xor:
897 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
898 break;
899 case nir_intrinsic_shared_atomic_exchange:
900 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
901 break;
902 case nir_intrinsic_shared_atomic_comp_swap:
903 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
904 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
905 ir3_get_src(ctx, &intr->src[2])[0],
906 src1,
907 }, 2);
908 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
909 break;
910 default:
911 unreachable("boo");
912 }
913
914 atomic->cat6.iim_val = 1;
915 atomic->cat6.d = 1;
916 atomic->cat6.type = type;
917 atomic->barrier_class = IR3_BARRIER_SHARED_W;
918 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
919
920 /* even if nothing consume the result, we can't DCE the instruction: */
921 array_insert(b, b->keeps, atomic);
922
923 return atomic;
924 }
925
926 /* TODO handle actual indirect/dynamic case.. which is going to be weird
927 * to handle with the image_mapping table..
928 */
929 static struct ir3_instruction *
930 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
931 {
932 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
933 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
934 struct ir3_instruction *texture, *sampler;
935
936 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
937 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
938
939 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
940 sampler,
941 texture,
942 }, 2);
943 }
944
945 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
946 static void
947 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
948 struct ir3_instruction **dst)
949 {
950 struct ir3_block *b = ctx->block;
951 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
952 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
953 struct ir3_instruction *sam;
954 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
955 struct ir3_instruction *coords[4];
956 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
957 type_t type = ir3_get_image_type(var);
958
959 /* hmm, this seems a bit odd, but it is what blob does and (at least
960 * a5xx) just faults on bogus addresses otherwise:
961 */
962 if (flags & IR3_INSTR_3D) {
963 flags &= ~IR3_INSTR_3D;
964 flags |= IR3_INSTR_A;
965 }
966
967 for (unsigned i = 0; i < ncoords; i++)
968 coords[i] = src0[i];
969
970 if (ncoords == 1)
971 coords[ncoords++] = create_immed(b, 0);
972
973 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
974 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
975
976 sam->barrier_class = IR3_BARRIER_IMAGE_R;
977 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
978
979 ir3_split_dest(b, dst, sam, 0, 4);
980 }
981
982 static void
983 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
984 struct ir3_instruction **dst)
985 {
986 struct ir3_block *b = ctx->block;
987 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
988 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
989 struct ir3_instruction *sam, *lod;
990 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
991
992 lod = create_immed(b, 0);
993 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
994 samp_tex, lod, NULL);
995
996 /* Array size actually ends up in .w rather than .z. This doesn't
997 * matter for miplevel 0, but for higher mips the value in z is
998 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
999 * returned, which means that we have to add 1 to it for arrays for
1000 * a3xx.
1001 *
1002 * Note use a temporary dst and then copy, since the size of the dst
1003 * array that is passed in is based on nir's understanding of the
1004 * result size, not the hardware's
1005 */
1006 struct ir3_instruction *tmp[4];
1007
1008 ir3_split_dest(b, tmp, sam, 0, 4);
1009
1010 /* get_size instruction returns size in bytes instead of texels
1011 * for imageBuffer, so we need to divide it by the pixel size
1012 * of the image format.
1013 *
1014 * TODO: This is at least true on a5xx. Check other gens.
1015 */
1016 enum glsl_sampler_dim dim =
1017 glsl_get_sampler_dim(glsl_without_array(var->type));
1018 if (dim == GLSL_SAMPLER_DIM_BUF) {
1019 /* Since all the possible values the divisor can take are
1020 * power-of-two (4, 8, or 16), the division is implemented
1021 * as a shift-right.
1022 * During shader setup, the log2 of the image format's
1023 * bytes-per-pixel should have been emitted in 2nd slot of
1024 * image_dims. See ir3_shader::emit_image_dims().
1025 */
1026 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1027 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1028 const_state->image_dims.off[var->data.driver_location];
1029 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1030
1031 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1032 }
1033
1034 for (unsigned i = 0; i < ncoords; i++)
1035 dst[i] = tmp[i];
1036
1037 if (flags & IR3_INSTR_A) {
1038 if (ctx->compiler->levels_add_one) {
1039 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1040 } else {
1041 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1042 }
1043 }
1044 }
1045
1046 static void
1047 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1048 {
1049 struct ir3_block *b = ctx->block;
1050 struct ir3_instruction *barrier;
1051
1052 switch (intr->intrinsic) {
1053 case nir_intrinsic_barrier:
1054 barrier = ir3_BAR(b);
1055 barrier->cat7.g = true;
1056 barrier->cat7.l = true;
1057 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1058 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1059 break;
1060 case nir_intrinsic_memory_barrier:
1061 barrier = ir3_FENCE(b);
1062 barrier->cat7.g = true;
1063 barrier->cat7.r = true;
1064 barrier->cat7.w = true;
1065 barrier->cat7.l = true;
1066 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1067 IR3_BARRIER_BUFFER_W;
1068 barrier->barrier_conflict =
1069 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1070 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1071 break;
1072 case nir_intrinsic_memory_barrier_atomic_counter:
1073 case nir_intrinsic_memory_barrier_buffer:
1074 barrier = ir3_FENCE(b);
1075 barrier->cat7.g = true;
1076 barrier->cat7.r = true;
1077 barrier->cat7.w = true;
1078 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1079 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1080 IR3_BARRIER_BUFFER_W;
1081 break;
1082 case nir_intrinsic_memory_barrier_image:
1083 // TODO double check if this should have .g set
1084 barrier = ir3_FENCE(b);
1085 barrier->cat7.g = true;
1086 barrier->cat7.r = true;
1087 barrier->cat7.w = true;
1088 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1089 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1090 IR3_BARRIER_IMAGE_W;
1091 break;
1092 case nir_intrinsic_memory_barrier_shared:
1093 barrier = ir3_FENCE(b);
1094 barrier->cat7.g = true;
1095 barrier->cat7.l = true;
1096 barrier->cat7.r = true;
1097 barrier->cat7.w = true;
1098 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1099 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1100 IR3_BARRIER_SHARED_W;
1101 break;
1102 case nir_intrinsic_group_memory_barrier:
1103 barrier = ir3_FENCE(b);
1104 barrier->cat7.g = true;
1105 barrier->cat7.l = true;
1106 barrier->cat7.r = true;
1107 barrier->cat7.w = true;
1108 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1109 IR3_BARRIER_IMAGE_W |
1110 IR3_BARRIER_BUFFER_W;
1111 barrier->barrier_conflict =
1112 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1113 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1114 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1115 break;
1116 default:
1117 unreachable("boo");
1118 }
1119
1120 /* make sure barrier doesn't get DCE'd */
1121 array_insert(b, b->keeps, barrier);
1122 }
1123
1124 static void add_sysval_input_compmask(struct ir3_context *ctx,
1125 gl_system_value slot, unsigned compmask,
1126 struct ir3_instruction *instr)
1127 {
1128 struct ir3_shader_variant *so = ctx->so;
1129 unsigned r = regid(so->inputs_count, 0);
1130 unsigned n = so->inputs_count++;
1131
1132 so->inputs[n].sysval = true;
1133 so->inputs[n].slot = slot;
1134 so->inputs[n].compmask = compmask;
1135 so->inputs[n].regid = r;
1136 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1137 so->total_in++;
1138
1139 ctx->ir->ninputs = MAX2(ctx->ir->ninputs, r + 1);
1140 ctx->ir->inputs[r] = instr;
1141 }
1142
1143 static void add_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1144 struct ir3_instruction *instr)
1145 {
1146 add_sysval_input_compmask(ctx, slot, 0x1, instr);
1147 }
1148
1149 static struct ir3_instruction *
1150 get_barycentric_centroid(struct ir3_context *ctx)
1151 {
1152 if (!ctx->ij_centroid) {
1153 struct ir3_instruction *xy[2];
1154 struct ir3_instruction *ij;
1155
1156 ij = create_input_compmask(ctx, 0, 0x3);
1157 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1158
1159 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1160
1161 add_sysval_input_compmask(ctx,
1162 SYSTEM_VALUE_BARYCENTRIC_CENTROID,
1163 0x3, ij);
1164 }
1165
1166 return ctx->ij_centroid;
1167 }
1168
1169 static struct ir3_instruction *
1170 get_barycentric_sample(struct ir3_context *ctx)
1171 {
1172 if (!ctx->ij_sample) {
1173 struct ir3_instruction *xy[2];
1174 struct ir3_instruction *ij;
1175
1176 ij = create_input_compmask(ctx, 0, 0x3);
1177 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1178
1179 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1180
1181 add_sysval_input_compmask(ctx,
1182 SYSTEM_VALUE_BARYCENTRIC_SAMPLE,
1183 0x3, ij);
1184 }
1185
1186 return ctx->ij_sample;
1187 }
1188
1189 static struct ir3_instruction *
1190 get_barycentric_pixel(struct ir3_context *ctx)
1191 {
1192 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1193 * this to create ij_pixel only on demand:
1194 */
1195 return ctx->ij_pixel;
1196 }
1197
1198 static struct ir3_instruction *
1199 get_frag_coord(struct ir3_context *ctx)
1200 {
1201 if (!ctx->frag_coord) {
1202 struct ir3_block *b = ctx->block;
1203 struct ir3_instruction *xyzw[4];
1204 struct ir3_instruction *hw_frag_coord;
1205
1206 hw_frag_coord = create_input_compmask(ctx, 0, 0xf);
1207 ir3_split_dest(ctx->block, xyzw, hw_frag_coord, 0, 4);
1208
1209 /* for frag_coord.xy, we get unsigned values.. we need
1210 * to subtract (integer) 8 and divide by 16 (right-
1211 * shift by 4) then convert to float:
1212 *
1213 * sub.s tmp, src, 8
1214 * shr.b tmp, tmp, 4
1215 * mov.u32f32 dst, tmp
1216 *
1217 */
1218 for (int i = 0; i < 2; i++) {
1219 xyzw[i] = ir3_SUB_S(b, xyzw[i], 0,
1220 create_immed(b, 8), 0);
1221 xyzw[i] = ir3_SHR_B(b, xyzw[i], 0,
1222 create_immed(b, 4), 0);
1223 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1224 }
1225
1226 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1227
1228 add_sysval_input_compmask(ctx,
1229 SYSTEM_VALUE_FRAG_COORD,
1230 0xf, hw_frag_coord);
1231
1232 ctx->so->frag_coord = true;
1233 }
1234
1235 return ctx->frag_coord;
1236 }
1237
1238 static void
1239 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1240 {
1241 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1242 struct ir3_instruction **dst;
1243 struct ir3_instruction * const *src;
1244 struct ir3_block *b = ctx->block;
1245 int idx, comp;
1246
1247 if (info->has_dest) {
1248 unsigned n = nir_intrinsic_dest_components(intr);
1249 dst = ir3_get_dst(ctx, &intr->dest, n);
1250 } else {
1251 dst = NULL;
1252 }
1253
1254 switch (intr->intrinsic) {
1255 case nir_intrinsic_load_uniform:
1256 idx = nir_intrinsic_base(intr);
1257 if (nir_src_is_const(intr->src[0])) {
1258 idx += nir_src_as_uint(intr->src[0]);
1259 for (int i = 0; i < intr->num_components; i++) {
1260 dst[i] = create_uniform_typed(b, idx + i,
1261 nir_dest_bit_size(intr->dest) < 32 ? TYPE_F16 : TYPE_F32);
1262 }
1263 } else {
1264 src = ir3_get_src(ctx, &intr->src[0]);
1265 for (int i = 0; i < intr->num_components; i++) {
1266 dst[i] = create_uniform_indirect(b, idx + i,
1267 ir3_get_addr(ctx, src[0], 1));
1268 }
1269 /* NOTE: if relative addressing is used, we set
1270 * constlen in the compiler (to worst-case value)
1271 * since we don't know in the assembler what the max
1272 * addr reg value can be:
1273 */
1274 ctx->so->constlen = MAX2(ctx->so->constlen,
1275 ctx->so->shader->ubo_state.size / 16);
1276 }
1277 break;
1278 case nir_intrinsic_load_ubo:
1279 emit_intrinsic_load_ubo(ctx, intr, dst);
1280 break;
1281 case nir_intrinsic_load_frag_coord:
1282 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1283 break;
1284 case nir_intrinsic_load_sample_pos_from_id: {
1285 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1286 * but that doesn't seem necessary.
1287 */
1288 struct ir3_instruction *offset =
1289 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1290 offset->regs[0]->wrmask = 0x3;
1291 offset->cat5.type = TYPE_F32;
1292
1293 ir3_split_dest(b, dst, offset, 0, 2);
1294
1295 break;
1296 }
1297 case nir_intrinsic_load_size_ir3:
1298 if (!ctx->ij_size) {
1299 ctx->ij_size = create_input(ctx, 0);
1300
1301 add_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SIZE,
1302 ctx->ij_size);
1303 }
1304 dst[0] = ctx->ij_size;
1305 break;
1306 case nir_intrinsic_load_barycentric_centroid:
1307 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1308 break;
1309 case nir_intrinsic_load_barycentric_sample:
1310 if (ctx->so->key.msaa) {
1311 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1312 } else {
1313 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1314 }
1315 break;
1316 case nir_intrinsic_load_barycentric_pixel:
1317 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1318 break;
1319 case nir_intrinsic_load_interpolated_input:
1320 idx = nir_intrinsic_base(intr);
1321 comp = nir_intrinsic_component(intr);
1322 src = ir3_get_src(ctx, &intr->src[0]);
1323 if (nir_src_is_const(intr->src[1])) {
1324 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1325 idx += nir_src_as_uint(intr->src[1]);
1326 for (int i = 0; i < intr->num_components; i++) {
1327 unsigned inloc = idx * 4 + i + comp;
1328 if (ctx->so->inputs[idx].bary &&
1329 !ctx->so->inputs[idx].use_ldlv) {
1330 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1331 } else {
1332 /* for non-varyings use the pre-setup input, since
1333 * that is easier than mapping things back to a
1334 * nir_variable to figure out what it is.
1335 */
1336 dst[i] = ctx->ir->inputs[inloc];
1337 }
1338 }
1339 } else {
1340 ir3_context_error(ctx, "unhandled");
1341 }
1342 break;
1343 case nir_intrinsic_load_input:
1344 idx = nir_intrinsic_base(intr);
1345 comp = nir_intrinsic_component(intr);
1346 if (nir_src_is_const(intr->src[0])) {
1347 idx += nir_src_as_uint(intr->src[0]);
1348 for (int i = 0; i < intr->num_components; i++) {
1349 unsigned n = idx * 4 + i + comp;
1350 dst[i] = ctx->ir->inputs[n];
1351 compile_assert(ctx, ctx->ir->inputs[n]);
1352 }
1353 } else {
1354 src = ir3_get_src(ctx, &intr->src[0]);
1355 struct ir3_instruction *collect =
1356 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ir->ninputs);
1357 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1358 for (int i = 0; i < intr->num_components; i++) {
1359 unsigned n = idx * 4 + i + comp;
1360 dst[i] = create_indirect_load(ctx, ctx->ir->ninputs,
1361 n, addr, collect);
1362 }
1363 }
1364 break;
1365 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1366 * pass and replaced by an ir3-specifc version that adds the
1367 * dword-offset in the last source.
1368 */
1369 case nir_intrinsic_load_ssbo_ir3:
1370 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1371 break;
1372 case nir_intrinsic_store_ssbo_ir3:
1373 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1374 !ctx->s->info.fs.early_fragment_tests)
1375 ctx->so->no_earlyz = true;
1376 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1377 break;
1378 case nir_intrinsic_get_buffer_size:
1379 emit_intrinsic_ssbo_size(ctx, intr, dst);
1380 break;
1381 case nir_intrinsic_ssbo_atomic_add_ir3:
1382 case nir_intrinsic_ssbo_atomic_imin_ir3:
1383 case nir_intrinsic_ssbo_atomic_umin_ir3:
1384 case nir_intrinsic_ssbo_atomic_imax_ir3:
1385 case nir_intrinsic_ssbo_atomic_umax_ir3:
1386 case nir_intrinsic_ssbo_atomic_and_ir3:
1387 case nir_intrinsic_ssbo_atomic_or_ir3:
1388 case nir_intrinsic_ssbo_atomic_xor_ir3:
1389 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1390 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1391 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1392 !ctx->s->info.fs.early_fragment_tests)
1393 ctx->so->no_earlyz = true;
1394 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1395 break;
1396 case nir_intrinsic_load_shared:
1397 emit_intrinsic_load_shared(ctx, intr, dst);
1398 break;
1399 case nir_intrinsic_store_shared:
1400 emit_intrinsic_store_shared(ctx, intr);
1401 break;
1402 case nir_intrinsic_shared_atomic_add:
1403 case nir_intrinsic_shared_atomic_imin:
1404 case nir_intrinsic_shared_atomic_umin:
1405 case nir_intrinsic_shared_atomic_imax:
1406 case nir_intrinsic_shared_atomic_umax:
1407 case nir_intrinsic_shared_atomic_and:
1408 case nir_intrinsic_shared_atomic_or:
1409 case nir_intrinsic_shared_atomic_xor:
1410 case nir_intrinsic_shared_atomic_exchange:
1411 case nir_intrinsic_shared_atomic_comp_swap:
1412 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1413 break;
1414 case nir_intrinsic_image_deref_load:
1415 emit_intrinsic_load_image(ctx, intr, dst);
1416 break;
1417 case nir_intrinsic_image_deref_store:
1418 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1419 !ctx->s->info.fs.early_fragment_tests)
1420 ctx->so->no_earlyz = true;
1421 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1422 break;
1423 case nir_intrinsic_image_deref_size:
1424 emit_intrinsic_image_size(ctx, intr, dst);
1425 break;
1426 case nir_intrinsic_image_deref_atomic_add:
1427 case nir_intrinsic_image_deref_atomic_imin:
1428 case nir_intrinsic_image_deref_atomic_umin:
1429 case nir_intrinsic_image_deref_atomic_imax:
1430 case nir_intrinsic_image_deref_atomic_umax:
1431 case nir_intrinsic_image_deref_atomic_and:
1432 case nir_intrinsic_image_deref_atomic_or:
1433 case nir_intrinsic_image_deref_atomic_xor:
1434 case nir_intrinsic_image_deref_atomic_exchange:
1435 case nir_intrinsic_image_deref_atomic_comp_swap:
1436 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1437 !ctx->s->info.fs.early_fragment_tests)
1438 ctx->so->no_earlyz = true;
1439 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1440 break;
1441 case nir_intrinsic_barrier:
1442 case nir_intrinsic_memory_barrier:
1443 case nir_intrinsic_group_memory_barrier:
1444 case nir_intrinsic_memory_barrier_atomic_counter:
1445 case nir_intrinsic_memory_barrier_buffer:
1446 case nir_intrinsic_memory_barrier_image:
1447 case nir_intrinsic_memory_barrier_shared:
1448 emit_intrinsic_barrier(ctx, intr);
1449 /* note that blk ptr no longer valid, make that obvious: */
1450 b = NULL;
1451 break;
1452 case nir_intrinsic_store_output:
1453 idx = nir_intrinsic_base(intr);
1454 comp = nir_intrinsic_component(intr);
1455 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1456 idx += nir_src_as_uint(intr->src[1]);
1457
1458 src = ir3_get_src(ctx, &intr->src[0]);
1459 for (int i = 0; i < intr->num_components; i++) {
1460 unsigned n = idx * 4 + i + comp;
1461 ctx->ir->outputs[n] = src[i];
1462 }
1463 break;
1464 case nir_intrinsic_load_base_vertex:
1465 case nir_intrinsic_load_first_vertex:
1466 if (!ctx->basevertex) {
1467 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1468 add_sysval_input(ctx, SYSTEM_VALUE_FIRST_VERTEX, ctx->basevertex);
1469 }
1470 dst[0] = ctx->basevertex;
1471 break;
1472 case nir_intrinsic_load_vertex_id_zero_base:
1473 case nir_intrinsic_load_vertex_id:
1474 if (!ctx->vertex_id) {
1475 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1476 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1477 ctx->vertex_id = create_input(ctx, 0);
1478 add_sysval_input(ctx, sv, ctx->vertex_id);
1479 }
1480 dst[0] = ctx->vertex_id;
1481 break;
1482 case nir_intrinsic_load_instance_id:
1483 if (!ctx->instance_id) {
1484 ctx->instance_id = create_input(ctx, 0);
1485 add_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID,
1486 ctx->instance_id);
1487 }
1488 dst[0] = ctx->instance_id;
1489 break;
1490 case nir_intrinsic_load_sample_id:
1491 ctx->so->per_samp = true;
1492 /* fall-thru */
1493 case nir_intrinsic_load_sample_id_no_per_sample:
1494 if (!ctx->samp_id) {
1495 ctx->samp_id = create_input(ctx, 0);
1496 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1497 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID,
1498 ctx->samp_id);
1499 }
1500 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1501 break;
1502 case nir_intrinsic_load_sample_mask_in:
1503 if (!ctx->samp_mask_in) {
1504 ctx->samp_mask_in = create_input(ctx, 0);
1505 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN,
1506 ctx->samp_mask_in);
1507 }
1508 dst[0] = ctx->samp_mask_in;
1509 break;
1510 case nir_intrinsic_load_user_clip_plane:
1511 idx = nir_intrinsic_ucp_id(intr);
1512 for (int i = 0; i < intr->num_components; i++) {
1513 unsigned n = idx * 4 + i;
1514 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1515 }
1516 break;
1517 case nir_intrinsic_load_front_face:
1518 if (!ctx->frag_face) {
1519 ctx->so->frag_face = true;
1520 ctx->frag_face = create_input(ctx, 0);
1521 add_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, ctx->frag_face);
1522 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1523 }
1524 /* for fragface, we get -1 for back and 0 for front. However this is
1525 * the inverse of what nir expects (where ~0 is true).
1526 */
1527 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1528 dst[0] = ir3_NOT_B(b, dst[0], 0);
1529 break;
1530 case nir_intrinsic_load_local_invocation_id:
1531 if (!ctx->local_invocation_id) {
1532 ctx->local_invocation_id = create_input_compmask(ctx, 0, 0x7);
1533 add_sysval_input_compmask(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID,
1534 0x7, ctx->local_invocation_id);
1535 }
1536 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1537 break;
1538 case nir_intrinsic_load_work_group_id:
1539 if (!ctx->work_group_id) {
1540 ctx->work_group_id = create_input_compmask(ctx, 0, 0x7);
1541 add_sysval_input_compmask(ctx, SYSTEM_VALUE_WORK_GROUP_ID,
1542 0x7, ctx->work_group_id);
1543 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1544 }
1545 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1546 break;
1547 case nir_intrinsic_load_num_work_groups:
1548 for (int i = 0; i < intr->num_components; i++) {
1549 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1550 }
1551 break;
1552 case nir_intrinsic_load_local_group_size:
1553 for (int i = 0; i < intr->num_components; i++) {
1554 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1555 }
1556 break;
1557 case nir_intrinsic_discard_if:
1558 case nir_intrinsic_discard: {
1559 struct ir3_instruction *cond, *kill;
1560
1561 if (intr->intrinsic == nir_intrinsic_discard_if) {
1562 /* conditional discard: */
1563 src = ir3_get_src(ctx, &intr->src[0]);
1564 cond = ir3_b2n(b, src[0]);
1565 } else {
1566 /* unconditional discard: */
1567 cond = create_immed(b, 1);
1568 }
1569
1570 /* NOTE: only cmps.*.* can write p0.x: */
1571 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1572 cond->cat2.condition = IR3_COND_NE;
1573
1574 /* condition always goes in predicate register: */
1575 cond->regs[0]->num = regid(REG_P0, 0);
1576
1577 kill = ir3_KILL(b, cond, 0);
1578 array_insert(ctx->ir, ctx->ir->predicates, kill);
1579
1580 array_insert(b, b->keeps, kill);
1581 ctx->so->no_earlyz = true;
1582
1583 break;
1584 }
1585 default:
1586 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1587 nir_intrinsic_infos[intr->intrinsic].name);
1588 break;
1589 }
1590
1591 if (info->has_dest)
1592 ir3_put_dst(ctx, &intr->dest);
1593 }
1594
1595 static void
1596 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1597 {
1598 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1599 instr->def.num_components);
1600
1601 if (instr->def.bit_size < 32) {
1602 for (int i = 0; i < instr->def.num_components; i++)
1603 dst[i] = create_immed_typed(ctx->block,
1604 instr->value[i].u16,
1605 TYPE_U16);
1606 } else {
1607 for (int i = 0; i < instr->def.num_components; i++)
1608 dst[i] = create_immed_typed(ctx->block,
1609 instr->value[i].u32,
1610 TYPE_U32);
1611 }
1612
1613 }
1614
1615 static void
1616 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1617 {
1618 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1619 undef->def.num_components);
1620 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1621
1622 /* backend doesn't want undefined instructions, so just plug
1623 * in 0.0..
1624 */
1625 for (int i = 0; i < undef->def.num_components; i++)
1626 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1627 }
1628
1629 /*
1630 * texture fetch/sample instructions:
1631 */
1632
1633 static void
1634 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1635 {
1636 unsigned coords, flags = 0;
1637
1638 /* note: would use tex->coord_components.. except txs.. also,
1639 * since array index goes after shadow ref, we don't want to
1640 * count it:
1641 */
1642 switch (tex->sampler_dim) {
1643 case GLSL_SAMPLER_DIM_1D:
1644 case GLSL_SAMPLER_DIM_BUF:
1645 coords = 1;
1646 break;
1647 case GLSL_SAMPLER_DIM_2D:
1648 case GLSL_SAMPLER_DIM_RECT:
1649 case GLSL_SAMPLER_DIM_EXTERNAL:
1650 case GLSL_SAMPLER_DIM_MS:
1651 coords = 2;
1652 break;
1653 case GLSL_SAMPLER_DIM_3D:
1654 case GLSL_SAMPLER_DIM_CUBE:
1655 coords = 3;
1656 flags |= IR3_INSTR_3D;
1657 break;
1658 default:
1659 unreachable("bad sampler_dim");
1660 }
1661
1662 if (tex->is_shadow && tex->op != nir_texop_lod)
1663 flags |= IR3_INSTR_S;
1664
1665 if (tex->is_array && tex->op != nir_texop_lod)
1666 flags |= IR3_INSTR_A;
1667
1668 *flagsp = flags;
1669 *coordsp = coords;
1670 }
1671
1672 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1673 * or immediate (in which case it will get lowered later to a non .s2en
1674 * version of the tex instruction which encode tex/samp as immediates:
1675 */
1676 static struct ir3_instruction *
1677 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1678 {
1679 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1680 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1681 struct ir3_instruction *texture, *sampler;
1682
1683 if (texture_idx >= 0) {
1684 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1685 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1686 } else {
1687 /* TODO what to do for dynamic case? I guess we only need the
1688 * max index for astc srgb workaround so maybe not a problem
1689 * to worry about if we don't enable indirect samplers for
1690 * a4xx?
1691 */
1692 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1693 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1694 }
1695
1696 if (sampler_idx >= 0) {
1697 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1698 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1699 } else {
1700 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1701 }
1702
1703 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1704 sampler,
1705 texture,
1706 }, 2);
1707 }
1708
1709 static void
1710 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1711 {
1712 struct ir3_block *b = ctx->block;
1713 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1714 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1715 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1716 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1717 unsigned i, coords, flags, ncomp;
1718 unsigned nsrc0 = 0, nsrc1 = 0;
1719 type_t type;
1720 opc_t opc = 0;
1721
1722 ncomp = nir_dest_num_components(tex->dest);
1723
1724 coord = off = ddx = ddy = NULL;
1725 lod = proj = compare = sample_index = NULL;
1726
1727 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1728
1729 for (unsigned i = 0; i < tex->num_srcs; i++) {
1730 switch (tex->src[i].src_type) {
1731 case nir_tex_src_coord:
1732 coord = ir3_get_src(ctx, &tex->src[i].src);
1733 break;
1734 case nir_tex_src_bias:
1735 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1736 has_bias = true;
1737 break;
1738 case nir_tex_src_lod:
1739 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1740 has_lod = true;
1741 break;
1742 case nir_tex_src_comparator: /* shadow comparator */
1743 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1744 break;
1745 case nir_tex_src_projector:
1746 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1747 has_proj = true;
1748 break;
1749 case nir_tex_src_offset:
1750 off = ir3_get_src(ctx, &tex->src[i].src);
1751 has_off = true;
1752 break;
1753 case nir_tex_src_ddx:
1754 ddx = ir3_get_src(ctx, &tex->src[i].src);
1755 break;
1756 case nir_tex_src_ddy:
1757 ddy = ir3_get_src(ctx, &tex->src[i].src);
1758 break;
1759 case nir_tex_src_ms_index:
1760 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
1761 break;
1762 case nir_tex_src_texture_offset:
1763 case nir_tex_src_sampler_offset:
1764 /* handled in get_tex_samp_src() */
1765 break;
1766 default:
1767 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
1768 tex->src[i].src_type);
1769 return;
1770 }
1771 }
1772
1773 switch (tex->op) {
1774 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
1775 case nir_texop_txb: opc = OPC_SAMB; break;
1776 case nir_texop_txl: opc = OPC_SAML; break;
1777 case nir_texop_txd: opc = OPC_SAMGQ; break;
1778 case nir_texop_txf: opc = OPC_ISAML; break;
1779 case nir_texop_lod: opc = OPC_GETLOD; break;
1780 case nir_texop_tg4:
1781 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1782 * what blob does, seems gather is broken?), and a3xx did
1783 * not support it (but probably could also emulate).
1784 */
1785 switch (tex->component) {
1786 case 0: opc = OPC_GATHER4R; break;
1787 case 1: opc = OPC_GATHER4G; break;
1788 case 2: opc = OPC_GATHER4B; break;
1789 case 3: opc = OPC_GATHER4A; break;
1790 }
1791 break;
1792 case nir_texop_txf_ms_fb:
1793 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
1794 default:
1795 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
1796 return;
1797 }
1798
1799 tex_info(tex, &flags, &coords);
1800
1801 /*
1802 * lay out the first argument in the proper order:
1803 * - actual coordinates first
1804 * - shadow reference
1805 * - array index
1806 * - projection w
1807 * - starting at offset 4, dpdx.xy, dpdy.xy
1808 *
1809 * bias/lod go into the second arg
1810 */
1811
1812 /* insert tex coords: */
1813 for (i = 0; i < coords; i++)
1814 src0[i] = coord[i];
1815
1816 nsrc0 = i;
1817
1818 /* scale up integer coords for TXF based on the LOD */
1819 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
1820 assert(has_lod);
1821 for (i = 0; i < coords; i++)
1822 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
1823 }
1824
1825 if (coords == 1) {
1826 /* hw doesn't do 1d, so we treat it as 2d with
1827 * height of 1, and patch up the y coord.
1828 */
1829 if (is_isam(opc)) {
1830 src0[nsrc0++] = create_immed(b, 0);
1831 } else {
1832 src0[nsrc0++] = create_immed(b, fui(0.5));
1833 }
1834 }
1835
1836 if (tex->is_shadow && tex->op != nir_texop_lod)
1837 src0[nsrc0++] = compare;
1838
1839 if (tex->is_array && tex->op != nir_texop_lod) {
1840 struct ir3_instruction *idx = coord[coords];
1841
1842 /* the array coord for cube arrays needs 0.5 added to it */
1843 if (ctx->compiler->array_index_add_half && !is_isam(opc))
1844 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
1845
1846 src0[nsrc0++] = idx;
1847 }
1848
1849 if (has_proj) {
1850 src0[nsrc0++] = proj;
1851 flags |= IR3_INSTR_P;
1852 }
1853
1854 /* pad to 4, then ddx/ddy: */
1855 if (tex->op == nir_texop_txd) {
1856 while (nsrc0 < 4)
1857 src0[nsrc0++] = create_immed(b, fui(0.0));
1858 for (i = 0; i < coords; i++)
1859 src0[nsrc0++] = ddx[i];
1860 if (coords < 2)
1861 src0[nsrc0++] = create_immed(b, fui(0.0));
1862 for (i = 0; i < coords; i++)
1863 src0[nsrc0++] = ddy[i];
1864 if (coords < 2)
1865 src0[nsrc0++] = create_immed(b, fui(0.0));
1866 }
1867
1868 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
1869 * with scaled x coord according to requested sample:
1870 */
1871 if (opc == OPC_ISAMM) {
1872 if (ctx->compiler->txf_ms_with_isaml) {
1873 /* the samples are laid out in x dimension as
1874 * 0 1 2 3
1875 * x_ms = (x << ms) + sample_index;
1876 */
1877 struct ir3_instruction *ms;
1878 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
1879
1880 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
1881 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
1882
1883 opc = OPC_ISAML;
1884 } else {
1885 src0[nsrc0++] = sample_index;
1886 }
1887 }
1888
1889 /*
1890 * second argument (if applicable):
1891 * - offsets
1892 * - lod
1893 * - bias
1894 */
1895 if (has_off | has_lod | has_bias) {
1896 if (has_off) {
1897 unsigned off_coords = coords;
1898 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
1899 off_coords--;
1900 for (i = 0; i < off_coords; i++)
1901 src1[nsrc1++] = off[i];
1902 if (off_coords < 2)
1903 src1[nsrc1++] = create_immed(b, fui(0.0));
1904 flags |= IR3_INSTR_O;
1905 }
1906
1907 if (has_lod | has_bias)
1908 src1[nsrc1++] = lod;
1909 }
1910
1911 switch (tex->dest_type) {
1912 case nir_type_invalid:
1913 case nir_type_float:
1914 type = TYPE_F32;
1915 break;
1916 case nir_type_int:
1917 type = TYPE_S32;
1918 break;
1919 case nir_type_uint:
1920 case nir_type_bool:
1921 type = TYPE_U32;
1922 break;
1923 default:
1924 unreachable("bad dest_type");
1925 }
1926
1927 if (opc == OPC_GETLOD)
1928 type = TYPE_S32;
1929
1930 struct ir3_instruction *samp_tex;
1931
1932 if (tex->op == nir_texop_txf_ms_fb) {
1933 /* only expect a single txf_ms_fb per shader: */
1934 compile_assert(ctx, !ctx->so->fb_read);
1935 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
1936
1937 ctx->so->fb_read = true;
1938 samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1939 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
1940 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
1941 }, 2);
1942
1943 ctx->so->num_samp++;
1944 } else {
1945 samp_tex = get_tex_samp_tex_src(ctx, tex);
1946 }
1947
1948 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
1949 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
1950
1951 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
1952 samp_tex, col0, col1);
1953
1954 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
1955 /* only need first 3 components: */
1956 sam->regs[0]->wrmask = 0x7;
1957 ir3_split_dest(b, dst, sam, 0, 3);
1958
1959 /* we need to sample the alpha separately with a non-ASTC
1960 * texture state:
1961 */
1962 sam = ir3_SAM(b, opc, type, 0b1000, flags,
1963 samp_tex, col0, col1);
1964
1965 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
1966
1967 /* fixup .w component: */
1968 ir3_split_dest(b, &dst[3], sam, 3, 1);
1969 } else {
1970 /* normal (non-workaround) case: */
1971 ir3_split_dest(b, dst, sam, 0, ncomp);
1972 }
1973
1974 /* GETLOD returns results in 4.8 fixed point */
1975 if (opc == OPC_GETLOD) {
1976 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
1977
1978 compile_assert(ctx, tex->dest_type == nir_type_float);
1979 for (i = 0; i < 2; i++) {
1980 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
1981 factor, 0);
1982 }
1983 }
1984
1985 ir3_put_dst(ctx, &tex->dest);
1986 }
1987
1988 static void
1989 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
1990 {
1991 struct ir3_block *b = ctx->block;
1992 struct ir3_instruction **dst, *sam;
1993
1994 dst = ir3_get_dst(ctx, &tex->dest, 1);
1995
1996 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, 1 << idx, 0,
1997 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
1998
1999 /* even though there is only one component, since it ends
2000 * up in .y/.z/.w rather than .x, we need a split_dest()
2001 */
2002 if (idx)
2003 ir3_split_dest(b, dst, sam, 0, idx + 1);
2004
2005 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2006 * the value in TEX_CONST_0 is zero-based.
2007 */
2008 if (ctx->compiler->levels_add_one)
2009 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2010
2011 ir3_put_dst(ctx, &tex->dest);
2012 }
2013
2014 static void
2015 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2016 {
2017 struct ir3_block *b = ctx->block;
2018 struct ir3_instruction **dst, *sam;
2019 struct ir3_instruction *lod;
2020 unsigned flags, coords;
2021
2022 tex_info(tex, &flags, &coords);
2023
2024 /* Actually we want the number of dimensions, not coordinates. This
2025 * distinction only matters for cubes.
2026 */
2027 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2028 coords = 2;
2029
2030 dst = ir3_get_dst(ctx, &tex->dest, 4);
2031
2032 compile_assert(ctx, tex->num_srcs == 1);
2033 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2034
2035 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2036
2037 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
2038 get_tex_samp_tex_src(ctx, tex), lod, NULL);
2039
2040 ir3_split_dest(b, dst, sam, 0, 4);
2041
2042 /* Array size actually ends up in .w rather than .z. This doesn't
2043 * matter for miplevel 0, but for higher mips the value in z is
2044 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2045 * returned, which means that we have to add 1 to it for arrays.
2046 */
2047 if (tex->is_array) {
2048 if (ctx->compiler->levels_add_one) {
2049 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2050 } else {
2051 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2052 }
2053 }
2054
2055 ir3_put_dst(ctx, &tex->dest);
2056 }
2057
2058 static void
2059 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2060 {
2061 switch (jump->type) {
2062 case nir_jump_break:
2063 case nir_jump_continue:
2064 case nir_jump_return:
2065 /* I *think* we can simply just ignore this, and use the
2066 * successor block link to figure out where we need to
2067 * jump to for break/continue
2068 */
2069 break;
2070 default:
2071 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2072 break;
2073 }
2074 }
2075
2076 static void
2077 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2078 {
2079 switch (instr->type) {
2080 case nir_instr_type_alu:
2081 emit_alu(ctx, nir_instr_as_alu(instr));
2082 break;
2083 case nir_instr_type_deref:
2084 /* ignored, handled as part of the intrinsic they are src to */
2085 break;
2086 case nir_instr_type_intrinsic:
2087 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2088 break;
2089 case nir_instr_type_load_const:
2090 emit_load_const(ctx, nir_instr_as_load_const(instr));
2091 break;
2092 case nir_instr_type_ssa_undef:
2093 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2094 break;
2095 case nir_instr_type_tex: {
2096 nir_tex_instr *tex = nir_instr_as_tex(instr);
2097 /* couple tex instructions get special-cased:
2098 */
2099 switch (tex->op) {
2100 case nir_texop_txs:
2101 emit_tex_txs(ctx, tex);
2102 break;
2103 case nir_texop_query_levels:
2104 emit_tex_info(ctx, tex, 2);
2105 break;
2106 case nir_texop_texture_samples:
2107 emit_tex_info(ctx, tex, 3);
2108 break;
2109 default:
2110 emit_tex(ctx, tex);
2111 break;
2112 }
2113 break;
2114 }
2115 case nir_instr_type_jump:
2116 emit_jump(ctx, nir_instr_as_jump(instr));
2117 break;
2118 case nir_instr_type_phi:
2119 /* we have converted phi webs to regs in NIR by now */
2120 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2121 break;
2122 case nir_instr_type_call:
2123 case nir_instr_type_parallel_copy:
2124 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2125 break;
2126 }
2127 }
2128
2129 static struct ir3_block *
2130 get_block(struct ir3_context *ctx, const nir_block *nblock)
2131 {
2132 struct ir3_block *block;
2133 struct hash_entry *hentry;
2134
2135 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2136 if (hentry)
2137 return hentry->data;
2138
2139 block = ir3_block_create(ctx->ir);
2140 block->nblock = nblock;
2141 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2142
2143 block->predecessors = _mesa_pointer_set_create(block);
2144 set_foreach(nblock->predecessors, sentry) {
2145 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2146 }
2147
2148 return block;
2149 }
2150
2151 static void
2152 emit_block(struct ir3_context *ctx, nir_block *nblock)
2153 {
2154 struct ir3_block *block = get_block(ctx, nblock);
2155
2156 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2157 if (nblock->successors[i]) {
2158 block->successors[i] =
2159 get_block(ctx, nblock->successors[i]);
2160 }
2161 }
2162
2163 ctx->block = block;
2164 list_addtail(&block->node, &ctx->ir->block_list);
2165
2166 /* re-emit addr register in each block if needed: */
2167 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2168 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2169 ctx->addr_ht[i] = NULL;
2170 }
2171
2172 nir_foreach_instr(instr, nblock) {
2173 ctx->cur_instr = instr;
2174 emit_instr(ctx, instr);
2175 ctx->cur_instr = NULL;
2176 if (ctx->error)
2177 return;
2178 }
2179 }
2180
2181 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2182
2183 static void
2184 emit_if(struct ir3_context *ctx, nir_if *nif)
2185 {
2186 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2187
2188 ctx->block->condition =
2189 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2190
2191 emit_cf_list(ctx, &nif->then_list);
2192 emit_cf_list(ctx, &nif->else_list);
2193 }
2194
2195 static void
2196 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2197 {
2198 emit_cf_list(ctx, &nloop->body);
2199 ctx->so->loops++;
2200 }
2201
2202 static void
2203 stack_push(struct ir3_context *ctx)
2204 {
2205 ctx->stack++;
2206 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2207 }
2208
2209 static void
2210 stack_pop(struct ir3_context *ctx)
2211 {
2212 compile_assert(ctx, ctx->stack > 0);
2213 ctx->stack--;
2214 }
2215
2216 static void
2217 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2218 {
2219 foreach_list_typed(nir_cf_node, node, node, list) {
2220 switch (node->type) {
2221 case nir_cf_node_block:
2222 emit_block(ctx, nir_cf_node_as_block(node));
2223 break;
2224 case nir_cf_node_if:
2225 stack_push(ctx);
2226 emit_if(ctx, nir_cf_node_as_if(node));
2227 stack_pop(ctx);
2228 break;
2229 case nir_cf_node_loop:
2230 stack_push(ctx);
2231 emit_loop(ctx, nir_cf_node_as_loop(node));
2232 stack_pop(ctx);
2233 break;
2234 case nir_cf_node_function:
2235 ir3_context_error(ctx, "TODO\n");
2236 break;
2237 }
2238 }
2239 }
2240
2241 /* emit stream-out code. At this point, the current block is the original
2242 * (nir) end block, and nir ensures that all flow control paths terminate
2243 * into the end block. We re-purpose the original end block to generate
2244 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2245 * block holding stream-out write instructions, followed by the new end
2246 * block:
2247 *
2248 * blockOrigEnd {
2249 * p0.x = (vtxcnt < maxvtxcnt)
2250 * // succs: blockStreamOut, blockNewEnd
2251 * }
2252 * blockStreamOut {
2253 * ... stream-out instructions ...
2254 * // succs: blockNewEnd
2255 * }
2256 * blockNewEnd {
2257 * }
2258 */
2259 static void
2260 emit_stream_out(struct ir3_context *ctx)
2261 {
2262 struct ir3 *ir = ctx->ir;
2263 struct ir3_stream_output_info *strmout =
2264 &ctx->so->shader->stream_output;
2265 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2266 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2267 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2268
2269 /* create vtxcnt input in input block at top of shader,
2270 * so that it is seen as live over the entire duration
2271 * of the shader:
2272 */
2273 vtxcnt = create_input(ctx, 0);
2274 add_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, vtxcnt);
2275
2276 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2277
2278 /* at this point, we are at the original 'end' block,
2279 * re-purpose this block to stream-out condition, then
2280 * append stream-out block and new-end block
2281 */
2282 orig_end_block = ctx->block;
2283
2284 // TODO these blocks need to update predecessors..
2285 // maybe w/ store_global intrinsic, we could do this
2286 // stuff in nir->nir pass
2287
2288 stream_out_block = ir3_block_create(ir);
2289 list_addtail(&stream_out_block->node, &ir->block_list);
2290
2291 new_end_block = ir3_block_create(ir);
2292 list_addtail(&new_end_block->node, &ir->block_list);
2293
2294 orig_end_block->successors[0] = stream_out_block;
2295 orig_end_block->successors[1] = new_end_block;
2296 stream_out_block->successors[0] = new_end_block;
2297
2298 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2299 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2300 cond->regs[0]->num = regid(REG_P0, 0);
2301 cond->cat2.condition = IR3_COND_LT;
2302
2303 /* condition goes on previous block to the conditional,
2304 * since it is used to pick which of the two successor
2305 * paths to take:
2306 */
2307 orig_end_block->condition = cond;
2308
2309 /* switch to stream_out_block to generate the stream-out
2310 * instructions:
2311 */
2312 ctx->block = stream_out_block;
2313
2314 /* Calculate base addresses based on vtxcnt. Instructions
2315 * generated for bases not used in following loop will be
2316 * stripped out in the backend.
2317 */
2318 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2319 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2320 unsigned stride = strmout->stride[i];
2321 struct ir3_instruction *base, *off;
2322
2323 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2324
2325 /* 24-bit should be enough: */
2326 off = ir3_MUL_U(ctx->block, vtxcnt, 0,
2327 create_immed(ctx->block, stride * 4), 0);
2328
2329 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2330 }
2331
2332 /* Generate the per-output store instructions: */
2333 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2334 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2335 unsigned c = j + strmout->output[i].start_component;
2336 struct ir3_instruction *base, *out, *stg;
2337
2338 base = bases[strmout->output[i].output_buffer];
2339 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2340
2341 stg = ir3_STG(ctx->block, base, 0, out, 0,
2342 create_immed(ctx->block, 1), 0);
2343 stg->cat6.type = TYPE_U32;
2344 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2345
2346 array_insert(ctx->block, ctx->block->keeps, stg);
2347 }
2348 }
2349
2350 /* and finally switch to the new_end_block: */
2351 ctx->block = new_end_block;
2352 }
2353
2354 static void
2355 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2356 {
2357 nir_metadata_require(impl, nir_metadata_block_index);
2358
2359 compile_assert(ctx, ctx->stack == 0);
2360
2361 emit_cf_list(ctx, &impl->body);
2362 emit_block(ctx, impl->end_block);
2363
2364 compile_assert(ctx, ctx->stack == 0);
2365
2366 /* at this point, we should have a single empty block,
2367 * into which we emit the 'end' instruction.
2368 */
2369 compile_assert(ctx, list_empty(&ctx->block->instr_list));
2370
2371 /* If stream-out (aka transform-feedback) enabled, emit the
2372 * stream-out instructions, followed by a new empty block (into
2373 * which the 'end' instruction lands).
2374 *
2375 * NOTE: it is done in this order, rather than inserting before
2376 * we emit end_block, because NIR guarantees that all blocks
2377 * flow into end_block, and that end_block has no successors.
2378 * So by re-purposing end_block as the first block of stream-
2379 * out, we guarantee that all exit paths flow into the stream-
2380 * out instructions.
2381 */
2382 if ((ctx->compiler->gpu_id < 500) &&
2383 (ctx->so->shader->stream_output.num_outputs > 0) &&
2384 !ctx->so->binning_pass) {
2385 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2386 emit_stream_out(ctx);
2387 }
2388
2389 ir3_END(ctx->block);
2390 }
2391
2392 static void
2393 setup_input(struct ir3_context *ctx, nir_variable *in)
2394 {
2395 struct ir3_shader_variant *so = ctx->so;
2396 unsigned ncomp = glsl_get_components(in->type);
2397 unsigned n = in->data.driver_location;
2398 unsigned frac = in->data.location_frac;
2399 unsigned slot = in->data.location;
2400
2401 /* skip unread inputs, we could end up with (for example), unsplit
2402 * matrix/etc inputs in the case they are not read, so just silently
2403 * skip these.
2404 */
2405 if (ncomp > 4)
2406 return;
2407
2408 so->inputs[n].slot = slot;
2409 so->inputs[n].compmask = (1 << (ncomp + frac)) - 1;
2410 so->inputs_count = MAX2(so->inputs_count, n + 1);
2411 so->inputs[n].interpolate = in->data.interpolation;
2412
2413 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2414
2415 /* if any varyings have 'sample' qualifer, that triggers us
2416 * to run in per-sample mode:
2417 */
2418 so->per_samp |= in->data.sample;
2419
2420 for (int i = 0; i < ncomp; i++) {
2421 struct ir3_instruction *instr = NULL;
2422 unsigned idx = (n * 4) + i + frac;
2423
2424 if (slot == VARYING_SLOT_POS) {
2425 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2426 } else if (slot == VARYING_SLOT_PNTC) {
2427 /* see for example st_nir_fixup_varying_slots().. this is
2428 * maybe a bit mesa/st specific. But we need things to line
2429 * up for this in fdN_program:
2430 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2431 * if (emit->sprite_coord_enable & texmask) {
2432 * ...
2433 * }
2434 */
2435 so->inputs[n].slot = VARYING_SLOT_VAR8;
2436 so->inputs[n].bary = true;
2437 instr = create_frag_input(ctx, false, idx);
2438 } else {
2439 /* detect the special case for front/back colors where
2440 * we need to do flat vs smooth shading depending on
2441 * rast state:
2442 */
2443 if (in->data.interpolation == INTERP_MODE_NONE) {
2444 switch (slot) {
2445 case VARYING_SLOT_COL0:
2446 case VARYING_SLOT_COL1:
2447 case VARYING_SLOT_BFC0:
2448 case VARYING_SLOT_BFC1:
2449 so->inputs[n].rasterflat = true;
2450 break;
2451 default:
2452 break;
2453 }
2454 }
2455
2456 if (ctx->compiler->flat_bypass) {
2457 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2458 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2459 so->inputs[n].use_ldlv = true;
2460 }
2461
2462 so->inputs[n].bary = true;
2463
2464 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2465 }
2466
2467 compile_assert(ctx, idx < ctx->ir->ninputs);
2468
2469 ctx->ir->inputs[idx] = instr;
2470 }
2471 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2472 for (int i = 0; i < ncomp; i++) {
2473 unsigned idx = (n * 4) + i + frac;
2474 compile_assert(ctx, idx < ctx->ir->ninputs);
2475 ctx->ir->inputs[idx] = create_input(ctx, idx);
2476 }
2477 } else {
2478 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2479 }
2480
2481 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2482 so->total_in += ncomp;
2483 }
2484 }
2485
2486 /* Initially we assign non-packed inloc's for varyings, as we don't really
2487 * know up-front which components will be unused. After all the compilation
2488 * stages we scan the shader to see which components are actually used, and
2489 * re-pack the inlocs to eliminate unneeded varyings.
2490 */
2491 static void
2492 pack_inlocs(struct ir3_context *ctx)
2493 {
2494 struct ir3_shader_variant *so = ctx->so;
2495 uint8_t used_components[so->inputs_count];
2496
2497 memset(used_components, 0, sizeof(used_components));
2498
2499 /*
2500 * First Step: scan shader to find which bary.f/ldlv remain:
2501 */
2502
2503 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2504 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2505 if (is_input(instr)) {
2506 unsigned inloc = instr->regs[1]->iim_val;
2507 unsigned i = inloc / 4;
2508 unsigned j = inloc % 4;
2509
2510 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
2511 compile_assert(ctx, i < so->inputs_count);
2512
2513 used_components[i] |= 1 << j;
2514 }
2515 }
2516 }
2517
2518 /*
2519 * Second Step: reassign varying inloc/slots:
2520 */
2521
2522 unsigned actual_in = 0;
2523 unsigned inloc = 0;
2524
2525 for (unsigned i = 0; i < so->inputs_count; i++) {
2526 unsigned compmask = 0, maxcomp = 0;
2527
2528 so->inputs[i].inloc = inloc;
2529 so->inputs[i].bary = false;
2530
2531 for (unsigned j = 0; j < 4; j++) {
2532 if (!(used_components[i] & (1 << j)))
2533 continue;
2534
2535 compmask |= (1 << j);
2536 actual_in++;
2537 maxcomp = j + 1;
2538
2539 /* at this point, since used_components[i] mask is only
2540 * considering varyings (ie. not sysvals) we know this
2541 * is a varying:
2542 */
2543 so->inputs[i].bary = true;
2544 }
2545
2546 if (so->inputs[i].bary) {
2547 so->varying_in++;
2548 so->inputs[i].compmask = (1 << maxcomp) - 1;
2549 inloc += maxcomp;
2550 }
2551 }
2552
2553 /*
2554 * Third Step: reassign packed inloc's:
2555 */
2556
2557 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2558 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2559 if (is_input(instr)) {
2560 unsigned inloc = instr->regs[1]->iim_val;
2561 unsigned i = inloc / 4;
2562 unsigned j = inloc % 4;
2563
2564 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
2565 }
2566 }
2567 }
2568 }
2569
2570 static void
2571 setup_output(struct ir3_context *ctx, nir_variable *out)
2572 {
2573 struct ir3_shader_variant *so = ctx->so;
2574 unsigned ncomp = glsl_get_components(out->type);
2575 unsigned n = out->data.driver_location;
2576 unsigned frac = out->data.location_frac;
2577 unsigned slot = out->data.location;
2578 unsigned comp = 0;
2579
2580 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2581 switch (slot) {
2582 case FRAG_RESULT_DEPTH:
2583 comp = 2; /* tgsi will write to .z component */
2584 so->writes_pos = true;
2585 break;
2586 case FRAG_RESULT_COLOR:
2587 so->color0_mrt = 1;
2588 break;
2589 case FRAG_RESULT_SAMPLE_MASK:
2590 so->writes_smask = true;
2591 break;
2592 default:
2593 if (slot >= FRAG_RESULT_DATA0)
2594 break;
2595 ir3_context_error(ctx, "unknown FS output name: %s\n",
2596 gl_frag_result_name(slot));
2597 }
2598 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2599 switch (slot) {
2600 case VARYING_SLOT_POS:
2601 so->writes_pos = true;
2602 break;
2603 case VARYING_SLOT_PSIZ:
2604 so->writes_psize = true;
2605 break;
2606 case VARYING_SLOT_COL0:
2607 case VARYING_SLOT_COL1:
2608 case VARYING_SLOT_BFC0:
2609 case VARYING_SLOT_BFC1:
2610 case VARYING_SLOT_FOGC:
2611 case VARYING_SLOT_CLIP_DIST0:
2612 case VARYING_SLOT_CLIP_DIST1:
2613 case VARYING_SLOT_CLIP_VERTEX:
2614 break;
2615 default:
2616 if (slot >= VARYING_SLOT_VAR0)
2617 break;
2618 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2619 break;
2620 ir3_context_error(ctx, "unknown VS output name: %s\n",
2621 gl_varying_slot_name(slot));
2622 }
2623 } else {
2624 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2625 }
2626
2627 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2628
2629 so->outputs[n].slot = slot;
2630 so->outputs[n].regid = regid(n, comp);
2631 so->outputs_count = MAX2(so->outputs_count, n + 1);
2632
2633 for (int i = 0; i < ncomp; i++) {
2634 unsigned idx = (n * 4) + i + frac;
2635 compile_assert(ctx, idx < ctx->ir->noutputs);
2636 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2637 }
2638
2639 /* if varying packing doesn't happen, we could end up in a situation
2640 * with "holes" in the output, and since the per-generation code that
2641 * sets up varying linkage registers doesn't expect to have more than
2642 * one varying per vec4 slot, pad the holes.
2643 *
2644 * Note that this should probably generate a performance warning of
2645 * some sort.
2646 */
2647 for (int i = 0; i < frac; i++) {
2648 unsigned idx = (n * 4) + i;
2649 if (!ctx->ir->outputs[idx]) {
2650 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2651 }
2652 }
2653 }
2654
2655 static int
2656 max_drvloc(struct exec_list *vars)
2657 {
2658 int drvloc = -1;
2659 nir_foreach_variable(var, vars) {
2660 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2661 }
2662 return drvloc;
2663 }
2664
2665 static const unsigned max_sysvals[] = {
2666 [MESA_SHADER_FRAGMENT] = 24, // TODO
2667 [MESA_SHADER_VERTEX] = 16,
2668 [MESA_SHADER_COMPUTE] = 16, // TODO how many do we actually need?
2669 [MESA_SHADER_KERNEL] = 16, // TODO how many do we actually need?
2670 };
2671
2672 static void
2673 emit_instructions(struct ir3_context *ctx)
2674 {
2675 unsigned ninputs, noutputs;
2676 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
2677
2678 ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
2679 noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
2680
2681 /* we need to leave room for sysvals:
2682 */
2683 ninputs += max_sysvals[ctx->so->type];
2684
2685 ctx->ir = ir3_create(ctx->compiler, ctx->so->type, ninputs, noutputs);
2686
2687 /* Create inputs in first block: */
2688 ctx->block = get_block(ctx, nir_start_block(fxn));
2689 ctx->in_block = ctx->block;
2690 list_addtail(&ctx->block->node, &ctx->ir->block_list);
2691
2692 ninputs -= max_sysvals[ctx->so->type];
2693
2694 /* for fragment shader, the vcoord input register is used as the
2695 * base for bary.f varying fetch instrs:
2696 *
2697 * TODO defer creating ctx->ij_pixel and corresponding sysvals
2698 * until emit_intrinsic when we know they are actually needed.
2699 * For now, we defer creating ctx->ij_centroid, etc, since we
2700 * only need ij_pixel for "old style" varying inputs (ie.
2701 * tgsi_to_nir)
2702 */
2703 struct ir3_instruction *vcoord = NULL;
2704 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2705 struct ir3_instruction *xy[2];
2706
2707 vcoord = create_input_compmask(ctx, 0, 0x3);
2708 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
2709
2710 ctx->ij_pixel = ir3_create_collect(ctx, xy, 2);
2711 }
2712
2713 /* Setup inputs: */
2714 nir_foreach_variable(var, &ctx->s->inputs) {
2715 setup_input(ctx, var);
2716 }
2717
2718 /* Defer add_sysval_input() stuff until after setup_inputs(),
2719 * because sysvals need to be appended after varyings:
2720 */
2721 if (vcoord) {
2722 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PIXEL,
2723 0x3, vcoord);
2724 }
2725
2726 /* Setup outputs: */
2727 nir_foreach_variable(var, &ctx->s->outputs) {
2728 setup_output(ctx, var);
2729 }
2730
2731 /* Find # of samplers: */
2732 nir_foreach_variable(var, &ctx->s->uniforms) {
2733 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
2734 /* just assume that we'll be reading from images.. if it
2735 * is write-only we don't have to count it, but not sure
2736 * if there is a good way to know?
2737 */
2738 ctx->so->num_samp += glsl_type_get_image_count(var->type);
2739 }
2740
2741 /* NOTE: need to do something more clever when we support >1 fxn */
2742 nir_foreach_register(reg, &fxn->registers) {
2743 ir3_declare_array(ctx, reg);
2744 }
2745 /* And emit the body: */
2746 ctx->impl = fxn;
2747 emit_function(ctx, fxn);
2748 }
2749
2750 /* from NIR perspective, we actually have varying inputs. But the varying
2751 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
2752 * only actual inputs are the sysvals.
2753 */
2754 static void
2755 fixup_frag_inputs(struct ir3_context *ctx)
2756 {
2757 struct ir3_shader_variant *so = ctx->so;
2758 struct ir3 *ir = ctx->ir;
2759 unsigned i = 0;
2760
2761 /* sysvals should appear at the end of the inputs, drop everything else: */
2762 while ((i < so->inputs_count) && !so->inputs[i].sysval)
2763 i++;
2764
2765 /* at IR level, inputs are always blocks of 4 scalars: */
2766 i *= 4;
2767
2768 ir->inputs = &ir->inputs[i];
2769 ir->ninputs -= i;
2770 }
2771
2772 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2773 * need to assign the tex state indexes for these after we know the
2774 * max tex index.
2775 */
2776 static void
2777 fixup_astc_srgb(struct ir3_context *ctx)
2778 {
2779 struct ir3_shader_variant *so = ctx->so;
2780 /* indexed by original tex idx, value is newly assigned alpha sampler
2781 * state tex idx. Zero is invalid since there is at least one sampler
2782 * if we get here.
2783 */
2784 unsigned alt_tex_state[16] = {0};
2785 unsigned tex_idx = ctx->max_texture_index + 1;
2786 unsigned idx = 0;
2787
2788 so->astc_srgb.base = tex_idx;
2789
2790 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
2791 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
2792
2793 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
2794
2795 if (alt_tex_state[sam->cat5.tex] == 0) {
2796 /* assign new alternate/alpha tex state slot: */
2797 alt_tex_state[sam->cat5.tex] = tex_idx++;
2798 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
2799 so->astc_srgb.count++;
2800 }
2801
2802 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
2803 }
2804 }
2805
2806 static void
2807 fixup_binning_pass(struct ir3_context *ctx)
2808 {
2809 struct ir3_shader_variant *so = ctx->so;
2810 struct ir3 *ir = ctx->ir;
2811 unsigned i, j;
2812
2813 for (i = 0, j = 0; i < so->outputs_count; i++) {
2814 unsigned slot = so->outputs[i].slot;
2815
2816 /* throw away everything but first position/psize */
2817 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
2818 if (i != j) {
2819 so->outputs[j] = so->outputs[i];
2820 ir->outputs[(j*4)+0] = ir->outputs[(i*4)+0];
2821 ir->outputs[(j*4)+1] = ir->outputs[(i*4)+1];
2822 ir->outputs[(j*4)+2] = ir->outputs[(i*4)+2];
2823 ir->outputs[(j*4)+3] = ir->outputs[(i*4)+3];
2824 }
2825 j++;
2826 }
2827 }
2828 so->outputs_count = j;
2829 ir->noutputs = j * 4;
2830 }
2831
2832 int
2833 ir3_compile_shader_nir(struct ir3_compiler *compiler,
2834 struct ir3_shader_variant *so)
2835 {
2836 struct ir3_context *ctx;
2837 struct ir3 *ir;
2838 struct ir3_instruction **inputs;
2839 unsigned i;
2840 int ret = 0, max_bary;
2841
2842 assert(!so->ir);
2843
2844 ctx = ir3_context_init(compiler, so);
2845 if (!ctx) {
2846 DBG("INIT failed!");
2847 ret = -1;
2848 goto out;
2849 }
2850
2851 emit_instructions(ctx);
2852
2853 if (ctx->error) {
2854 DBG("EMIT failed!");
2855 ret = -1;
2856 goto out;
2857 }
2858
2859 ir = so->ir = ctx->ir;
2860
2861 /* keep track of the inputs from TGSI perspective.. */
2862 inputs = ir->inputs;
2863
2864 /* but fixup actual inputs for frag shader: */
2865 if (so->type == MESA_SHADER_FRAGMENT)
2866 fixup_frag_inputs(ctx);
2867
2868 /* at this point, for binning pass, throw away unneeded outputs: */
2869 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
2870 fixup_binning_pass(ctx);
2871
2872 /* if we want half-precision outputs, mark the output registers
2873 * as half:
2874 */
2875 if (so->key.half_precision) {
2876 for (i = 0; i < ir->noutputs; i++) {
2877 struct ir3_instruction *out = ir->outputs[i];
2878
2879 if (!out)
2880 continue;
2881
2882 /* if frag shader writes z, that needs to be full precision: */
2883 if (so->outputs[i/4].slot == FRAG_RESULT_DEPTH)
2884 continue;
2885
2886 out->regs[0]->flags |= IR3_REG_HALF;
2887 /* output could be a fanout (ie. texture fetch output)
2888 * in which case we need to propagate the half-reg flag
2889 * up to the definer so that RA sees it:
2890 */
2891 if (out->opc == OPC_META_FO) {
2892 out = out->regs[1]->instr;
2893 out->regs[0]->flags |= IR3_REG_HALF;
2894 }
2895
2896 if (out->opc == OPC_MOV) {
2897 out->cat1.dst_type = half_type(out->cat1.dst_type);
2898 }
2899 }
2900 }
2901
2902 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2903 printf("BEFORE CP:\n");
2904 ir3_print(ir);
2905 }
2906
2907 ir3_cp(ir, so);
2908
2909 /* at this point, for binning pass, throw away unneeded outputs:
2910 * Note that for a6xx and later, we do this after ir3_cp to ensure
2911 * that the uniform/constant layout for BS and VS matches, so that
2912 * we can re-use same VS_CONST state group.
2913 */
2914 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
2915 fixup_binning_pass(ctx);
2916
2917 /* for a6xx+, binning and draw pass VS use same VBO state, so we
2918 * need to make sure not to remove any inputs that are used by
2919 * the nonbinning VS.
2920 */
2921 if (ctx->compiler->gpu_id >= 600 && so->binning_pass) {
2922 debug_assert(so->type == MESA_SHADER_VERTEX);
2923 for (int i = 0; i < ir->ninputs; i++) {
2924 struct ir3_instruction *in = ir->inputs[i];
2925
2926 if (!in)
2927 continue;
2928
2929 unsigned n = i / 4;
2930 unsigned c = i % 4;
2931
2932 debug_assert(n < so->nonbinning->inputs_count);
2933
2934 if (so->nonbinning->inputs[n].sysval)
2935 continue;
2936
2937 /* be sure to keep inputs, even if only used in VS */
2938 if (so->nonbinning->inputs[n].compmask & (1 << c))
2939 array_insert(in->block, in->block->keeps, in);
2940 }
2941 }
2942
2943 /* Insert mov if there's same instruction for each output.
2944 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
2945 */
2946 for (int i = ir->noutputs - 1; i >= 0; i--) {
2947 if (!ir->outputs[i])
2948 continue;
2949 for (unsigned j = 0; j < i; j++) {
2950 if (ir->outputs[i] == ir->outputs[j]) {
2951 ir->outputs[i] =
2952 ir3_MOV(ir->outputs[i]->block, ir->outputs[i], TYPE_F32);
2953 }
2954 }
2955 }
2956
2957 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2958 printf("BEFORE GROUPING:\n");
2959 ir3_print(ir);
2960 }
2961
2962 ir3_sched_add_deps(ir);
2963
2964 /* Group left/right neighbors, inserting mov's where needed to
2965 * solve conflicts:
2966 */
2967 ir3_group(ir);
2968
2969 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2970 printf("AFTER GROUPING:\n");
2971 ir3_print(ir);
2972 }
2973
2974 ir3_depth(ir);
2975
2976 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2977 printf("AFTER DEPTH:\n");
2978 ir3_print(ir);
2979 }
2980
2981 /* do Sethi–Ullman numbering before scheduling: */
2982 ir3_sun(ir);
2983
2984 ret = ir3_sched(ir);
2985 if (ret) {
2986 DBG("SCHED failed!");
2987 goto out;
2988 }
2989
2990 if (compiler->gpu_id >= 600) {
2991 ir3_a6xx_fixup_atomic_dests(ir, so);
2992 }
2993
2994 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2995 printf("AFTER SCHED:\n");
2996 ir3_print(ir);
2997 }
2998
2999 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3000 * with draw pass VS, so binning and draw pass can both use the
3001 * same VBO state.
3002 *
3003 * Note that VS inputs are expected to be full precision.
3004 */
3005 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3006 (ir->type == MESA_SHADER_VERTEX) &&
3007 so->binning_pass;
3008
3009 if (pre_assign_inputs) {
3010 for (unsigned i = 0; i < ir->ninputs; i++) {
3011 struct ir3_instruction *instr = ir->inputs[i];
3012
3013 if (!instr)
3014 continue;
3015
3016 unsigned n = i / 4;
3017 unsigned c = i % 4;
3018 unsigned regid = so->nonbinning->inputs[n].regid + c;
3019
3020 instr->regs[0]->num = regid;
3021 }
3022
3023 ret = ir3_ra(so, ir->inputs, ir->ninputs);
3024 } else {
3025 ret = ir3_ra(so, NULL, 0);
3026 }
3027
3028 if (ret) {
3029 DBG("RA failed!");
3030 goto out;
3031 }
3032
3033 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3034 printf("AFTER RA:\n");
3035 ir3_print(ir);
3036 }
3037
3038 if (so->type == MESA_SHADER_FRAGMENT)
3039 pack_inlocs(ctx);
3040
3041 /* fixup input/outputs: */
3042 for (i = 0; i < so->outputs_count; i++) {
3043 /* sometimes we get outputs that don't write the .x coord, like:
3044 *
3045 * decl_var shader_out INTERP_MODE_NONE float Color (VARYING_SLOT_VAR9.z, 1, 0)
3046 *
3047 * Presumably the result of varying packing and then eliminating
3048 * some unneeded varyings? Just skip head to the first valid
3049 * component of the output.
3050 */
3051 for (unsigned j = 0; j < 4; j++) {
3052 struct ir3_instruction *instr = ir->outputs[(i*4) + j];
3053 if (instr) {
3054 so->outputs[i].regid = instr->regs[0]->num;
3055 so->outputs[i].half = !!(instr->regs[0]->flags & IR3_REG_HALF);
3056 break;
3057 }
3058 }
3059 }
3060
3061 /* Note that some or all channels of an input may be unused: */
3062 for (i = 0; i < so->inputs_count; i++) {
3063 unsigned j, reg = regid(63,0);
3064 bool half = false;
3065 for (j = 0; j < 4; j++) {
3066 struct ir3_instruction *in = inputs[(i*4) + j];
3067
3068 if (!in)
3069 continue;
3070
3071 if (in->flags & IR3_INSTR_UNUSED)
3072 continue;
3073
3074 reg = in->regs[0]->num - j;
3075 if (half) {
3076 compile_assert(ctx, in->regs[0]->flags & IR3_REG_HALF);
3077 } else {
3078 half = !!(in->regs[0]->flags & IR3_REG_HALF);
3079 }
3080 }
3081 so->inputs[i].regid = reg;
3082 so->inputs[i].half = half;
3083 }
3084
3085 if (ctx->astc_srgb)
3086 fixup_astc_srgb(ctx);
3087
3088 /* We need to do legalize after (for frag shader's) the "bary.f"
3089 * offsets (inloc) have been assigned.
3090 */
3091 ir3_legalize(ir, &so->has_ssbo, &so->need_pixlod, &max_bary);
3092
3093 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3094 printf("AFTER LEGALIZE:\n");
3095 ir3_print(ir);
3096 }
3097
3098 so->branchstack = ctx->max_stack;
3099
3100 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3101 if (so->type == MESA_SHADER_FRAGMENT)
3102 so->total_in = max_bary + 1;
3103
3104 so->max_sun = ir->max_sun;
3105
3106 out:
3107 if (ret) {
3108 if (so->ir)
3109 ir3_destroy(so->ir);
3110 so->ir = NULL;
3111 }
3112 ir3_context_free(ctx);
3113
3114 return ret;
3115 }