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freedreno/ir3: Implement f2b16 and i2b16
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 __ssa_dst(mov);
55 src = __ssa_src(mov, collect, IR3_REG_RELATIV);
56 src->size = arrsz;
57 src->array.offset = n;
58
59 ir3_instr_set_address(mov, address);
60
61 return mov;
62 }
63
64 static struct ir3_instruction *
65 create_input(struct ir3_context *ctx, unsigned compmask)
66 {
67 struct ir3_instruction *in;
68
69 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
70 in->input.sysval = ~0;
71 __ssa_dst(in)->wrmask = compmask;
72
73 array_insert(ctx->ir, ctx->ir->inputs, in);
74
75 return in;
76 }
77
78 static struct ir3_instruction *
79 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
80 {
81 struct ir3_block *block = ctx->block;
82 struct ir3_instruction *instr;
83 /* packed inloc is fixed up later: */
84 struct ir3_instruction *inloc = create_immed(block, n);
85
86 if (use_ldlv) {
87 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
88 instr->cat6.type = TYPE_U32;
89 instr->cat6.iim_val = 1;
90 } else {
91 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
92 instr->regs[2]->wrmask = 0x3;
93 }
94
95 return instr;
96 }
97
98 static struct ir3_instruction *
99 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
100 {
101 /* first four vec4 sysval's reserved for UBOs: */
102 /* NOTE: dp is in scalar, but there can be >4 dp components: */
103 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
104 unsigned n = const_state->offsets.driver_param;
105 unsigned r = regid(n + dp / 4, dp % 4);
106 return create_uniform(ctx->block, r);
107 }
108
109 /*
110 * Adreno uses uint rather than having dedicated bool type,
111 * which (potentially) requires some conversion, in particular
112 * when using output of an bool instr to int input, or visa
113 * versa.
114 *
115 * | Adreno | NIR |
116 * -------+---------+-------+-
117 * true | 1 | ~0 |
118 * false | 0 | 0 |
119 *
120 * To convert from an adreno bool (uint) to nir, use:
121 *
122 * absneg.s dst, (neg)src
123 *
124 * To convert back in the other direction:
125 *
126 * absneg.s dst, (abs)arc
127 *
128 * The CP step can clean up the absneg.s that cancel each other
129 * out, and with a slight bit of extra cleverness (to recognize
130 * the instructions which produce either a 0 or 1) can eliminate
131 * the absneg.s's completely when an instruction that wants
132 * 0/1 consumes the result. For example, when a nir 'bcsel'
133 * consumes the result of 'feq'. So we should be able to get by
134 * without a boolean resolve step, and without incuring any
135 * extra penalty in instruction count.
136 */
137
138 /* NIR bool -> native (adreno): */
139 static struct ir3_instruction *
140 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
141 {
142 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
143 }
144
145 /* native (adreno) -> NIR bool: */
146 static struct ir3_instruction *
147 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
148 {
149 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
150 }
151
152 /*
153 * alu/sfu instructions:
154 */
155
156 static struct ir3_instruction *
157 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
158 unsigned src_bitsize, nir_op op)
159 {
160 type_t src_type, dst_type;
161
162 switch (op) {
163 case nir_op_f2f32:
164 case nir_op_f2f16_rtne:
165 case nir_op_f2f16_rtz:
166 case nir_op_f2f16:
167 case nir_op_f2i32:
168 case nir_op_f2i16:
169 case nir_op_f2i8:
170 case nir_op_f2u32:
171 case nir_op_f2u16:
172 case nir_op_f2u8:
173 switch (src_bitsize) {
174 case 32:
175 src_type = TYPE_F32;
176 break;
177 case 16:
178 src_type = TYPE_F16;
179 break;
180 default:
181 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
182 }
183 break;
184
185 case nir_op_i2f32:
186 case nir_op_i2f16:
187 case nir_op_i2i32:
188 case nir_op_i2i16:
189 case nir_op_i2i8:
190 switch (src_bitsize) {
191 case 32:
192 src_type = TYPE_S32;
193 break;
194 case 16:
195 src_type = TYPE_S16;
196 break;
197 case 8:
198 src_type = TYPE_S8;
199 break;
200 default:
201 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
202 }
203 break;
204
205 case nir_op_u2f32:
206 case nir_op_u2f16:
207 case nir_op_u2u32:
208 case nir_op_u2u16:
209 case nir_op_u2u8:
210 switch (src_bitsize) {
211 case 32:
212 src_type = TYPE_U32;
213 break;
214 case 16:
215 src_type = TYPE_U16;
216 break;
217 case 8:
218 src_type = TYPE_U8;
219 break;
220 default:
221 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
222 }
223 break;
224
225 default:
226 ir3_context_error(ctx, "invalid conversion op: %u", op);
227 }
228
229 switch (op) {
230 case nir_op_f2f32:
231 case nir_op_i2f32:
232 case nir_op_u2f32:
233 dst_type = TYPE_F32;
234 break;
235
236 case nir_op_f2f16_rtne:
237 case nir_op_f2f16_rtz:
238 case nir_op_f2f16:
239 /* TODO how to handle rounding mode? */
240 case nir_op_i2f16:
241 case nir_op_u2f16:
242 dst_type = TYPE_F16;
243 break;
244
245 case nir_op_f2i32:
246 case nir_op_i2i32:
247 dst_type = TYPE_S32;
248 break;
249
250 case nir_op_f2i16:
251 case nir_op_i2i16:
252 dst_type = TYPE_S16;
253 break;
254
255 case nir_op_f2i8:
256 case nir_op_i2i8:
257 dst_type = TYPE_S8;
258 break;
259
260 case nir_op_f2u32:
261 case nir_op_u2u32:
262 dst_type = TYPE_U32;
263 break;
264
265 case nir_op_f2u16:
266 case nir_op_u2u16:
267 dst_type = TYPE_U16;
268 break;
269
270 case nir_op_f2u8:
271 case nir_op_u2u8:
272 dst_type = TYPE_U8;
273 break;
274
275 default:
276 ir3_context_error(ctx, "invalid conversion op: %u", op);
277 }
278
279 return ir3_COV(ctx->block, src, src_type, dst_type);
280 }
281
282 static void
283 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
284 {
285 const nir_op_info *info = &nir_op_infos[alu->op];
286 struct ir3_instruction **dst, *src[info->num_inputs];
287 unsigned bs[info->num_inputs]; /* bit size */
288 struct ir3_block *b = ctx->block;
289 unsigned dst_sz, wrmask;
290 type_t dst_type = nir_dest_bit_size(alu->dest.dest) < 32 ?
291 TYPE_U16 : TYPE_U32;
292
293 if (alu->dest.dest.is_ssa) {
294 dst_sz = alu->dest.dest.ssa.num_components;
295 wrmask = (1 << dst_sz) - 1;
296 } else {
297 dst_sz = alu->dest.dest.reg.reg->num_components;
298 wrmask = alu->dest.write_mask;
299 }
300
301 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
302
303 /* Vectors are special in that they have non-scalarized writemasks,
304 * and just take the first swizzle channel for each argument in
305 * order into each writemask channel.
306 */
307 if ((alu->op == nir_op_vec2) ||
308 (alu->op == nir_op_vec3) ||
309 (alu->op == nir_op_vec4)) {
310
311 for (int i = 0; i < info->num_inputs; i++) {
312 nir_alu_src *asrc = &alu->src[i];
313
314 compile_assert(ctx, !asrc->abs);
315 compile_assert(ctx, !asrc->negate);
316
317 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
318 if (!src[i])
319 src[i] = create_immed_typed(ctx->block, 0, dst_type);
320 dst[i] = ir3_MOV(b, src[i], dst_type);
321 }
322
323 ir3_put_dst(ctx, &alu->dest.dest);
324 return;
325 }
326
327 /* We also get mov's with more than one component for mov's so
328 * handle those specially:
329 */
330 if (alu->op == nir_op_mov) {
331 nir_alu_src *asrc = &alu->src[0];
332 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
333
334 for (unsigned i = 0; i < dst_sz; i++) {
335 if (wrmask & (1 << i)) {
336 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
337 } else {
338 dst[i] = NULL;
339 }
340 }
341
342 ir3_put_dst(ctx, &alu->dest.dest);
343 return;
344 }
345
346 /* General case: We can just grab the one used channel per src. */
347 for (int i = 0; i < info->num_inputs; i++) {
348 unsigned chan = ffs(alu->dest.write_mask) - 1;
349 nir_alu_src *asrc = &alu->src[i];
350
351 compile_assert(ctx, !asrc->abs);
352 compile_assert(ctx, !asrc->negate);
353
354 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
355 bs[i] = nir_src_bit_size(asrc->src);
356
357 compile_assert(ctx, src[i]);
358 }
359
360 switch (alu->op) {
361 case nir_op_f2f32:
362 case nir_op_f2f16_rtne:
363 case nir_op_f2f16_rtz:
364 case nir_op_f2f16:
365 case nir_op_f2i32:
366 case nir_op_f2i16:
367 case nir_op_f2i8:
368 case nir_op_f2u32:
369 case nir_op_f2u16:
370 case nir_op_f2u8:
371 case nir_op_i2f32:
372 case nir_op_i2f16:
373 case nir_op_i2i32:
374 case nir_op_i2i16:
375 case nir_op_i2i8:
376 case nir_op_u2f32:
377 case nir_op_u2f16:
378 case nir_op_u2u32:
379 case nir_op_u2u16:
380 case nir_op_u2u8:
381 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
382 break;
383 case nir_op_fquantize2f16:
384 dst[0] = create_cov(ctx,
385 create_cov(ctx, src[0], 32, nir_op_f2f16),
386 16, nir_op_f2f32);
387 break;
388 case nir_op_f2b16: {
389 struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_F16);
390 dst[0] = ir3_CMPS_F(b, src[0], 0, zero, 0);
391 dst[0]->cat2.condition = IR3_COND_NE;
392 break;
393 }
394 case nir_op_f2b32:
395 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
396 dst[0]->cat2.condition = IR3_COND_NE;
397 break;
398 case nir_op_b2f16:
399 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F16);
400 break;
401 case nir_op_b2f32:
402 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
403 break;
404 case nir_op_b2i8:
405 case nir_op_b2i16:
406 case nir_op_b2i32:
407 dst[0] = ir3_b2n(b, src[0]);
408 break;
409 case nir_op_i2b16: {
410 struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_S16);
411 dst[0] = ir3_CMPS_S(b, src[0], 0, zero, 0);
412 dst[0]->cat2.condition = IR3_COND_NE;
413 break;
414 }
415 case nir_op_i2b32:
416 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
417 dst[0]->cat2.condition = IR3_COND_NE;
418 break;
419
420 case nir_op_fneg:
421 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
422 break;
423 case nir_op_fabs:
424 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
425 break;
426 case nir_op_fmax:
427 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
428 break;
429 case nir_op_fmin:
430 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
431 break;
432 case nir_op_fsat:
433 /* if there is just a single use of the src, and it supports
434 * (sat) bit, we can just fold the (sat) flag back to the
435 * src instruction and create a mov. This is easier for cp
436 * to eliminate.
437 *
438 * TODO probably opc_cat==4 is ok too
439 */
440 if (alu->src[0].src.is_ssa &&
441 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
442 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
443 src[0]->flags |= IR3_INSTR_SAT;
444 dst[0] = ir3_MOV(b, src[0], dst_type);
445 } else {
446 /* otherwise generate a max.f that saturates.. blob does
447 * similar (generating a cat2 mov using max.f)
448 */
449 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
450 dst[0]->flags |= IR3_INSTR_SAT;
451 }
452 break;
453 case nir_op_fmul:
454 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
455 break;
456 case nir_op_fadd:
457 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
458 break;
459 case nir_op_fsub:
460 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
461 break;
462 case nir_op_ffma:
463 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
464 break;
465 case nir_op_fddx:
466 case nir_op_fddx_coarse:
467 dst[0] = ir3_DSX(b, src[0], 0);
468 dst[0]->cat5.type = TYPE_F32;
469 break;
470 case nir_op_fddy:
471 case nir_op_fddy_coarse:
472 dst[0] = ir3_DSY(b, src[0], 0);
473 dst[0]->cat5.type = TYPE_F32;
474 break;
475 break;
476 case nir_op_flt16:
477 case nir_op_flt32:
478 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
479 dst[0]->cat2.condition = IR3_COND_LT;
480 break;
481 case nir_op_fge16:
482 case nir_op_fge32:
483 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
484 dst[0]->cat2.condition = IR3_COND_GE;
485 break;
486 case nir_op_feq16:
487 case nir_op_feq32:
488 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
489 dst[0]->cat2.condition = IR3_COND_EQ;
490 break;
491 case nir_op_fne16:
492 case nir_op_fne32:
493 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
494 dst[0]->cat2.condition = IR3_COND_NE;
495 break;
496 case nir_op_fceil:
497 dst[0] = ir3_CEIL_F(b, src[0], 0);
498 break;
499 case nir_op_ffloor:
500 dst[0] = ir3_FLOOR_F(b, src[0], 0);
501 break;
502 case nir_op_ftrunc:
503 dst[0] = ir3_TRUNC_F(b, src[0], 0);
504 break;
505 case nir_op_fround_even:
506 dst[0] = ir3_RNDNE_F(b, src[0], 0);
507 break;
508 case nir_op_fsign:
509 dst[0] = ir3_SIGN_F(b, src[0], 0);
510 break;
511
512 case nir_op_fsin:
513 dst[0] = ir3_SIN(b, src[0], 0);
514 break;
515 case nir_op_fcos:
516 dst[0] = ir3_COS(b, src[0], 0);
517 break;
518 case nir_op_frsq:
519 dst[0] = ir3_RSQ(b, src[0], 0);
520 break;
521 case nir_op_frcp:
522 dst[0] = ir3_RCP(b, src[0], 0);
523 break;
524 case nir_op_flog2:
525 dst[0] = ir3_LOG2(b, src[0], 0);
526 break;
527 case nir_op_fexp2:
528 dst[0] = ir3_EXP2(b, src[0], 0);
529 break;
530 case nir_op_fsqrt:
531 dst[0] = ir3_SQRT(b, src[0], 0);
532 break;
533
534 case nir_op_iabs:
535 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
536 break;
537 case nir_op_iadd:
538 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
539 break;
540 case nir_op_iand:
541 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
542 break;
543 case nir_op_imax:
544 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
545 break;
546 case nir_op_umax:
547 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
548 break;
549 case nir_op_imin:
550 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
551 break;
552 case nir_op_umin:
553 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
554 break;
555 case nir_op_umul_low:
556 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
557 break;
558 case nir_op_imadsh_mix16:
559 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
560 break;
561 case nir_op_imad24_ir3:
562 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
563 break;
564 case nir_op_imul24:
565 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
566 break;
567 case nir_op_ineg:
568 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
569 break;
570 case nir_op_inot:
571 dst[0] = ir3_NOT_B(b, src[0], 0);
572 break;
573 case nir_op_ior:
574 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
575 break;
576 case nir_op_ishl:
577 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
578 break;
579 case nir_op_ishr:
580 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
581 break;
582 case nir_op_isub:
583 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
584 break;
585 case nir_op_ixor:
586 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
587 break;
588 case nir_op_ushr:
589 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
590 break;
591 case nir_op_ilt16:
592 case nir_op_ilt32:
593 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
594 dst[0]->cat2.condition = IR3_COND_LT;
595 break;
596 case nir_op_ige16:
597 case nir_op_ige32:
598 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
599 dst[0]->cat2.condition = IR3_COND_GE;
600 break;
601 case nir_op_ieq16:
602 case nir_op_ieq32:
603 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
604 dst[0]->cat2.condition = IR3_COND_EQ;
605 break;
606 case nir_op_ine16:
607 case nir_op_ine32:
608 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
609 dst[0]->cat2.condition = IR3_COND_NE;
610 break;
611 case nir_op_ult16:
612 case nir_op_ult32:
613 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
614 dst[0]->cat2.condition = IR3_COND_LT;
615 break;
616 case nir_op_uge16:
617 case nir_op_uge32:
618 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
619 dst[0]->cat2.condition = IR3_COND_GE;
620 break;
621
622 case nir_op_b16csel:
623 case nir_op_b32csel: {
624 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
625
626 if ((src[0]->regs[0]->flags & IR3_REG_HALF))
627 cond->regs[0]->flags |= IR3_REG_HALF;
628
629 compile_assert(ctx, bs[1] == bs[2]);
630 /* Make sure the boolean condition has the same bit size as the other
631 * two arguments, adding a conversion if necessary.
632 */
633 if (bs[1] < bs[0])
634 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
635 else if (bs[1] > bs[0])
636 cond = ir3_COV(b, cond, TYPE_U16, TYPE_U32);
637
638 if (bs[1] > 16)
639 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
640 else
641 dst[0] = ir3_SEL_B16(b, src[1], 0, cond, 0, src[2], 0);
642 break;
643 }
644 case nir_op_bit_count: {
645 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
646 // double check on earlier gen's. Once half-precision support is
647 // in place, this should probably move to a NIR lowering pass:
648 struct ir3_instruction *hi, *lo;
649
650 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
651 TYPE_U32, TYPE_U16);
652 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
653
654 hi = ir3_CBITS_B(b, hi, 0);
655 lo = ir3_CBITS_B(b, lo, 0);
656
657 // TODO maybe the builders should default to making dst half-precision
658 // if the src's were half precision, to make this less awkward.. otoh
659 // we should probably just do this lowering in NIR.
660 hi->regs[0]->flags |= IR3_REG_HALF;
661 lo->regs[0]->flags |= IR3_REG_HALF;
662
663 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
664 dst[0]->regs[0]->flags |= IR3_REG_HALF;
665 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
666 break;
667 }
668 case nir_op_ifind_msb: {
669 struct ir3_instruction *cmp;
670 dst[0] = ir3_CLZ_S(b, src[0], 0);
671 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
672 cmp->cat2.condition = IR3_COND_GE;
673 dst[0] = ir3_SEL_B32(b,
674 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
675 cmp, 0, dst[0], 0);
676 break;
677 }
678 case nir_op_ufind_msb:
679 dst[0] = ir3_CLZ_B(b, src[0], 0);
680 dst[0] = ir3_SEL_B32(b,
681 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
682 src[0], 0, dst[0], 0);
683 break;
684 case nir_op_find_lsb:
685 dst[0] = ir3_BFREV_B(b, src[0], 0);
686 dst[0] = ir3_CLZ_B(b, dst[0], 0);
687 break;
688 case nir_op_bitfield_reverse:
689 dst[0] = ir3_BFREV_B(b, src[0], 0);
690 break;
691
692 default:
693 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
694 nir_op_infos[alu->op].name);
695 break;
696 }
697
698 if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) {
699 assert(dst_sz == 1);
700
701 if (nir_dest_bit_size(alu->dest.dest) < 32)
702 dst[0]->regs[0]->flags |= IR3_REG_HALF;
703
704 dst[0] = ir3_n2b(b, dst[0]);
705 }
706
707 if (nir_dest_bit_size(alu->dest.dest) < 32) {
708 for (unsigned i = 0; i < dst_sz; i++) {
709 dst[i]->regs[0]->flags |= IR3_REG_HALF;
710 }
711 }
712
713 ir3_put_dst(ctx, &alu->dest.dest);
714 }
715
716 /* handles direct/indirect UBO reads: */
717 static void
718 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
719 struct ir3_instruction **dst)
720 {
721 struct ir3_block *b = ctx->block;
722 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
723 /* UBO addresses are the first driver params, but subtract 2 here to
724 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
725 * is the uniforms: */
726 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
727 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
728 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
729
730 int off = 0;
731
732 /* First src is ubo index, which could either be an immed or not: */
733 src0 = ir3_get_src(ctx, &intr->src[0])[0];
734 if (is_same_type_mov(src0) &&
735 (src0->regs[1]->flags & IR3_REG_IMMED)) {
736 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
737 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
738 } else {
739 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
740 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
741
742 /* NOTE: since relative addressing is used, make sure constlen is
743 * at least big enough to cover all the UBO addresses, since the
744 * assembler won't know what the max address reg is.
745 */
746 ctx->so->constlen = MAX2(ctx->so->constlen,
747 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
748 }
749
750 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
751 addr = base_lo;
752
753 if (nir_src_is_const(intr->src[1])) {
754 off += nir_src_as_uint(intr->src[1]);
755 } else {
756 /* For load_ubo_indirect, second src is indirect offset: */
757 src1 = ir3_get_src(ctx, &intr->src[1])[0];
758
759 /* and add offset to addr: */
760 addr = ir3_ADD_S(b, addr, 0, src1, 0);
761 }
762
763 /* if offset is to large to encode in the ldg, split it out: */
764 if ((off + (intr->num_components * 4)) > 1024) {
765 /* split out the minimal amount to improve the odds that
766 * cp can fit the immediate in the add.s instruction:
767 */
768 unsigned off2 = off + (intr->num_components * 4) - 1024;
769 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
770 off -= off2;
771 }
772
773 if (ptrsz == 2) {
774 struct ir3_instruction *carry;
775
776 /* handle 32b rollover, ie:
777 * if (addr < base_lo)
778 * base_hi++
779 */
780 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
781 carry->cat2.condition = IR3_COND_LT;
782 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
783
784 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
785 }
786
787 for (int i = 0; i < intr->num_components; i++) {
788 struct ir3_instruction *load =
789 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
790 create_immed(b, off + i * 4), 0);
791 load->cat6.type = TYPE_U32;
792 dst[i] = load;
793 }
794 }
795
796 /* src[] = { block_index } */
797 static void
798 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
799 struct ir3_instruction **dst)
800 {
801 /* SSBO size stored as a const starting at ssbo_sizes: */
802 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
803 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
804 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
805 const_state->ssbo_size.off[blk_idx];
806
807 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
808
809 dst[0] = create_uniform(ctx->block, idx);
810 }
811
812 /* src[] = { offset }. const_index[] = { base } */
813 static void
814 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
815 struct ir3_instruction **dst)
816 {
817 struct ir3_block *b = ctx->block;
818 struct ir3_instruction *ldl, *offset;
819 unsigned base;
820
821 offset = ir3_get_src(ctx, &intr->src[0])[0];
822 base = nir_intrinsic_base(intr);
823
824 ldl = ir3_LDL(b, offset, 0,
825 create_immed(b, intr->num_components), 0,
826 create_immed(b, base), 0);
827
828 ldl->cat6.type = utype_dst(intr->dest);
829 ldl->regs[0]->wrmask = MASK(intr->num_components);
830
831 ldl->barrier_class = IR3_BARRIER_SHARED_R;
832 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
833
834 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
835 }
836
837 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
838 static void
839 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
840 {
841 struct ir3_block *b = ctx->block;
842 struct ir3_instruction *stl, *offset;
843 struct ir3_instruction * const *value;
844 unsigned base, wrmask;
845
846 value = ir3_get_src(ctx, &intr->src[0]);
847 offset = ir3_get_src(ctx, &intr->src[1])[0];
848
849 base = nir_intrinsic_base(intr);
850 wrmask = nir_intrinsic_write_mask(intr);
851
852 /* Combine groups of consecutive enabled channels in one write
853 * message. We use ffs to find the first enabled channel and then ffs on
854 * the bit-inverse, down-shifted writemask to determine the length of
855 * the block of enabled bits.
856 *
857 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
858 */
859 while (wrmask) {
860 unsigned first_component = ffs(wrmask) - 1;
861 unsigned length = ffs(~(wrmask >> first_component)) - 1;
862
863 stl = ir3_STL(b, offset, 0,
864 ir3_create_collect(ctx, &value[first_component], length), 0,
865 create_immed(b, length), 0);
866 stl->cat6.dst_offset = first_component + base;
867 stl->cat6.type = utype_src(intr->src[0]);
868 stl->barrier_class = IR3_BARRIER_SHARED_W;
869 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
870
871 array_insert(b, b->keeps, stl);
872
873 /* Clear the bits in the writemask that we just wrote, then try
874 * again to see if more channels are left.
875 */
876 wrmask &= (15 << (first_component + length));
877 }
878 }
879
880 /* src[] = { offset }. const_index[] = { base } */
881 static void
882 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
883 struct ir3_instruction **dst)
884 {
885 struct ir3_block *b = ctx->block;
886 struct ir3_instruction *load, *offset;
887 unsigned base;
888
889 offset = ir3_get_src(ctx, &intr->src[0])[0];
890 base = nir_intrinsic_base(intr);
891
892 load = ir3_LDLW(b, offset, 0,
893 create_immed(b, intr->num_components), 0,
894 create_immed(b, base), 0);
895
896 load->cat6.type = utype_dst(intr->dest);
897 load->regs[0]->wrmask = MASK(intr->num_components);
898
899 load->barrier_class = IR3_BARRIER_SHARED_R;
900 load->barrier_conflict = IR3_BARRIER_SHARED_W;
901
902 ir3_split_dest(b, dst, load, 0, intr->num_components);
903 }
904
905 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
906 static void
907 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
908 {
909 struct ir3_block *b = ctx->block;
910 struct ir3_instruction *store, *offset;
911 struct ir3_instruction * const *value;
912 unsigned base, wrmask;
913
914 value = ir3_get_src(ctx, &intr->src[0]);
915 offset = ir3_get_src(ctx, &intr->src[1])[0];
916
917 base = nir_intrinsic_base(intr);
918 wrmask = nir_intrinsic_write_mask(intr);
919
920 /* Combine groups of consecutive enabled channels in one write
921 * message. We use ffs to find the first enabled channel and then ffs on
922 * the bit-inverse, down-shifted writemask to determine the length of
923 * the block of enabled bits.
924 *
925 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
926 */
927 while (wrmask) {
928 unsigned first_component = ffs(wrmask) - 1;
929 unsigned length = ffs(~(wrmask >> first_component)) - 1;
930
931 store = ir3_STLW(b, offset, 0,
932 ir3_create_collect(ctx, &value[first_component], length), 0,
933 create_immed(b, length), 0);
934
935 store->cat6.dst_offset = first_component + base;
936 store->cat6.type = utype_src(intr->src[0]);
937 store->barrier_class = IR3_BARRIER_SHARED_W;
938 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
939
940 array_insert(b, b->keeps, store);
941
942 /* Clear the bits in the writemask that we just wrote, then try
943 * again to see if more channels are left.
944 */
945 wrmask &= (15 << (first_component + length));
946 }
947 }
948
949 /*
950 * CS shared variable atomic intrinsics
951 *
952 * All of the shared variable atomic memory operations read a value from
953 * memory, compute a new value using one of the operations below, write the
954 * new value to memory, and return the original value read.
955 *
956 * All operations take 2 sources except CompSwap that takes 3. These
957 * sources represent:
958 *
959 * 0: The offset into the shared variable storage region that the atomic
960 * operation will operate on.
961 * 1: The data parameter to the atomic function (i.e. the value to add
962 * in shared_atomic_add, etc).
963 * 2: For CompSwap only: the second data parameter.
964 */
965 static struct ir3_instruction *
966 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
967 {
968 struct ir3_block *b = ctx->block;
969 struct ir3_instruction *atomic, *src0, *src1;
970 type_t type = TYPE_U32;
971
972 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
973 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
974
975 switch (intr->intrinsic) {
976 case nir_intrinsic_shared_atomic_add:
977 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
978 break;
979 case nir_intrinsic_shared_atomic_imin:
980 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
981 type = TYPE_S32;
982 break;
983 case nir_intrinsic_shared_atomic_umin:
984 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
985 break;
986 case nir_intrinsic_shared_atomic_imax:
987 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
988 type = TYPE_S32;
989 break;
990 case nir_intrinsic_shared_atomic_umax:
991 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
992 break;
993 case nir_intrinsic_shared_atomic_and:
994 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
995 break;
996 case nir_intrinsic_shared_atomic_or:
997 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
998 break;
999 case nir_intrinsic_shared_atomic_xor:
1000 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
1001 break;
1002 case nir_intrinsic_shared_atomic_exchange:
1003 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
1004 break;
1005 case nir_intrinsic_shared_atomic_comp_swap:
1006 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1007 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1008 ir3_get_src(ctx, &intr->src[2])[0],
1009 src1,
1010 }, 2);
1011 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
1012 break;
1013 default:
1014 unreachable("boo");
1015 }
1016
1017 atomic->cat6.iim_val = 1;
1018 atomic->cat6.d = 1;
1019 atomic->cat6.type = type;
1020 atomic->barrier_class = IR3_BARRIER_SHARED_W;
1021 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1022
1023 /* even if nothing consume the result, we can't DCE the instruction: */
1024 array_insert(b, b->keeps, atomic);
1025
1026 return atomic;
1027 }
1028
1029 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1030 * to handle with the image_mapping table..
1031 */
1032 static struct ir3_instruction *
1033 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1034 {
1035 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
1036 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1037 struct ir3_instruction *texture, *sampler;
1038
1039 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1040 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1041
1042 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1043 sampler,
1044 texture,
1045 }, 2);
1046 }
1047
1048 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1049 static void
1050 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1051 struct ir3_instruction **dst)
1052 {
1053 struct ir3_block *b = ctx->block;
1054 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1055 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1056 struct ir3_instruction *sam;
1057 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1058 struct ir3_instruction *coords[4];
1059 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1060 type_t type = ir3_get_image_type(var);
1061
1062 /* hmm, this seems a bit odd, but it is what blob does and (at least
1063 * a5xx) just faults on bogus addresses otherwise:
1064 */
1065 if (flags & IR3_INSTR_3D) {
1066 flags &= ~IR3_INSTR_3D;
1067 flags |= IR3_INSTR_A;
1068 }
1069
1070 for (unsigned i = 0; i < ncoords; i++)
1071 coords[i] = src0[i];
1072
1073 if (ncoords == 1)
1074 coords[ncoords++] = create_immed(b, 0);
1075
1076 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
1077 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
1078
1079 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1080 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1081
1082 ir3_split_dest(b, dst, sam, 0, 4);
1083 }
1084
1085 static void
1086 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1087 struct ir3_instruction **dst)
1088 {
1089 struct ir3_block *b = ctx->block;
1090 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1091 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1092 struct ir3_instruction *sam, *lod;
1093 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1094
1095 lod = create_immed(b, 0);
1096 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
1097 samp_tex, lod, NULL);
1098
1099 /* Array size actually ends up in .w rather than .z. This doesn't
1100 * matter for miplevel 0, but for higher mips the value in z is
1101 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1102 * returned, which means that we have to add 1 to it for arrays for
1103 * a3xx.
1104 *
1105 * Note use a temporary dst and then copy, since the size of the dst
1106 * array that is passed in is based on nir's understanding of the
1107 * result size, not the hardware's
1108 */
1109 struct ir3_instruction *tmp[4];
1110
1111 ir3_split_dest(b, tmp, sam, 0, 4);
1112
1113 /* get_size instruction returns size in bytes instead of texels
1114 * for imageBuffer, so we need to divide it by the pixel size
1115 * of the image format.
1116 *
1117 * TODO: This is at least true on a5xx. Check other gens.
1118 */
1119 enum glsl_sampler_dim dim =
1120 glsl_get_sampler_dim(glsl_without_array(var->type));
1121 if (dim == GLSL_SAMPLER_DIM_BUF) {
1122 /* Since all the possible values the divisor can take are
1123 * power-of-two (4, 8, or 16), the division is implemented
1124 * as a shift-right.
1125 * During shader setup, the log2 of the image format's
1126 * bytes-per-pixel should have been emitted in 2nd slot of
1127 * image_dims. See ir3_shader::emit_image_dims().
1128 */
1129 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1130 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1131 const_state->image_dims.off[var->data.driver_location];
1132 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1133
1134 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1135 }
1136
1137 for (unsigned i = 0; i < ncoords; i++)
1138 dst[i] = tmp[i];
1139
1140 if (flags & IR3_INSTR_A) {
1141 if (ctx->compiler->levels_add_one) {
1142 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1143 } else {
1144 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1145 }
1146 }
1147 }
1148
1149 static void
1150 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1151 {
1152 struct ir3_block *b = ctx->block;
1153 struct ir3_instruction *barrier;
1154
1155 switch (intr->intrinsic) {
1156 case nir_intrinsic_barrier:
1157 barrier = ir3_BAR(b);
1158 barrier->cat7.g = true;
1159 barrier->cat7.l = true;
1160 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1161 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1162 break;
1163 case nir_intrinsic_memory_barrier:
1164 barrier = ir3_FENCE(b);
1165 barrier->cat7.g = true;
1166 barrier->cat7.r = true;
1167 barrier->cat7.w = true;
1168 barrier->cat7.l = true;
1169 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1170 IR3_BARRIER_BUFFER_W;
1171 barrier->barrier_conflict =
1172 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1173 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1174 break;
1175 case nir_intrinsic_memory_barrier_atomic_counter:
1176 case nir_intrinsic_memory_barrier_buffer:
1177 barrier = ir3_FENCE(b);
1178 barrier->cat7.g = true;
1179 barrier->cat7.r = true;
1180 barrier->cat7.w = true;
1181 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1182 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1183 IR3_BARRIER_BUFFER_W;
1184 break;
1185 case nir_intrinsic_memory_barrier_image:
1186 // TODO double check if this should have .g set
1187 barrier = ir3_FENCE(b);
1188 barrier->cat7.g = true;
1189 barrier->cat7.r = true;
1190 barrier->cat7.w = true;
1191 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1192 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1193 IR3_BARRIER_IMAGE_W;
1194 break;
1195 case nir_intrinsic_memory_barrier_shared:
1196 barrier = ir3_FENCE(b);
1197 barrier->cat7.g = true;
1198 barrier->cat7.l = true;
1199 barrier->cat7.r = true;
1200 barrier->cat7.w = true;
1201 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1202 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1203 IR3_BARRIER_SHARED_W;
1204 break;
1205 case nir_intrinsic_group_memory_barrier:
1206 barrier = ir3_FENCE(b);
1207 barrier->cat7.g = true;
1208 barrier->cat7.l = true;
1209 barrier->cat7.r = true;
1210 barrier->cat7.w = true;
1211 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1212 IR3_BARRIER_IMAGE_W |
1213 IR3_BARRIER_BUFFER_W;
1214 barrier->barrier_conflict =
1215 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1216 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1217 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1218 break;
1219 default:
1220 unreachable("boo");
1221 }
1222
1223 /* make sure barrier doesn't get DCE'd */
1224 array_insert(b, b->keeps, barrier);
1225 }
1226
1227 static void add_sysval_input_compmask(struct ir3_context *ctx,
1228 gl_system_value slot, unsigned compmask,
1229 struct ir3_instruction *instr)
1230 {
1231 struct ir3_shader_variant *so = ctx->so;
1232 unsigned n = so->inputs_count++;
1233
1234 assert(instr->opc == OPC_META_INPUT);
1235 instr->input.inidx = n;
1236 instr->input.sysval = slot;
1237
1238 so->inputs[n].sysval = true;
1239 so->inputs[n].slot = slot;
1240 so->inputs[n].compmask = compmask;
1241 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1242 so->total_in++;
1243 }
1244
1245 static struct ir3_instruction *
1246 create_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1247 unsigned compmask)
1248 {
1249 assert(compmask);
1250 struct ir3_instruction *sysval = create_input(ctx, compmask);
1251 add_sysval_input_compmask(ctx, slot, compmask, sysval);
1252 return sysval;
1253 }
1254
1255 static struct ir3_instruction *
1256 get_barycentric_centroid(struct ir3_context *ctx)
1257 {
1258 if (!ctx->ij_centroid) {
1259 struct ir3_instruction *xy[2];
1260 struct ir3_instruction *ij;
1261
1262 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_CENTROID, 0x3);
1263 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1264
1265 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1266 }
1267
1268 return ctx->ij_centroid;
1269 }
1270
1271 static struct ir3_instruction *
1272 get_barycentric_sample(struct ir3_context *ctx)
1273 {
1274 if (!ctx->ij_sample) {
1275 struct ir3_instruction *xy[2];
1276 struct ir3_instruction *ij;
1277
1278 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SAMPLE, 0x3);
1279 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1280
1281 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1282 }
1283
1284 return ctx->ij_sample;
1285 }
1286
1287 static struct ir3_instruction *
1288 get_barycentric_pixel(struct ir3_context *ctx)
1289 {
1290 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1291 * this to create ij_pixel only on demand:
1292 */
1293 return ctx->ij_pixel;
1294 }
1295
1296 static struct ir3_instruction *
1297 get_frag_coord(struct ir3_context *ctx)
1298 {
1299 if (!ctx->frag_coord) {
1300 struct ir3_block *b = ctx->block;
1301 struct ir3_instruction *xyzw[4];
1302 struct ir3_instruction *hw_frag_coord;
1303
1304 hw_frag_coord = create_sysval_input(ctx, SYSTEM_VALUE_FRAG_COORD, 0xf);
1305 ir3_split_dest(ctx->block, xyzw, hw_frag_coord, 0, 4);
1306
1307 /* for frag_coord.xy, we get unsigned values.. we need
1308 * to subtract (integer) 8 and divide by 16 (right-
1309 * shift by 4) then convert to float:
1310 *
1311 * sub.s tmp, src, 8
1312 * shr.b tmp, tmp, 4
1313 * mov.u32f32 dst, tmp
1314 *
1315 */
1316 for (int i = 0; i < 2; i++) {
1317 xyzw[i] = ir3_SUB_S(b, xyzw[i], 0,
1318 create_immed(b, 8), 0);
1319 xyzw[i] = ir3_SHR_B(b, xyzw[i], 0,
1320 create_immed(b, 4), 0);
1321 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1322 }
1323
1324 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1325 ctx->so->frag_coord = true;
1326 }
1327
1328 return ctx->frag_coord;
1329 }
1330
1331 static void
1332 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1333 {
1334 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1335 struct ir3_instruction **dst;
1336 struct ir3_instruction * const *src;
1337 struct ir3_block *b = ctx->block;
1338 int idx, comp;
1339
1340 if (info->has_dest) {
1341 unsigned n = nir_intrinsic_dest_components(intr);
1342 dst = ir3_get_dst(ctx, &intr->dest, n);
1343 } else {
1344 dst = NULL;
1345 }
1346
1347 const unsigned primitive_param = ctx->so->shader->const_state.offsets.primitive_param * 4;
1348 const unsigned primitive_map = ctx->so->shader->const_state.offsets.primitive_map * 4;
1349
1350 switch (intr->intrinsic) {
1351 case nir_intrinsic_load_uniform:
1352 idx = nir_intrinsic_base(intr);
1353 if (nir_src_is_const(intr->src[0])) {
1354 idx += nir_src_as_uint(intr->src[0]);
1355 for (int i = 0; i < intr->num_components; i++) {
1356 dst[i] = create_uniform_typed(b, idx + i,
1357 nir_dest_bit_size(intr->dest) < 32 ? TYPE_F16 : TYPE_F32);
1358 }
1359 } else {
1360 src = ir3_get_src(ctx, &intr->src[0]);
1361 for (int i = 0; i < intr->num_components; i++) {
1362 dst[i] = create_uniform_indirect(b, idx + i,
1363 ir3_get_addr(ctx, src[0], 1));
1364 }
1365 /* NOTE: if relative addressing is used, we set
1366 * constlen in the compiler (to worst-case value)
1367 * since we don't know in the assembler what the max
1368 * addr reg value can be:
1369 */
1370 ctx->so->constlen = MAX2(ctx->so->constlen,
1371 ctx->so->shader->ubo_state.size / 16);
1372 }
1373 break;
1374
1375 case nir_intrinsic_load_vs_primitive_stride_ir3:
1376 dst[0] = create_uniform(b, primitive_param + 0);
1377 break;
1378 case nir_intrinsic_load_vs_vertex_stride_ir3:
1379 dst[0] = create_uniform(b, primitive_param + 1);
1380 break;
1381 case nir_intrinsic_load_hs_patch_stride_ir3:
1382 dst[0] = create_uniform(b, primitive_param + 2);
1383 break;
1384 case nir_intrinsic_load_patch_vertices_in:
1385 dst[0] = create_uniform(b, primitive_param + 3);
1386 break;
1387 case nir_intrinsic_load_tess_param_base_ir3:
1388 dst[0] = create_uniform(b, primitive_param + 4);
1389 dst[1] = create_uniform(b, primitive_param + 5);
1390 break;
1391 case nir_intrinsic_load_tess_factor_base_ir3:
1392 dst[0] = create_uniform(b, primitive_param + 6);
1393 dst[1] = create_uniform(b, primitive_param + 7);
1394 break;
1395
1396 case nir_intrinsic_load_primitive_location_ir3:
1397 idx = nir_intrinsic_driver_location(intr);
1398 dst[0] = create_uniform(b, primitive_map + idx);
1399 break;
1400
1401 case nir_intrinsic_load_gs_header_ir3:
1402 dst[0] = ctx->gs_header;
1403 break;
1404 case nir_intrinsic_load_tcs_header_ir3:
1405 dst[0] = ctx->tcs_header;
1406 break;
1407
1408 case nir_intrinsic_load_primitive_id:
1409 dst[0] = ctx->primitive_id;
1410 break;
1411
1412 case nir_intrinsic_load_tess_coord:
1413 if (!ctx->tess_coord) {
1414 ctx->tess_coord =
1415 create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
1416 }
1417 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1418
1419 /* Unused, but ir3_put_dst() below wants to free something */
1420 dst[2] = create_immed(b, 0);
1421 break;
1422
1423 case nir_intrinsic_end_patch_ir3:
1424 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1425 struct ir3_instruction *end = ir3_ENDPATCH(b);
1426 array_insert(b, b->keeps, end);
1427
1428 end->barrier_class = IR3_BARRIER_EVERYTHING;
1429 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1430 break;
1431
1432 case nir_intrinsic_store_global_ir3: {
1433 struct ir3_instruction *value, *addr, *offset;
1434
1435 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1436 ir3_get_src(ctx, &intr->src[1])[0],
1437 ir3_get_src(ctx, &intr->src[1])[1]
1438 }, 2);
1439
1440 offset = ir3_get_src(ctx, &intr->src[2])[0];
1441
1442 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]),
1443 intr->num_components);
1444
1445 struct ir3_instruction *stg =
1446 ir3_STG_G(ctx->block, addr, 0, value, 0,
1447 create_immed(ctx->block, intr->num_components), 0, offset, 0);
1448 stg->cat6.type = TYPE_U32;
1449 stg->cat6.iim_val = 1;
1450
1451 array_insert(b, b->keeps, stg);
1452
1453 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1454 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1455 break;
1456 }
1457
1458 case nir_intrinsic_load_global_ir3: {
1459 struct ir3_instruction *addr, *offset;
1460
1461 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1462 ir3_get_src(ctx, &intr->src[0])[0],
1463 ir3_get_src(ctx, &intr->src[0])[1]
1464 }, 2);
1465
1466 offset = ir3_get_src(ctx, &intr->src[1])[0];
1467
1468 struct ir3_instruction *load =
1469 ir3_LDG(b, addr, 0, create_immed(ctx->block, intr->num_components),
1470 0, offset, 0);
1471 load->cat6.type = TYPE_U32;
1472 load->regs[0]->wrmask = MASK(intr->num_components);
1473
1474 load->barrier_class = IR3_BARRIER_BUFFER_R;
1475 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1476
1477 ir3_split_dest(b, dst, load, 0, intr->num_components);
1478 break;
1479 }
1480
1481 case nir_intrinsic_load_ubo:
1482 emit_intrinsic_load_ubo(ctx, intr, dst);
1483 break;
1484 case nir_intrinsic_load_frag_coord:
1485 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1486 break;
1487 case nir_intrinsic_load_sample_pos_from_id: {
1488 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1489 * but that doesn't seem necessary.
1490 */
1491 struct ir3_instruction *offset =
1492 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1493 offset->regs[0]->wrmask = 0x3;
1494 offset->cat5.type = TYPE_F32;
1495
1496 ir3_split_dest(b, dst, offset, 0, 2);
1497
1498 break;
1499 }
1500 case nir_intrinsic_load_size_ir3:
1501 if (!ctx->ij_size) {
1502 ctx->ij_size =
1503 create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SIZE, 0x1);
1504 }
1505 dst[0] = ctx->ij_size;
1506 break;
1507 case nir_intrinsic_load_barycentric_centroid:
1508 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1509 break;
1510 case nir_intrinsic_load_barycentric_sample:
1511 if (ctx->so->key.msaa) {
1512 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1513 } else {
1514 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1515 }
1516 break;
1517 case nir_intrinsic_load_barycentric_pixel:
1518 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1519 break;
1520 case nir_intrinsic_load_interpolated_input:
1521 idx = nir_intrinsic_base(intr);
1522 comp = nir_intrinsic_component(intr);
1523 src = ir3_get_src(ctx, &intr->src[0]);
1524 if (nir_src_is_const(intr->src[1])) {
1525 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1526 idx += nir_src_as_uint(intr->src[1]);
1527 for (int i = 0; i < intr->num_components; i++) {
1528 unsigned inloc = idx * 4 + i + comp;
1529 if (ctx->so->inputs[idx].bary &&
1530 !ctx->so->inputs[idx].use_ldlv) {
1531 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1532 } else {
1533 /* for non-varyings use the pre-setup input, since
1534 * that is easier than mapping things back to a
1535 * nir_variable to figure out what it is.
1536 */
1537 dst[i] = ctx->ir->inputs[inloc];
1538 }
1539 }
1540 } else {
1541 ir3_context_error(ctx, "unhandled");
1542 }
1543 break;
1544 case nir_intrinsic_load_input:
1545 idx = nir_intrinsic_base(intr);
1546 comp = nir_intrinsic_component(intr);
1547 if (nir_src_is_const(intr->src[0])) {
1548 idx += nir_src_as_uint(intr->src[0]);
1549 for (int i = 0; i < intr->num_components; i++) {
1550 unsigned n = idx * 4 + i + comp;
1551 dst[i] = ctx->inputs[n];
1552 compile_assert(ctx, ctx->inputs[n]);
1553 }
1554 } else {
1555 src = ir3_get_src(ctx, &intr->src[0]);
1556 struct ir3_instruction *collect =
1557 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ninputs);
1558 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1559 for (int i = 0; i < intr->num_components; i++) {
1560 unsigned n = idx * 4 + i + comp;
1561 dst[i] = create_indirect_load(ctx, ctx->ninputs,
1562 n, addr, collect);
1563 }
1564 }
1565 break;
1566 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1567 * pass and replaced by an ir3-specifc version that adds the
1568 * dword-offset in the last source.
1569 */
1570 case nir_intrinsic_load_ssbo_ir3:
1571 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1572 break;
1573 case nir_intrinsic_store_ssbo_ir3:
1574 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1575 !ctx->s->info.fs.early_fragment_tests)
1576 ctx->so->no_earlyz = true;
1577 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1578 break;
1579 case nir_intrinsic_get_buffer_size:
1580 emit_intrinsic_ssbo_size(ctx, intr, dst);
1581 break;
1582 case nir_intrinsic_ssbo_atomic_add_ir3:
1583 case nir_intrinsic_ssbo_atomic_imin_ir3:
1584 case nir_intrinsic_ssbo_atomic_umin_ir3:
1585 case nir_intrinsic_ssbo_atomic_imax_ir3:
1586 case nir_intrinsic_ssbo_atomic_umax_ir3:
1587 case nir_intrinsic_ssbo_atomic_and_ir3:
1588 case nir_intrinsic_ssbo_atomic_or_ir3:
1589 case nir_intrinsic_ssbo_atomic_xor_ir3:
1590 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1591 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1592 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1593 !ctx->s->info.fs.early_fragment_tests)
1594 ctx->so->no_earlyz = true;
1595 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1596 break;
1597 case nir_intrinsic_load_shared:
1598 emit_intrinsic_load_shared(ctx, intr, dst);
1599 break;
1600 case nir_intrinsic_store_shared:
1601 emit_intrinsic_store_shared(ctx, intr);
1602 break;
1603 case nir_intrinsic_shared_atomic_add:
1604 case nir_intrinsic_shared_atomic_imin:
1605 case nir_intrinsic_shared_atomic_umin:
1606 case nir_intrinsic_shared_atomic_imax:
1607 case nir_intrinsic_shared_atomic_umax:
1608 case nir_intrinsic_shared_atomic_and:
1609 case nir_intrinsic_shared_atomic_or:
1610 case nir_intrinsic_shared_atomic_xor:
1611 case nir_intrinsic_shared_atomic_exchange:
1612 case nir_intrinsic_shared_atomic_comp_swap:
1613 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1614 break;
1615 case nir_intrinsic_image_deref_load:
1616 emit_intrinsic_load_image(ctx, intr, dst);
1617 break;
1618 case nir_intrinsic_image_deref_store:
1619 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1620 !ctx->s->info.fs.early_fragment_tests)
1621 ctx->so->no_earlyz = true;
1622 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1623 break;
1624 case nir_intrinsic_image_deref_size:
1625 emit_intrinsic_image_size(ctx, intr, dst);
1626 break;
1627 case nir_intrinsic_image_deref_atomic_add:
1628 case nir_intrinsic_image_deref_atomic_imin:
1629 case nir_intrinsic_image_deref_atomic_umin:
1630 case nir_intrinsic_image_deref_atomic_imax:
1631 case nir_intrinsic_image_deref_atomic_umax:
1632 case nir_intrinsic_image_deref_atomic_and:
1633 case nir_intrinsic_image_deref_atomic_or:
1634 case nir_intrinsic_image_deref_atomic_xor:
1635 case nir_intrinsic_image_deref_atomic_exchange:
1636 case nir_intrinsic_image_deref_atomic_comp_swap:
1637 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1638 !ctx->s->info.fs.early_fragment_tests)
1639 ctx->so->no_earlyz = true;
1640 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1641 break;
1642 case nir_intrinsic_barrier:
1643 case nir_intrinsic_memory_barrier:
1644 case nir_intrinsic_group_memory_barrier:
1645 case nir_intrinsic_memory_barrier_atomic_counter:
1646 case nir_intrinsic_memory_barrier_buffer:
1647 case nir_intrinsic_memory_barrier_image:
1648 case nir_intrinsic_memory_barrier_shared:
1649 emit_intrinsic_barrier(ctx, intr);
1650 /* note that blk ptr no longer valid, make that obvious: */
1651 b = NULL;
1652 break;
1653 case nir_intrinsic_store_output:
1654 idx = nir_intrinsic_base(intr);
1655 comp = nir_intrinsic_component(intr);
1656 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1657 idx += nir_src_as_uint(intr->src[1]);
1658
1659 src = ir3_get_src(ctx, &intr->src[0]);
1660 for (int i = 0; i < intr->num_components; i++) {
1661 unsigned n = idx * 4 + i + comp;
1662 ctx->outputs[n] = src[i];
1663 }
1664 break;
1665 case nir_intrinsic_load_base_vertex:
1666 case nir_intrinsic_load_first_vertex:
1667 if (!ctx->basevertex) {
1668 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1669 }
1670 dst[0] = ctx->basevertex;
1671 break;
1672 case nir_intrinsic_load_vertex_id_zero_base:
1673 case nir_intrinsic_load_vertex_id:
1674 if (!ctx->vertex_id) {
1675 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1676 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1677 ctx->vertex_id = create_sysval_input(ctx, sv, 0x1);
1678 }
1679 dst[0] = ctx->vertex_id;
1680 break;
1681 case nir_intrinsic_load_instance_id:
1682 if (!ctx->instance_id) {
1683 ctx->instance_id = create_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 0x1);
1684 }
1685 dst[0] = ctx->instance_id;
1686 break;
1687 case nir_intrinsic_load_sample_id:
1688 ctx->so->per_samp = true;
1689 /* fall-thru */
1690 case nir_intrinsic_load_sample_id_no_per_sample:
1691 if (!ctx->samp_id) {
1692 ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1);
1693 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1694 }
1695 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1696 break;
1697 case nir_intrinsic_load_sample_mask_in:
1698 if (!ctx->samp_mask_in) {
1699 ctx->samp_mask_in = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
1700 }
1701 dst[0] = ctx->samp_mask_in;
1702 break;
1703 case nir_intrinsic_load_user_clip_plane:
1704 idx = nir_intrinsic_ucp_id(intr);
1705 for (int i = 0; i < intr->num_components; i++) {
1706 unsigned n = idx * 4 + i;
1707 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1708 }
1709 break;
1710 case nir_intrinsic_load_front_face:
1711 if (!ctx->frag_face) {
1712 ctx->so->frag_face = true;
1713 ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1);
1714 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1715 }
1716 /* for fragface, we get -1 for back and 0 for front. However this is
1717 * the inverse of what nir expects (where ~0 is true).
1718 */
1719 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1720 dst[0] = ir3_NOT_B(b, dst[0], 0);
1721 break;
1722 case nir_intrinsic_load_local_invocation_id:
1723 if (!ctx->local_invocation_id) {
1724 ctx->local_invocation_id =
1725 create_sysval_input(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 0x7);
1726 }
1727 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1728 break;
1729 case nir_intrinsic_load_work_group_id:
1730 if (!ctx->work_group_id) {
1731 ctx->work_group_id =
1732 create_sysval_input(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 0x7);
1733 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1734 }
1735 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1736 break;
1737 case nir_intrinsic_load_num_work_groups:
1738 for (int i = 0; i < intr->num_components; i++) {
1739 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1740 }
1741 break;
1742 case nir_intrinsic_load_local_group_size:
1743 for (int i = 0; i < intr->num_components; i++) {
1744 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1745 }
1746 break;
1747 case nir_intrinsic_discard_if:
1748 case nir_intrinsic_discard: {
1749 struct ir3_instruction *cond, *kill;
1750
1751 if (intr->intrinsic == nir_intrinsic_discard_if) {
1752 /* conditional discard: */
1753 src = ir3_get_src(ctx, &intr->src[0]);
1754 cond = ir3_b2n(b, src[0]);
1755 } else {
1756 /* unconditional discard: */
1757 cond = create_immed(b, 1);
1758 }
1759
1760 /* NOTE: only cmps.*.* can write p0.x: */
1761 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1762 cond->cat2.condition = IR3_COND_NE;
1763
1764 /* condition always goes in predicate register: */
1765 cond->regs[0]->num = regid(REG_P0, 0);
1766 cond->regs[0]->flags &= ~IR3_REG_SSA;
1767
1768 kill = ir3_KILL(b, cond, 0);
1769 array_insert(ctx->ir, ctx->ir->predicates, kill);
1770
1771 array_insert(b, b->keeps, kill);
1772 ctx->so->no_earlyz = true;
1773
1774 break;
1775 }
1776
1777 case nir_intrinsic_cond_end_ir3: {
1778 struct ir3_instruction *cond, *kill;
1779
1780 src = ir3_get_src(ctx, &intr->src[0]);
1781 cond = ir3_b2n(b, src[0]);
1782
1783 /* NOTE: only cmps.*.* can write p0.x: */
1784 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1785 cond->cat2.condition = IR3_COND_NE;
1786
1787 /* condition always goes in predicate register: */
1788 cond->regs[0]->num = regid(REG_P0, 0);
1789
1790 kill = ir3_CONDEND(b, cond, 0);
1791
1792 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1793 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1794
1795 array_insert(ctx->ir, ctx->ir->predicates, kill);
1796 array_insert(b, b->keeps, kill);
1797 break;
1798 }
1799
1800 case nir_intrinsic_load_shared_ir3:
1801 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1802 break;
1803 case nir_intrinsic_store_shared_ir3:
1804 emit_intrinsic_store_shared_ir3(ctx, intr);
1805 break;
1806 default:
1807 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1808 nir_intrinsic_infos[intr->intrinsic].name);
1809 break;
1810 }
1811
1812 if (info->has_dest)
1813 ir3_put_dst(ctx, &intr->dest);
1814 }
1815
1816 static void
1817 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1818 {
1819 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1820 instr->def.num_components);
1821
1822 if (instr->def.bit_size < 32) {
1823 for (int i = 0; i < instr->def.num_components; i++)
1824 dst[i] = create_immed_typed(ctx->block,
1825 instr->value[i].u16,
1826 TYPE_U16);
1827 } else {
1828 for (int i = 0; i < instr->def.num_components; i++)
1829 dst[i] = create_immed_typed(ctx->block,
1830 instr->value[i].u32,
1831 TYPE_U32);
1832 }
1833
1834 }
1835
1836 static void
1837 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1838 {
1839 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1840 undef->def.num_components);
1841 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1842
1843 /* backend doesn't want undefined instructions, so just plug
1844 * in 0.0..
1845 */
1846 for (int i = 0; i < undef->def.num_components; i++)
1847 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1848 }
1849
1850 /*
1851 * texture fetch/sample instructions:
1852 */
1853
1854 static void
1855 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1856 {
1857 unsigned coords, flags = 0;
1858
1859 /* note: would use tex->coord_components.. except txs.. also,
1860 * since array index goes after shadow ref, we don't want to
1861 * count it:
1862 */
1863 switch (tex->sampler_dim) {
1864 case GLSL_SAMPLER_DIM_1D:
1865 case GLSL_SAMPLER_DIM_BUF:
1866 coords = 1;
1867 break;
1868 case GLSL_SAMPLER_DIM_2D:
1869 case GLSL_SAMPLER_DIM_RECT:
1870 case GLSL_SAMPLER_DIM_EXTERNAL:
1871 case GLSL_SAMPLER_DIM_MS:
1872 coords = 2;
1873 break;
1874 case GLSL_SAMPLER_DIM_3D:
1875 case GLSL_SAMPLER_DIM_CUBE:
1876 coords = 3;
1877 flags |= IR3_INSTR_3D;
1878 break;
1879 default:
1880 unreachable("bad sampler_dim");
1881 }
1882
1883 if (tex->is_shadow && tex->op != nir_texop_lod)
1884 flags |= IR3_INSTR_S;
1885
1886 if (tex->is_array && tex->op != nir_texop_lod)
1887 flags |= IR3_INSTR_A;
1888
1889 *flagsp = flags;
1890 *coordsp = coords;
1891 }
1892
1893 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1894 * or immediate (in which case it will get lowered later to a non .s2en
1895 * version of the tex instruction which encode tex/samp as immediates:
1896 */
1897 static struct ir3_instruction *
1898 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1899 {
1900 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1901 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1902 struct ir3_instruction *texture, *sampler;
1903
1904 if (texture_idx >= 0) {
1905 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1906 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1907 } else {
1908 /* TODO what to do for dynamic case? I guess we only need the
1909 * max index for astc srgb workaround so maybe not a problem
1910 * to worry about if we don't enable indirect samplers for
1911 * a4xx?
1912 */
1913 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1914 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1915 }
1916
1917 if (sampler_idx >= 0) {
1918 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1919 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1920 } else {
1921 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1922 }
1923
1924 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1925 sampler,
1926 texture,
1927 }, 2);
1928 }
1929
1930 static void
1931 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1932 {
1933 struct ir3_block *b = ctx->block;
1934 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1935 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1936 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1937 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1938 unsigned i, coords, flags, ncomp;
1939 unsigned nsrc0 = 0, nsrc1 = 0;
1940 type_t type;
1941 opc_t opc = 0;
1942
1943 ncomp = nir_dest_num_components(tex->dest);
1944
1945 coord = off = ddx = ddy = NULL;
1946 lod = proj = compare = sample_index = NULL;
1947
1948 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1949
1950 for (unsigned i = 0; i < tex->num_srcs; i++) {
1951 switch (tex->src[i].src_type) {
1952 case nir_tex_src_coord:
1953 coord = ir3_get_src(ctx, &tex->src[i].src);
1954 break;
1955 case nir_tex_src_bias:
1956 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1957 has_bias = true;
1958 break;
1959 case nir_tex_src_lod:
1960 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1961 has_lod = true;
1962 break;
1963 case nir_tex_src_comparator: /* shadow comparator */
1964 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1965 break;
1966 case nir_tex_src_projector:
1967 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1968 has_proj = true;
1969 break;
1970 case nir_tex_src_offset:
1971 off = ir3_get_src(ctx, &tex->src[i].src);
1972 has_off = true;
1973 break;
1974 case nir_tex_src_ddx:
1975 ddx = ir3_get_src(ctx, &tex->src[i].src);
1976 break;
1977 case nir_tex_src_ddy:
1978 ddy = ir3_get_src(ctx, &tex->src[i].src);
1979 break;
1980 case nir_tex_src_ms_index:
1981 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
1982 break;
1983 case nir_tex_src_texture_offset:
1984 case nir_tex_src_sampler_offset:
1985 /* handled in get_tex_samp_src() */
1986 break;
1987 default:
1988 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
1989 tex->src[i].src_type);
1990 return;
1991 }
1992 }
1993
1994 switch (tex->op) {
1995 case nir_texop_tex_prefetch:
1996 compile_assert(ctx, !has_bias);
1997 compile_assert(ctx, !has_lod);
1998 compile_assert(ctx, !compare);
1999 compile_assert(ctx, !has_proj);
2000 compile_assert(ctx, !has_off);
2001 compile_assert(ctx, !ddx);
2002 compile_assert(ctx, !ddy);
2003 compile_assert(ctx, !sample_index);
2004 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
2005 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
2006
2007 if (ctx->so->num_sampler_prefetch < IR3_MAX_SAMPLER_PREFETCH) {
2008 opc = OPC_META_TEX_PREFETCH;
2009 ctx->so->num_sampler_prefetch++;
2010 break;
2011 }
2012 /* fallthru */
2013 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
2014 case nir_texop_txb: opc = OPC_SAMB; break;
2015 case nir_texop_txl: opc = OPC_SAML; break;
2016 case nir_texop_txd: opc = OPC_SAMGQ; break;
2017 case nir_texop_txf: opc = OPC_ISAML; break;
2018 case nir_texop_lod: opc = OPC_GETLOD; break;
2019 case nir_texop_tg4:
2020 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2021 * what blob does, seems gather is broken?), and a3xx did
2022 * not support it (but probably could also emulate).
2023 */
2024 switch (tex->component) {
2025 case 0: opc = OPC_GATHER4R; break;
2026 case 1: opc = OPC_GATHER4G; break;
2027 case 2: opc = OPC_GATHER4B; break;
2028 case 3: opc = OPC_GATHER4A; break;
2029 }
2030 break;
2031 case nir_texop_txf_ms_fb:
2032 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2033 default:
2034 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2035 return;
2036 }
2037
2038 tex_info(tex, &flags, &coords);
2039
2040 /*
2041 * lay out the first argument in the proper order:
2042 * - actual coordinates first
2043 * - shadow reference
2044 * - array index
2045 * - projection w
2046 * - starting at offset 4, dpdx.xy, dpdy.xy
2047 *
2048 * bias/lod go into the second arg
2049 */
2050
2051 /* insert tex coords: */
2052 for (i = 0; i < coords; i++)
2053 src0[i] = coord[i];
2054
2055 nsrc0 = i;
2056
2057 /* scale up integer coords for TXF based on the LOD */
2058 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2059 assert(has_lod);
2060 for (i = 0; i < coords; i++)
2061 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2062 }
2063
2064 if (coords == 1) {
2065 /* hw doesn't do 1d, so we treat it as 2d with
2066 * height of 1, and patch up the y coord.
2067 */
2068 if (is_isam(opc)) {
2069 src0[nsrc0++] = create_immed(b, 0);
2070 } else {
2071 src0[nsrc0++] = create_immed(b, fui(0.5));
2072 }
2073 }
2074
2075 if (tex->is_shadow && tex->op != nir_texop_lod)
2076 src0[nsrc0++] = compare;
2077
2078 if (tex->is_array && tex->op != nir_texop_lod) {
2079 struct ir3_instruction *idx = coord[coords];
2080
2081 /* the array coord for cube arrays needs 0.5 added to it */
2082 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2083 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2084
2085 src0[nsrc0++] = idx;
2086 }
2087
2088 if (has_proj) {
2089 src0[nsrc0++] = proj;
2090 flags |= IR3_INSTR_P;
2091 }
2092
2093 /* pad to 4, then ddx/ddy: */
2094 if (tex->op == nir_texop_txd) {
2095 while (nsrc0 < 4)
2096 src0[nsrc0++] = create_immed(b, fui(0.0));
2097 for (i = 0; i < coords; i++)
2098 src0[nsrc0++] = ddx[i];
2099 if (coords < 2)
2100 src0[nsrc0++] = create_immed(b, fui(0.0));
2101 for (i = 0; i < coords; i++)
2102 src0[nsrc0++] = ddy[i];
2103 if (coords < 2)
2104 src0[nsrc0++] = create_immed(b, fui(0.0));
2105 }
2106
2107 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2108 * with scaled x coord according to requested sample:
2109 */
2110 if (opc == OPC_ISAMM) {
2111 if (ctx->compiler->txf_ms_with_isaml) {
2112 /* the samples are laid out in x dimension as
2113 * 0 1 2 3
2114 * x_ms = (x << ms) + sample_index;
2115 */
2116 struct ir3_instruction *ms;
2117 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2118
2119 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2120 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2121
2122 opc = OPC_ISAML;
2123 } else {
2124 src0[nsrc0++] = sample_index;
2125 }
2126 }
2127
2128 /*
2129 * second argument (if applicable):
2130 * - offsets
2131 * - lod
2132 * - bias
2133 */
2134 if (has_off | has_lod | has_bias) {
2135 if (has_off) {
2136 unsigned off_coords = coords;
2137 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2138 off_coords--;
2139 for (i = 0; i < off_coords; i++)
2140 src1[nsrc1++] = off[i];
2141 if (off_coords < 2)
2142 src1[nsrc1++] = create_immed(b, fui(0.0));
2143 flags |= IR3_INSTR_O;
2144 }
2145
2146 if (has_lod | has_bias)
2147 src1[nsrc1++] = lod;
2148 }
2149
2150 switch (tex->dest_type) {
2151 case nir_type_invalid:
2152 case nir_type_float:
2153 type = TYPE_F32;
2154 break;
2155 case nir_type_int:
2156 type = TYPE_S32;
2157 break;
2158 case nir_type_uint:
2159 case nir_type_bool:
2160 type = TYPE_U32;
2161 break;
2162 default:
2163 unreachable("bad dest_type");
2164 }
2165
2166 if (opc == OPC_GETLOD)
2167 type = TYPE_S32;
2168
2169 struct ir3_instruction *samp_tex;
2170
2171 if (tex->op == nir_texop_txf_ms_fb) {
2172 /* only expect a single txf_ms_fb per shader: */
2173 compile_assert(ctx, !ctx->so->fb_read);
2174 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2175
2176 ctx->so->fb_read = true;
2177 samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2178 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2179 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2180 }, 2);
2181
2182 ctx->so->num_samp++;
2183 } else {
2184 samp_tex = get_tex_samp_tex_src(ctx, tex);
2185 }
2186
2187 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2188 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2189
2190 if (opc == OPC_META_TEX_PREFETCH) {
2191 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2192
2193 compile_assert(ctx, tex->src[idx].src.is_ssa);
2194
2195 sam = ir3_META_TEX_PREFETCH(b);
2196 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2197 sam->prefetch.input_offset =
2198 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2199 sam->prefetch.tex = tex->texture_index;
2200 sam->prefetch.samp = tex->sampler_index;
2201 } else {
2202 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
2203 samp_tex, col0, col1);
2204 }
2205
2206 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2207 assert(opc != OPC_META_TEX_PREFETCH);
2208
2209 /* only need first 3 components: */
2210 sam->regs[0]->wrmask = 0x7;
2211 ir3_split_dest(b, dst, sam, 0, 3);
2212
2213 /* we need to sample the alpha separately with a non-ASTC
2214 * texture state:
2215 */
2216 sam = ir3_SAM(b, opc, type, 0b1000, flags,
2217 samp_tex, col0, col1);
2218
2219 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2220
2221 /* fixup .w component: */
2222 ir3_split_dest(b, &dst[3], sam, 3, 1);
2223 } else {
2224 /* normal (non-workaround) case: */
2225 ir3_split_dest(b, dst, sam, 0, ncomp);
2226 }
2227
2228 /* GETLOD returns results in 4.8 fixed point */
2229 if (opc == OPC_GETLOD) {
2230 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2231
2232 compile_assert(ctx, tex->dest_type == nir_type_float);
2233 for (i = 0; i < 2; i++) {
2234 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2235 factor, 0);
2236 }
2237 }
2238
2239 ir3_put_dst(ctx, &tex->dest);
2240 }
2241
2242 static void
2243 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2244 {
2245 struct ir3_block *b = ctx->block;
2246 struct ir3_instruction **dst, *sam;
2247
2248 dst = ir3_get_dst(ctx, &tex->dest, 1);
2249
2250 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, 1 << idx, 0,
2251 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
2252
2253 /* even though there is only one component, since it ends
2254 * up in .y/.z/.w rather than .x, we need a split_dest()
2255 */
2256 if (idx)
2257 ir3_split_dest(b, dst, sam, 0, idx + 1);
2258
2259 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2260 * the value in TEX_CONST_0 is zero-based.
2261 */
2262 if (ctx->compiler->levels_add_one)
2263 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2264
2265 ir3_put_dst(ctx, &tex->dest);
2266 }
2267
2268 static void
2269 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2270 {
2271 struct ir3_block *b = ctx->block;
2272 struct ir3_instruction **dst, *sam;
2273 struct ir3_instruction *lod;
2274 unsigned flags, coords;
2275
2276 tex_info(tex, &flags, &coords);
2277
2278 /* Actually we want the number of dimensions, not coordinates. This
2279 * distinction only matters for cubes.
2280 */
2281 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2282 coords = 2;
2283
2284 dst = ir3_get_dst(ctx, &tex->dest, 4);
2285
2286 compile_assert(ctx, tex->num_srcs == 1);
2287 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2288
2289 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2290
2291 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
2292 get_tex_samp_tex_src(ctx, tex), lod, NULL);
2293
2294 ir3_split_dest(b, dst, sam, 0, 4);
2295
2296 /* Array size actually ends up in .w rather than .z. This doesn't
2297 * matter for miplevel 0, but for higher mips the value in z is
2298 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2299 * returned, which means that we have to add 1 to it for arrays.
2300 */
2301 if (tex->is_array) {
2302 if (ctx->compiler->levels_add_one) {
2303 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2304 } else {
2305 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2306 }
2307 }
2308
2309 ir3_put_dst(ctx, &tex->dest);
2310 }
2311
2312 static void
2313 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2314 {
2315 switch (jump->type) {
2316 case nir_jump_break:
2317 case nir_jump_continue:
2318 case nir_jump_return:
2319 /* I *think* we can simply just ignore this, and use the
2320 * successor block link to figure out where we need to
2321 * jump to for break/continue
2322 */
2323 break;
2324 default:
2325 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2326 break;
2327 }
2328 }
2329
2330 static void
2331 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2332 {
2333 switch (instr->type) {
2334 case nir_instr_type_alu:
2335 emit_alu(ctx, nir_instr_as_alu(instr));
2336 break;
2337 case nir_instr_type_deref:
2338 /* ignored, handled as part of the intrinsic they are src to */
2339 break;
2340 case nir_instr_type_intrinsic:
2341 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2342 break;
2343 case nir_instr_type_load_const:
2344 emit_load_const(ctx, nir_instr_as_load_const(instr));
2345 break;
2346 case nir_instr_type_ssa_undef:
2347 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2348 break;
2349 case nir_instr_type_tex: {
2350 nir_tex_instr *tex = nir_instr_as_tex(instr);
2351 /* couple tex instructions get special-cased:
2352 */
2353 switch (tex->op) {
2354 case nir_texop_txs:
2355 emit_tex_txs(ctx, tex);
2356 break;
2357 case nir_texop_query_levels:
2358 emit_tex_info(ctx, tex, 2);
2359 break;
2360 case nir_texop_texture_samples:
2361 emit_tex_info(ctx, tex, 3);
2362 break;
2363 default:
2364 emit_tex(ctx, tex);
2365 break;
2366 }
2367 break;
2368 }
2369 case nir_instr_type_jump:
2370 emit_jump(ctx, nir_instr_as_jump(instr));
2371 break;
2372 case nir_instr_type_phi:
2373 /* we have converted phi webs to regs in NIR by now */
2374 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2375 break;
2376 case nir_instr_type_call:
2377 case nir_instr_type_parallel_copy:
2378 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2379 break;
2380 }
2381 }
2382
2383 static struct ir3_block *
2384 get_block(struct ir3_context *ctx, const nir_block *nblock)
2385 {
2386 struct ir3_block *block;
2387 struct hash_entry *hentry;
2388
2389 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2390 if (hentry)
2391 return hentry->data;
2392
2393 block = ir3_block_create(ctx->ir);
2394 block->nblock = nblock;
2395 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2396
2397 block->predecessors = _mesa_pointer_set_create(block);
2398 set_foreach(nblock->predecessors, sentry) {
2399 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2400 }
2401
2402 return block;
2403 }
2404
2405 static void
2406 emit_block(struct ir3_context *ctx, nir_block *nblock)
2407 {
2408 struct ir3_block *block = get_block(ctx, nblock);
2409
2410 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2411 if (nblock->successors[i]) {
2412 block->successors[i] =
2413 get_block(ctx, nblock->successors[i]);
2414 }
2415 }
2416
2417 ctx->block = block;
2418 list_addtail(&block->node, &ctx->ir->block_list);
2419
2420 /* re-emit addr register in each block if needed: */
2421 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2422 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2423 ctx->addr_ht[i] = NULL;
2424 }
2425
2426 nir_foreach_instr(instr, nblock) {
2427 ctx->cur_instr = instr;
2428 emit_instr(ctx, instr);
2429 ctx->cur_instr = NULL;
2430 if (ctx->error)
2431 return;
2432 }
2433 }
2434
2435 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2436
2437 static void
2438 emit_if(struct ir3_context *ctx, nir_if *nif)
2439 {
2440 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2441
2442 ctx->block->condition =
2443 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2444
2445 emit_cf_list(ctx, &nif->then_list);
2446 emit_cf_list(ctx, &nif->else_list);
2447 }
2448
2449 static void
2450 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2451 {
2452 emit_cf_list(ctx, &nloop->body);
2453 ctx->so->loops++;
2454 }
2455
2456 static void
2457 stack_push(struct ir3_context *ctx)
2458 {
2459 ctx->stack++;
2460 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2461 }
2462
2463 static void
2464 stack_pop(struct ir3_context *ctx)
2465 {
2466 compile_assert(ctx, ctx->stack > 0);
2467 ctx->stack--;
2468 }
2469
2470 static void
2471 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2472 {
2473 foreach_list_typed(nir_cf_node, node, node, list) {
2474 switch (node->type) {
2475 case nir_cf_node_block:
2476 emit_block(ctx, nir_cf_node_as_block(node));
2477 break;
2478 case nir_cf_node_if:
2479 stack_push(ctx);
2480 emit_if(ctx, nir_cf_node_as_if(node));
2481 stack_pop(ctx);
2482 break;
2483 case nir_cf_node_loop:
2484 stack_push(ctx);
2485 emit_loop(ctx, nir_cf_node_as_loop(node));
2486 stack_pop(ctx);
2487 break;
2488 case nir_cf_node_function:
2489 ir3_context_error(ctx, "TODO\n");
2490 break;
2491 }
2492 }
2493 }
2494
2495 /* emit stream-out code. At this point, the current block is the original
2496 * (nir) end block, and nir ensures that all flow control paths terminate
2497 * into the end block. We re-purpose the original end block to generate
2498 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2499 * block holding stream-out write instructions, followed by the new end
2500 * block:
2501 *
2502 * blockOrigEnd {
2503 * p0.x = (vtxcnt < maxvtxcnt)
2504 * // succs: blockStreamOut, blockNewEnd
2505 * }
2506 * blockStreamOut {
2507 * ... stream-out instructions ...
2508 * // succs: blockNewEnd
2509 * }
2510 * blockNewEnd {
2511 * }
2512 */
2513 static void
2514 emit_stream_out(struct ir3_context *ctx)
2515 {
2516 struct ir3 *ir = ctx->ir;
2517 struct ir3_stream_output_info *strmout =
2518 &ctx->so->shader->stream_output;
2519 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2520 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2521 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2522
2523 /* create vtxcnt input in input block at top of shader,
2524 * so that it is seen as live over the entire duration
2525 * of the shader:
2526 */
2527 vtxcnt = create_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, 0x1);
2528 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2529
2530 /* at this point, we are at the original 'end' block,
2531 * re-purpose this block to stream-out condition, then
2532 * append stream-out block and new-end block
2533 */
2534 orig_end_block = ctx->block;
2535
2536 // TODO these blocks need to update predecessors..
2537 // maybe w/ store_global intrinsic, we could do this
2538 // stuff in nir->nir pass
2539
2540 stream_out_block = ir3_block_create(ir);
2541 list_addtail(&stream_out_block->node, &ir->block_list);
2542
2543 new_end_block = ir3_block_create(ir);
2544 list_addtail(&new_end_block->node, &ir->block_list);
2545
2546 orig_end_block->successors[0] = stream_out_block;
2547 orig_end_block->successors[1] = new_end_block;
2548 stream_out_block->successors[0] = new_end_block;
2549
2550 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2551 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2552 cond->regs[0]->num = regid(REG_P0, 0);
2553 cond->regs[0]->flags &= ~IR3_REG_SSA;
2554 cond->cat2.condition = IR3_COND_LT;
2555
2556 /* condition goes on previous block to the conditional,
2557 * since it is used to pick which of the two successor
2558 * paths to take:
2559 */
2560 orig_end_block->condition = cond;
2561
2562 /* switch to stream_out_block to generate the stream-out
2563 * instructions:
2564 */
2565 ctx->block = stream_out_block;
2566
2567 /* Calculate base addresses based on vtxcnt. Instructions
2568 * generated for bases not used in following loop will be
2569 * stripped out in the backend.
2570 */
2571 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2572 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2573 unsigned stride = strmout->stride[i];
2574 struct ir3_instruction *base, *off;
2575
2576 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2577
2578 /* 24-bit should be enough: */
2579 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2580 create_immed(ctx->block, stride * 4), 0);
2581
2582 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2583 }
2584
2585 /* Generate the per-output store instructions: */
2586 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2587 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2588 unsigned c = j + strmout->output[i].start_component;
2589 struct ir3_instruction *base, *out, *stg;
2590
2591 base = bases[strmout->output[i].output_buffer];
2592 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2593
2594 stg = ir3_STG(ctx->block, base, 0, out, 0,
2595 create_immed(ctx->block, 1), 0);
2596 stg->cat6.type = TYPE_U32;
2597 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2598
2599 array_insert(ctx->block, ctx->block->keeps, stg);
2600 }
2601 }
2602
2603 /* and finally switch to the new_end_block: */
2604 ctx->block = new_end_block;
2605 }
2606
2607 static void
2608 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2609 {
2610 nir_metadata_require(impl, nir_metadata_block_index);
2611
2612 compile_assert(ctx, ctx->stack == 0);
2613
2614 emit_cf_list(ctx, &impl->body);
2615 emit_block(ctx, impl->end_block);
2616
2617 compile_assert(ctx, ctx->stack == 0);
2618
2619 /* at this point, we should have a single empty block,
2620 * into which we emit the 'end' instruction.
2621 */
2622 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2623
2624 /* If stream-out (aka transform-feedback) enabled, emit the
2625 * stream-out instructions, followed by a new empty block (into
2626 * which the 'end' instruction lands).
2627 *
2628 * NOTE: it is done in this order, rather than inserting before
2629 * we emit end_block, because NIR guarantees that all blocks
2630 * flow into end_block, and that end_block has no successors.
2631 * So by re-purposing end_block as the first block of stream-
2632 * out, we guarantee that all exit paths flow into the stream-
2633 * out instructions.
2634 */
2635 if ((ctx->compiler->gpu_id < 500) &&
2636 (ctx->so->shader->stream_output.num_outputs > 0) &&
2637 !ctx->so->binning_pass) {
2638 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2639 emit_stream_out(ctx);
2640 }
2641
2642 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2643 * NOP and has an epilogue that writes the VS outputs to local storage, to
2644 * be read by the HS. Then it resets execution mask (chmask) and chains
2645 * to the next shader (chsh).
2646 */
2647 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2648 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2649 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2650 struct ir3_instruction *chmask =
2651 ir3_CHMASK(ctx->block);
2652 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2653 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2654
2655 struct ir3_instruction *chsh =
2656 ir3_CHSH(ctx->block);
2657 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2658 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2659 } else {
2660 ir3_END(ctx->block);
2661 }
2662 }
2663
2664 static void
2665 setup_input(struct ir3_context *ctx, nir_variable *in)
2666 {
2667 struct ir3_shader_variant *so = ctx->so;
2668 unsigned ncomp = glsl_get_components(in->type);
2669 unsigned n = in->data.driver_location;
2670 unsigned frac = in->data.location_frac;
2671 unsigned slot = in->data.location;
2672
2673 /* Inputs are loaded using ldlw or ldg for these stages. */
2674 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2675 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2676 ctx->so->type == MESA_SHADER_GEOMETRY)
2677 return;
2678
2679 /* skip unread inputs, we could end up with (for example), unsplit
2680 * matrix/etc inputs in the case they are not read, so just silently
2681 * skip these.
2682 */
2683 if (ncomp > 4)
2684 return;
2685
2686 so->inputs[n].slot = slot;
2687 so->inputs[n].compmask = (1 << (ncomp + frac)) - 1;
2688 so->inputs_count = MAX2(so->inputs_count, n + 1);
2689 so->inputs[n].interpolate = in->data.interpolation;
2690
2691 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2692
2693 /* if any varyings have 'sample' qualifer, that triggers us
2694 * to run in per-sample mode:
2695 */
2696 so->per_samp |= in->data.sample;
2697
2698 for (int i = 0; i < ncomp; i++) {
2699 struct ir3_instruction *instr = NULL;
2700 unsigned idx = (n * 4) + i + frac;
2701
2702 if (slot == VARYING_SLOT_POS) {
2703 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2704 } else if (slot == VARYING_SLOT_PNTC) {
2705 /* see for example st_nir_fixup_varying_slots().. this is
2706 * maybe a bit mesa/st specific. But we need things to line
2707 * up for this in fdN_program:
2708 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2709 * if (emit->sprite_coord_enable & texmask) {
2710 * ...
2711 * }
2712 */
2713 so->inputs[n].slot = VARYING_SLOT_VAR8;
2714 so->inputs[n].bary = true;
2715 instr = create_frag_input(ctx, false, idx);
2716 } else {
2717 /* detect the special case for front/back colors where
2718 * we need to do flat vs smooth shading depending on
2719 * rast state:
2720 */
2721 if (in->data.interpolation == INTERP_MODE_NONE) {
2722 switch (slot) {
2723 case VARYING_SLOT_COL0:
2724 case VARYING_SLOT_COL1:
2725 case VARYING_SLOT_BFC0:
2726 case VARYING_SLOT_BFC1:
2727 so->inputs[n].rasterflat = true;
2728 break;
2729 default:
2730 break;
2731 }
2732 }
2733
2734 if (ctx->compiler->flat_bypass) {
2735 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2736 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2737 so->inputs[n].use_ldlv = true;
2738 }
2739
2740 so->inputs[n].bary = true;
2741
2742 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2743 }
2744
2745 compile_assert(ctx, idx < ctx->ninputs);
2746
2747 ctx->inputs[idx] = instr;
2748 }
2749 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2750 /* We shouldn't have fractional input for VS input.. that only shows
2751 * up with varying packing
2752 */
2753 assert(frac == 0);
2754
2755 struct ir3_instruction *input = create_input(ctx, (1 << ncomp) - 1);
2756 struct ir3_instruction *components[ncomp];
2757
2758 input->input.inidx = n;
2759
2760 ir3_split_dest(ctx->block, components, input, 0, ncomp);
2761
2762 for (int i = 0; i < ncomp; i++) {
2763 unsigned idx = (n * 4) + i + frac;
2764 compile_assert(ctx, idx < ctx->ninputs);
2765 ctx->inputs[idx] = components[i];
2766 }
2767 } else {
2768 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2769 }
2770
2771 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2772 so->total_in += ncomp;
2773 }
2774 }
2775
2776 /* Initially we assign non-packed inloc's for varyings, as we don't really
2777 * know up-front which components will be unused. After all the compilation
2778 * stages we scan the shader to see which components are actually used, and
2779 * re-pack the inlocs to eliminate unneeded varyings.
2780 */
2781 static void
2782 pack_inlocs(struct ir3_context *ctx)
2783 {
2784 struct ir3_shader_variant *so = ctx->so;
2785 uint8_t used_components[so->inputs_count];
2786
2787 memset(used_components, 0, sizeof(used_components));
2788
2789 /*
2790 * First Step: scan shader to find which bary.f/ldlv remain:
2791 */
2792
2793 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2794 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2795 if (is_input(instr)) {
2796 unsigned inloc = instr->regs[1]->iim_val;
2797 unsigned i = inloc / 4;
2798 unsigned j = inloc % 4;
2799
2800 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
2801 compile_assert(ctx, i < so->inputs_count);
2802
2803 used_components[i] |= 1 << j;
2804 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
2805 for (int n = 0; n < 2; n++) {
2806 unsigned inloc = instr->prefetch.input_offset + n;
2807 unsigned i = inloc / 4;
2808 unsigned j = inloc % 4;
2809
2810 compile_assert(ctx, i < so->inputs_count);
2811
2812 used_components[i] |= 1 << j;
2813 }
2814 }
2815 }
2816 }
2817
2818 /*
2819 * Second Step: reassign varying inloc/slots:
2820 */
2821
2822 unsigned actual_in = 0;
2823 unsigned inloc = 0;
2824
2825 for (unsigned i = 0; i < so->inputs_count; i++) {
2826 unsigned compmask = 0, maxcomp = 0;
2827
2828 so->inputs[i].inloc = inloc;
2829 so->inputs[i].bary = false;
2830
2831 for (unsigned j = 0; j < 4; j++) {
2832 if (!(used_components[i] & (1 << j)))
2833 continue;
2834
2835 compmask |= (1 << j);
2836 actual_in++;
2837 maxcomp = j + 1;
2838
2839 /* at this point, since used_components[i] mask is only
2840 * considering varyings (ie. not sysvals) we know this
2841 * is a varying:
2842 */
2843 so->inputs[i].bary = true;
2844 }
2845
2846 if (so->inputs[i].bary) {
2847 so->varying_in++;
2848 so->inputs[i].compmask = (1 << maxcomp) - 1;
2849 inloc += maxcomp;
2850 }
2851 }
2852
2853 /*
2854 * Third Step: reassign packed inloc's:
2855 */
2856
2857 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2858 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2859 if (is_input(instr)) {
2860 unsigned inloc = instr->regs[1]->iim_val;
2861 unsigned i = inloc / 4;
2862 unsigned j = inloc % 4;
2863
2864 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
2865 }
2866 }
2867 }
2868 }
2869
2870 static void
2871 setup_output(struct ir3_context *ctx, nir_variable *out)
2872 {
2873 struct ir3_shader_variant *so = ctx->so;
2874 unsigned ncomp = glsl_get_components(out->type);
2875 unsigned n = out->data.driver_location;
2876 unsigned frac = out->data.location_frac;
2877 unsigned slot = out->data.location;
2878 unsigned comp = 0;
2879
2880 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2881 switch (slot) {
2882 case FRAG_RESULT_DEPTH:
2883 comp = 2; /* tgsi will write to .z component */
2884 so->writes_pos = true;
2885 break;
2886 case FRAG_RESULT_COLOR:
2887 so->color0_mrt = 1;
2888 break;
2889 case FRAG_RESULT_SAMPLE_MASK:
2890 so->writes_smask = true;
2891 break;
2892 default:
2893 if (slot >= FRAG_RESULT_DATA0)
2894 break;
2895 ir3_context_error(ctx, "unknown FS output name: %s\n",
2896 gl_frag_result_name(slot));
2897 }
2898 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
2899 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2900 ctx->so->type == MESA_SHADER_GEOMETRY) {
2901 switch (slot) {
2902 case VARYING_SLOT_POS:
2903 so->writes_pos = true;
2904 break;
2905 case VARYING_SLOT_PSIZ:
2906 so->writes_psize = true;
2907 break;
2908 case VARYING_SLOT_PRIMITIVE_ID:
2909 case VARYING_SLOT_LAYER:
2910 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
2911 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
2912 /* fall through */
2913 case VARYING_SLOT_COL0:
2914 case VARYING_SLOT_COL1:
2915 case VARYING_SLOT_BFC0:
2916 case VARYING_SLOT_BFC1:
2917 case VARYING_SLOT_FOGC:
2918 case VARYING_SLOT_CLIP_DIST0:
2919 case VARYING_SLOT_CLIP_DIST1:
2920 case VARYING_SLOT_CLIP_VERTEX:
2921 break;
2922 default:
2923 if (slot >= VARYING_SLOT_VAR0)
2924 break;
2925 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2926 break;
2927 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
2928 _mesa_shader_stage_to_string(ctx->so->type),
2929 gl_varying_slot_name(slot));
2930 }
2931 } else if (ctx->so->type == MESA_SHADER_TESS_CTRL) {
2932 /* output lowered to buffer writes. */
2933 return;
2934 } else {
2935 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2936 }
2937
2938 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2939
2940 so->outputs[n].slot = slot;
2941 so->outputs[n].regid = regid(n, comp);
2942 so->outputs_count = MAX2(so->outputs_count, n + 1);
2943
2944 for (int i = 0; i < ncomp; i++) {
2945 unsigned idx = (n * 4) + i + frac;
2946 compile_assert(ctx, idx < ctx->noutputs);
2947 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
2948 }
2949
2950 /* if varying packing doesn't happen, we could end up in a situation
2951 * with "holes" in the output, and since the per-generation code that
2952 * sets up varying linkage registers doesn't expect to have more than
2953 * one varying per vec4 slot, pad the holes.
2954 *
2955 * Note that this should probably generate a performance warning of
2956 * some sort.
2957 */
2958 for (int i = 0; i < frac; i++) {
2959 unsigned idx = (n * 4) + i;
2960 if (!ctx->outputs[idx]) {
2961 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
2962 }
2963 }
2964 }
2965
2966 static int
2967 max_drvloc(struct exec_list *vars)
2968 {
2969 int drvloc = -1;
2970 nir_foreach_variable(var, vars) {
2971 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2972 }
2973 return drvloc;
2974 }
2975
2976 static void
2977 emit_instructions(struct ir3_context *ctx)
2978 {
2979 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
2980
2981 ctx->ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
2982 ctx->noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
2983
2984 ctx->inputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->ninputs);
2985 ctx->outputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->noutputs);
2986
2987 ctx->ir = ir3_create(ctx->compiler, ctx->so->type);
2988
2989 /* Create inputs in first block: */
2990 ctx->block = get_block(ctx, nir_start_block(fxn));
2991 ctx->in_block = ctx->block;
2992 list_addtail(&ctx->block->node, &ctx->ir->block_list);
2993
2994 /* for fragment shader, the vcoord input register is used as the
2995 * base for bary.f varying fetch instrs:
2996 *
2997 * TODO defer creating ctx->ij_pixel and corresponding sysvals
2998 * until emit_intrinsic when we know they are actually needed.
2999 * For now, we defer creating ctx->ij_centroid, etc, since we
3000 * only need ij_pixel for "old style" varying inputs (ie.
3001 * tgsi_to_nir)
3002 */
3003 struct ir3_instruction *vcoord = NULL;
3004 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3005 struct ir3_instruction *xy[2];
3006
3007 vcoord = create_input(ctx, 0x3);
3008 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
3009
3010 ctx->ij_pixel = ir3_create_collect(ctx, xy, 2);
3011 }
3012
3013 /* Setup inputs: */
3014 nir_foreach_variable(var, &ctx->s->inputs) {
3015 setup_input(ctx, var);
3016 }
3017
3018 /* Defer add_sysval_input() stuff until after setup_inputs(),
3019 * because sysvals need to be appended after varyings:
3020 */
3021 if (vcoord) {
3022 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PIXEL,
3023 0x3, vcoord);
3024 }
3025
3026
3027 /* Tesselation shaders always need primitive ID for indexing the
3028 * BO. Geometry shaders don't always need it but when they do it has be
3029 * delivered and unclobbered in the VS. To make things easy, we always
3030 * make room for it in VS/DS.
3031 */
3032 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
3033 bool has_gs = ctx->so->key.has_gs;
3034 switch (ctx->so->type) {
3035 case MESA_SHADER_VERTEX:
3036 if (has_tess) {
3037 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3038 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3039 } else if (has_gs) {
3040 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3041 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3042 }
3043 break;
3044 case MESA_SHADER_TESS_CTRL:
3045 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3046 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3047 break;
3048 case MESA_SHADER_TESS_EVAL:
3049 if (has_gs)
3050 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3051 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3052 break;
3053 case MESA_SHADER_GEOMETRY:
3054 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3055 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3056 break;
3057 default:
3058 break;
3059 }
3060
3061 /* Setup outputs: */
3062 nir_foreach_variable(var, &ctx->s->outputs) {
3063 setup_output(ctx, var);
3064 }
3065
3066 /* Find # of samplers: */
3067 nir_foreach_variable(var, &ctx->s->uniforms) {
3068 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
3069 /* just assume that we'll be reading from images.. if it
3070 * is write-only we don't have to count it, but not sure
3071 * if there is a good way to know?
3072 */
3073 ctx->so->num_samp += glsl_type_get_image_count(var->type);
3074 }
3075
3076 /* NOTE: need to do something more clever when we support >1 fxn */
3077 nir_foreach_register(reg, &fxn->registers) {
3078 ir3_declare_array(ctx, reg);
3079 }
3080 /* And emit the body: */
3081 ctx->impl = fxn;
3082 emit_function(ctx, fxn);
3083 }
3084
3085 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3086 * need to assign the tex state indexes for these after we know the
3087 * max tex index.
3088 */
3089 static void
3090 fixup_astc_srgb(struct ir3_context *ctx)
3091 {
3092 struct ir3_shader_variant *so = ctx->so;
3093 /* indexed by original tex idx, value is newly assigned alpha sampler
3094 * state tex idx. Zero is invalid since there is at least one sampler
3095 * if we get here.
3096 */
3097 unsigned alt_tex_state[16] = {0};
3098 unsigned tex_idx = ctx->max_texture_index + 1;
3099 unsigned idx = 0;
3100
3101 so->astc_srgb.base = tex_idx;
3102
3103 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3104 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3105
3106 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3107
3108 if (alt_tex_state[sam->cat5.tex] == 0) {
3109 /* assign new alternate/alpha tex state slot: */
3110 alt_tex_state[sam->cat5.tex] = tex_idx++;
3111 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3112 so->astc_srgb.count++;
3113 }
3114
3115 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3116 }
3117 }
3118
3119 static void
3120 fixup_binning_pass(struct ir3_context *ctx)
3121 {
3122 struct ir3_shader_variant *so = ctx->so;
3123 struct ir3 *ir = ctx->ir;
3124 unsigned i, j;
3125
3126 /* first pass, remove unused outputs from the IR level outputs: */
3127 for (i = 0, j = 0; i < ir->outputs_count; i++) {
3128 struct ir3_instruction *out = ir->outputs[i];
3129 assert(out->opc == OPC_META_COLLECT);
3130 unsigned outidx = out->collect.outidx;
3131 unsigned slot = so->outputs[outidx].slot;
3132
3133 /* throw away everything but first position/psize */
3134 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3135 ir->outputs[j] = ir->outputs[i];
3136 j++;
3137 }
3138 }
3139 ir->outputs_count = j;
3140
3141 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3142 * table:
3143 */
3144 for (i = 0, j = 0; i < so->outputs_count; i++) {
3145 unsigned slot = so->outputs[i].slot;
3146
3147 /* throw away everything but first position/psize */
3148 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3149 so->outputs[j] = so->outputs[i];
3150
3151 /* fixup outidx to point to new output table entry: */
3152 struct ir3_instruction *out;
3153 foreach_output(out, ir) {
3154 if (out->collect.outidx == i) {
3155 out->collect.outidx = j;
3156 break;
3157 }
3158 }
3159
3160 j++;
3161 }
3162 }
3163 so->outputs_count = j;
3164 }
3165
3166 static void
3167 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3168 {
3169 unsigned idx = 0;
3170
3171 /* Collect sampling instructions eligible for pre-dispatch. */
3172 list_for_each_entry(struct ir3_block, block, &ir->block_list, node) {
3173 list_for_each_entry_safe(struct ir3_instruction, instr,
3174 &block->instr_list, node) {
3175 if (instr->opc == OPC_META_TEX_PREFETCH) {
3176 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3177 struct ir3_sampler_prefetch *fetch =
3178 &ctx->so->sampler_prefetch[idx];
3179 idx++;
3180
3181 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3182 fetch->wrmask = instr->regs[0]->wrmask;
3183 fetch->tex_id = instr->prefetch.tex;
3184 fetch->samp_id = instr->prefetch.samp;
3185 fetch->dst = instr->regs[0]->num;
3186 fetch->src = instr->prefetch.input_offset;
3187
3188 ctx->so->total_in =
3189 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3190
3191 /* Disable half precision until supported. */
3192 fetch->half_precision = 0x0;
3193
3194 /* Remove the prefetch placeholder instruction: */
3195 list_delinit(&instr->node);
3196 }
3197 }
3198 }
3199 }
3200
3201 int
3202 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3203 struct ir3_shader_variant *so)
3204 {
3205 struct ir3_context *ctx;
3206 struct ir3 *ir;
3207 int ret = 0, max_bary;
3208
3209 assert(!so->ir);
3210
3211 ctx = ir3_context_init(compiler, so);
3212 if (!ctx) {
3213 DBG("INIT failed!");
3214 ret = -1;
3215 goto out;
3216 }
3217
3218 emit_instructions(ctx);
3219
3220 if (ctx->error) {
3221 DBG("EMIT failed!");
3222 ret = -1;
3223 goto out;
3224 }
3225
3226 ir = so->ir = ctx->ir;
3227
3228 assert((ctx->noutputs % 4) == 0);
3229
3230 /* Setup IR level outputs, which are "collects" that gather
3231 * the scalar components of outputs.
3232 */
3233 for (unsigned i = 0; i < ctx->noutputs; i += 4) {
3234 unsigned ncomp = 0;
3235 /* figure out the # of components written:
3236 *
3237 * TODO do we need to handle holes, ie. if .x and .z
3238 * components written, but .y component not written?
3239 */
3240 for (unsigned j = 0; j < 4; j++) {
3241 if (!ctx->outputs[i + j])
3242 break;
3243 ncomp++;
3244 }
3245
3246 /* Note that in some stages, like TCS, store_output is
3247 * lowered to memory writes, so no components of the
3248 * are "written" from the PoV of traditional store-
3249 * output instructions:
3250 */
3251 if (!ncomp)
3252 continue;
3253
3254 struct ir3_instruction *out =
3255 ir3_create_collect(ctx, &ctx->outputs[i], ncomp);
3256
3257 int outidx = i / 4;
3258 assert(outidx < so->outputs_count);
3259
3260 /* stash index into so->outputs[] so we can map the
3261 * output back to slot/etc later:
3262 */
3263 out->collect.outidx = outidx;
3264
3265 array_insert(ir, ir->outputs, out);
3266 }
3267
3268 /* Set up the gs header as an output for the vertex shader so it won't
3269 * clobber it for the tess ctrl shader.
3270 *
3271 * TODO this could probably be done more cleanly in a nir pass.
3272 */
3273 if (ctx->so->type == MESA_SHADER_VERTEX ||
3274 (ctx->so->key.has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3275 if (ctx->primitive_id) {
3276 unsigned n = so->outputs_count++;
3277 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3278
3279 struct ir3_instruction *out =
3280 ir3_create_collect(ctx, &ctx->primitive_id, 1);
3281 out->collect.outidx = n;
3282 array_insert(ir, ir->outputs, out);
3283 }
3284
3285 if (ctx->gs_header) {
3286 unsigned n = so->outputs_count++;
3287 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3288 struct ir3_instruction *out =
3289 ir3_create_collect(ctx, &ctx->gs_header, 1);
3290 out->collect.outidx = n;
3291 array_insert(ir, ir->outputs, out);
3292 }
3293
3294 if (ctx->tcs_header) {
3295 unsigned n = so->outputs_count++;
3296 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3297 struct ir3_instruction *out =
3298 ir3_create_collect(ctx, &ctx->tcs_header, 1);
3299 out->collect.outidx = n;
3300 array_insert(ir, ir->outputs, out);
3301 }
3302 }
3303
3304 /* at this point, for binning pass, throw away unneeded outputs: */
3305 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3306 fixup_binning_pass(ctx);
3307
3308 ir3_debug_print(ir, "BEFORE CP");
3309
3310 ir3_cp(ir, so);
3311
3312 /* at this point, for binning pass, throw away unneeded outputs:
3313 * Note that for a6xx and later, we do this after ir3_cp to ensure
3314 * that the uniform/constant layout for BS and VS matches, so that
3315 * we can re-use same VS_CONST state group.
3316 */
3317 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
3318 fixup_binning_pass(ctx);
3319
3320 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3321 * need to make sure not to remove any inputs that are used by
3322 * the nonbinning VS.
3323 */
3324 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3325 so->type == MESA_SHADER_VERTEX) {
3326 for (int i = 0; i < ctx->ninputs; i++) {
3327 struct ir3_instruction *in = ctx->inputs[i];
3328
3329 if (!in)
3330 continue;
3331
3332 unsigned n = i / 4;
3333 unsigned c = i % 4;
3334
3335 debug_assert(n < so->nonbinning->inputs_count);
3336
3337 if (so->nonbinning->inputs[n].sysval)
3338 continue;
3339
3340 /* be sure to keep inputs, even if only used in VS */
3341 if (so->nonbinning->inputs[n].compmask & (1 << c))
3342 array_insert(in->block, in->block->keeps, in);
3343 }
3344 }
3345
3346 ir3_debug_print(ir, "BEFORE GROUPING");
3347
3348 ir3_sched_add_deps(ir);
3349
3350 /* Group left/right neighbors, inserting mov's where needed to
3351 * solve conflicts:
3352 */
3353 ir3_group(ir);
3354
3355 ir3_debug_print(ir, "AFTER GROUPING");
3356
3357 ir3_depth(ir, so);
3358
3359 ir3_debug_print(ir, "AFTER DEPTH");
3360
3361 /* do Sethi–Ullman numbering before scheduling: */
3362 ir3_sun(ir);
3363
3364 ret = ir3_sched(ir);
3365 if (ret) {
3366 DBG("SCHED failed!");
3367 goto out;
3368 }
3369
3370 if (compiler->gpu_id >= 600) {
3371 ir3_a6xx_fixup_atomic_dests(ir, so);
3372 }
3373
3374 ir3_debug_print(ir, "AFTER SCHED");
3375
3376 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3377 * with draw pass VS, so binning and draw pass can both use the
3378 * same VBO state.
3379 *
3380 * Note that VS inputs are expected to be full precision.
3381 */
3382 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3383 (ir->type == MESA_SHADER_VERTEX) &&
3384 so->binning_pass;
3385
3386 if (pre_assign_inputs) {
3387 for (unsigned i = 0; i < ctx->ninputs; i++) {
3388 struct ir3_instruction *instr = ctx->inputs[i];
3389
3390 if (!instr)
3391 continue;
3392
3393 unsigned n = i / 4;
3394 unsigned c = i % 4;
3395 unsigned regid = so->nonbinning->inputs[n].regid + c;
3396
3397 instr->regs[0]->num = regid;
3398 }
3399
3400 ret = ir3_ra(so, ctx->inputs, ctx->ninputs);
3401 } else if (ctx->tcs_header) {
3402 /* We need to have these values in the same registers between VS and TCS
3403 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3404 */
3405
3406 ctx->tcs_header->regs[0]->num = regid(0, 0);
3407 ctx->primitive_id->regs[0]->num = regid(0, 1);
3408 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3409 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3410 } else if (ctx->gs_header) {
3411 /* We need to have these values in the same registers between producer
3412 * (VS or DS) and GS since the producer chains to GS and doesn't get
3413 * the sysvals redelivered.
3414 */
3415
3416 ctx->gs_header->regs[0]->num = regid(0, 0);
3417 ctx->primitive_id->regs[0]->num = regid(0, 1);
3418 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3419 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3420 } else if (so->num_sampler_prefetch) {
3421 assert(so->type == MESA_SHADER_FRAGMENT);
3422 struct ir3_instruction *instr, *precolor[2];
3423 int idx = 0;
3424
3425 foreach_input(instr, ir) {
3426 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PIXEL)
3427 continue;
3428
3429 assert(idx < ARRAY_SIZE(precolor));
3430
3431 precolor[idx] = instr;
3432 instr->regs[0]->num = idx;
3433
3434 idx++;
3435 }
3436 ret = ir3_ra(so, precolor, idx);
3437 } else {
3438 ret = ir3_ra(so, NULL, 0);
3439 }
3440
3441 if (ret) {
3442 DBG("RA failed!");
3443 goto out;
3444 }
3445
3446 ir3_debug_print(ir, "AFTER RA");
3447
3448 if (so->type == MESA_SHADER_FRAGMENT)
3449 pack_inlocs(ctx);
3450
3451 /*
3452 * Fixup inputs/outputs to point to the actual registers assigned:
3453 *
3454 * 1) initialize to r63.x (invalid/unused)
3455 * 2) iterate IR level inputs/outputs and update the variants
3456 * inputs/outputs table based on the assigned registers for
3457 * the remaining inputs/outputs.
3458 */
3459
3460 for (unsigned i = 0; i < so->inputs_count; i++)
3461 so->inputs[i].regid = regid(63, 0);
3462 for (unsigned i = 0; i < so->outputs_count; i++)
3463 so->outputs[i].regid = regid(63, 0);
3464
3465 struct ir3_instruction *out;
3466 foreach_output(out, ir) {
3467 assert(out->opc == OPC_META_COLLECT);
3468 unsigned outidx = out->collect.outidx;
3469
3470 so->outputs[outidx].regid = out->regs[0]->num;
3471 so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF);
3472 }
3473
3474 struct ir3_instruction *in;
3475 foreach_input(in, ir) {
3476 assert(in->opc == OPC_META_INPUT);
3477 unsigned inidx = in->input.inidx;
3478
3479 so->inputs[inidx].regid = in->regs[0]->num;
3480 so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
3481 }
3482
3483 if (ctx->astc_srgb)
3484 fixup_astc_srgb(ctx);
3485
3486 /* We need to do legalize after (for frag shader's) the "bary.f"
3487 * offsets (inloc) have been assigned.
3488 */
3489 ir3_legalize(ir, &so->has_ssbo, &so->need_pixlod, &max_bary);
3490
3491 ir3_debug_print(ir, "AFTER LEGALIZE");
3492
3493 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3494 * know what we might have to wait on when coming in from VS chsh.
3495 */
3496 if (so->type == MESA_SHADER_TESS_CTRL ||
3497 so->type == MESA_SHADER_GEOMETRY ) {
3498 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
3499 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
3500 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3501 break;
3502 }
3503 }
3504 }
3505
3506 so->branchstack = ctx->max_stack;
3507
3508 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3509 if (so->type == MESA_SHADER_FRAGMENT)
3510 so->total_in = max_bary + 1;
3511
3512 so->max_sun = ir->max_sun;
3513
3514 /* Collect sampling instructions eligible for pre-dispatch. */
3515 collect_tex_prefetches(ctx, ir);
3516
3517 out:
3518 if (ret) {
3519 if (so->ir)
3520 ir3_destroy(so->ir);
3521 so->ir = NULL;
3522 }
3523 ir3_context_free(ctx);
3524
3525 return ret;
3526 }