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freedreno/ir3: Handle GL_NONE in get_num_components_for_glformat()
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_shader.h"
35 #include "ir3_nir.h"
36
37 #include "instr-a3xx.h"
38 #include "ir3.h"
39 #include "ir3_context.h"
40
41
42 static struct ir3_instruction *
43 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
44 struct ir3_instruction *address, struct ir3_instruction *collect)
45 {
46 struct ir3_block *block = ctx->block;
47 struct ir3_instruction *mov;
48 struct ir3_register *src;
49
50 mov = ir3_instr_create(block, OPC_MOV);
51 mov->cat1.src_type = TYPE_U32;
52 mov->cat1.dst_type = TYPE_U32;
53 ir3_reg_create(mov, 0, 0);
54 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
55 src->instr = collect;
56 src->size = arrsz;
57 src->array.offset = n;
58
59 ir3_instr_set_address(mov, address);
60
61 return mov;
62 }
63
64 static struct ir3_instruction *
65 create_input_compmask(struct ir3_context *ctx, unsigned n, unsigned compmask)
66 {
67 struct ir3_instruction *in;
68
69 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
70 in->inout.block = ctx->in_block;
71 ir3_reg_create(in, n, 0);
72
73 in->regs[0]->wrmask = compmask;
74
75 return in;
76 }
77
78 static struct ir3_instruction *
79 create_input(struct ir3_context *ctx, unsigned n)
80 {
81 return create_input_compmask(ctx, n, 0x1);
82 }
83
84 static struct ir3_instruction *
85 create_frag_input(struct ir3_context *ctx, bool use_ldlv)
86 {
87 struct ir3_block *block = ctx->block;
88 struct ir3_instruction *instr;
89 /* actual inloc is assigned and fixed up later: */
90 struct ir3_instruction *inloc = create_immed(block, 0);
91
92 if (use_ldlv) {
93 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
94 instr->cat6.type = TYPE_U32;
95 instr->cat6.iim_val = 1;
96 } else {
97 instr = ir3_BARY_F(block, inloc, 0, ctx->frag_vcoord, 0);
98 instr->regs[2]->wrmask = 0x3;
99 }
100
101 return instr;
102 }
103
104 static struct ir3_instruction *
105 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
106 {
107 /* first four vec4 sysval's reserved for UBOs: */
108 /* NOTE: dp is in scalar, but there can be >4 dp components: */
109 unsigned n = ctx->so->constbase.driver_param;
110 unsigned r = regid(n + dp / 4, dp % 4);
111 return create_uniform(ctx->block, r);
112 }
113
114 /*
115 * Adreno uses uint rather than having dedicated bool type,
116 * which (potentially) requires some conversion, in particular
117 * when using output of an bool instr to int input, or visa
118 * versa.
119 *
120 * | Adreno | NIR |
121 * -------+---------+-------+-
122 * true | 1 | ~0 |
123 * false | 0 | 0 |
124 *
125 * To convert from an adreno bool (uint) to nir, use:
126 *
127 * absneg.s dst, (neg)src
128 *
129 * To convert back in the other direction:
130 *
131 * absneg.s dst, (abs)arc
132 *
133 * The CP step can clean up the absneg.s that cancel each other
134 * out, and with a slight bit of extra cleverness (to recognize
135 * the instructions which produce either a 0 or 1) can eliminate
136 * the absneg.s's completely when an instruction that wants
137 * 0/1 consumes the result. For example, when a nir 'bcsel'
138 * consumes the result of 'feq'. So we should be able to get by
139 * without a boolean resolve step, and without incuring any
140 * extra penalty in instruction count.
141 */
142
143 /* NIR bool -> native (adreno): */
144 static struct ir3_instruction *
145 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
146 {
147 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
148 }
149
150 /* native (adreno) -> NIR bool: */
151 static struct ir3_instruction *
152 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
153 {
154 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
155 }
156
157 /*
158 * alu/sfu instructions:
159 */
160
161 static struct ir3_instruction *
162 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
163 unsigned src_bitsize, nir_op op)
164 {
165 type_t src_type, dst_type;
166
167 switch (op) {
168 case nir_op_f2f32:
169 case nir_op_f2f16_rtne:
170 case nir_op_f2f16_rtz:
171 case nir_op_f2f16:
172 case nir_op_f2i32:
173 case nir_op_f2i16:
174 case nir_op_f2i8:
175 case nir_op_f2u32:
176 case nir_op_f2u16:
177 case nir_op_f2u8:
178 switch (src_bitsize) {
179 case 32:
180 src_type = TYPE_F32;
181 break;
182 case 16:
183 src_type = TYPE_F16;
184 break;
185 default:
186 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
187 }
188 break;
189
190 case nir_op_i2f32:
191 case nir_op_i2f16:
192 case nir_op_i2i32:
193 case nir_op_i2i16:
194 case nir_op_i2i8:
195 switch (src_bitsize) {
196 case 32:
197 src_type = TYPE_S32;
198 break;
199 case 16:
200 src_type = TYPE_S16;
201 break;
202 case 8:
203 src_type = TYPE_S8;
204 break;
205 default:
206 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
207 }
208 break;
209
210 case nir_op_u2f32:
211 case nir_op_u2f16:
212 case nir_op_u2u32:
213 case nir_op_u2u16:
214 case nir_op_u2u8:
215 switch (src_bitsize) {
216 case 32:
217 src_type = TYPE_U32;
218 break;
219 case 16:
220 src_type = TYPE_U16;
221 break;
222 case 8:
223 src_type = TYPE_U8;
224 break;
225 default:
226 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
227 }
228 break;
229
230 default:
231 ir3_context_error(ctx, "invalid conversion op: %u", op);
232 }
233
234 switch (op) {
235 case nir_op_f2f32:
236 case nir_op_i2f32:
237 case nir_op_u2f32:
238 dst_type = TYPE_F32;
239 break;
240
241 case nir_op_f2f16_rtne:
242 case nir_op_f2f16_rtz:
243 case nir_op_f2f16:
244 /* TODO how to handle rounding mode? */
245 case nir_op_i2f16:
246 case nir_op_u2f16:
247 dst_type = TYPE_F16;
248 break;
249
250 case nir_op_f2i32:
251 case nir_op_i2i32:
252 dst_type = TYPE_S32;
253 break;
254
255 case nir_op_f2i16:
256 case nir_op_i2i16:
257 dst_type = TYPE_S16;
258 break;
259
260 case nir_op_f2i8:
261 case nir_op_i2i8:
262 dst_type = TYPE_S8;
263 break;
264
265 case nir_op_f2u32:
266 case nir_op_u2u32:
267 dst_type = TYPE_U32;
268 break;
269
270 case nir_op_f2u16:
271 case nir_op_u2u16:
272 dst_type = TYPE_U16;
273 break;
274
275 case nir_op_f2u8:
276 case nir_op_u2u8:
277 dst_type = TYPE_U8;
278 break;
279
280 default:
281 ir3_context_error(ctx, "invalid conversion op: %u", op);
282 }
283
284 return ir3_COV(ctx->block, src, src_type, dst_type);
285 }
286
287 static void
288 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
289 {
290 const nir_op_info *info = &nir_op_infos[alu->op];
291 struct ir3_instruction **dst, *src[info->num_inputs];
292 unsigned bs[info->num_inputs]; /* bit size */
293 struct ir3_block *b = ctx->block;
294 unsigned dst_sz, wrmask;
295
296 if (alu->dest.dest.is_ssa) {
297 dst_sz = alu->dest.dest.ssa.num_components;
298 wrmask = (1 << dst_sz) - 1;
299 } else {
300 dst_sz = alu->dest.dest.reg.reg->num_components;
301 wrmask = alu->dest.write_mask;
302 }
303
304 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
305
306 /* Vectors are special in that they have non-scalarized writemasks,
307 * and just take the first swizzle channel for each argument in
308 * order into each writemask channel.
309 */
310 if ((alu->op == nir_op_vec2) ||
311 (alu->op == nir_op_vec3) ||
312 (alu->op == nir_op_vec4)) {
313
314 for (int i = 0; i < info->num_inputs; i++) {
315 nir_alu_src *asrc = &alu->src[i];
316
317 compile_assert(ctx, !asrc->abs);
318 compile_assert(ctx, !asrc->negate);
319
320 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
321 if (!src[i])
322 src[i] = create_immed(ctx->block, 0);
323 dst[i] = ir3_MOV(b, src[i], TYPE_U32);
324 }
325
326 put_dst(ctx, &alu->dest.dest);
327 return;
328 }
329
330 /* We also get mov's with more than one component for mov's so
331 * handle those specially:
332 */
333 if ((alu->op == nir_op_imov) || (alu->op == nir_op_fmov)) {
334 type_t type = (alu->op == nir_op_imov) ? TYPE_U32 : TYPE_F32;
335 nir_alu_src *asrc = &alu->src[0];
336 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
337
338 for (unsigned i = 0; i < dst_sz; i++) {
339 if (wrmask & (1 << i)) {
340 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], type);
341 } else {
342 dst[i] = NULL;
343 }
344 }
345
346 put_dst(ctx, &alu->dest.dest);
347 return;
348 }
349
350 /* General case: We can just grab the one used channel per src. */
351 for (int i = 0; i < info->num_inputs; i++) {
352 unsigned chan = ffs(alu->dest.write_mask) - 1;
353 nir_alu_src *asrc = &alu->src[i];
354
355 compile_assert(ctx, !asrc->abs);
356 compile_assert(ctx, !asrc->negate);
357
358 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
359 bs[i] = nir_src_bit_size(asrc->src);
360
361 compile_assert(ctx, src[i]);
362 }
363
364 switch (alu->op) {
365 case nir_op_f2f32:
366 case nir_op_f2f16_rtne:
367 case nir_op_f2f16_rtz:
368 case nir_op_f2f16:
369 case nir_op_f2i32:
370 case nir_op_f2i16:
371 case nir_op_f2i8:
372 case nir_op_f2u32:
373 case nir_op_f2u16:
374 case nir_op_f2u8:
375 case nir_op_i2f32:
376 case nir_op_i2f16:
377 case nir_op_i2i32:
378 case nir_op_i2i16:
379 case nir_op_i2i8:
380 case nir_op_u2f32:
381 case nir_op_u2f16:
382 case nir_op_u2u32:
383 case nir_op_u2u16:
384 case nir_op_u2u8:
385 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
386 break;
387 case nir_op_f2b32:
388 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
389 dst[0]->cat2.condition = IR3_COND_NE;
390 dst[0] = ir3_n2b(b, dst[0]);
391 break;
392 case nir_op_b2f16:
393 case nir_op_b2f32:
394 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
395 break;
396 case nir_op_b2i8:
397 case nir_op_b2i16:
398 case nir_op_b2i32:
399 dst[0] = ir3_b2n(b, src[0]);
400 break;
401 case nir_op_i2b32:
402 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
403 dst[0]->cat2.condition = IR3_COND_NE;
404 dst[0] = ir3_n2b(b, dst[0]);
405 break;
406
407 case nir_op_fneg:
408 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
409 break;
410 case nir_op_fabs:
411 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
412 break;
413 case nir_op_fmax:
414 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
415 break;
416 case nir_op_fmin:
417 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
418 break;
419 case nir_op_fsat:
420 /* if there is just a single use of the src, and it supports
421 * (sat) bit, we can just fold the (sat) flag back to the
422 * src instruction and create a mov. This is easier for cp
423 * to eliminate.
424 *
425 * TODO probably opc_cat==4 is ok too
426 */
427 if (alu->src[0].src.is_ssa &&
428 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
429 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
430 src[0]->flags |= IR3_INSTR_SAT;
431 dst[0] = ir3_MOV(b, src[0], TYPE_U32);
432 } else {
433 /* otherwise generate a max.f that saturates.. blob does
434 * similar (generating a cat2 mov using max.f)
435 */
436 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
437 dst[0]->flags |= IR3_INSTR_SAT;
438 }
439 break;
440 case nir_op_fmul:
441 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
442 break;
443 case nir_op_fadd:
444 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
445 break;
446 case nir_op_fsub:
447 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
448 break;
449 case nir_op_ffma:
450 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
451 break;
452 case nir_op_fddx:
453 dst[0] = ir3_DSX(b, src[0], 0);
454 dst[0]->cat5.type = TYPE_F32;
455 break;
456 case nir_op_fddy:
457 dst[0] = ir3_DSY(b, src[0], 0);
458 dst[0]->cat5.type = TYPE_F32;
459 break;
460 break;
461 case nir_op_flt32:
462 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
463 dst[0]->cat2.condition = IR3_COND_LT;
464 dst[0] = ir3_n2b(b, dst[0]);
465 break;
466 case nir_op_fge32:
467 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
468 dst[0]->cat2.condition = IR3_COND_GE;
469 dst[0] = ir3_n2b(b, dst[0]);
470 break;
471 case nir_op_feq32:
472 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
473 dst[0]->cat2.condition = IR3_COND_EQ;
474 dst[0] = ir3_n2b(b, dst[0]);
475 break;
476 case nir_op_fne32:
477 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
478 dst[0]->cat2.condition = IR3_COND_NE;
479 dst[0] = ir3_n2b(b, dst[0]);
480 break;
481 case nir_op_fceil:
482 dst[0] = ir3_CEIL_F(b, src[0], 0);
483 break;
484 case nir_op_ffloor:
485 dst[0] = ir3_FLOOR_F(b, src[0], 0);
486 break;
487 case nir_op_ftrunc:
488 dst[0] = ir3_TRUNC_F(b, src[0], 0);
489 break;
490 case nir_op_fround_even:
491 dst[0] = ir3_RNDNE_F(b, src[0], 0);
492 break;
493 case nir_op_fsign:
494 dst[0] = ir3_SIGN_F(b, src[0], 0);
495 break;
496
497 case nir_op_fsin:
498 dst[0] = ir3_SIN(b, src[0], 0);
499 break;
500 case nir_op_fcos:
501 dst[0] = ir3_COS(b, src[0], 0);
502 break;
503 case nir_op_frsq:
504 dst[0] = ir3_RSQ(b, src[0], 0);
505 break;
506 case nir_op_frcp:
507 dst[0] = ir3_RCP(b, src[0], 0);
508 break;
509 case nir_op_flog2:
510 dst[0] = ir3_LOG2(b, src[0], 0);
511 break;
512 case nir_op_fexp2:
513 dst[0] = ir3_EXP2(b, src[0], 0);
514 break;
515 case nir_op_fsqrt:
516 dst[0] = ir3_SQRT(b, src[0], 0);
517 break;
518
519 case nir_op_iabs:
520 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
521 break;
522 case nir_op_iadd:
523 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
524 break;
525 case nir_op_iand:
526 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
527 break;
528 case nir_op_imax:
529 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
530 break;
531 case nir_op_umax:
532 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
533 break;
534 case nir_op_imin:
535 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
536 break;
537 case nir_op_umin:
538 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
539 break;
540 case nir_op_imul:
541 /*
542 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
543 * mull.u tmp0, a, b ; mul low, i.e. al * bl
544 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
545 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
546 */
547 dst[0] = ir3_MADSH_M16(b, src[1], 0, src[0], 0,
548 ir3_MADSH_M16(b, src[0], 0, src[1], 0,
549 ir3_MULL_U(b, src[0], 0, src[1], 0), 0), 0);
550 break;
551 case nir_op_ineg:
552 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
553 break;
554 case nir_op_inot:
555 dst[0] = ir3_NOT_B(b, src[0], 0);
556 break;
557 case nir_op_ior:
558 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
559 break;
560 case nir_op_ishl:
561 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
562 break;
563 case nir_op_ishr:
564 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
565 break;
566 case nir_op_isign: {
567 /* maybe this would be sane to lower in nir.. */
568 struct ir3_instruction *neg, *pos;
569
570 neg = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
571 neg->cat2.condition = IR3_COND_LT;
572
573 pos = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
574 pos->cat2.condition = IR3_COND_GT;
575
576 dst[0] = ir3_SUB_U(b, pos, 0, neg, 0);
577
578 break;
579 }
580 case nir_op_isub:
581 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
582 break;
583 case nir_op_ixor:
584 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
585 break;
586 case nir_op_ushr:
587 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
588 break;
589 case nir_op_ilt32:
590 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
591 dst[0]->cat2.condition = IR3_COND_LT;
592 dst[0] = ir3_n2b(b, dst[0]);
593 break;
594 case nir_op_ige32:
595 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
596 dst[0]->cat2.condition = IR3_COND_GE;
597 dst[0] = ir3_n2b(b, dst[0]);
598 break;
599 case nir_op_ieq32:
600 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
601 dst[0]->cat2.condition = IR3_COND_EQ;
602 dst[0] = ir3_n2b(b, dst[0]);
603 break;
604 case nir_op_ine32:
605 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
606 dst[0]->cat2.condition = IR3_COND_NE;
607 dst[0] = ir3_n2b(b, dst[0]);
608 break;
609 case nir_op_ult32:
610 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
611 dst[0]->cat2.condition = IR3_COND_LT;
612 dst[0] = ir3_n2b(b, dst[0]);
613 break;
614 case nir_op_uge32:
615 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
616 dst[0]->cat2.condition = IR3_COND_GE;
617 dst[0] = ir3_n2b(b, dst[0]);
618 break;
619
620 case nir_op_b32csel: {
621 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
622 compile_assert(ctx, bs[1] == bs[2]);
623 /* the boolean condition is 32b even if src[1] and src[2] are
624 * half-precision, but sel.b16 wants all three src's to be the
625 * same type.
626 */
627 if (bs[1] < 32)
628 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
629 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
630 break;
631 }
632 case nir_op_bit_count:
633 dst[0] = ir3_CBITS_B(b, src[0], 0);
634 break;
635 case nir_op_ifind_msb: {
636 struct ir3_instruction *cmp;
637 dst[0] = ir3_CLZ_S(b, src[0], 0);
638 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
639 cmp->cat2.condition = IR3_COND_GE;
640 dst[0] = ir3_SEL_B32(b,
641 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
642 cmp, 0, dst[0], 0);
643 break;
644 }
645 case nir_op_ufind_msb:
646 dst[0] = ir3_CLZ_B(b, src[0], 0);
647 dst[0] = ir3_SEL_B32(b,
648 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
649 src[0], 0, dst[0], 0);
650 break;
651 case nir_op_find_lsb:
652 dst[0] = ir3_BFREV_B(b, src[0], 0);
653 dst[0] = ir3_CLZ_B(b, dst[0], 0);
654 break;
655 case nir_op_bitfield_reverse:
656 dst[0] = ir3_BFREV_B(b, src[0], 0);
657 break;
658
659 default:
660 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
661 nir_op_infos[alu->op].name);
662 break;
663 }
664
665 put_dst(ctx, &alu->dest.dest);
666 }
667
668 /* handles direct/indirect UBO reads: */
669 static void
670 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
671 struct ir3_instruction **dst)
672 {
673 struct ir3_block *b = ctx->block;
674 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
675 nir_const_value *const_offset;
676 /* UBO addresses are the first driver params: */
677 unsigned ubo = regid(ctx->so->constbase.ubo, 0);
678 const unsigned ptrsz = ir3_pointer_size(ctx);
679
680 int off = 0;
681
682 /* First src is ubo index, which could either be an immed or not: */
683 src0 = ir3_get_src(ctx, &intr->src[0])[0];
684 if (is_same_type_mov(src0) &&
685 (src0->regs[1]->flags & IR3_REG_IMMED)) {
686 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
687 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
688 } else {
689 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, 4));
690 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, 4));
691 }
692
693 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
694 addr = base_lo;
695
696 const_offset = nir_src_as_const_value(intr->src[1]);
697 if (const_offset) {
698 off += const_offset->u32[0];
699 } else {
700 /* For load_ubo_indirect, second src is indirect offset: */
701 src1 = ir3_get_src(ctx, &intr->src[1])[0];
702
703 /* and add offset to addr: */
704 addr = ir3_ADD_S(b, addr, 0, src1, 0);
705 }
706
707 /* if offset is to large to encode in the ldg, split it out: */
708 if ((off + (intr->num_components * 4)) > 1024) {
709 /* split out the minimal amount to improve the odds that
710 * cp can fit the immediate in the add.s instruction:
711 */
712 unsigned off2 = off + (intr->num_components * 4) - 1024;
713 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
714 off -= off2;
715 }
716
717 if (ptrsz == 2) {
718 struct ir3_instruction *carry;
719
720 /* handle 32b rollover, ie:
721 * if (addr < base_lo)
722 * base_hi++
723 */
724 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
725 carry->cat2.condition = IR3_COND_LT;
726 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
727
728 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
729 }
730
731 for (int i = 0; i < intr->num_components; i++) {
732 struct ir3_instruction *load =
733 ir3_LDG(b, addr, 0, create_immed(b, 1), 0);
734 load->cat6.type = TYPE_U32;
735 load->cat6.src_offset = off + i * 4; /* byte offset */
736 dst[i] = load;
737 }
738 }
739
740 /* src[] = { buffer_index, offset }. No const_index */
741 static void
742 emit_intrinsic_load_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
743 struct ir3_instruction **dst)
744 {
745 struct ir3_block *b = ctx->block;
746 struct ir3_instruction *ldgb, *src0, *src1, *offset;
747 nir_const_value *const_offset;
748
749 /* can this be non-const buffer_index? how do we handle that? */
750 const_offset = nir_src_as_const_value(intr->src[0]);
751 compile_assert(ctx, const_offset);
752
753 offset = ir3_get_src(ctx, &intr->src[1])[0];
754
755 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
756 src0 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
757 offset,
758 create_immed(b, 0),
759 }, 2);
760 src1 = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0);
761
762 ldgb = ir3_LDGB(b, create_immed(b, const_offset->u32[0]), 0,
763 src0, 0, src1, 0);
764 ldgb->regs[0]->wrmask = MASK(intr->num_components);
765 ldgb->cat6.iim_val = intr->num_components;
766 ldgb->cat6.d = 4;
767 ldgb->cat6.type = TYPE_U32;
768 ldgb->barrier_class = IR3_BARRIER_BUFFER_R;
769 ldgb->barrier_conflict = IR3_BARRIER_BUFFER_W;
770
771 ir3_split_dest(b, dst, ldgb, 0, intr->num_components);
772 }
773
774 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
775 static void
776 emit_intrinsic_store_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
777 {
778 struct ir3_block *b = ctx->block;
779 struct ir3_instruction *stgb, *src0, *src1, *src2, *offset;
780 nir_const_value *const_offset;
781 /* TODO handle wrmask properly, see _store_shared().. but I think
782 * it is more a PITA than that, since blob ends up loading the
783 * masked components and writing them back out.
784 */
785 unsigned wrmask = intr->const_index[0];
786 unsigned ncomp = ffs(~wrmask) - 1;
787
788 /* can this be non-const buffer_index? how do we handle that? */
789 const_offset = nir_src_as_const_value(intr->src[1]);
790 compile_assert(ctx, const_offset);
791
792 offset = ir3_get_src(ctx, &intr->src[2])[0];
793
794 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
795 * nir already *= 4:
796 */
797 src0 = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]), ncomp);
798 src1 = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0);
799 src2 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
800 offset,
801 create_immed(b, 0),
802 }, 2);
803
804 stgb = ir3_STGB(b, create_immed(b, const_offset->u32[0]), 0,
805 src0, 0, src1, 0, src2, 0);
806 stgb->cat6.iim_val = ncomp;
807 stgb->cat6.d = 4;
808 stgb->cat6.type = TYPE_U32;
809 stgb->barrier_class = IR3_BARRIER_BUFFER_W;
810 stgb->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
811
812 array_insert(b, b->keeps, stgb);
813 }
814
815 /* src[] = { block_index } */
816 static void
817 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
818 struct ir3_instruction **dst)
819 {
820 /* SSBO size stored as a const starting at ssbo_sizes: */
821 unsigned blk_idx = nir_src_as_const_value(intr->src[0])->u32[0];
822 unsigned idx = regid(ctx->so->constbase.ssbo_sizes, 0) +
823 ctx->so->const_layout.ssbo_size.off[blk_idx];
824
825 debug_assert(ctx->so->const_layout.ssbo_size.mask & (1 << blk_idx));
826
827 dst[0] = create_uniform(ctx->block, idx);
828 }
829
830 /*
831 * SSBO atomic intrinsics
832 *
833 * All of the SSBO atomic memory operations read a value from memory,
834 * compute a new value using one of the operations below, write the new
835 * value to memory, and return the original value read.
836 *
837 * All operations take 3 sources except CompSwap that takes 4. These
838 * sources represent:
839 *
840 * 0: The SSBO buffer index.
841 * 1: The offset into the SSBO buffer of the variable that the atomic
842 * operation will operate on.
843 * 2: The data parameter to the atomic function (i.e. the value to add
844 * in ssbo_atomic_add, etc).
845 * 3: For CompSwap only: the second data parameter.
846 */
847 static struct ir3_instruction *
848 emit_intrinsic_atomic_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
849 {
850 struct ir3_block *b = ctx->block;
851 struct ir3_instruction *atomic, *ssbo, *src0, *src1, *src2, *offset;
852 nir_const_value *const_offset;
853 type_t type = TYPE_U32;
854
855 /* can this be non-const buffer_index? how do we handle that? */
856 const_offset = nir_src_as_const_value(intr->src[0]);
857 compile_assert(ctx, const_offset);
858 ssbo = create_immed(b, const_offset->u32[0]);
859
860 offset = ir3_get_src(ctx, &intr->src[1])[0];
861
862 /* src0 is data (or uvec2(data, compare))
863 * src1 is offset
864 * src2 is uvec2(offset*4, 0) (appears to be 64b byte offset)
865 *
866 * Note that nir already multiplies the offset by four
867 */
868 src0 = ir3_get_src(ctx, &intr->src[2])[0];
869 src1 = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0);
870 src2 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
871 offset,
872 create_immed(b, 0),
873 }, 2);
874
875 switch (intr->intrinsic) {
876 case nir_intrinsic_ssbo_atomic_add:
877 atomic = ir3_ATOMIC_ADD_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
878 break;
879 case nir_intrinsic_ssbo_atomic_imin:
880 atomic = ir3_ATOMIC_MIN_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
881 type = TYPE_S32;
882 break;
883 case nir_intrinsic_ssbo_atomic_umin:
884 atomic = ir3_ATOMIC_MIN_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
885 break;
886 case nir_intrinsic_ssbo_atomic_imax:
887 atomic = ir3_ATOMIC_MAX_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
888 type = TYPE_S32;
889 break;
890 case nir_intrinsic_ssbo_atomic_umax:
891 atomic = ir3_ATOMIC_MAX_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
892 break;
893 case nir_intrinsic_ssbo_atomic_and:
894 atomic = ir3_ATOMIC_AND_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
895 break;
896 case nir_intrinsic_ssbo_atomic_or:
897 atomic = ir3_ATOMIC_OR_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
898 break;
899 case nir_intrinsic_ssbo_atomic_xor:
900 atomic = ir3_ATOMIC_XOR_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
901 break;
902 case nir_intrinsic_ssbo_atomic_exchange:
903 atomic = ir3_ATOMIC_XCHG_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
904 break;
905 case nir_intrinsic_ssbo_atomic_comp_swap:
906 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
907 src0 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
908 ir3_get_src(ctx, &intr->src[3])[0],
909 src0,
910 }, 2);
911 atomic = ir3_ATOMIC_CMPXCHG_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
912 break;
913 default:
914 unreachable("boo");
915 }
916
917 atomic->cat6.iim_val = 1;
918 atomic->cat6.d = 4;
919 atomic->cat6.type = type;
920 atomic->barrier_class = IR3_BARRIER_BUFFER_W;
921 atomic->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
922
923 /* even if nothing consume the result, we can't DCE the instruction: */
924 array_insert(b, b->keeps, atomic);
925
926 return atomic;
927 }
928
929 /* src[] = { offset }. const_index[] = { base } */
930 static void
931 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
932 struct ir3_instruction **dst)
933 {
934 struct ir3_block *b = ctx->block;
935 struct ir3_instruction *ldl, *offset;
936 unsigned base;
937
938 offset = ir3_get_src(ctx, &intr->src[0])[0];
939 base = nir_intrinsic_base(intr);
940
941 ldl = ir3_LDL(b, offset, 0, create_immed(b, intr->num_components), 0);
942 ldl->cat6.src_offset = base;
943 ldl->cat6.type = utype_dst(intr->dest);
944 ldl->regs[0]->wrmask = MASK(intr->num_components);
945
946 ldl->barrier_class = IR3_BARRIER_SHARED_R;
947 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
948
949 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
950 }
951
952 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
953 static void
954 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
955 {
956 struct ir3_block *b = ctx->block;
957 struct ir3_instruction *stl, *offset;
958 struct ir3_instruction * const *value;
959 unsigned base, wrmask;
960
961 value = ir3_get_src(ctx, &intr->src[0]);
962 offset = ir3_get_src(ctx, &intr->src[1])[0];
963
964 base = nir_intrinsic_base(intr);
965 wrmask = nir_intrinsic_write_mask(intr);
966
967 /* Combine groups of consecutive enabled channels in one write
968 * message. We use ffs to find the first enabled channel and then ffs on
969 * the bit-inverse, down-shifted writemask to determine the length of
970 * the block of enabled bits.
971 *
972 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
973 */
974 while (wrmask) {
975 unsigned first_component = ffs(wrmask) - 1;
976 unsigned length = ffs(~(wrmask >> first_component)) - 1;
977
978 stl = ir3_STL(b, offset, 0,
979 ir3_create_collect(ctx, &value[first_component], length), 0,
980 create_immed(b, length), 0);
981 stl->cat6.dst_offset = first_component + base;
982 stl->cat6.type = utype_src(intr->src[0]);
983 stl->barrier_class = IR3_BARRIER_SHARED_W;
984 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
985
986 array_insert(b, b->keeps, stl);
987
988 /* Clear the bits in the writemask that we just wrote, then try
989 * again to see if more channels are left.
990 */
991 wrmask &= (15 << (first_component + length));
992 }
993 }
994
995 /*
996 * CS shared variable atomic intrinsics
997 *
998 * All of the shared variable atomic memory operations read a value from
999 * memory, compute a new value using one of the operations below, write the
1000 * new value to memory, and return the original value read.
1001 *
1002 * All operations take 2 sources except CompSwap that takes 3. These
1003 * sources represent:
1004 *
1005 * 0: The offset into the shared variable storage region that the atomic
1006 * operation will operate on.
1007 * 1: The data parameter to the atomic function (i.e. the value to add
1008 * in shared_atomic_add, etc).
1009 * 2: For CompSwap only: the second data parameter.
1010 */
1011 static struct ir3_instruction *
1012 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1013 {
1014 struct ir3_block *b = ctx->block;
1015 struct ir3_instruction *atomic, *src0, *src1;
1016 type_t type = TYPE_U32;
1017
1018 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
1019 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
1020
1021 switch (intr->intrinsic) {
1022 case nir_intrinsic_shared_atomic_add:
1023 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
1024 break;
1025 case nir_intrinsic_shared_atomic_imin:
1026 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1027 type = TYPE_S32;
1028 break;
1029 case nir_intrinsic_shared_atomic_umin:
1030 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1031 break;
1032 case nir_intrinsic_shared_atomic_imax:
1033 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1034 type = TYPE_S32;
1035 break;
1036 case nir_intrinsic_shared_atomic_umax:
1037 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1038 break;
1039 case nir_intrinsic_shared_atomic_and:
1040 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
1041 break;
1042 case nir_intrinsic_shared_atomic_or:
1043 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
1044 break;
1045 case nir_intrinsic_shared_atomic_xor:
1046 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
1047 break;
1048 case nir_intrinsic_shared_atomic_exchange:
1049 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
1050 break;
1051 case nir_intrinsic_shared_atomic_comp_swap:
1052 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1053 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1054 ir3_get_src(ctx, &intr->src[2])[0],
1055 src1,
1056 }, 2);
1057 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
1058 break;
1059 default:
1060 unreachable("boo");
1061 }
1062
1063 atomic->cat6.iim_val = 1;
1064 atomic->cat6.d = 1;
1065 atomic->cat6.type = type;
1066 atomic->barrier_class = IR3_BARRIER_SHARED_W;
1067 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1068
1069 /* even if nothing consume the result, we can't DCE the instruction: */
1070 array_insert(b, b->keeps, atomic);
1071
1072 return atomic;
1073 }
1074
1075 /* Images get mapped into SSBO/image state (for store/atomic) and texture
1076 * state block (for load). To simplify things, invert the image id and
1077 * map it from end of state block, ie. image 0 becomes num-1, image 1
1078 * becomes num-2, etc. This potentially avoids needing to re-emit texture
1079 * state when switching shaders.
1080 *
1081 * TODO is max # of samplers and SSBOs the same. This shouldn't be hard-
1082 * coded. Also, since all the gl shader stages (ie. everything but CS)
1083 * share the same SSBO/image state block, this might require some more
1084 * logic if we supported images in anything other than FS..
1085 */
1086 static unsigned
1087 get_image_slot(struct ir3_context *ctx, nir_deref_instr *deref)
1088 {
1089 unsigned int loc = 0;
1090 unsigned inner_size = 1;
1091
1092 while (deref->deref_type != nir_deref_type_var) {
1093 assert(deref->deref_type == nir_deref_type_array);
1094 nir_const_value *const_index = nir_src_as_const_value(deref->arr.index);
1095 assert(const_index);
1096
1097 /* Go to the next instruction */
1098 deref = nir_deref_instr_parent(deref);
1099
1100 assert(glsl_type_is_array(deref->type));
1101 const unsigned array_len = glsl_get_length(deref->type);
1102 loc += MIN2(const_index->u32[0], array_len - 1) * inner_size;
1103
1104 /* Update the inner size */
1105 inner_size *= array_len;
1106 }
1107
1108 loc += deref->var->data.driver_location;
1109
1110 /* TODO figure out real limit per generation, and don't hardcode: */
1111 const unsigned max_samplers = 16;
1112 return max_samplers - loc - 1;
1113 }
1114
1115 /* see tex_info() for equiv logic for texture instructions.. it would be
1116 * nice if this could be better unified..
1117 */
1118 static unsigned
1119 get_image_coords(const nir_variable *var, unsigned *flagsp)
1120 {
1121 const struct glsl_type *type = glsl_without_array(var->type);
1122 unsigned coords, flags = 0;
1123
1124 switch (glsl_get_sampler_dim(type)) {
1125 case GLSL_SAMPLER_DIM_1D:
1126 case GLSL_SAMPLER_DIM_BUF:
1127 coords = 1;
1128 break;
1129 case GLSL_SAMPLER_DIM_2D:
1130 case GLSL_SAMPLER_DIM_RECT:
1131 case GLSL_SAMPLER_DIM_EXTERNAL:
1132 case GLSL_SAMPLER_DIM_MS:
1133 coords = 2;
1134 break;
1135 case GLSL_SAMPLER_DIM_3D:
1136 case GLSL_SAMPLER_DIM_CUBE:
1137 flags |= IR3_INSTR_3D;
1138 coords = 3;
1139 break;
1140 default:
1141 unreachable("bad sampler dim");
1142 return 0;
1143 }
1144
1145 if (glsl_sampler_type_is_array(type)) {
1146 /* note: unlike tex_info(), adjust # of coords to include array idx: */
1147 coords++;
1148 flags |= IR3_INSTR_A;
1149 }
1150
1151 if (flagsp)
1152 *flagsp = flags;
1153
1154 return coords;
1155 }
1156
1157 static type_t
1158 get_image_type(const nir_variable *var)
1159 {
1160 switch (glsl_get_sampler_result_type(glsl_without_array(var->type))) {
1161 case GLSL_TYPE_UINT:
1162 return TYPE_U32;
1163 case GLSL_TYPE_INT:
1164 return TYPE_S32;
1165 case GLSL_TYPE_FLOAT:
1166 return TYPE_F32;
1167 default:
1168 unreachable("bad sampler type.");
1169 return 0;
1170 }
1171 }
1172
1173 static struct ir3_instruction *
1174 get_image_offset(struct ir3_context *ctx, const nir_variable *var,
1175 struct ir3_instruction * const *coords, bool byteoff)
1176 {
1177 struct ir3_block *b = ctx->block;
1178 struct ir3_instruction *offset;
1179 unsigned ncoords = get_image_coords(var, NULL);
1180
1181 /* to calculate the byte offset (yes, uggg) we need (up to) three
1182 * const values to know the bytes per pixel, and y and z stride:
1183 */
1184 unsigned cb = regid(ctx->so->constbase.image_dims, 0) +
1185 ctx->so->const_layout.image_dims.off[var->data.driver_location];
1186
1187 debug_assert(ctx->so->const_layout.image_dims.mask &
1188 (1 << var->data.driver_location));
1189
1190 /* offset = coords.x * bytes_per_pixel: */
1191 offset = ir3_MUL_S(b, coords[0], 0, create_uniform(b, cb + 0), 0);
1192 if (ncoords > 1) {
1193 /* offset += coords.y * y_pitch: */
1194 offset = ir3_MAD_S24(b, create_uniform(b, cb + 1), 0,
1195 coords[1], 0, offset, 0);
1196 }
1197 if (ncoords > 2) {
1198 /* offset += coords.z * z_pitch: */
1199 offset = ir3_MAD_S24(b, create_uniform(b, cb + 2), 0,
1200 coords[2], 0, offset, 0);
1201 }
1202
1203 if (!byteoff) {
1204 /* Some cases, like atomics, seem to use dword offset instead
1205 * of byte offsets.. blob just puts an extra shr.b in there
1206 * in those cases:
1207 */
1208 offset = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0);
1209 }
1210
1211 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1212 offset,
1213 create_immed(b, 0),
1214 }, 2);
1215 }
1216
1217 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1218 static void
1219 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1220 struct ir3_instruction **dst)
1221 {
1222 struct ir3_block *b = ctx->block;
1223 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1224 struct ir3_instruction *sam;
1225 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1226 struct ir3_instruction *coords[4];
1227 unsigned flags, ncoords = get_image_coords(var, &flags);
1228 unsigned tex_idx = get_image_slot(ctx, nir_src_as_deref(intr->src[0]));
1229 type_t type = get_image_type(var);
1230
1231 /* hmm, this seems a bit odd, but it is what blob does and (at least
1232 * a5xx) just faults on bogus addresses otherwise:
1233 */
1234 if (flags & IR3_INSTR_3D) {
1235 flags &= ~IR3_INSTR_3D;
1236 flags |= IR3_INSTR_A;
1237 }
1238
1239 for (unsigned i = 0; i < ncoords; i++)
1240 coords[i] = src0[i];
1241
1242 if (ncoords == 1)
1243 coords[ncoords++] = create_immed(b, 0);
1244
1245 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
1246 tex_idx, tex_idx, ir3_create_collect(ctx, coords, ncoords), NULL);
1247
1248 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1249 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1250
1251 ir3_split_dest(b, dst, sam, 0, 4);
1252 }
1253
1254 /* Returns the number of components for the different image formats
1255 * supported by the GLES 3.1 spec, plus those added by the
1256 * GL_NV_image_formats extension.
1257 */
1258 static unsigned
1259 get_num_components_for_glformat(GLuint format)
1260 {
1261 switch (format) {
1262 case GL_R32F:
1263 case GL_R32I:
1264 case GL_R32UI:
1265 case GL_R16F:
1266 case GL_R16I:
1267 case GL_R16UI:
1268 case GL_R16:
1269 case GL_R16_SNORM:
1270 case GL_R8I:
1271 case GL_R8UI:
1272 case GL_R8:
1273 case GL_R8_SNORM:
1274 return 1;
1275
1276 case GL_RG32F:
1277 case GL_RG32I:
1278 case GL_RG32UI:
1279 case GL_RG16F:
1280 case GL_RG16I:
1281 case GL_RG16UI:
1282 case GL_RG16:
1283 case GL_RG16_SNORM:
1284 case GL_RG8I:
1285 case GL_RG8UI:
1286 case GL_RG8:
1287 case GL_RG8_SNORM:
1288 return 2;
1289
1290 case GL_R11F_G11F_B10F:
1291 return 3;
1292
1293 case GL_RGBA32F:
1294 case GL_RGBA32I:
1295 case GL_RGBA32UI:
1296 case GL_RGBA16F:
1297 case GL_RGBA16I:
1298 case GL_RGBA16UI:
1299 case GL_RGBA16:
1300 case GL_RGBA16_SNORM:
1301 case GL_RGBA8I:
1302 case GL_RGBA8UI:
1303 case GL_RGBA8:
1304 case GL_RGBA8_SNORM:
1305 case GL_RGB10_A2UI:
1306 case GL_RGB10_A2:
1307 return 4;
1308
1309 case GL_NONE:
1310 /* Omitting the image format qualifier is allowed on desktop GL
1311 * profiles. Assuming 4 components is always safe.
1312 */
1313 return 4;
1314
1315 default:
1316 /* Return 4 components also for all other formats we don't know
1317 * about. The format should have been validated already by
1318 * the higher level API, but drop a debug message just in case.
1319 */
1320 debug_printf("Unhandled GL format %u while emitting imageStore()\n",
1321 format);
1322 return 4;
1323 }
1324 }
1325
1326 /* src[] = { deref, coord, sample_index, value }. const_index[] = {} */
1327 static void
1328 emit_intrinsic_store_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1329 {
1330 struct ir3_block *b = ctx->block;
1331 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1332 struct ir3_instruction *stib, *offset;
1333 struct ir3_instruction * const *value = ir3_get_src(ctx, &intr->src[3]);
1334 struct ir3_instruction * const *coords = ir3_get_src(ctx, &intr->src[1]);
1335 unsigned ncoords = get_image_coords(var, NULL);
1336 unsigned tex_idx = get_image_slot(ctx, nir_src_as_deref(intr->src[0]));
1337 unsigned ncomp = get_num_components_for_glformat(var->data.image.format);
1338
1339 /* src0 is value
1340 * src1 is coords
1341 * src2 is 64b byte offset
1342 */
1343
1344 offset = get_image_offset(ctx, var, coords, true);
1345
1346 /* NOTE: stib seems to take byte offset, but stgb.typed can be used
1347 * too and takes a dword offset.. not quite sure yet why blob uses
1348 * one over the other in various cases.
1349 */
1350
1351 stib = ir3_STIB(b, create_immed(b, tex_idx), 0,
1352 ir3_create_collect(ctx, value, ncomp), 0,
1353 ir3_create_collect(ctx, coords, ncoords), 0,
1354 offset, 0);
1355 stib->cat6.iim_val = ncomp;
1356 stib->cat6.d = ncoords;
1357 stib->cat6.type = get_image_type(var);
1358 stib->cat6.typed = true;
1359 stib->barrier_class = IR3_BARRIER_IMAGE_W;
1360 stib->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W;
1361
1362 array_insert(b, b->keeps, stib);
1363 }
1364
1365 static void
1366 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1367 struct ir3_instruction **dst)
1368 {
1369 struct ir3_block *b = ctx->block;
1370 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1371 unsigned tex_idx = get_image_slot(ctx, nir_src_as_deref(intr->src[0]));
1372 struct ir3_instruction *sam, *lod;
1373 unsigned flags, ncoords = get_image_coords(var, &flags);
1374
1375 lod = create_immed(b, 0);
1376 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
1377 tex_idx, tex_idx, lod, NULL);
1378
1379 /* Array size actually ends up in .w rather than .z. This doesn't
1380 * matter for miplevel 0, but for higher mips the value in z is
1381 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1382 * returned, which means that we have to add 1 to it for arrays for
1383 * a3xx.
1384 *
1385 * Note use a temporary dst and then copy, since the size of the dst
1386 * array that is passed in is based on nir's understanding of the
1387 * result size, not the hardware's
1388 */
1389 struct ir3_instruction *tmp[4];
1390
1391 ir3_split_dest(b, tmp, sam, 0, 4);
1392
1393 /* get_size instruction returns size in bytes instead of texels
1394 * for imageBuffer, so we need to divide it by the pixel size
1395 * of the image format.
1396 *
1397 * TODO: This is at least true on a5xx. Check other gens.
1398 */
1399 enum glsl_sampler_dim dim =
1400 glsl_get_sampler_dim(glsl_without_array(var->type));
1401 if (dim == GLSL_SAMPLER_DIM_BUF) {
1402 /* Since all the possible values the divisor can take are
1403 * power-of-two (4, 8, or 16), the division is implemented
1404 * as a shift-right.
1405 * During shader setup, the log2 of the image format's
1406 * bytes-per-pixel should have been emitted in 2nd slot of
1407 * image_dims. See ir3_shader::emit_image_dims().
1408 */
1409 unsigned cb = regid(ctx->so->constbase.image_dims, 0) +
1410 ctx->so->const_layout.image_dims.off[var->data.driver_location];
1411 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1412
1413 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1414 }
1415
1416 for (unsigned i = 0; i < ncoords; i++)
1417 dst[i] = tmp[i];
1418
1419 if (flags & IR3_INSTR_A) {
1420 if (ctx->compiler->levels_add_one) {
1421 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1422 } else {
1423 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1424 }
1425 }
1426 }
1427
1428 /* src[] = { deref, coord, sample_index, value, compare }. const_index[] = {} */
1429 static struct ir3_instruction *
1430 emit_intrinsic_atomic_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1431 {
1432 struct ir3_block *b = ctx->block;
1433 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1434 struct ir3_instruction *atomic, *image, *src0, *src1, *src2;
1435 struct ir3_instruction * const *coords = ir3_get_src(ctx, &intr->src[1]);
1436 unsigned ncoords = get_image_coords(var, NULL);
1437
1438 image = create_immed(b, get_image_slot(ctx, nir_src_as_deref(intr->src[0])));
1439
1440 /* src0 is value (or uvec2(value, compare))
1441 * src1 is coords
1442 * src2 is 64b byte offset
1443 */
1444 src0 = ir3_get_src(ctx, &intr->src[3])[0];
1445 src1 = ir3_create_collect(ctx, coords, ncoords);
1446 src2 = get_image_offset(ctx, var, coords, false);
1447
1448 switch (intr->intrinsic) {
1449 case nir_intrinsic_image_deref_atomic_add:
1450 atomic = ir3_ATOMIC_ADD_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1451 break;
1452 case nir_intrinsic_image_deref_atomic_min:
1453 atomic = ir3_ATOMIC_MIN_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1454 break;
1455 case nir_intrinsic_image_deref_atomic_max:
1456 atomic = ir3_ATOMIC_MAX_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1457 break;
1458 case nir_intrinsic_image_deref_atomic_and:
1459 atomic = ir3_ATOMIC_AND_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1460 break;
1461 case nir_intrinsic_image_deref_atomic_or:
1462 atomic = ir3_ATOMIC_OR_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1463 break;
1464 case nir_intrinsic_image_deref_atomic_xor:
1465 atomic = ir3_ATOMIC_XOR_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1466 break;
1467 case nir_intrinsic_image_deref_atomic_exchange:
1468 atomic = ir3_ATOMIC_XCHG_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1469 break;
1470 case nir_intrinsic_image_deref_atomic_comp_swap:
1471 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1472 src0 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1473 ir3_get_src(ctx, &intr->src[4])[0],
1474 src0,
1475 }, 2);
1476 atomic = ir3_ATOMIC_CMPXCHG_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1477 break;
1478 default:
1479 unreachable("boo");
1480 }
1481
1482 atomic->cat6.iim_val = 1;
1483 atomic->cat6.d = ncoords;
1484 atomic->cat6.type = get_image_type(var);
1485 atomic->cat6.typed = true;
1486 atomic->barrier_class = IR3_BARRIER_IMAGE_W;
1487 atomic->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W;
1488
1489 /* even if nothing consume the result, we can't DCE the instruction: */
1490 array_insert(b, b->keeps, atomic);
1491
1492 return atomic;
1493 }
1494
1495 static void
1496 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1497 {
1498 struct ir3_block *b = ctx->block;
1499 struct ir3_instruction *barrier;
1500
1501 switch (intr->intrinsic) {
1502 case nir_intrinsic_barrier:
1503 barrier = ir3_BAR(b);
1504 barrier->cat7.g = true;
1505 barrier->cat7.l = true;
1506 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1507 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1508 break;
1509 case nir_intrinsic_memory_barrier:
1510 barrier = ir3_FENCE(b);
1511 barrier->cat7.g = true;
1512 barrier->cat7.r = true;
1513 barrier->cat7.w = true;
1514 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1515 IR3_BARRIER_BUFFER_W;
1516 barrier->barrier_conflict =
1517 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1518 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1519 break;
1520 case nir_intrinsic_memory_barrier_atomic_counter:
1521 case nir_intrinsic_memory_barrier_buffer:
1522 barrier = ir3_FENCE(b);
1523 barrier->cat7.g = true;
1524 barrier->cat7.r = true;
1525 barrier->cat7.w = true;
1526 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1527 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1528 IR3_BARRIER_BUFFER_W;
1529 break;
1530 case nir_intrinsic_memory_barrier_image:
1531 // TODO double check if this should have .g set
1532 barrier = ir3_FENCE(b);
1533 barrier->cat7.g = true;
1534 barrier->cat7.r = true;
1535 barrier->cat7.w = true;
1536 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1537 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1538 IR3_BARRIER_IMAGE_W;
1539 break;
1540 case nir_intrinsic_memory_barrier_shared:
1541 barrier = ir3_FENCE(b);
1542 barrier->cat7.g = true;
1543 barrier->cat7.l = true;
1544 barrier->cat7.r = true;
1545 barrier->cat7.w = true;
1546 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1547 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1548 IR3_BARRIER_SHARED_W;
1549 break;
1550 case nir_intrinsic_group_memory_barrier:
1551 barrier = ir3_FENCE(b);
1552 barrier->cat7.g = true;
1553 barrier->cat7.l = true;
1554 barrier->cat7.r = true;
1555 barrier->cat7.w = true;
1556 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1557 IR3_BARRIER_IMAGE_W |
1558 IR3_BARRIER_BUFFER_W;
1559 barrier->barrier_conflict =
1560 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1561 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1562 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1563 break;
1564 default:
1565 unreachable("boo");
1566 }
1567
1568 /* make sure barrier doesn't get DCE'd */
1569 array_insert(b, b->keeps, barrier);
1570 }
1571
1572 static void add_sysval_input_compmask(struct ir3_context *ctx,
1573 gl_system_value slot, unsigned compmask,
1574 struct ir3_instruction *instr)
1575 {
1576 struct ir3_shader_variant *so = ctx->so;
1577 unsigned r = regid(so->inputs_count, 0);
1578 unsigned n = so->inputs_count++;
1579
1580 so->inputs[n].sysval = true;
1581 so->inputs[n].slot = slot;
1582 so->inputs[n].compmask = compmask;
1583 so->inputs[n].regid = r;
1584 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1585 so->total_in++;
1586
1587 ctx->ir->ninputs = MAX2(ctx->ir->ninputs, r + 1);
1588 ctx->ir->inputs[r] = instr;
1589 }
1590
1591 static void add_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1592 struct ir3_instruction *instr)
1593 {
1594 add_sysval_input_compmask(ctx, slot, 0x1, instr);
1595 }
1596
1597 static void
1598 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1599 {
1600 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1601 struct ir3_instruction **dst;
1602 struct ir3_instruction * const *src;
1603 struct ir3_block *b = ctx->block;
1604 nir_const_value *const_offset;
1605 int idx, comp;
1606
1607 if (info->has_dest) {
1608 unsigned n = nir_intrinsic_dest_components(intr);
1609 dst = ir3_get_dst(ctx, &intr->dest, n);
1610 } else {
1611 dst = NULL;
1612 }
1613
1614 switch (intr->intrinsic) {
1615 case nir_intrinsic_load_uniform:
1616 idx = nir_intrinsic_base(intr);
1617 const_offset = nir_src_as_const_value(intr->src[0]);
1618 if (const_offset) {
1619 idx += const_offset->u32[0];
1620 for (int i = 0; i < intr->num_components; i++) {
1621 unsigned n = idx * 4 + i;
1622 dst[i] = create_uniform(b, n);
1623 }
1624 } else {
1625 src = ir3_get_src(ctx, &intr->src[0]);
1626 for (int i = 0; i < intr->num_components; i++) {
1627 int n = idx * 4 + i;
1628 dst[i] = create_uniform_indirect(b, n,
1629 ir3_get_addr(ctx, src[0], 4));
1630 }
1631 /* NOTE: if relative addressing is used, we set
1632 * constlen in the compiler (to worst-case value)
1633 * since we don't know in the assembler what the max
1634 * addr reg value can be:
1635 */
1636 ctx->so->constlen = ctx->s->num_uniforms;
1637 }
1638 break;
1639 case nir_intrinsic_load_ubo:
1640 emit_intrinsic_load_ubo(ctx, intr, dst);
1641 break;
1642 case nir_intrinsic_load_input:
1643 idx = nir_intrinsic_base(intr);
1644 comp = nir_intrinsic_component(intr);
1645 const_offset = nir_src_as_const_value(intr->src[0]);
1646 if (const_offset) {
1647 idx += const_offset->u32[0];
1648 for (int i = 0; i < intr->num_components; i++) {
1649 unsigned n = idx * 4 + i + comp;
1650 dst[i] = ctx->ir->inputs[n];
1651 }
1652 } else {
1653 src = ir3_get_src(ctx, &intr->src[0]);
1654 struct ir3_instruction *collect =
1655 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ir->ninputs);
1656 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1657 for (int i = 0; i < intr->num_components; i++) {
1658 unsigned n = idx * 4 + i + comp;
1659 dst[i] = create_indirect_load(ctx, ctx->ir->ninputs,
1660 n, addr, collect);
1661 }
1662 }
1663 break;
1664 case nir_intrinsic_load_ssbo:
1665 emit_intrinsic_load_ssbo(ctx, intr, dst);
1666 break;
1667 case nir_intrinsic_store_ssbo:
1668 emit_intrinsic_store_ssbo(ctx, intr);
1669 break;
1670 case nir_intrinsic_get_buffer_size:
1671 emit_intrinsic_ssbo_size(ctx, intr, dst);
1672 break;
1673 case nir_intrinsic_ssbo_atomic_add:
1674 case nir_intrinsic_ssbo_atomic_imin:
1675 case nir_intrinsic_ssbo_atomic_umin:
1676 case nir_intrinsic_ssbo_atomic_imax:
1677 case nir_intrinsic_ssbo_atomic_umax:
1678 case nir_intrinsic_ssbo_atomic_and:
1679 case nir_intrinsic_ssbo_atomic_or:
1680 case nir_intrinsic_ssbo_atomic_xor:
1681 case nir_intrinsic_ssbo_atomic_exchange:
1682 case nir_intrinsic_ssbo_atomic_comp_swap:
1683 dst[0] = emit_intrinsic_atomic_ssbo(ctx, intr);
1684 break;
1685 case nir_intrinsic_load_shared:
1686 emit_intrinsic_load_shared(ctx, intr, dst);
1687 break;
1688 case nir_intrinsic_store_shared:
1689 emit_intrinsic_store_shared(ctx, intr);
1690 break;
1691 case nir_intrinsic_shared_atomic_add:
1692 case nir_intrinsic_shared_atomic_imin:
1693 case nir_intrinsic_shared_atomic_umin:
1694 case nir_intrinsic_shared_atomic_imax:
1695 case nir_intrinsic_shared_atomic_umax:
1696 case nir_intrinsic_shared_atomic_and:
1697 case nir_intrinsic_shared_atomic_or:
1698 case nir_intrinsic_shared_atomic_xor:
1699 case nir_intrinsic_shared_atomic_exchange:
1700 case nir_intrinsic_shared_atomic_comp_swap:
1701 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1702 break;
1703 case nir_intrinsic_image_deref_load:
1704 emit_intrinsic_load_image(ctx, intr, dst);
1705 break;
1706 case nir_intrinsic_image_deref_store:
1707 emit_intrinsic_store_image(ctx, intr);
1708 break;
1709 case nir_intrinsic_image_deref_size:
1710 emit_intrinsic_image_size(ctx, intr, dst);
1711 break;
1712 case nir_intrinsic_image_deref_atomic_add:
1713 case nir_intrinsic_image_deref_atomic_min:
1714 case nir_intrinsic_image_deref_atomic_max:
1715 case nir_intrinsic_image_deref_atomic_and:
1716 case nir_intrinsic_image_deref_atomic_or:
1717 case nir_intrinsic_image_deref_atomic_xor:
1718 case nir_intrinsic_image_deref_atomic_exchange:
1719 case nir_intrinsic_image_deref_atomic_comp_swap:
1720 dst[0] = emit_intrinsic_atomic_image(ctx, intr);
1721 break;
1722 case nir_intrinsic_barrier:
1723 case nir_intrinsic_memory_barrier:
1724 case nir_intrinsic_group_memory_barrier:
1725 case nir_intrinsic_memory_barrier_atomic_counter:
1726 case nir_intrinsic_memory_barrier_buffer:
1727 case nir_intrinsic_memory_barrier_image:
1728 case nir_intrinsic_memory_barrier_shared:
1729 emit_intrinsic_barrier(ctx, intr);
1730 /* note that blk ptr no longer valid, make that obvious: */
1731 b = NULL;
1732 break;
1733 case nir_intrinsic_store_output:
1734 idx = nir_intrinsic_base(intr);
1735 comp = nir_intrinsic_component(intr);
1736 const_offset = nir_src_as_const_value(intr->src[1]);
1737 compile_assert(ctx, const_offset != NULL);
1738 idx += const_offset->u32[0];
1739
1740 src = ir3_get_src(ctx, &intr->src[0]);
1741 for (int i = 0; i < intr->num_components; i++) {
1742 unsigned n = idx * 4 + i + comp;
1743 ctx->ir->outputs[n] = src[i];
1744 }
1745 break;
1746 case nir_intrinsic_load_base_vertex:
1747 case nir_intrinsic_load_first_vertex:
1748 if (!ctx->basevertex) {
1749 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1750 add_sysval_input(ctx, SYSTEM_VALUE_FIRST_VERTEX, ctx->basevertex);
1751 }
1752 dst[0] = ctx->basevertex;
1753 break;
1754 case nir_intrinsic_load_vertex_id_zero_base:
1755 case nir_intrinsic_load_vertex_id:
1756 if (!ctx->vertex_id) {
1757 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1758 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1759 ctx->vertex_id = create_input(ctx, 0);
1760 add_sysval_input(ctx, sv, ctx->vertex_id);
1761 }
1762 dst[0] = ctx->vertex_id;
1763 break;
1764 case nir_intrinsic_load_instance_id:
1765 if (!ctx->instance_id) {
1766 ctx->instance_id = create_input(ctx, 0);
1767 add_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID,
1768 ctx->instance_id);
1769 }
1770 dst[0] = ctx->instance_id;
1771 break;
1772 case nir_intrinsic_load_sample_id:
1773 case nir_intrinsic_load_sample_id_no_per_sample:
1774 if (!ctx->samp_id) {
1775 ctx->samp_id = create_input(ctx, 0);
1776 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1777 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID,
1778 ctx->samp_id);
1779 }
1780 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1781 break;
1782 case nir_intrinsic_load_sample_mask_in:
1783 if (!ctx->samp_mask_in) {
1784 ctx->samp_mask_in = create_input(ctx, 0);
1785 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN,
1786 ctx->samp_mask_in);
1787 }
1788 dst[0] = ctx->samp_mask_in;
1789 break;
1790 case nir_intrinsic_load_user_clip_plane:
1791 idx = nir_intrinsic_ucp_id(intr);
1792 for (int i = 0; i < intr->num_components; i++) {
1793 unsigned n = idx * 4 + i;
1794 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1795 }
1796 break;
1797 case nir_intrinsic_load_front_face:
1798 if (!ctx->frag_face) {
1799 ctx->so->frag_face = true;
1800 ctx->frag_face = create_input(ctx, 0);
1801 add_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, ctx->frag_face);
1802 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1803 }
1804 /* for fragface, we get -1 for back and 0 for front. However this is
1805 * the inverse of what nir expects (where ~0 is true).
1806 */
1807 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1808 dst[0] = ir3_NOT_B(b, dst[0], 0);
1809 break;
1810 case nir_intrinsic_load_local_invocation_id:
1811 if (!ctx->local_invocation_id) {
1812 ctx->local_invocation_id = create_input_compmask(ctx, 0, 0x7);
1813 add_sysval_input_compmask(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID,
1814 0x7, ctx->local_invocation_id);
1815 }
1816 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1817 break;
1818 case nir_intrinsic_load_work_group_id:
1819 if (!ctx->work_group_id) {
1820 ctx->work_group_id = create_input_compmask(ctx, 0, 0x7);
1821 add_sysval_input_compmask(ctx, SYSTEM_VALUE_WORK_GROUP_ID,
1822 0x7, ctx->work_group_id);
1823 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1824 }
1825 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1826 break;
1827 case nir_intrinsic_load_num_work_groups:
1828 for (int i = 0; i < intr->num_components; i++) {
1829 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1830 }
1831 break;
1832 case nir_intrinsic_load_local_group_size:
1833 for (int i = 0; i < intr->num_components; i++) {
1834 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1835 }
1836 break;
1837 case nir_intrinsic_discard_if:
1838 case nir_intrinsic_discard: {
1839 struct ir3_instruction *cond, *kill;
1840
1841 if (intr->intrinsic == nir_intrinsic_discard_if) {
1842 /* conditional discard: */
1843 src = ir3_get_src(ctx, &intr->src[0]);
1844 cond = ir3_b2n(b, src[0]);
1845 } else {
1846 /* unconditional discard: */
1847 cond = create_immed(b, 1);
1848 }
1849
1850 /* NOTE: only cmps.*.* can write p0.x: */
1851 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1852 cond->cat2.condition = IR3_COND_NE;
1853
1854 /* condition always goes in predicate register: */
1855 cond->regs[0]->num = regid(REG_P0, 0);
1856
1857 kill = ir3_KILL(b, cond, 0);
1858 array_insert(ctx->ir, ctx->ir->predicates, kill);
1859
1860 array_insert(b, b->keeps, kill);
1861 ctx->so->has_kill = true;
1862
1863 break;
1864 }
1865 default:
1866 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1867 nir_intrinsic_infos[intr->intrinsic].name);
1868 break;
1869 }
1870
1871 if (info->has_dest)
1872 put_dst(ctx, &intr->dest);
1873 }
1874
1875 static void
1876 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1877 {
1878 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1879 instr->def.num_components);
1880 type_t type = (instr->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1881
1882 for (int i = 0; i < instr->def.num_components; i++)
1883 dst[i] = create_immed_typed(ctx->block, instr->value.u32[i], type);
1884 }
1885
1886 static void
1887 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1888 {
1889 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1890 undef->def.num_components);
1891 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1892
1893 /* backend doesn't want undefined instructions, so just plug
1894 * in 0.0..
1895 */
1896 for (int i = 0; i < undef->def.num_components; i++)
1897 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1898 }
1899
1900 /*
1901 * texture fetch/sample instructions:
1902 */
1903
1904 static void
1905 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1906 {
1907 unsigned coords, flags = 0;
1908
1909 /* note: would use tex->coord_components.. except txs.. also,
1910 * since array index goes after shadow ref, we don't want to
1911 * count it:
1912 */
1913 switch (tex->sampler_dim) {
1914 case GLSL_SAMPLER_DIM_1D:
1915 case GLSL_SAMPLER_DIM_BUF:
1916 coords = 1;
1917 break;
1918 case GLSL_SAMPLER_DIM_2D:
1919 case GLSL_SAMPLER_DIM_RECT:
1920 case GLSL_SAMPLER_DIM_EXTERNAL:
1921 case GLSL_SAMPLER_DIM_MS:
1922 coords = 2;
1923 break;
1924 case GLSL_SAMPLER_DIM_3D:
1925 case GLSL_SAMPLER_DIM_CUBE:
1926 coords = 3;
1927 flags |= IR3_INSTR_3D;
1928 break;
1929 default:
1930 unreachable("bad sampler_dim");
1931 }
1932
1933 if (tex->is_shadow && tex->op != nir_texop_lod)
1934 flags |= IR3_INSTR_S;
1935
1936 if (tex->is_array && tex->op != nir_texop_lod)
1937 flags |= IR3_INSTR_A;
1938
1939 *flagsp = flags;
1940 *coordsp = coords;
1941 }
1942
1943 static void
1944 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1945 {
1946 struct ir3_block *b = ctx->block;
1947 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1948 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1949 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1950 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1951 unsigned i, coords, flags;
1952 unsigned nsrc0 = 0, nsrc1 = 0;
1953 type_t type;
1954 opc_t opc = 0;
1955
1956 coord = off = ddx = ddy = NULL;
1957 lod = proj = compare = sample_index = NULL;
1958
1959 /* TODO: might just be one component for gathers? */
1960 dst = ir3_get_dst(ctx, &tex->dest, 4);
1961
1962 for (unsigned i = 0; i < tex->num_srcs; i++) {
1963 switch (tex->src[i].src_type) {
1964 case nir_tex_src_coord:
1965 coord = ir3_get_src(ctx, &tex->src[i].src);
1966 break;
1967 case nir_tex_src_bias:
1968 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1969 has_bias = true;
1970 break;
1971 case nir_tex_src_lod:
1972 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1973 has_lod = true;
1974 break;
1975 case nir_tex_src_comparator: /* shadow comparator */
1976 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1977 break;
1978 case nir_tex_src_projector:
1979 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1980 has_proj = true;
1981 break;
1982 case nir_tex_src_offset:
1983 off = ir3_get_src(ctx, &tex->src[i].src);
1984 has_off = true;
1985 break;
1986 case nir_tex_src_ddx:
1987 ddx = ir3_get_src(ctx, &tex->src[i].src);
1988 break;
1989 case nir_tex_src_ddy:
1990 ddy = ir3_get_src(ctx, &tex->src[i].src);
1991 break;
1992 case nir_tex_src_ms_index:
1993 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
1994 break;
1995 default:
1996 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
1997 tex->src[i].src_type);
1998 return;
1999 }
2000 }
2001
2002 switch (tex->op) {
2003 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
2004 case nir_texop_txb: opc = OPC_SAMB; break;
2005 case nir_texop_txl: opc = OPC_SAML; break;
2006 case nir_texop_txd: opc = OPC_SAMGQ; break;
2007 case nir_texop_txf: opc = OPC_ISAML; break;
2008 case nir_texop_lod: opc = OPC_GETLOD; break;
2009 case nir_texop_tg4:
2010 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2011 * what blob does, seems gather is broken?), and a3xx did
2012 * not support it (but probably could also emulate).
2013 */
2014 switch (tex->component) {
2015 case 0: opc = OPC_GATHER4R; break;
2016 case 1: opc = OPC_GATHER4G; break;
2017 case 2: opc = OPC_GATHER4B; break;
2018 case 3: opc = OPC_GATHER4A; break;
2019 }
2020 break;
2021 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2022 case nir_texop_txs:
2023 case nir_texop_query_levels:
2024 case nir_texop_texture_samples:
2025 case nir_texop_samples_identical:
2026 case nir_texop_txf_ms_mcs:
2027 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2028 return;
2029 }
2030
2031 tex_info(tex, &flags, &coords);
2032
2033 /*
2034 * lay out the first argument in the proper order:
2035 * - actual coordinates first
2036 * - shadow reference
2037 * - array index
2038 * - projection w
2039 * - starting at offset 4, dpdx.xy, dpdy.xy
2040 *
2041 * bias/lod go into the second arg
2042 */
2043
2044 /* insert tex coords: */
2045 for (i = 0; i < coords; i++)
2046 src0[i] = coord[i];
2047
2048 nsrc0 = i;
2049
2050 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2051 * with scaled x coord according to requested sample:
2052 */
2053 if (tex->op == nir_texop_txf_ms) {
2054 if (ctx->compiler->txf_ms_with_isaml) {
2055 /* the samples are laid out in x dimension as
2056 * 0 1 2 3
2057 * x_ms = (x << ms) + sample_index;
2058 */
2059 struct ir3_instruction *ms;
2060 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2061
2062 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2063 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2064
2065 opc = OPC_ISAML;
2066 } else {
2067 src0[nsrc0++] = sample_index;
2068 }
2069 }
2070
2071 /* scale up integer coords for TXF based on the LOD */
2072 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2073 assert(has_lod);
2074 for (i = 0; i < coords; i++)
2075 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2076 }
2077
2078 if (coords == 1) {
2079 /* hw doesn't do 1d, so we treat it as 2d with
2080 * height of 1, and patch up the y coord.
2081 * TODO: y coord should be (int)0 in some cases..
2082 */
2083 src0[nsrc0++] = create_immed(b, fui(0.5));
2084 }
2085
2086 if (tex->is_shadow && tex->op != nir_texop_lod)
2087 src0[nsrc0++] = compare;
2088
2089 if (tex->is_array && tex->op != nir_texop_lod) {
2090 struct ir3_instruction *idx = coord[coords];
2091
2092 /* the array coord for cube arrays needs 0.5 added to it */
2093 if (ctx->compiler->array_index_add_half && (opc != OPC_ISAML))
2094 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2095
2096 src0[nsrc0++] = idx;
2097 }
2098
2099 if (has_proj) {
2100 src0[nsrc0++] = proj;
2101 flags |= IR3_INSTR_P;
2102 }
2103
2104 /* pad to 4, then ddx/ddy: */
2105 if (tex->op == nir_texop_txd) {
2106 while (nsrc0 < 4)
2107 src0[nsrc0++] = create_immed(b, fui(0.0));
2108 for (i = 0; i < coords; i++)
2109 src0[nsrc0++] = ddx[i];
2110 if (coords < 2)
2111 src0[nsrc0++] = create_immed(b, fui(0.0));
2112 for (i = 0; i < coords; i++)
2113 src0[nsrc0++] = ddy[i];
2114 if (coords < 2)
2115 src0[nsrc0++] = create_immed(b, fui(0.0));
2116 }
2117
2118 /*
2119 * second argument (if applicable):
2120 * - offsets
2121 * - lod
2122 * - bias
2123 */
2124 if (has_off | has_lod | has_bias) {
2125 if (has_off) {
2126 unsigned off_coords = coords;
2127 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2128 off_coords--;
2129 for (i = 0; i < off_coords; i++)
2130 src1[nsrc1++] = off[i];
2131 if (off_coords < 2)
2132 src1[nsrc1++] = create_immed(b, fui(0.0));
2133 flags |= IR3_INSTR_O;
2134 }
2135
2136 if (has_lod | has_bias)
2137 src1[nsrc1++] = lod;
2138 }
2139
2140 switch (tex->dest_type) {
2141 case nir_type_invalid:
2142 case nir_type_float:
2143 type = TYPE_F32;
2144 break;
2145 case nir_type_int:
2146 type = TYPE_S32;
2147 break;
2148 case nir_type_uint:
2149 case nir_type_bool:
2150 type = TYPE_U32;
2151 break;
2152 default:
2153 unreachable("bad dest_type");
2154 }
2155
2156 if (opc == OPC_GETLOD)
2157 type = TYPE_U32;
2158
2159 unsigned tex_idx = tex->texture_index;
2160
2161 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex_idx);
2162
2163 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2164 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2165
2166 sam = ir3_SAM(b, opc, type, 0b1111, flags,
2167 tex_idx, tex_idx, col0, col1);
2168
2169 if ((ctx->astc_srgb & (1 << tex_idx)) && !nir_tex_instr_is_query(tex)) {
2170 /* only need first 3 components: */
2171 sam->regs[0]->wrmask = 0x7;
2172 ir3_split_dest(b, dst, sam, 0, 3);
2173
2174 /* we need to sample the alpha separately with a non-ASTC
2175 * texture state:
2176 */
2177 sam = ir3_SAM(b, opc, type, 0b1000, flags,
2178 tex_idx, tex_idx, col0, col1);
2179
2180 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2181
2182 /* fixup .w component: */
2183 ir3_split_dest(b, &dst[3], sam, 3, 1);
2184 } else {
2185 /* normal (non-workaround) case: */
2186 ir3_split_dest(b, dst, sam, 0, 4);
2187 }
2188
2189 /* GETLOD returns results in 4.8 fixed point */
2190 if (opc == OPC_GETLOD) {
2191 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2192
2193 compile_assert(ctx, tex->dest_type == nir_type_float);
2194 for (i = 0; i < 2; i++) {
2195 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_U32, TYPE_F32), 0,
2196 factor, 0);
2197 }
2198 }
2199
2200 put_dst(ctx, &tex->dest);
2201 }
2202
2203 static void
2204 emit_tex_query_levels(struct ir3_context *ctx, nir_tex_instr *tex)
2205 {
2206 struct ir3_block *b = ctx->block;
2207 struct ir3_instruction **dst, *sam;
2208
2209 dst = ir3_get_dst(ctx, &tex->dest, 1);
2210
2211 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, 0b0100, 0,
2212 tex->texture_index, tex->texture_index, NULL, NULL);
2213
2214 /* even though there is only one component, since it ends
2215 * up in .z rather than .x, we need a split_dest()
2216 */
2217 ir3_split_dest(b, dst, sam, 0, 3);
2218
2219 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2220 * the value in TEX_CONST_0 is zero-based.
2221 */
2222 if (ctx->compiler->levels_add_one)
2223 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2224
2225 put_dst(ctx, &tex->dest);
2226 }
2227
2228 static void
2229 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2230 {
2231 struct ir3_block *b = ctx->block;
2232 struct ir3_instruction **dst, *sam;
2233 struct ir3_instruction *lod;
2234 unsigned flags, coords;
2235
2236 tex_info(tex, &flags, &coords);
2237
2238 /* Actually we want the number of dimensions, not coordinates. This
2239 * distinction only matters for cubes.
2240 */
2241 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2242 coords = 2;
2243
2244 dst = ir3_get_dst(ctx, &tex->dest, 4);
2245
2246 compile_assert(ctx, tex->num_srcs == 1);
2247 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2248
2249 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2250
2251 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
2252 tex->texture_index, tex->texture_index, lod, NULL);
2253
2254 ir3_split_dest(b, dst, sam, 0, 4);
2255
2256 /* Array size actually ends up in .w rather than .z. This doesn't
2257 * matter for miplevel 0, but for higher mips the value in z is
2258 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2259 * returned, which means that we have to add 1 to it for arrays.
2260 */
2261 if (tex->is_array) {
2262 if (ctx->compiler->levels_add_one) {
2263 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2264 } else {
2265 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2266 }
2267 }
2268
2269 put_dst(ctx, &tex->dest);
2270 }
2271
2272 static void
2273 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2274 {
2275 switch (jump->type) {
2276 case nir_jump_break:
2277 case nir_jump_continue:
2278 case nir_jump_return:
2279 /* I *think* we can simply just ignore this, and use the
2280 * successor block link to figure out where we need to
2281 * jump to for break/continue
2282 */
2283 break;
2284 default:
2285 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2286 break;
2287 }
2288 }
2289
2290 static void
2291 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2292 {
2293 switch (instr->type) {
2294 case nir_instr_type_alu:
2295 emit_alu(ctx, nir_instr_as_alu(instr));
2296 break;
2297 case nir_instr_type_deref:
2298 /* ignored, handled as part of the intrinsic they are src to */
2299 break;
2300 case nir_instr_type_intrinsic:
2301 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2302 break;
2303 case nir_instr_type_load_const:
2304 emit_load_const(ctx, nir_instr_as_load_const(instr));
2305 break;
2306 case nir_instr_type_ssa_undef:
2307 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2308 break;
2309 case nir_instr_type_tex: {
2310 nir_tex_instr *tex = nir_instr_as_tex(instr);
2311 /* couple tex instructions get special-cased:
2312 */
2313 switch (tex->op) {
2314 case nir_texop_txs:
2315 emit_tex_txs(ctx, tex);
2316 break;
2317 case nir_texop_query_levels:
2318 emit_tex_query_levels(ctx, tex);
2319 break;
2320 default:
2321 emit_tex(ctx, tex);
2322 break;
2323 }
2324 break;
2325 }
2326 case nir_instr_type_jump:
2327 emit_jump(ctx, nir_instr_as_jump(instr));
2328 break;
2329 case nir_instr_type_phi:
2330 /* we have converted phi webs to regs in NIR by now */
2331 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2332 break;
2333 case nir_instr_type_call:
2334 case nir_instr_type_parallel_copy:
2335 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2336 break;
2337 }
2338 }
2339
2340 static struct ir3_block *
2341 get_block(struct ir3_context *ctx, const nir_block *nblock)
2342 {
2343 struct ir3_block *block;
2344 struct hash_entry *hentry;
2345 unsigned i;
2346
2347 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2348 if (hentry)
2349 return hentry->data;
2350
2351 block = ir3_block_create(ctx->ir);
2352 block->nblock = nblock;
2353 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2354
2355 block->predecessors_count = nblock->predecessors->entries;
2356 block->predecessors = ralloc_array_size(block,
2357 sizeof(block->predecessors[0]), block->predecessors_count);
2358 i = 0;
2359 set_foreach(nblock->predecessors, sentry) {
2360 block->predecessors[i++] = get_block(ctx, sentry->key);
2361 }
2362
2363 return block;
2364 }
2365
2366 static void
2367 emit_block(struct ir3_context *ctx, nir_block *nblock)
2368 {
2369 struct ir3_block *block = get_block(ctx, nblock);
2370
2371 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2372 if (nblock->successors[i]) {
2373 block->successors[i] =
2374 get_block(ctx, nblock->successors[i]);
2375 }
2376 }
2377
2378 ctx->block = block;
2379 list_addtail(&block->node, &ctx->ir->block_list);
2380
2381 /* re-emit addr register in each block if needed: */
2382 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2383 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2384 ctx->addr_ht[i] = NULL;
2385 }
2386
2387 nir_foreach_instr(instr, nblock) {
2388 ctx->cur_instr = instr;
2389 emit_instr(ctx, instr);
2390 ctx->cur_instr = NULL;
2391 if (ctx->error)
2392 return;
2393 }
2394 }
2395
2396 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2397
2398 static void
2399 emit_if(struct ir3_context *ctx, nir_if *nif)
2400 {
2401 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2402
2403 ctx->block->condition =
2404 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2405
2406 emit_cf_list(ctx, &nif->then_list);
2407 emit_cf_list(ctx, &nif->else_list);
2408 }
2409
2410 static void
2411 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2412 {
2413 emit_cf_list(ctx, &nloop->body);
2414 }
2415
2416 static void
2417 stack_push(struct ir3_context *ctx)
2418 {
2419 ctx->stack++;
2420 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2421 }
2422
2423 static void
2424 stack_pop(struct ir3_context *ctx)
2425 {
2426 compile_assert(ctx, ctx->stack > 0);
2427 ctx->stack--;
2428 }
2429
2430 static void
2431 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2432 {
2433 foreach_list_typed(nir_cf_node, node, node, list) {
2434 switch (node->type) {
2435 case nir_cf_node_block:
2436 emit_block(ctx, nir_cf_node_as_block(node));
2437 break;
2438 case nir_cf_node_if:
2439 stack_push(ctx);
2440 emit_if(ctx, nir_cf_node_as_if(node));
2441 stack_pop(ctx);
2442 break;
2443 case nir_cf_node_loop:
2444 stack_push(ctx);
2445 emit_loop(ctx, nir_cf_node_as_loop(node));
2446 stack_pop(ctx);
2447 break;
2448 case nir_cf_node_function:
2449 ir3_context_error(ctx, "TODO\n");
2450 break;
2451 }
2452 }
2453 }
2454
2455 /* emit stream-out code. At this point, the current block is the original
2456 * (nir) end block, and nir ensures that all flow control paths terminate
2457 * into the end block. We re-purpose the original end block to generate
2458 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2459 * block holding stream-out write instructions, followed by the new end
2460 * block:
2461 *
2462 * blockOrigEnd {
2463 * p0.x = (vtxcnt < maxvtxcnt)
2464 * // succs: blockStreamOut, blockNewEnd
2465 * }
2466 * blockStreamOut {
2467 * ... stream-out instructions ...
2468 * // succs: blockNewEnd
2469 * }
2470 * blockNewEnd {
2471 * }
2472 */
2473 static void
2474 emit_stream_out(struct ir3_context *ctx)
2475 {
2476 struct ir3_shader_variant *v = ctx->so;
2477 struct ir3 *ir = ctx->ir;
2478 struct ir3_stream_output_info *strmout =
2479 &ctx->so->shader->stream_output;
2480 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2481 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2482 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2483
2484 /* create vtxcnt input in input block at top of shader,
2485 * so that it is seen as live over the entire duration
2486 * of the shader:
2487 */
2488 vtxcnt = create_input(ctx, 0);
2489 add_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, vtxcnt);
2490
2491 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2492
2493 /* at this point, we are at the original 'end' block,
2494 * re-purpose this block to stream-out condition, then
2495 * append stream-out block and new-end block
2496 */
2497 orig_end_block = ctx->block;
2498
2499 // TODO these blocks need to update predecessors..
2500 // maybe w/ store_global intrinsic, we could do this
2501 // stuff in nir->nir pass
2502
2503 stream_out_block = ir3_block_create(ir);
2504 list_addtail(&stream_out_block->node, &ir->block_list);
2505
2506 new_end_block = ir3_block_create(ir);
2507 list_addtail(&new_end_block->node, &ir->block_list);
2508
2509 orig_end_block->successors[0] = stream_out_block;
2510 orig_end_block->successors[1] = new_end_block;
2511 stream_out_block->successors[0] = new_end_block;
2512
2513 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2514 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2515 cond->regs[0]->num = regid(REG_P0, 0);
2516 cond->cat2.condition = IR3_COND_LT;
2517
2518 /* condition goes on previous block to the conditional,
2519 * since it is used to pick which of the two successor
2520 * paths to take:
2521 */
2522 orig_end_block->condition = cond;
2523
2524 /* switch to stream_out_block to generate the stream-out
2525 * instructions:
2526 */
2527 ctx->block = stream_out_block;
2528
2529 /* Calculate base addresses based on vtxcnt. Instructions
2530 * generated for bases not used in following loop will be
2531 * stripped out in the backend.
2532 */
2533 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2534 unsigned stride = strmout->stride[i];
2535 struct ir3_instruction *base, *off;
2536
2537 base = create_uniform(ctx->block, regid(v->constbase.tfbo, i));
2538
2539 /* 24-bit should be enough: */
2540 off = ir3_MUL_U(ctx->block, vtxcnt, 0,
2541 create_immed(ctx->block, stride * 4), 0);
2542
2543 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2544 }
2545
2546 /* Generate the per-output store instructions: */
2547 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2548 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2549 unsigned c = j + strmout->output[i].start_component;
2550 struct ir3_instruction *base, *out, *stg;
2551
2552 base = bases[strmout->output[i].output_buffer];
2553 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2554
2555 stg = ir3_STG(ctx->block, base, 0, out, 0,
2556 create_immed(ctx->block, 1), 0);
2557 stg->cat6.type = TYPE_U32;
2558 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2559
2560 array_insert(ctx->block, ctx->block->keeps, stg);
2561 }
2562 }
2563
2564 /* and finally switch to the new_end_block: */
2565 ctx->block = new_end_block;
2566 }
2567
2568 static void
2569 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2570 {
2571 nir_metadata_require(impl, nir_metadata_block_index);
2572
2573 compile_assert(ctx, ctx->stack == 0);
2574
2575 emit_cf_list(ctx, &impl->body);
2576 emit_block(ctx, impl->end_block);
2577
2578 compile_assert(ctx, ctx->stack == 0);
2579
2580 /* at this point, we should have a single empty block,
2581 * into which we emit the 'end' instruction.
2582 */
2583 compile_assert(ctx, list_empty(&ctx->block->instr_list));
2584
2585 /* If stream-out (aka transform-feedback) enabled, emit the
2586 * stream-out instructions, followed by a new empty block (into
2587 * which the 'end' instruction lands).
2588 *
2589 * NOTE: it is done in this order, rather than inserting before
2590 * we emit end_block, because NIR guarantees that all blocks
2591 * flow into end_block, and that end_block has no successors.
2592 * So by re-purposing end_block as the first block of stream-
2593 * out, we guarantee that all exit paths flow into the stream-
2594 * out instructions.
2595 */
2596 if ((ctx->compiler->gpu_id < 500) &&
2597 (ctx->so->shader->stream_output.num_outputs > 0) &&
2598 !ctx->so->binning_pass) {
2599 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2600 emit_stream_out(ctx);
2601 }
2602
2603 ir3_END(ctx->block);
2604 }
2605
2606 static struct ir3_instruction *
2607 create_frag_coord(struct ir3_context *ctx, unsigned comp)
2608 {
2609 struct ir3_block *block = ctx->block;
2610 struct ir3_instruction *instr;
2611
2612 if (!ctx->frag_coord) {
2613 ctx->frag_coord = create_input_compmask(ctx, 0, 0xf);
2614 /* defer add_sysval_input() until after all inputs created */
2615 }
2616
2617 ir3_split_dest(block, &instr, ctx->frag_coord, comp, 1);
2618
2619 switch (comp) {
2620 case 0: /* .x */
2621 case 1: /* .y */
2622 /* for frag_coord, we get unsigned values.. we need
2623 * to subtract (integer) 8 and divide by 16 (right-
2624 * shift by 4) then convert to float:
2625 *
2626 * sub.s tmp, src, 8
2627 * shr.b tmp, tmp, 4
2628 * mov.u32f32 dst, tmp
2629 *
2630 */
2631 instr = ir3_SUB_S(block, instr, 0,
2632 create_immed(block, 8), 0);
2633 instr = ir3_SHR_B(block, instr, 0,
2634 create_immed(block, 4), 0);
2635 instr = ir3_COV(block, instr, TYPE_U32, TYPE_F32);
2636
2637 return instr;
2638 case 2: /* .z */
2639 case 3: /* .w */
2640 default:
2641 /* seems that we can use these as-is: */
2642 return instr;
2643 }
2644 }
2645
2646 static void
2647 setup_input(struct ir3_context *ctx, nir_variable *in)
2648 {
2649 struct ir3_shader_variant *so = ctx->so;
2650 unsigned ncomp = glsl_get_components(in->type);
2651 unsigned n = in->data.driver_location;
2652 unsigned slot = in->data.location;
2653
2654 /* let's pretend things other than vec4 don't exist: */
2655 ncomp = MAX2(ncomp, 4);
2656
2657 /* skip unread inputs, we could end up with (for example), unsplit
2658 * matrix/etc inputs in the case they are not read, so just silently
2659 * skip these.
2660 */
2661 if (ncomp > 4)
2662 return;
2663
2664 compile_assert(ctx, ncomp == 4);
2665
2666 so->inputs[n].slot = slot;
2667 so->inputs[n].compmask = (1 << ncomp) - 1;
2668 so->inputs_count = MAX2(so->inputs_count, n + 1);
2669 so->inputs[n].interpolate = in->data.interpolation;
2670
2671 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2672 for (int i = 0; i < ncomp; i++) {
2673 struct ir3_instruction *instr = NULL;
2674 unsigned idx = (n * 4) + i;
2675
2676 if (slot == VARYING_SLOT_POS) {
2677 so->inputs[n].bary = false;
2678 so->frag_coord = true;
2679 instr = create_frag_coord(ctx, i);
2680 } else if (slot == VARYING_SLOT_PNTC) {
2681 /* see for example st_nir_fixup_varying_slots().. this is
2682 * maybe a bit mesa/st specific. But we need things to line
2683 * up for this in fdN_program:
2684 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2685 * if (emit->sprite_coord_enable & texmask) {
2686 * ...
2687 * }
2688 */
2689 so->inputs[n].slot = VARYING_SLOT_VAR8;
2690 so->inputs[n].bary = true;
2691 instr = create_frag_input(ctx, false);
2692 } else {
2693 bool use_ldlv = false;
2694
2695 /* detect the special case for front/back colors where
2696 * we need to do flat vs smooth shading depending on
2697 * rast state:
2698 */
2699 if (in->data.interpolation == INTERP_MODE_NONE) {
2700 switch (slot) {
2701 case VARYING_SLOT_COL0:
2702 case VARYING_SLOT_COL1:
2703 case VARYING_SLOT_BFC0:
2704 case VARYING_SLOT_BFC1:
2705 so->inputs[n].rasterflat = true;
2706 break;
2707 default:
2708 break;
2709 }
2710 }
2711
2712 if (ctx->compiler->flat_bypass) {
2713 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2714 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2715 use_ldlv = true;
2716 }
2717
2718 so->inputs[n].bary = true;
2719
2720 instr = create_frag_input(ctx, use_ldlv);
2721 }
2722
2723 compile_assert(ctx, idx < ctx->ir->ninputs);
2724
2725 ctx->ir->inputs[idx] = instr;
2726 }
2727 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2728 for (int i = 0; i < ncomp; i++) {
2729 unsigned idx = (n * 4) + i;
2730 compile_assert(ctx, idx < ctx->ir->ninputs);
2731 ctx->ir->inputs[idx] = create_input(ctx, idx);
2732 }
2733 } else {
2734 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2735 }
2736
2737 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2738 so->total_in += ncomp;
2739 }
2740 }
2741
2742 static void
2743 setup_output(struct ir3_context *ctx, nir_variable *out)
2744 {
2745 struct ir3_shader_variant *so = ctx->so;
2746 unsigned ncomp = glsl_get_components(out->type);
2747 unsigned n = out->data.driver_location;
2748 unsigned slot = out->data.location;
2749 unsigned comp = 0;
2750
2751 /* let's pretend things other than vec4 don't exist: */
2752 ncomp = MAX2(ncomp, 4);
2753 compile_assert(ctx, ncomp == 4);
2754
2755 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2756 switch (slot) {
2757 case FRAG_RESULT_DEPTH:
2758 comp = 2; /* tgsi will write to .z component */
2759 so->writes_pos = true;
2760 break;
2761 case FRAG_RESULT_COLOR:
2762 so->color0_mrt = 1;
2763 break;
2764 default:
2765 if (slot >= FRAG_RESULT_DATA0)
2766 break;
2767 ir3_context_error(ctx, "unknown FS output name: %s\n",
2768 gl_frag_result_name(slot));
2769 }
2770 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2771 switch (slot) {
2772 case VARYING_SLOT_POS:
2773 so->writes_pos = true;
2774 break;
2775 case VARYING_SLOT_PSIZ:
2776 so->writes_psize = true;
2777 break;
2778 case VARYING_SLOT_COL0:
2779 case VARYING_SLOT_COL1:
2780 case VARYING_SLOT_BFC0:
2781 case VARYING_SLOT_BFC1:
2782 case VARYING_SLOT_FOGC:
2783 case VARYING_SLOT_CLIP_DIST0:
2784 case VARYING_SLOT_CLIP_DIST1:
2785 case VARYING_SLOT_CLIP_VERTEX:
2786 break;
2787 default:
2788 if (slot >= VARYING_SLOT_VAR0)
2789 break;
2790 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2791 break;
2792 ir3_context_error(ctx, "unknown VS output name: %s\n",
2793 gl_varying_slot_name(slot));
2794 }
2795 } else {
2796 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2797 }
2798
2799 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2800
2801 so->outputs[n].slot = slot;
2802 so->outputs[n].regid = regid(n, comp);
2803 so->outputs_count = MAX2(so->outputs_count, n + 1);
2804
2805 for (int i = 0; i < ncomp; i++) {
2806 unsigned idx = (n * 4) + i;
2807 compile_assert(ctx, idx < ctx->ir->noutputs);
2808 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2809 }
2810 }
2811
2812 static int
2813 max_drvloc(struct exec_list *vars)
2814 {
2815 int drvloc = -1;
2816 nir_foreach_variable(var, vars) {
2817 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2818 }
2819 return drvloc;
2820 }
2821
2822 static const unsigned max_sysvals[] = {
2823 [MESA_SHADER_FRAGMENT] = 24, // TODO
2824 [MESA_SHADER_VERTEX] = 16,
2825 [MESA_SHADER_COMPUTE] = 16, // TODO how many do we actually need?
2826 };
2827
2828 static void
2829 emit_instructions(struct ir3_context *ctx)
2830 {
2831 unsigned ninputs, noutputs;
2832 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
2833
2834 ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
2835 noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
2836
2837 /* we need to leave room for sysvals:
2838 */
2839 ninputs += max_sysvals[ctx->so->type];
2840
2841 ctx->ir = ir3_create(ctx->compiler, ninputs, noutputs);
2842
2843 /* Create inputs in first block: */
2844 ctx->block = get_block(ctx, nir_start_block(fxn));
2845 ctx->in_block = ctx->block;
2846 list_addtail(&ctx->block->node, &ctx->ir->block_list);
2847
2848 ninputs -= max_sysvals[ctx->so->type];
2849
2850 /* for fragment shader, the vcoord input register is used as the
2851 * base for bary.f varying fetch instrs:
2852 */
2853 struct ir3_instruction *vcoord = NULL;
2854 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2855 struct ir3_instruction *xy[2];
2856
2857 vcoord = create_input_compmask(ctx, 0, 0x3);
2858 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
2859
2860 ctx->frag_vcoord = ir3_create_collect(ctx, xy, 2);
2861 }
2862
2863 /* Setup inputs: */
2864 nir_foreach_variable(var, &ctx->s->inputs) {
2865 setup_input(ctx, var);
2866 }
2867
2868 /* Defer add_sysval_input() stuff until after setup_inputs(),
2869 * because sysvals need to be appended after varyings:
2870 */
2871 if (vcoord) {
2872 add_sysval_input_compmask(ctx, SYSTEM_VALUE_VARYING_COORD,
2873 0x3, vcoord);
2874 }
2875
2876 if (ctx->frag_coord) {
2877 add_sysval_input_compmask(ctx, SYSTEM_VALUE_FRAG_COORD,
2878 0xf, ctx->frag_coord);
2879 }
2880
2881 /* Setup outputs: */
2882 nir_foreach_variable(var, &ctx->s->outputs) {
2883 setup_output(ctx, var);
2884 }
2885
2886 /* Setup registers (which should only be arrays): */
2887 nir_foreach_register(reg, &ctx->s->registers) {
2888 ir3_declare_array(ctx, reg);
2889 }
2890
2891 /* NOTE: need to do something more clever when we support >1 fxn */
2892 nir_foreach_register(reg, &fxn->registers) {
2893 ir3_declare_array(ctx, reg);
2894 }
2895 /* And emit the body: */
2896 ctx->impl = fxn;
2897 emit_function(ctx, fxn);
2898 }
2899
2900 /* from NIR perspective, we actually have varying inputs. But the varying
2901 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
2902 * only actual inputs are the sysvals.
2903 */
2904 static void
2905 fixup_frag_inputs(struct ir3_context *ctx)
2906 {
2907 struct ir3_shader_variant *so = ctx->so;
2908 struct ir3 *ir = ctx->ir;
2909 unsigned i = 0;
2910
2911 /* sysvals should appear at the end of the inputs, drop everything else: */
2912 while ((i < so->inputs_count) && !so->inputs[i].sysval)
2913 i++;
2914
2915 /* at IR level, inputs are always blocks of 4 scalars: */
2916 i *= 4;
2917
2918 ir->inputs = &ir->inputs[i];
2919 ir->ninputs -= i;
2920 }
2921
2922 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2923 * need to assign the tex state indexes for these after we know the
2924 * max tex index.
2925 */
2926 static void
2927 fixup_astc_srgb(struct ir3_context *ctx)
2928 {
2929 struct ir3_shader_variant *so = ctx->so;
2930 /* indexed by original tex idx, value is newly assigned alpha sampler
2931 * state tex idx. Zero is invalid since there is at least one sampler
2932 * if we get here.
2933 */
2934 unsigned alt_tex_state[16] = {0};
2935 unsigned tex_idx = ctx->max_texture_index + 1;
2936 unsigned idx = 0;
2937
2938 so->astc_srgb.base = tex_idx;
2939
2940 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
2941 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
2942
2943 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
2944
2945 if (alt_tex_state[sam->cat5.tex] == 0) {
2946 /* assign new alternate/alpha tex state slot: */
2947 alt_tex_state[sam->cat5.tex] = tex_idx++;
2948 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
2949 so->astc_srgb.count++;
2950 }
2951
2952 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
2953 }
2954 }
2955
2956 static void
2957 fixup_binning_pass(struct ir3_context *ctx)
2958 {
2959 struct ir3_shader_variant *so = ctx->so;
2960 struct ir3 *ir = ctx->ir;
2961 unsigned i, j;
2962
2963 for (i = 0, j = 0; i < so->outputs_count; i++) {
2964 unsigned slot = so->outputs[i].slot;
2965
2966 /* throw away everything but first position/psize */
2967 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
2968 if (i != j) {
2969 so->outputs[j] = so->outputs[i];
2970 ir->outputs[(j*4)+0] = ir->outputs[(i*4)+0];
2971 ir->outputs[(j*4)+1] = ir->outputs[(i*4)+1];
2972 ir->outputs[(j*4)+2] = ir->outputs[(i*4)+2];
2973 ir->outputs[(j*4)+3] = ir->outputs[(i*4)+3];
2974 }
2975 j++;
2976 }
2977 }
2978 so->outputs_count = j;
2979 ir->noutputs = j * 4;
2980 }
2981
2982 int
2983 ir3_compile_shader_nir(struct ir3_compiler *compiler,
2984 struct ir3_shader_variant *so)
2985 {
2986 struct ir3_context *ctx;
2987 struct ir3 *ir;
2988 struct ir3_instruction **inputs;
2989 unsigned i, actual_in, inloc;
2990 int ret = 0, max_bary;
2991
2992 assert(!so->ir);
2993
2994 ctx = ir3_context_init(compiler, so);
2995 if (!ctx) {
2996 DBG("INIT failed!");
2997 ret = -1;
2998 goto out;
2999 }
3000
3001 emit_instructions(ctx);
3002
3003 if (ctx->error) {
3004 DBG("EMIT failed!");
3005 ret = -1;
3006 goto out;
3007 }
3008
3009 ir = so->ir = ctx->ir;
3010
3011 /* keep track of the inputs from TGSI perspective.. */
3012 inputs = ir->inputs;
3013
3014 /* but fixup actual inputs for frag shader: */
3015 if (so->type == MESA_SHADER_FRAGMENT)
3016 fixup_frag_inputs(ctx);
3017
3018 /* at this point, for binning pass, throw away unneeded outputs: */
3019 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3020 fixup_binning_pass(ctx);
3021
3022 /* if we want half-precision outputs, mark the output registers
3023 * as half:
3024 */
3025 if (so->key.half_precision) {
3026 for (i = 0; i < ir->noutputs; i++) {
3027 struct ir3_instruction *out = ir->outputs[i];
3028
3029 if (!out)
3030 continue;
3031
3032 /* if frag shader writes z, that needs to be full precision: */
3033 if (so->outputs[i/4].slot == FRAG_RESULT_DEPTH)
3034 continue;
3035
3036 out->regs[0]->flags |= IR3_REG_HALF;
3037 /* output could be a fanout (ie. texture fetch output)
3038 * in which case we need to propagate the half-reg flag
3039 * up to the definer so that RA sees it:
3040 */
3041 if (out->opc == OPC_META_FO) {
3042 out = out->regs[1]->instr;
3043 out->regs[0]->flags |= IR3_REG_HALF;
3044 }
3045
3046 if (out->opc == OPC_MOV) {
3047 out->cat1.dst_type = half_type(out->cat1.dst_type);
3048 }
3049 }
3050 }
3051
3052 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3053 printf("BEFORE CP:\n");
3054 ir3_print(ir);
3055 }
3056
3057 ir3_cp(ir, so);
3058
3059 /* at this point, for binning pass, throw away unneeded outputs:
3060 * Note that for a6xx and later, we do this after ir3_cp to ensure
3061 * that the uniform/constant layout for BS and VS matches, so that
3062 * we can re-use same VS_CONST state group.
3063 */
3064 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
3065 fixup_binning_pass(ctx);
3066
3067 /* Insert mov if there's same instruction for each output.
3068 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
3069 */
3070 for (int i = ir->noutputs - 1; i >= 0; i--) {
3071 if (!ir->outputs[i])
3072 continue;
3073 for (unsigned j = 0; j < i; j++) {
3074 if (ir->outputs[i] == ir->outputs[j]) {
3075 ir->outputs[i] =
3076 ir3_MOV(ir->outputs[i]->block, ir->outputs[i], TYPE_F32);
3077 }
3078 }
3079 }
3080
3081 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3082 printf("BEFORE GROUPING:\n");
3083 ir3_print(ir);
3084 }
3085
3086 ir3_sched_add_deps(ir);
3087
3088 /* Group left/right neighbors, inserting mov's where needed to
3089 * solve conflicts:
3090 */
3091 ir3_group(ir);
3092
3093 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3094 printf("AFTER GROUPING:\n");
3095 ir3_print(ir);
3096 }
3097
3098 ir3_depth(ir);
3099
3100 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3101 printf("AFTER DEPTH:\n");
3102 ir3_print(ir);
3103 }
3104
3105 ret = ir3_sched(ir);
3106 if (ret) {
3107 DBG("SCHED failed!");
3108 goto out;
3109 }
3110
3111 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3112 printf("AFTER SCHED:\n");
3113 ir3_print(ir);
3114 }
3115
3116 ret = ir3_ra(ir, so->type, so->frag_coord, so->frag_face);
3117 if (ret) {
3118 DBG("RA failed!");
3119 goto out;
3120 }
3121
3122 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3123 printf("AFTER RA:\n");
3124 ir3_print(ir);
3125 }
3126
3127 /* fixup input/outputs: */
3128 for (i = 0; i < so->outputs_count; i++) {
3129 so->outputs[i].regid = ir->outputs[i*4]->regs[0]->num;
3130 }
3131
3132 /* Note that some or all channels of an input may be unused: */
3133 actual_in = 0;
3134 inloc = 0;
3135 for (i = 0; i < so->inputs_count; i++) {
3136 unsigned j, reg = regid(63,0), compmask = 0, maxcomp = 0;
3137 so->inputs[i].ncomp = 0;
3138 so->inputs[i].inloc = inloc;
3139 for (j = 0; j < 4; j++) {
3140 struct ir3_instruction *in = inputs[(i*4) + j];
3141 if (in && !(in->flags & IR3_INSTR_UNUSED)) {
3142 compmask |= (1 << j);
3143 reg = in->regs[0]->num - j;
3144 actual_in++;
3145 so->inputs[i].ncomp++;
3146 if ((so->type == MESA_SHADER_FRAGMENT) && so->inputs[i].bary) {
3147 /* assign inloc: */
3148 assert(in->regs[1]->flags & IR3_REG_IMMED);
3149 in->regs[1]->iim_val = inloc + j;
3150 maxcomp = j + 1;
3151 }
3152 }
3153 }
3154 if ((so->type == MESA_SHADER_FRAGMENT) && compmask && so->inputs[i].bary) {
3155 so->varying_in++;
3156 so->inputs[i].compmask = (1 << maxcomp) - 1;
3157 inloc += maxcomp;
3158 } else if (!so->inputs[i].sysval) {
3159 so->inputs[i].compmask = compmask;
3160 }
3161 so->inputs[i].regid = reg;
3162 }
3163
3164 if (ctx->astc_srgb)
3165 fixup_astc_srgb(ctx);
3166
3167 /* We need to do legalize after (for frag shader's) the "bary.f"
3168 * offsets (inloc) have been assigned.
3169 */
3170 ir3_legalize(ir, &so->num_samp, &so->has_ssbo, &max_bary);
3171
3172 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3173 printf("AFTER LEGALIZE:\n");
3174 ir3_print(ir);
3175 }
3176
3177 so->branchstack = ctx->max_stack;
3178
3179 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3180 if (so->type == MESA_SHADER_VERTEX)
3181 so->total_in = actual_in;
3182 else
3183 so->total_in = max_bary + 1;
3184
3185 out:
3186 if (ret) {
3187 if (so->ir)
3188 ir3_destroy(so->ir);
3189 so->ir = NULL;
3190 }
3191 ir3_context_free(ctx);
3192
3193 return ret;
3194 }