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nir: Rename nir_intrinsic_barrier to control_barrier
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 __ssa_dst(mov);
55 src = __ssa_src(mov, collect, IR3_REG_RELATIV);
56 src->size = arrsz;
57 src->array.offset = n;
58
59 ir3_instr_set_address(mov, address);
60
61 return mov;
62 }
63
64 static struct ir3_instruction *
65 create_input(struct ir3_context *ctx, unsigned compmask)
66 {
67 struct ir3_instruction *in;
68
69 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
70 in->input.sysval = ~0;
71 __ssa_dst(in)->wrmask = compmask;
72
73 array_insert(ctx->ir, ctx->ir->inputs, in);
74
75 return in;
76 }
77
78 static struct ir3_instruction *
79 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
80 {
81 struct ir3_block *block = ctx->block;
82 struct ir3_instruction *instr;
83 /* packed inloc is fixed up later: */
84 struct ir3_instruction *inloc = create_immed(block, n);
85
86 if (use_ldlv) {
87 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
88 instr->cat6.type = TYPE_U32;
89 instr->cat6.iim_val = 1;
90 } else {
91 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
92 instr->regs[2]->wrmask = 0x3;
93 }
94
95 return instr;
96 }
97
98 static struct ir3_instruction *
99 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
100 {
101 /* first four vec4 sysval's reserved for UBOs: */
102 /* NOTE: dp is in scalar, but there can be >4 dp components: */
103 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
104 unsigned n = const_state->offsets.driver_param;
105 unsigned r = regid(n + dp / 4, dp % 4);
106 return create_uniform(ctx->block, r);
107 }
108
109 /*
110 * Adreno uses uint rather than having dedicated bool type,
111 * which (potentially) requires some conversion, in particular
112 * when using output of an bool instr to int input, or visa
113 * versa.
114 *
115 * | Adreno | NIR |
116 * -------+---------+-------+-
117 * true | 1 | ~0 |
118 * false | 0 | 0 |
119 *
120 * To convert from an adreno bool (uint) to nir, use:
121 *
122 * absneg.s dst, (neg)src
123 *
124 * To convert back in the other direction:
125 *
126 * absneg.s dst, (abs)arc
127 *
128 * The CP step can clean up the absneg.s that cancel each other
129 * out, and with a slight bit of extra cleverness (to recognize
130 * the instructions which produce either a 0 or 1) can eliminate
131 * the absneg.s's completely when an instruction that wants
132 * 0/1 consumes the result. For example, when a nir 'bcsel'
133 * consumes the result of 'feq'. So we should be able to get by
134 * without a boolean resolve step, and without incuring any
135 * extra penalty in instruction count.
136 */
137
138 /* NIR bool -> native (adreno): */
139 static struct ir3_instruction *
140 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
141 {
142 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
143 }
144
145 /* native (adreno) -> NIR bool: */
146 static struct ir3_instruction *
147 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
148 {
149 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
150 }
151
152 /*
153 * alu/sfu instructions:
154 */
155
156 static struct ir3_instruction *
157 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
158 unsigned src_bitsize, nir_op op)
159 {
160 type_t src_type, dst_type;
161
162 switch (op) {
163 case nir_op_f2f32:
164 case nir_op_f2f16_rtne:
165 case nir_op_f2f16_rtz:
166 case nir_op_f2f16:
167 case nir_op_f2i32:
168 case nir_op_f2i16:
169 case nir_op_f2i8:
170 case nir_op_f2u32:
171 case nir_op_f2u16:
172 case nir_op_f2u8:
173 switch (src_bitsize) {
174 case 32:
175 src_type = TYPE_F32;
176 break;
177 case 16:
178 src_type = TYPE_F16;
179 break;
180 default:
181 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
182 }
183 break;
184
185 case nir_op_i2f32:
186 case nir_op_i2f16:
187 case nir_op_i2i32:
188 case nir_op_i2i16:
189 case nir_op_i2i8:
190 switch (src_bitsize) {
191 case 32:
192 src_type = TYPE_S32;
193 break;
194 case 16:
195 src_type = TYPE_S16;
196 break;
197 case 8:
198 src_type = TYPE_S8;
199 break;
200 default:
201 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
202 }
203 break;
204
205 case nir_op_u2f32:
206 case nir_op_u2f16:
207 case nir_op_u2u32:
208 case nir_op_u2u16:
209 case nir_op_u2u8:
210 switch (src_bitsize) {
211 case 32:
212 src_type = TYPE_U32;
213 break;
214 case 16:
215 src_type = TYPE_U16;
216 break;
217 case 8:
218 src_type = TYPE_U8;
219 break;
220 default:
221 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
222 }
223 break;
224
225 default:
226 ir3_context_error(ctx, "invalid conversion op: %u", op);
227 }
228
229 switch (op) {
230 case nir_op_f2f32:
231 case nir_op_i2f32:
232 case nir_op_u2f32:
233 dst_type = TYPE_F32;
234 break;
235
236 case nir_op_f2f16_rtne:
237 case nir_op_f2f16_rtz:
238 case nir_op_f2f16:
239 /* TODO how to handle rounding mode? */
240 case nir_op_i2f16:
241 case nir_op_u2f16:
242 dst_type = TYPE_F16;
243 break;
244
245 case nir_op_f2i32:
246 case nir_op_i2i32:
247 dst_type = TYPE_S32;
248 break;
249
250 case nir_op_f2i16:
251 case nir_op_i2i16:
252 dst_type = TYPE_S16;
253 break;
254
255 case nir_op_f2i8:
256 case nir_op_i2i8:
257 dst_type = TYPE_S8;
258 break;
259
260 case nir_op_f2u32:
261 case nir_op_u2u32:
262 dst_type = TYPE_U32;
263 break;
264
265 case nir_op_f2u16:
266 case nir_op_u2u16:
267 dst_type = TYPE_U16;
268 break;
269
270 case nir_op_f2u8:
271 case nir_op_u2u8:
272 dst_type = TYPE_U8;
273 break;
274
275 default:
276 ir3_context_error(ctx, "invalid conversion op: %u", op);
277 }
278
279 return ir3_COV(ctx->block, src, src_type, dst_type);
280 }
281
282 static void
283 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
284 {
285 const nir_op_info *info = &nir_op_infos[alu->op];
286 struct ir3_instruction **dst, *src[info->num_inputs];
287 unsigned bs[info->num_inputs]; /* bit size */
288 struct ir3_block *b = ctx->block;
289 unsigned dst_sz, wrmask;
290 type_t dst_type = nir_dest_bit_size(alu->dest.dest) < 32 ?
291 TYPE_U16 : TYPE_U32;
292
293 if (alu->dest.dest.is_ssa) {
294 dst_sz = alu->dest.dest.ssa.num_components;
295 wrmask = (1 << dst_sz) - 1;
296 } else {
297 dst_sz = alu->dest.dest.reg.reg->num_components;
298 wrmask = alu->dest.write_mask;
299 }
300
301 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
302
303 /* Vectors are special in that they have non-scalarized writemasks,
304 * and just take the first swizzle channel for each argument in
305 * order into each writemask channel.
306 */
307 if ((alu->op == nir_op_vec2) ||
308 (alu->op == nir_op_vec3) ||
309 (alu->op == nir_op_vec4)) {
310
311 for (int i = 0; i < info->num_inputs; i++) {
312 nir_alu_src *asrc = &alu->src[i];
313
314 compile_assert(ctx, !asrc->abs);
315 compile_assert(ctx, !asrc->negate);
316
317 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
318 if (!src[i])
319 src[i] = create_immed_typed(ctx->block, 0, dst_type);
320 dst[i] = ir3_MOV(b, src[i], dst_type);
321 }
322
323 ir3_put_dst(ctx, &alu->dest.dest);
324 return;
325 }
326
327 /* We also get mov's with more than one component for mov's so
328 * handle those specially:
329 */
330 if (alu->op == nir_op_mov) {
331 nir_alu_src *asrc = &alu->src[0];
332 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
333
334 for (unsigned i = 0; i < dst_sz; i++) {
335 if (wrmask & (1 << i)) {
336 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
337 } else {
338 dst[i] = NULL;
339 }
340 }
341
342 ir3_put_dst(ctx, &alu->dest.dest);
343 return;
344 }
345
346 /* General case: We can just grab the one used channel per src. */
347 for (int i = 0; i < info->num_inputs; i++) {
348 unsigned chan = ffs(alu->dest.write_mask) - 1;
349 nir_alu_src *asrc = &alu->src[i];
350
351 compile_assert(ctx, !asrc->abs);
352 compile_assert(ctx, !asrc->negate);
353
354 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
355 bs[i] = nir_src_bit_size(asrc->src);
356
357 compile_assert(ctx, src[i]);
358 }
359
360 switch (alu->op) {
361 case nir_op_f2f32:
362 case nir_op_f2f16_rtne:
363 case nir_op_f2f16_rtz:
364 case nir_op_f2f16:
365 case nir_op_f2i32:
366 case nir_op_f2i16:
367 case nir_op_f2i8:
368 case nir_op_f2u32:
369 case nir_op_f2u16:
370 case nir_op_f2u8:
371 case nir_op_i2f32:
372 case nir_op_i2f16:
373 case nir_op_i2i32:
374 case nir_op_i2i16:
375 case nir_op_i2i8:
376 case nir_op_u2f32:
377 case nir_op_u2f16:
378 case nir_op_u2u32:
379 case nir_op_u2u16:
380 case nir_op_u2u8:
381 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
382 break;
383 case nir_op_fquantize2f16:
384 dst[0] = create_cov(ctx,
385 create_cov(ctx, src[0], 32, nir_op_f2f16),
386 16, nir_op_f2f32);
387 break;
388 case nir_op_f2b16: {
389 struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_F16);
390 dst[0] = ir3_CMPS_F(b, src[0], 0, zero, 0);
391 dst[0]->cat2.condition = IR3_COND_NE;
392 break;
393 }
394 case nir_op_f2b32:
395 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
396 dst[0]->cat2.condition = IR3_COND_NE;
397 break;
398 case nir_op_b2f16:
399 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F16);
400 break;
401 case nir_op_b2f32:
402 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
403 break;
404 case nir_op_b2i8:
405 case nir_op_b2i16:
406 case nir_op_b2i32:
407 dst[0] = ir3_b2n(b, src[0]);
408 break;
409 case nir_op_i2b16: {
410 struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_S16);
411 dst[0] = ir3_CMPS_S(b, src[0], 0, zero, 0);
412 dst[0]->cat2.condition = IR3_COND_NE;
413 break;
414 }
415 case nir_op_i2b32:
416 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
417 dst[0]->cat2.condition = IR3_COND_NE;
418 break;
419
420 case nir_op_fneg:
421 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
422 break;
423 case nir_op_fabs:
424 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
425 break;
426 case nir_op_fmax:
427 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
428 break;
429 case nir_op_fmin:
430 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
431 break;
432 case nir_op_fsat:
433 /* if there is just a single use of the src, and it supports
434 * (sat) bit, we can just fold the (sat) flag back to the
435 * src instruction and create a mov. This is easier for cp
436 * to eliminate.
437 *
438 * TODO probably opc_cat==4 is ok too
439 */
440 if (alu->src[0].src.is_ssa &&
441 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
442 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
443 src[0]->flags |= IR3_INSTR_SAT;
444 dst[0] = ir3_MOV(b, src[0], dst_type);
445 } else {
446 /* otherwise generate a max.f that saturates.. blob does
447 * similar (generating a cat2 mov using max.f)
448 */
449 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
450 dst[0]->flags |= IR3_INSTR_SAT;
451 }
452 break;
453 case nir_op_fmul:
454 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
455 break;
456 case nir_op_fadd:
457 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
458 break;
459 case nir_op_fsub:
460 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
461 break;
462 case nir_op_ffma:
463 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
464 break;
465 case nir_op_fddx:
466 case nir_op_fddx_coarse:
467 dst[0] = ir3_DSX(b, src[0], 0);
468 dst[0]->cat5.type = TYPE_F32;
469 break;
470 case nir_op_fddy:
471 case nir_op_fddy_coarse:
472 dst[0] = ir3_DSY(b, src[0], 0);
473 dst[0]->cat5.type = TYPE_F32;
474 break;
475 break;
476 case nir_op_flt16:
477 case nir_op_flt32:
478 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
479 dst[0]->cat2.condition = IR3_COND_LT;
480 break;
481 case nir_op_fge16:
482 case nir_op_fge32:
483 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
484 dst[0]->cat2.condition = IR3_COND_GE;
485 break;
486 case nir_op_feq16:
487 case nir_op_feq32:
488 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
489 dst[0]->cat2.condition = IR3_COND_EQ;
490 break;
491 case nir_op_fne16:
492 case nir_op_fne32:
493 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
494 dst[0]->cat2.condition = IR3_COND_NE;
495 break;
496 case nir_op_fceil:
497 dst[0] = ir3_CEIL_F(b, src[0], 0);
498 break;
499 case nir_op_ffloor:
500 dst[0] = ir3_FLOOR_F(b, src[0], 0);
501 break;
502 case nir_op_ftrunc:
503 dst[0] = ir3_TRUNC_F(b, src[0], 0);
504 break;
505 case nir_op_fround_even:
506 dst[0] = ir3_RNDNE_F(b, src[0], 0);
507 break;
508 case nir_op_fsign:
509 dst[0] = ir3_SIGN_F(b, src[0], 0);
510 break;
511
512 case nir_op_fsin:
513 dst[0] = ir3_SIN(b, src[0], 0);
514 break;
515 case nir_op_fcos:
516 dst[0] = ir3_COS(b, src[0], 0);
517 break;
518 case nir_op_frsq:
519 dst[0] = ir3_RSQ(b, src[0], 0);
520 break;
521 case nir_op_frcp:
522 dst[0] = ir3_RCP(b, src[0], 0);
523 break;
524 case nir_op_flog2:
525 dst[0] = ir3_LOG2(b, src[0], 0);
526 break;
527 case nir_op_fexp2:
528 dst[0] = ir3_EXP2(b, src[0], 0);
529 break;
530 case nir_op_fsqrt:
531 dst[0] = ir3_SQRT(b, src[0], 0);
532 break;
533
534 case nir_op_iabs:
535 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
536 break;
537 case nir_op_iadd:
538 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
539 break;
540 case nir_op_iand:
541 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
542 break;
543 case nir_op_imax:
544 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
545 break;
546 case nir_op_umax:
547 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
548 break;
549 case nir_op_imin:
550 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
551 break;
552 case nir_op_umin:
553 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
554 break;
555 case nir_op_umul_low:
556 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
557 break;
558 case nir_op_imadsh_mix16:
559 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
560 break;
561 case nir_op_imad24_ir3:
562 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
563 break;
564 case nir_op_imul24:
565 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
566 break;
567 case nir_op_ineg:
568 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
569 break;
570 case nir_op_inot:
571 dst[0] = ir3_NOT_B(b, src[0], 0);
572 break;
573 case nir_op_ior:
574 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
575 break;
576 case nir_op_ishl:
577 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
578 break;
579 case nir_op_ishr:
580 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
581 break;
582 case nir_op_isub:
583 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
584 break;
585 case nir_op_ixor:
586 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
587 break;
588 case nir_op_ushr:
589 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
590 break;
591 case nir_op_ilt16:
592 case nir_op_ilt32:
593 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
594 dst[0]->cat2.condition = IR3_COND_LT;
595 break;
596 case nir_op_ige16:
597 case nir_op_ige32:
598 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
599 dst[0]->cat2.condition = IR3_COND_GE;
600 break;
601 case nir_op_ieq16:
602 case nir_op_ieq32:
603 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
604 dst[0]->cat2.condition = IR3_COND_EQ;
605 break;
606 case nir_op_ine16:
607 case nir_op_ine32:
608 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
609 dst[0]->cat2.condition = IR3_COND_NE;
610 break;
611 case nir_op_ult16:
612 case nir_op_ult32:
613 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
614 dst[0]->cat2.condition = IR3_COND_LT;
615 break;
616 case nir_op_uge16:
617 case nir_op_uge32:
618 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
619 dst[0]->cat2.condition = IR3_COND_GE;
620 break;
621
622 case nir_op_b16csel:
623 case nir_op_b32csel: {
624 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
625
626 if ((src[0]->regs[0]->flags & IR3_REG_HALF))
627 cond->regs[0]->flags |= IR3_REG_HALF;
628
629 compile_assert(ctx, bs[1] == bs[2]);
630 /* Make sure the boolean condition has the same bit size as the other
631 * two arguments, adding a conversion if necessary.
632 */
633 if (bs[1] < bs[0])
634 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
635 else if (bs[1] > bs[0])
636 cond = ir3_COV(b, cond, TYPE_U16, TYPE_U32);
637
638 if (bs[1] > 16)
639 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
640 else
641 dst[0] = ir3_SEL_B16(b, src[1], 0, cond, 0, src[2], 0);
642 break;
643 }
644 case nir_op_bit_count: {
645 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
646 // double check on earlier gen's. Once half-precision support is
647 // in place, this should probably move to a NIR lowering pass:
648 struct ir3_instruction *hi, *lo;
649
650 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
651 TYPE_U32, TYPE_U16);
652 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
653
654 hi = ir3_CBITS_B(b, hi, 0);
655 lo = ir3_CBITS_B(b, lo, 0);
656
657 // TODO maybe the builders should default to making dst half-precision
658 // if the src's were half precision, to make this less awkward.. otoh
659 // we should probably just do this lowering in NIR.
660 hi->regs[0]->flags |= IR3_REG_HALF;
661 lo->regs[0]->flags |= IR3_REG_HALF;
662
663 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
664 dst[0]->regs[0]->flags |= IR3_REG_HALF;
665 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
666 break;
667 }
668 case nir_op_ifind_msb: {
669 struct ir3_instruction *cmp;
670 dst[0] = ir3_CLZ_S(b, src[0], 0);
671 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
672 cmp->cat2.condition = IR3_COND_GE;
673 dst[0] = ir3_SEL_B32(b,
674 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
675 cmp, 0, dst[0], 0);
676 break;
677 }
678 case nir_op_ufind_msb:
679 dst[0] = ir3_CLZ_B(b, src[0], 0);
680 dst[0] = ir3_SEL_B32(b,
681 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
682 src[0], 0, dst[0], 0);
683 break;
684 case nir_op_find_lsb:
685 dst[0] = ir3_BFREV_B(b, src[0], 0);
686 dst[0] = ir3_CLZ_B(b, dst[0], 0);
687 break;
688 case nir_op_bitfield_reverse:
689 dst[0] = ir3_BFREV_B(b, src[0], 0);
690 break;
691
692 default:
693 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
694 nir_op_infos[alu->op].name);
695 break;
696 }
697
698 if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) {
699 assert(dst_sz == 1);
700
701 if (nir_dest_bit_size(alu->dest.dest) < 32)
702 dst[0]->regs[0]->flags |= IR3_REG_HALF;
703
704 dst[0] = ir3_n2b(b, dst[0]);
705 }
706
707 if (nir_dest_bit_size(alu->dest.dest) < 32) {
708 for (unsigned i = 0; i < dst_sz; i++) {
709 dst[i]->regs[0]->flags |= IR3_REG_HALF;
710 }
711 }
712
713 ir3_put_dst(ctx, &alu->dest.dest);
714 }
715
716 /* handles direct/indirect UBO reads: */
717 static void
718 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
719 struct ir3_instruction **dst)
720 {
721 struct ir3_block *b = ctx->block;
722 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
723 /* UBO addresses are the first driver params, but subtract 2 here to
724 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
725 * is the uniforms: */
726 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
727 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
728 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
729
730 int off = 0;
731
732 /* First src is ubo index, which could either be an immed or not: */
733 src0 = ir3_get_src(ctx, &intr->src[0])[0];
734 if (is_same_type_mov(src0) &&
735 (src0->regs[1]->flags & IR3_REG_IMMED)) {
736 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
737 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
738 } else {
739 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
740 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
741
742 /* NOTE: since relative addressing is used, make sure constlen is
743 * at least big enough to cover all the UBO addresses, since the
744 * assembler won't know what the max address reg is.
745 */
746 ctx->so->constlen = MAX2(ctx->so->constlen,
747 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
748 }
749
750 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
751 addr = base_lo;
752
753 if (nir_src_is_const(intr->src[1])) {
754 off += nir_src_as_uint(intr->src[1]);
755 } else {
756 /* For load_ubo_indirect, second src is indirect offset: */
757 src1 = ir3_get_src(ctx, &intr->src[1])[0];
758
759 /* and add offset to addr: */
760 addr = ir3_ADD_S(b, addr, 0, src1, 0);
761 }
762
763 /* if offset is to large to encode in the ldg, split it out: */
764 if ((off + (intr->num_components * 4)) > 1024) {
765 /* split out the minimal amount to improve the odds that
766 * cp can fit the immediate in the add.s instruction:
767 */
768 unsigned off2 = off + (intr->num_components * 4) - 1024;
769 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
770 off -= off2;
771 }
772
773 if (ptrsz == 2) {
774 struct ir3_instruction *carry;
775
776 /* handle 32b rollover, ie:
777 * if (addr < base_lo)
778 * base_hi++
779 */
780 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
781 carry->cat2.condition = IR3_COND_LT;
782 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
783
784 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
785 }
786
787 for (int i = 0; i < intr->num_components; i++) {
788 struct ir3_instruction *load =
789 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
790 create_immed(b, off + i * 4), 0);
791 load->cat6.type = TYPE_U32;
792 dst[i] = load;
793 }
794 }
795
796 /* src[] = { block_index } */
797 static void
798 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
799 struct ir3_instruction **dst)
800 {
801 /* SSBO size stored as a const starting at ssbo_sizes: */
802 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
803 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
804 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
805 const_state->ssbo_size.off[blk_idx];
806
807 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
808
809 dst[0] = create_uniform(ctx->block, idx);
810 }
811
812 /* src[] = { offset }. const_index[] = { base } */
813 static void
814 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
815 struct ir3_instruction **dst)
816 {
817 struct ir3_block *b = ctx->block;
818 struct ir3_instruction *ldl, *offset;
819 unsigned base;
820
821 offset = ir3_get_src(ctx, &intr->src[0])[0];
822 base = nir_intrinsic_base(intr);
823
824 ldl = ir3_LDL(b, offset, 0,
825 create_immed(b, intr->num_components), 0,
826 create_immed(b, base), 0);
827
828 ldl->cat6.type = utype_dst(intr->dest);
829 ldl->regs[0]->wrmask = MASK(intr->num_components);
830
831 ldl->barrier_class = IR3_BARRIER_SHARED_R;
832 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
833
834 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
835 }
836
837 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
838 static void
839 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
840 {
841 struct ir3_block *b = ctx->block;
842 struct ir3_instruction *stl, *offset;
843 struct ir3_instruction * const *value;
844 unsigned base, wrmask;
845
846 value = ir3_get_src(ctx, &intr->src[0]);
847 offset = ir3_get_src(ctx, &intr->src[1])[0];
848
849 base = nir_intrinsic_base(intr);
850 wrmask = nir_intrinsic_write_mask(intr);
851
852 /* Combine groups of consecutive enabled channels in one write
853 * message. We use ffs to find the first enabled channel and then ffs on
854 * the bit-inverse, down-shifted writemask to determine the length of
855 * the block of enabled bits.
856 *
857 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
858 */
859 while (wrmask) {
860 unsigned first_component = ffs(wrmask) - 1;
861 unsigned length = ffs(~(wrmask >> first_component)) - 1;
862
863 stl = ir3_STL(b, offset, 0,
864 ir3_create_collect(ctx, &value[first_component], length), 0,
865 create_immed(b, length), 0);
866 stl->cat6.dst_offset = first_component + base;
867 stl->cat6.type = utype_src(intr->src[0]);
868 stl->barrier_class = IR3_BARRIER_SHARED_W;
869 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
870
871 array_insert(b, b->keeps, stl);
872
873 /* Clear the bits in the writemask that we just wrote, then try
874 * again to see if more channels are left.
875 */
876 wrmask &= (15 << (first_component + length));
877 }
878 }
879
880 /* src[] = { offset }. const_index[] = { base } */
881 static void
882 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
883 struct ir3_instruction **dst)
884 {
885 struct ir3_block *b = ctx->block;
886 struct ir3_instruction *load, *offset;
887 unsigned base;
888
889 offset = ir3_get_src(ctx, &intr->src[0])[0];
890 base = nir_intrinsic_base(intr);
891
892 load = ir3_LDLW(b, offset, 0,
893 create_immed(b, intr->num_components), 0,
894 create_immed(b, base), 0);
895
896 load->cat6.type = utype_dst(intr->dest);
897 load->regs[0]->wrmask = MASK(intr->num_components);
898
899 load->barrier_class = IR3_BARRIER_SHARED_R;
900 load->barrier_conflict = IR3_BARRIER_SHARED_W;
901
902 ir3_split_dest(b, dst, load, 0, intr->num_components);
903 }
904
905 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
906 static void
907 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
908 {
909 struct ir3_block *b = ctx->block;
910 struct ir3_instruction *store, *offset;
911 struct ir3_instruction * const *value;
912 unsigned base, wrmask;
913
914 value = ir3_get_src(ctx, &intr->src[0]);
915 offset = ir3_get_src(ctx, &intr->src[1])[0];
916
917 base = nir_intrinsic_base(intr);
918 wrmask = nir_intrinsic_write_mask(intr);
919
920 /* Combine groups of consecutive enabled channels in one write
921 * message. We use ffs to find the first enabled channel and then ffs on
922 * the bit-inverse, down-shifted writemask to determine the length of
923 * the block of enabled bits.
924 *
925 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
926 */
927 while (wrmask) {
928 unsigned first_component = ffs(wrmask) - 1;
929 unsigned length = ffs(~(wrmask >> first_component)) - 1;
930
931 store = ir3_STLW(b, offset, 0,
932 ir3_create_collect(ctx, &value[first_component], length), 0,
933 create_immed(b, length), 0);
934
935 store->cat6.dst_offset = first_component + base;
936 store->cat6.type = utype_src(intr->src[0]);
937 store->barrier_class = IR3_BARRIER_SHARED_W;
938 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
939
940 array_insert(b, b->keeps, store);
941
942 /* Clear the bits in the writemask that we just wrote, then try
943 * again to see if more channels are left.
944 */
945 wrmask &= (15 << (first_component + length));
946 }
947 }
948
949 /*
950 * CS shared variable atomic intrinsics
951 *
952 * All of the shared variable atomic memory operations read a value from
953 * memory, compute a new value using one of the operations below, write the
954 * new value to memory, and return the original value read.
955 *
956 * All operations take 2 sources except CompSwap that takes 3. These
957 * sources represent:
958 *
959 * 0: The offset into the shared variable storage region that the atomic
960 * operation will operate on.
961 * 1: The data parameter to the atomic function (i.e. the value to add
962 * in shared_atomic_add, etc).
963 * 2: For CompSwap only: the second data parameter.
964 */
965 static struct ir3_instruction *
966 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
967 {
968 struct ir3_block *b = ctx->block;
969 struct ir3_instruction *atomic, *src0, *src1;
970 type_t type = TYPE_U32;
971
972 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
973 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
974
975 switch (intr->intrinsic) {
976 case nir_intrinsic_shared_atomic_add:
977 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
978 break;
979 case nir_intrinsic_shared_atomic_imin:
980 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
981 type = TYPE_S32;
982 break;
983 case nir_intrinsic_shared_atomic_umin:
984 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
985 break;
986 case nir_intrinsic_shared_atomic_imax:
987 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
988 type = TYPE_S32;
989 break;
990 case nir_intrinsic_shared_atomic_umax:
991 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
992 break;
993 case nir_intrinsic_shared_atomic_and:
994 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
995 break;
996 case nir_intrinsic_shared_atomic_or:
997 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
998 break;
999 case nir_intrinsic_shared_atomic_xor:
1000 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
1001 break;
1002 case nir_intrinsic_shared_atomic_exchange:
1003 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
1004 break;
1005 case nir_intrinsic_shared_atomic_comp_swap:
1006 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1007 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1008 ir3_get_src(ctx, &intr->src[2])[0],
1009 src1,
1010 }, 2);
1011 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
1012 break;
1013 default:
1014 unreachable("boo");
1015 }
1016
1017 atomic->cat6.iim_val = 1;
1018 atomic->cat6.d = 1;
1019 atomic->cat6.type = type;
1020 atomic->barrier_class = IR3_BARRIER_SHARED_W;
1021 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1022
1023 /* even if nothing consume the result, we can't DCE the instruction: */
1024 array_insert(b, b->keeps, atomic);
1025
1026 return atomic;
1027 }
1028
1029 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1030 * to handle with the image_mapping table..
1031 */
1032 static struct ir3_instruction *
1033 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1034 {
1035 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
1036 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1037 struct ir3_instruction *texture, *sampler;
1038
1039 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1040 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1041
1042 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1043 sampler,
1044 texture,
1045 }, 2);
1046 }
1047
1048 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1049 static void
1050 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1051 struct ir3_instruction **dst)
1052 {
1053 struct ir3_block *b = ctx->block;
1054 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1055 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1056 struct ir3_instruction *sam;
1057 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1058 struct ir3_instruction *coords[4];
1059 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1060 type_t type = ir3_get_image_type(var);
1061
1062 /* hmm, this seems a bit odd, but it is what blob does and (at least
1063 * a5xx) just faults on bogus addresses otherwise:
1064 */
1065 if (flags & IR3_INSTR_3D) {
1066 flags &= ~IR3_INSTR_3D;
1067 flags |= IR3_INSTR_A;
1068 }
1069
1070 for (unsigned i = 0; i < ncoords; i++)
1071 coords[i] = src0[i];
1072
1073 if (ncoords == 1)
1074 coords[ncoords++] = create_immed(b, 0);
1075
1076 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
1077 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
1078
1079 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1080 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1081
1082 ir3_split_dest(b, dst, sam, 0, 4);
1083 }
1084
1085 static void
1086 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1087 struct ir3_instruction **dst)
1088 {
1089 struct ir3_block *b = ctx->block;
1090 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1091 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1092 struct ir3_instruction *sam, *lod;
1093 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1094 type_t dst_type = nir_dest_bit_size(intr->dest) < 32 ?
1095 TYPE_U16 : TYPE_U32;
1096
1097 lod = create_immed(b, 0);
1098 sam = ir3_SAM(b, OPC_GETSIZE, dst_type, 0b1111, flags,
1099 samp_tex, lod, NULL);
1100
1101 /* Array size actually ends up in .w rather than .z. This doesn't
1102 * matter for miplevel 0, but for higher mips the value in z is
1103 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1104 * returned, which means that we have to add 1 to it for arrays for
1105 * a3xx.
1106 *
1107 * Note use a temporary dst and then copy, since the size of the dst
1108 * array that is passed in is based on nir's understanding of the
1109 * result size, not the hardware's
1110 */
1111 struct ir3_instruction *tmp[4];
1112
1113 ir3_split_dest(b, tmp, sam, 0, 4);
1114
1115 /* get_size instruction returns size in bytes instead of texels
1116 * for imageBuffer, so we need to divide it by the pixel size
1117 * of the image format.
1118 *
1119 * TODO: This is at least true on a5xx. Check other gens.
1120 */
1121 enum glsl_sampler_dim dim =
1122 glsl_get_sampler_dim(glsl_without_array(var->type));
1123 if (dim == GLSL_SAMPLER_DIM_BUF) {
1124 /* Since all the possible values the divisor can take are
1125 * power-of-two (4, 8, or 16), the division is implemented
1126 * as a shift-right.
1127 * During shader setup, the log2 of the image format's
1128 * bytes-per-pixel should have been emitted in 2nd slot of
1129 * image_dims. See ir3_shader::emit_image_dims().
1130 */
1131 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1132 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1133 const_state->image_dims.off[var->data.driver_location];
1134 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1135
1136 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1137 }
1138
1139 for (unsigned i = 0; i < ncoords; i++)
1140 dst[i] = tmp[i];
1141
1142 if (flags & IR3_INSTR_A) {
1143 if (ctx->compiler->levels_add_one) {
1144 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1145 } else {
1146 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1147 }
1148 }
1149 }
1150
1151 static void
1152 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1153 {
1154 struct ir3_block *b = ctx->block;
1155 struct ir3_instruction *barrier;
1156
1157 switch (intr->intrinsic) {
1158 case nir_intrinsic_control_barrier:
1159 barrier = ir3_BAR(b);
1160 barrier->cat7.g = true;
1161 barrier->cat7.l = true;
1162 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1163 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1164 break;
1165 case nir_intrinsic_memory_barrier:
1166 barrier = ir3_FENCE(b);
1167 barrier->cat7.g = true;
1168 barrier->cat7.r = true;
1169 barrier->cat7.w = true;
1170 barrier->cat7.l = true;
1171 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1172 IR3_BARRIER_BUFFER_W;
1173 barrier->barrier_conflict =
1174 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1175 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1176 break;
1177 case nir_intrinsic_memory_barrier_atomic_counter:
1178 case nir_intrinsic_memory_barrier_buffer:
1179 barrier = ir3_FENCE(b);
1180 barrier->cat7.g = true;
1181 barrier->cat7.r = true;
1182 barrier->cat7.w = true;
1183 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1184 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1185 IR3_BARRIER_BUFFER_W;
1186 break;
1187 case nir_intrinsic_memory_barrier_image:
1188 // TODO double check if this should have .g set
1189 barrier = ir3_FENCE(b);
1190 barrier->cat7.g = true;
1191 barrier->cat7.r = true;
1192 barrier->cat7.w = true;
1193 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1194 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1195 IR3_BARRIER_IMAGE_W;
1196 break;
1197 case nir_intrinsic_memory_barrier_shared:
1198 barrier = ir3_FENCE(b);
1199 barrier->cat7.g = true;
1200 barrier->cat7.l = true;
1201 barrier->cat7.r = true;
1202 barrier->cat7.w = true;
1203 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1204 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1205 IR3_BARRIER_SHARED_W;
1206 break;
1207 case nir_intrinsic_group_memory_barrier:
1208 barrier = ir3_FENCE(b);
1209 barrier->cat7.g = true;
1210 barrier->cat7.l = true;
1211 barrier->cat7.r = true;
1212 barrier->cat7.w = true;
1213 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1214 IR3_BARRIER_IMAGE_W |
1215 IR3_BARRIER_BUFFER_W;
1216 barrier->barrier_conflict =
1217 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1218 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1219 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1220 break;
1221 default:
1222 unreachable("boo");
1223 }
1224
1225 /* make sure barrier doesn't get DCE'd */
1226 array_insert(b, b->keeps, barrier);
1227 }
1228
1229 static void add_sysval_input_compmask(struct ir3_context *ctx,
1230 gl_system_value slot, unsigned compmask,
1231 struct ir3_instruction *instr)
1232 {
1233 struct ir3_shader_variant *so = ctx->so;
1234 unsigned n = so->inputs_count++;
1235
1236 assert(instr->opc == OPC_META_INPUT);
1237 instr->input.inidx = n;
1238 instr->input.sysval = slot;
1239
1240 so->inputs[n].sysval = true;
1241 so->inputs[n].slot = slot;
1242 so->inputs[n].compmask = compmask;
1243 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1244 so->total_in++;
1245 }
1246
1247 static struct ir3_instruction *
1248 create_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1249 unsigned compmask)
1250 {
1251 assert(compmask);
1252 struct ir3_instruction *sysval = create_input(ctx, compmask);
1253 add_sysval_input_compmask(ctx, slot, compmask, sysval);
1254 return sysval;
1255 }
1256
1257 static struct ir3_instruction *
1258 get_barycentric_centroid(struct ir3_context *ctx)
1259 {
1260 if (!ctx->ij_centroid) {
1261 struct ir3_instruction *xy[2];
1262 struct ir3_instruction *ij;
1263
1264 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_CENTROID, 0x3);
1265 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1266
1267 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1268 }
1269
1270 return ctx->ij_centroid;
1271 }
1272
1273 static struct ir3_instruction *
1274 get_barycentric_sample(struct ir3_context *ctx)
1275 {
1276 if (!ctx->ij_sample) {
1277 struct ir3_instruction *xy[2];
1278 struct ir3_instruction *ij;
1279
1280 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SAMPLE, 0x3);
1281 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1282
1283 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1284 }
1285
1286 return ctx->ij_sample;
1287 }
1288
1289 static struct ir3_instruction *
1290 get_barycentric_pixel(struct ir3_context *ctx)
1291 {
1292 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1293 * this to create ij_pixel only on demand:
1294 */
1295 return ctx->ij_pixel;
1296 }
1297
1298 static struct ir3_instruction *
1299 get_frag_coord(struct ir3_context *ctx)
1300 {
1301 if (!ctx->frag_coord) {
1302 struct ir3_block *b = ctx->block;
1303 struct ir3_instruction *xyzw[4];
1304 struct ir3_instruction *hw_frag_coord;
1305
1306 hw_frag_coord = create_sysval_input(ctx, SYSTEM_VALUE_FRAG_COORD, 0xf);
1307 ir3_split_dest(ctx->block, xyzw, hw_frag_coord, 0, 4);
1308
1309 /* for frag_coord.xy, we get unsigned values.. we need
1310 * to subtract (integer) 8 and divide by 16 (right-
1311 * shift by 4) then convert to float:
1312 *
1313 * sub.s tmp, src, 8
1314 * shr.b tmp, tmp, 4
1315 * mov.u32f32 dst, tmp
1316 *
1317 */
1318 for (int i = 0; i < 2; i++) {
1319 xyzw[i] = ir3_SUB_S(b, xyzw[i], 0,
1320 create_immed(b, 8), 0);
1321 xyzw[i] = ir3_SHR_B(b, xyzw[i], 0,
1322 create_immed(b, 4), 0);
1323 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1324 }
1325
1326 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1327 ctx->so->frag_coord = true;
1328 }
1329
1330 return ctx->frag_coord;
1331 }
1332
1333 static void
1334 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1335 {
1336 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1337 struct ir3_instruction **dst;
1338 struct ir3_instruction * const *src;
1339 struct ir3_block *b = ctx->block;
1340 int idx, comp;
1341
1342 if (info->has_dest) {
1343 unsigned n = nir_intrinsic_dest_components(intr);
1344 dst = ir3_get_dst(ctx, &intr->dest, n);
1345 } else {
1346 dst = NULL;
1347 }
1348
1349 const unsigned primitive_param = ctx->so->shader->const_state.offsets.primitive_param * 4;
1350 const unsigned primitive_map = ctx->so->shader->const_state.offsets.primitive_map * 4;
1351
1352 switch (intr->intrinsic) {
1353 case nir_intrinsic_load_uniform:
1354 idx = nir_intrinsic_base(intr);
1355 if (nir_src_is_const(intr->src[0])) {
1356 idx += nir_src_as_uint(intr->src[0]);
1357 for (int i = 0; i < intr->num_components; i++) {
1358 dst[i] = create_uniform_typed(b, idx + i,
1359 nir_dest_bit_size(intr->dest) < 32 ? TYPE_F16 : TYPE_F32);
1360 }
1361 } else {
1362 src = ir3_get_src(ctx, &intr->src[0]);
1363 for (int i = 0; i < intr->num_components; i++) {
1364 dst[i] = create_uniform_indirect(b, idx + i,
1365 ir3_get_addr(ctx, src[0], 1));
1366 }
1367 /* NOTE: if relative addressing is used, we set
1368 * constlen in the compiler (to worst-case value)
1369 * since we don't know in the assembler what the max
1370 * addr reg value can be:
1371 */
1372 ctx->so->constlen = MAX2(ctx->so->constlen,
1373 ctx->so->shader->ubo_state.size / 16);
1374 }
1375 break;
1376
1377 case nir_intrinsic_load_vs_primitive_stride_ir3:
1378 dst[0] = create_uniform(b, primitive_param + 0);
1379 break;
1380 case nir_intrinsic_load_vs_vertex_stride_ir3:
1381 dst[0] = create_uniform(b, primitive_param + 1);
1382 break;
1383 case nir_intrinsic_load_hs_patch_stride_ir3:
1384 dst[0] = create_uniform(b, primitive_param + 2);
1385 break;
1386 case nir_intrinsic_load_patch_vertices_in:
1387 dst[0] = create_uniform(b, primitive_param + 3);
1388 break;
1389 case nir_intrinsic_load_tess_param_base_ir3:
1390 dst[0] = create_uniform(b, primitive_param + 4);
1391 dst[1] = create_uniform(b, primitive_param + 5);
1392 break;
1393 case nir_intrinsic_load_tess_factor_base_ir3:
1394 dst[0] = create_uniform(b, primitive_param + 6);
1395 dst[1] = create_uniform(b, primitive_param + 7);
1396 break;
1397
1398 case nir_intrinsic_load_primitive_location_ir3:
1399 idx = nir_intrinsic_driver_location(intr);
1400 dst[0] = create_uniform(b, primitive_map + idx);
1401 break;
1402
1403 case nir_intrinsic_load_gs_header_ir3:
1404 dst[0] = ctx->gs_header;
1405 break;
1406 case nir_intrinsic_load_tcs_header_ir3:
1407 dst[0] = ctx->tcs_header;
1408 break;
1409
1410 case nir_intrinsic_load_primitive_id:
1411 dst[0] = ctx->primitive_id;
1412 break;
1413
1414 case nir_intrinsic_load_tess_coord:
1415 if (!ctx->tess_coord) {
1416 ctx->tess_coord =
1417 create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
1418 }
1419 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1420
1421 /* Unused, but ir3_put_dst() below wants to free something */
1422 dst[2] = create_immed(b, 0);
1423 break;
1424
1425 case nir_intrinsic_end_patch_ir3:
1426 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1427 struct ir3_instruction *end = ir3_ENDPATCH(b);
1428 array_insert(b, b->keeps, end);
1429
1430 end->barrier_class = IR3_BARRIER_EVERYTHING;
1431 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1432 break;
1433
1434 case nir_intrinsic_store_global_ir3: {
1435 struct ir3_instruction *value, *addr, *offset;
1436
1437 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1438 ir3_get_src(ctx, &intr->src[1])[0],
1439 ir3_get_src(ctx, &intr->src[1])[1]
1440 }, 2);
1441
1442 offset = ir3_get_src(ctx, &intr->src[2])[0];
1443
1444 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]),
1445 intr->num_components);
1446
1447 struct ir3_instruction *stg =
1448 ir3_STG_G(ctx->block, addr, 0, value, 0,
1449 create_immed(ctx->block, intr->num_components), 0, offset, 0);
1450 stg->cat6.type = TYPE_U32;
1451 stg->cat6.iim_val = 1;
1452
1453 array_insert(b, b->keeps, stg);
1454
1455 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1456 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1457 break;
1458 }
1459
1460 case nir_intrinsic_load_global_ir3: {
1461 struct ir3_instruction *addr, *offset;
1462
1463 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1464 ir3_get_src(ctx, &intr->src[0])[0],
1465 ir3_get_src(ctx, &intr->src[0])[1]
1466 }, 2);
1467
1468 offset = ir3_get_src(ctx, &intr->src[1])[0];
1469
1470 struct ir3_instruction *load =
1471 ir3_LDG(b, addr, 0, create_immed(ctx->block, intr->num_components),
1472 0, offset, 0);
1473 load->cat6.type = TYPE_U32;
1474 load->regs[0]->wrmask = MASK(intr->num_components);
1475
1476 load->barrier_class = IR3_BARRIER_BUFFER_R;
1477 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1478
1479 ir3_split_dest(b, dst, load, 0, intr->num_components);
1480 break;
1481 }
1482
1483 case nir_intrinsic_load_ubo:
1484 emit_intrinsic_load_ubo(ctx, intr, dst);
1485 break;
1486 case nir_intrinsic_load_frag_coord:
1487 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1488 break;
1489 case nir_intrinsic_load_sample_pos_from_id: {
1490 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1491 * but that doesn't seem necessary.
1492 */
1493 struct ir3_instruction *offset =
1494 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1495 offset->regs[0]->wrmask = 0x3;
1496 offset->cat5.type = TYPE_F32;
1497
1498 ir3_split_dest(b, dst, offset, 0, 2);
1499
1500 break;
1501 }
1502 case nir_intrinsic_load_size_ir3:
1503 if (!ctx->ij_size) {
1504 ctx->ij_size =
1505 create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SIZE, 0x1);
1506 }
1507 dst[0] = ctx->ij_size;
1508 break;
1509 case nir_intrinsic_load_barycentric_centroid:
1510 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1511 break;
1512 case nir_intrinsic_load_barycentric_sample:
1513 if (ctx->so->key.msaa) {
1514 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1515 } else {
1516 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1517 }
1518 break;
1519 case nir_intrinsic_load_barycentric_pixel:
1520 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1521 break;
1522 case nir_intrinsic_load_interpolated_input:
1523 idx = nir_intrinsic_base(intr);
1524 comp = nir_intrinsic_component(intr);
1525 src = ir3_get_src(ctx, &intr->src[0]);
1526 if (nir_src_is_const(intr->src[1])) {
1527 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1528 idx += nir_src_as_uint(intr->src[1]);
1529 for (int i = 0; i < intr->num_components; i++) {
1530 unsigned inloc = idx * 4 + i + comp;
1531 if (ctx->so->inputs[idx].bary &&
1532 !ctx->so->inputs[idx].use_ldlv) {
1533 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1534 } else {
1535 /* for non-varyings use the pre-setup input, since
1536 * that is easier than mapping things back to a
1537 * nir_variable to figure out what it is.
1538 */
1539 dst[i] = ctx->inputs[inloc];
1540 }
1541 }
1542 } else {
1543 ir3_context_error(ctx, "unhandled");
1544 }
1545 break;
1546 case nir_intrinsic_load_input:
1547 idx = nir_intrinsic_base(intr);
1548 comp = nir_intrinsic_component(intr);
1549 if (nir_src_is_const(intr->src[0])) {
1550 idx += nir_src_as_uint(intr->src[0]);
1551 for (int i = 0; i < intr->num_components; i++) {
1552 unsigned n = idx * 4 + i + comp;
1553 dst[i] = ctx->inputs[n];
1554 compile_assert(ctx, ctx->inputs[n]);
1555 }
1556 } else {
1557 src = ir3_get_src(ctx, &intr->src[0]);
1558 struct ir3_instruction *collect =
1559 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ninputs);
1560 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1561 for (int i = 0; i < intr->num_components; i++) {
1562 unsigned n = idx * 4 + i + comp;
1563 dst[i] = create_indirect_load(ctx, ctx->ninputs,
1564 n, addr, collect);
1565 }
1566 }
1567 break;
1568 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1569 * pass and replaced by an ir3-specifc version that adds the
1570 * dword-offset in the last source.
1571 */
1572 case nir_intrinsic_load_ssbo_ir3:
1573 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1574 break;
1575 case nir_intrinsic_store_ssbo_ir3:
1576 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1577 !ctx->s->info.fs.early_fragment_tests)
1578 ctx->so->no_earlyz = true;
1579 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1580 break;
1581 case nir_intrinsic_get_buffer_size:
1582 emit_intrinsic_ssbo_size(ctx, intr, dst);
1583 break;
1584 case nir_intrinsic_ssbo_atomic_add_ir3:
1585 case nir_intrinsic_ssbo_atomic_imin_ir3:
1586 case nir_intrinsic_ssbo_atomic_umin_ir3:
1587 case nir_intrinsic_ssbo_atomic_imax_ir3:
1588 case nir_intrinsic_ssbo_atomic_umax_ir3:
1589 case nir_intrinsic_ssbo_atomic_and_ir3:
1590 case nir_intrinsic_ssbo_atomic_or_ir3:
1591 case nir_intrinsic_ssbo_atomic_xor_ir3:
1592 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1593 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1594 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1595 !ctx->s->info.fs.early_fragment_tests)
1596 ctx->so->no_earlyz = true;
1597 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1598 break;
1599 case nir_intrinsic_load_shared:
1600 emit_intrinsic_load_shared(ctx, intr, dst);
1601 break;
1602 case nir_intrinsic_store_shared:
1603 emit_intrinsic_store_shared(ctx, intr);
1604 break;
1605 case nir_intrinsic_shared_atomic_add:
1606 case nir_intrinsic_shared_atomic_imin:
1607 case nir_intrinsic_shared_atomic_umin:
1608 case nir_intrinsic_shared_atomic_imax:
1609 case nir_intrinsic_shared_atomic_umax:
1610 case nir_intrinsic_shared_atomic_and:
1611 case nir_intrinsic_shared_atomic_or:
1612 case nir_intrinsic_shared_atomic_xor:
1613 case nir_intrinsic_shared_atomic_exchange:
1614 case nir_intrinsic_shared_atomic_comp_swap:
1615 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1616 break;
1617 case nir_intrinsic_image_deref_load:
1618 emit_intrinsic_load_image(ctx, intr, dst);
1619 break;
1620 case nir_intrinsic_image_deref_store:
1621 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1622 !ctx->s->info.fs.early_fragment_tests)
1623 ctx->so->no_earlyz = true;
1624 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1625 break;
1626 case nir_intrinsic_image_deref_size:
1627 emit_intrinsic_image_size(ctx, intr, dst);
1628 break;
1629 case nir_intrinsic_image_deref_atomic_add:
1630 case nir_intrinsic_image_deref_atomic_imin:
1631 case nir_intrinsic_image_deref_atomic_umin:
1632 case nir_intrinsic_image_deref_atomic_imax:
1633 case nir_intrinsic_image_deref_atomic_umax:
1634 case nir_intrinsic_image_deref_atomic_and:
1635 case nir_intrinsic_image_deref_atomic_or:
1636 case nir_intrinsic_image_deref_atomic_xor:
1637 case nir_intrinsic_image_deref_atomic_exchange:
1638 case nir_intrinsic_image_deref_atomic_comp_swap:
1639 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1640 !ctx->s->info.fs.early_fragment_tests)
1641 ctx->so->no_earlyz = true;
1642 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1643 break;
1644 case nir_intrinsic_control_barrier:
1645 case nir_intrinsic_memory_barrier:
1646 case nir_intrinsic_group_memory_barrier:
1647 case nir_intrinsic_memory_barrier_atomic_counter:
1648 case nir_intrinsic_memory_barrier_buffer:
1649 case nir_intrinsic_memory_barrier_image:
1650 case nir_intrinsic_memory_barrier_shared:
1651 emit_intrinsic_barrier(ctx, intr);
1652 /* note that blk ptr no longer valid, make that obvious: */
1653 b = NULL;
1654 break;
1655 case nir_intrinsic_store_output:
1656 idx = nir_intrinsic_base(intr);
1657 comp = nir_intrinsic_component(intr);
1658 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1659 idx += nir_src_as_uint(intr->src[1]);
1660
1661 src = ir3_get_src(ctx, &intr->src[0]);
1662 for (int i = 0; i < intr->num_components; i++) {
1663 unsigned n = idx * 4 + i + comp;
1664 ctx->outputs[n] = src[i];
1665 }
1666 break;
1667 case nir_intrinsic_load_base_vertex:
1668 case nir_intrinsic_load_first_vertex:
1669 if (!ctx->basevertex) {
1670 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1671 }
1672 dst[0] = ctx->basevertex;
1673 break;
1674 case nir_intrinsic_load_base_instance:
1675 if (!ctx->base_instance) {
1676 ctx->base_instance = create_driver_param(ctx, IR3_DP_INSTID_BASE);
1677 }
1678 dst[0] = ctx->base_instance;
1679 break;
1680 case nir_intrinsic_load_vertex_id_zero_base:
1681 case nir_intrinsic_load_vertex_id:
1682 if (!ctx->vertex_id) {
1683 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1684 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1685 ctx->vertex_id = create_sysval_input(ctx, sv, 0x1);
1686 }
1687 dst[0] = ctx->vertex_id;
1688 break;
1689 case nir_intrinsic_load_instance_id:
1690 if (!ctx->instance_id) {
1691 ctx->instance_id = create_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 0x1);
1692 }
1693 dst[0] = ctx->instance_id;
1694 break;
1695 case nir_intrinsic_load_sample_id:
1696 ctx->so->per_samp = true;
1697 /* fall-thru */
1698 case nir_intrinsic_load_sample_id_no_per_sample:
1699 if (!ctx->samp_id) {
1700 ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1);
1701 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1702 }
1703 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1704 break;
1705 case nir_intrinsic_load_sample_mask_in:
1706 if (!ctx->samp_mask_in) {
1707 ctx->samp_mask_in = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
1708 }
1709 dst[0] = ctx->samp_mask_in;
1710 break;
1711 case nir_intrinsic_load_user_clip_plane:
1712 idx = nir_intrinsic_ucp_id(intr);
1713 for (int i = 0; i < intr->num_components; i++) {
1714 unsigned n = idx * 4 + i;
1715 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1716 }
1717 break;
1718 case nir_intrinsic_load_front_face:
1719 if (!ctx->frag_face) {
1720 ctx->so->frag_face = true;
1721 ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1);
1722 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1723 }
1724 /* for fragface, we get -1 for back and 0 for front. However this is
1725 * the inverse of what nir expects (where ~0 is true).
1726 */
1727 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1728 dst[0] = ir3_NOT_B(b, dst[0], 0);
1729 break;
1730 case nir_intrinsic_load_local_invocation_id:
1731 if (!ctx->local_invocation_id) {
1732 ctx->local_invocation_id =
1733 create_sysval_input(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 0x7);
1734 }
1735 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1736 break;
1737 case nir_intrinsic_load_work_group_id:
1738 if (!ctx->work_group_id) {
1739 ctx->work_group_id =
1740 create_sysval_input(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 0x7);
1741 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1742 }
1743 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1744 break;
1745 case nir_intrinsic_load_num_work_groups:
1746 for (int i = 0; i < intr->num_components; i++) {
1747 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1748 }
1749 break;
1750 case nir_intrinsic_load_local_group_size:
1751 for (int i = 0; i < intr->num_components; i++) {
1752 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1753 }
1754 break;
1755 case nir_intrinsic_discard_if:
1756 case nir_intrinsic_discard: {
1757 struct ir3_instruction *cond, *kill;
1758
1759 if (intr->intrinsic == nir_intrinsic_discard_if) {
1760 /* conditional discard: */
1761 src = ir3_get_src(ctx, &intr->src[0]);
1762 cond = ir3_b2n(b, src[0]);
1763 } else {
1764 /* unconditional discard: */
1765 cond = create_immed(b, 1);
1766 }
1767
1768 /* NOTE: only cmps.*.* can write p0.x: */
1769 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1770 cond->cat2.condition = IR3_COND_NE;
1771
1772 /* condition always goes in predicate register: */
1773 cond->regs[0]->num = regid(REG_P0, 0);
1774 cond->regs[0]->flags &= ~IR3_REG_SSA;
1775
1776 kill = ir3_KILL(b, cond, 0);
1777 array_insert(ctx->ir, ctx->ir->predicates, kill);
1778
1779 array_insert(b, b->keeps, kill);
1780 ctx->so->no_earlyz = true;
1781
1782 break;
1783 }
1784
1785 case nir_intrinsic_cond_end_ir3: {
1786 struct ir3_instruction *cond, *kill;
1787
1788 src = ir3_get_src(ctx, &intr->src[0]);
1789 cond = ir3_b2n(b, src[0]);
1790
1791 /* NOTE: only cmps.*.* can write p0.x: */
1792 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1793 cond->cat2.condition = IR3_COND_NE;
1794
1795 /* condition always goes in predicate register: */
1796 cond->regs[0]->num = regid(REG_P0, 0);
1797
1798 kill = ir3_CONDEND(b, cond, 0);
1799
1800 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1801 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1802
1803 array_insert(ctx->ir, ctx->ir->predicates, kill);
1804 array_insert(b, b->keeps, kill);
1805 break;
1806 }
1807
1808 case nir_intrinsic_load_shared_ir3:
1809 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1810 break;
1811 case nir_intrinsic_store_shared_ir3:
1812 emit_intrinsic_store_shared_ir3(ctx, intr);
1813 break;
1814 default:
1815 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1816 nir_intrinsic_infos[intr->intrinsic].name);
1817 break;
1818 }
1819
1820 if (info->has_dest)
1821 ir3_put_dst(ctx, &intr->dest);
1822 }
1823
1824 static void
1825 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1826 {
1827 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1828 instr->def.num_components);
1829
1830 if (instr->def.bit_size < 32) {
1831 for (int i = 0; i < instr->def.num_components; i++)
1832 dst[i] = create_immed_typed(ctx->block,
1833 instr->value[i].u16,
1834 TYPE_U16);
1835 } else {
1836 for (int i = 0; i < instr->def.num_components; i++)
1837 dst[i] = create_immed_typed(ctx->block,
1838 instr->value[i].u32,
1839 TYPE_U32);
1840 }
1841
1842 }
1843
1844 static void
1845 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1846 {
1847 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1848 undef->def.num_components);
1849 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1850
1851 /* backend doesn't want undefined instructions, so just plug
1852 * in 0.0..
1853 */
1854 for (int i = 0; i < undef->def.num_components; i++)
1855 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1856 }
1857
1858 /*
1859 * texture fetch/sample instructions:
1860 */
1861
1862 static type_t
1863 get_tex_dest_type(nir_tex_instr *tex)
1864 {
1865 type_t type;
1866
1867 switch (nir_alu_type_get_base_type(tex->dest_type)) {
1868 case nir_type_invalid:
1869 case nir_type_float:
1870 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_F16 : TYPE_F32;
1871 break;
1872 case nir_type_int:
1873 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_S16 : TYPE_S32;
1874 break;
1875 case nir_type_uint:
1876 case nir_type_bool:
1877 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_U16 : TYPE_U32;
1878 break;
1879 default:
1880 unreachable("bad dest_type");
1881 }
1882
1883 return type;
1884 }
1885
1886 static void
1887 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1888 {
1889 unsigned coords, flags = 0;
1890
1891 /* note: would use tex->coord_components.. except txs.. also,
1892 * since array index goes after shadow ref, we don't want to
1893 * count it:
1894 */
1895 switch (tex->sampler_dim) {
1896 case GLSL_SAMPLER_DIM_1D:
1897 case GLSL_SAMPLER_DIM_BUF:
1898 coords = 1;
1899 break;
1900 case GLSL_SAMPLER_DIM_2D:
1901 case GLSL_SAMPLER_DIM_RECT:
1902 case GLSL_SAMPLER_DIM_EXTERNAL:
1903 case GLSL_SAMPLER_DIM_MS:
1904 case GLSL_SAMPLER_DIM_SUBPASS:
1905 case GLSL_SAMPLER_DIM_SUBPASS_MS:
1906 coords = 2;
1907 break;
1908 case GLSL_SAMPLER_DIM_3D:
1909 case GLSL_SAMPLER_DIM_CUBE:
1910 coords = 3;
1911 flags |= IR3_INSTR_3D;
1912 break;
1913 default:
1914 unreachable("bad sampler_dim");
1915 }
1916
1917 if (tex->is_shadow && tex->op != nir_texop_lod)
1918 flags |= IR3_INSTR_S;
1919
1920 if (tex->is_array && tex->op != nir_texop_lod)
1921 flags |= IR3_INSTR_A;
1922
1923 *flagsp = flags;
1924 *coordsp = coords;
1925 }
1926
1927 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1928 * or immediate (in which case it will get lowered later to a non .s2en
1929 * version of the tex instruction which encode tex/samp as immediates:
1930 */
1931 static struct ir3_instruction *
1932 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1933 {
1934 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1935 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1936 struct ir3_instruction *texture, *sampler;
1937
1938 if (texture_idx >= 0) {
1939 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1940 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1941 } else {
1942 /* TODO what to do for dynamic case? I guess we only need the
1943 * max index for astc srgb workaround so maybe not a problem
1944 * to worry about if we don't enable indirect samplers for
1945 * a4xx?
1946 */
1947 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1948 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1949 }
1950
1951 if (sampler_idx >= 0) {
1952 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1953 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1954 } else {
1955 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1956 }
1957
1958 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1959 sampler,
1960 texture,
1961 }, 2);
1962 }
1963
1964 static void
1965 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1966 {
1967 struct ir3_block *b = ctx->block;
1968 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1969 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1970 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1971 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1972 unsigned i, coords, flags, ncomp;
1973 unsigned nsrc0 = 0, nsrc1 = 0;
1974 type_t type;
1975 opc_t opc = 0;
1976
1977 ncomp = nir_dest_num_components(tex->dest);
1978
1979 coord = off = ddx = ddy = NULL;
1980 lod = proj = compare = sample_index = NULL;
1981
1982 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1983
1984 for (unsigned i = 0; i < tex->num_srcs; i++) {
1985 switch (tex->src[i].src_type) {
1986 case nir_tex_src_coord:
1987 coord = ir3_get_src(ctx, &tex->src[i].src);
1988 break;
1989 case nir_tex_src_bias:
1990 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1991 has_bias = true;
1992 break;
1993 case nir_tex_src_lod:
1994 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1995 has_lod = true;
1996 break;
1997 case nir_tex_src_comparator: /* shadow comparator */
1998 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1999 break;
2000 case nir_tex_src_projector:
2001 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
2002 has_proj = true;
2003 break;
2004 case nir_tex_src_offset:
2005 off = ir3_get_src(ctx, &tex->src[i].src);
2006 has_off = true;
2007 break;
2008 case nir_tex_src_ddx:
2009 ddx = ir3_get_src(ctx, &tex->src[i].src);
2010 break;
2011 case nir_tex_src_ddy:
2012 ddy = ir3_get_src(ctx, &tex->src[i].src);
2013 break;
2014 case nir_tex_src_ms_index:
2015 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
2016 break;
2017 case nir_tex_src_texture_offset:
2018 case nir_tex_src_sampler_offset:
2019 /* handled in get_tex_samp_src() */
2020 break;
2021 default:
2022 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
2023 tex->src[i].src_type);
2024 return;
2025 }
2026 }
2027
2028 switch (tex->op) {
2029 case nir_texop_tex_prefetch:
2030 compile_assert(ctx, !has_bias);
2031 compile_assert(ctx, !has_lod);
2032 compile_assert(ctx, !compare);
2033 compile_assert(ctx, !has_proj);
2034 compile_assert(ctx, !has_off);
2035 compile_assert(ctx, !ddx);
2036 compile_assert(ctx, !ddy);
2037 compile_assert(ctx, !sample_index);
2038 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
2039 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
2040
2041 if (ctx->so->num_sampler_prefetch < IR3_MAX_SAMPLER_PREFETCH) {
2042 opc = OPC_META_TEX_PREFETCH;
2043 ctx->so->num_sampler_prefetch++;
2044 break;
2045 }
2046 /* fallthru */
2047 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
2048 case nir_texop_txb: opc = OPC_SAMB; break;
2049 case nir_texop_txl: opc = OPC_SAML; break;
2050 case nir_texop_txd: opc = OPC_SAMGQ; break;
2051 case nir_texop_txf: opc = OPC_ISAML; break;
2052 case nir_texop_lod: opc = OPC_GETLOD; break;
2053 case nir_texop_tg4:
2054 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2055 * what blob does, seems gather is broken?), and a3xx did
2056 * not support it (but probably could also emulate).
2057 */
2058 switch (tex->component) {
2059 case 0: opc = OPC_GATHER4R; break;
2060 case 1: opc = OPC_GATHER4G; break;
2061 case 2: opc = OPC_GATHER4B; break;
2062 case 3: opc = OPC_GATHER4A; break;
2063 }
2064 break;
2065 case nir_texop_txf_ms_fb:
2066 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2067 default:
2068 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2069 return;
2070 }
2071
2072 tex_info(tex, &flags, &coords);
2073
2074 /*
2075 * lay out the first argument in the proper order:
2076 * - actual coordinates first
2077 * - shadow reference
2078 * - array index
2079 * - projection w
2080 * - starting at offset 4, dpdx.xy, dpdy.xy
2081 *
2082 * bias/lod go into the second arg
2083 */
2084
2085 /* insert tex coords: */
2086 for (i = 0; i < coords; i++)
2087 src0[i] = coord[i];
2088
2089 nsrc0 = i;
2090
2091 /* scale up integer coords for TXF based on the LOD */
2092 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2093 assert(has_lod);
2094 for (i = 0; i < coords; i++)
2095 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2096 }
2097
2098 if (coords == 1) {
2099 /* hw doesn't do 1d, so we treat it as 2d with
2100 * height of 1, and patch up the y coord.
2101 */
2102 if (is_isam(opc)) {
2103 src0[nsrc0++] = create_immed(b, 0);
2104 } else {
2105 src0[nsrc0++] = create_immed(b, fui(0.5));
2106 }
2107 }
2108
2109 if (tex->is_shadow && tex->op != nir_texop_lod)
2110 src0[nsrc0++] = compare;
2111
2112 if (tex->is_array && tex->op != nir_texop_lod) {
2113 struct ir3_instruction *idx = coord[coords];
2114
2115 /* the array coord for cube arrays needs 0.5 added to it */
2116 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2117 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2118
2119 src0[nsrc0++] = idx;
2120 }
2121
2122 if (has_proj) {
2123 src0[nsrc0++] = proj;
2124 flags |= IR3_INSTR_P;
2125 }
2126
2127 /* pad to 4, then ddx/ddy: */
2128 if (tex->op == nir_texop_txd) {
2129 while (nsrc0 < 4)
2130 src0[nsrc0++] = create_immed(b, fui(0.0));
2131 for (i = 0; i < coords; i++)
2132 src0[nsrc0++] = ddx[i];
2133 if (coords < 2)
2134 src0[nsrc0++] = create_immed(b, fui(0.0));
2135 for (i = 0; i < coords; i++)
2136 src0[nsrc0++] = ddy[i];
2137 if (coords < 2)
2138 src0[nsrc0++] = create_immed(b, fui(0.0));
2139 }
2140
2141 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2142 * with scaled x coord according to requested sample:
2143 */
2144 if (opc == OPC_ISAMM) {
2145 if (ctx->compiler->txf_ms_with_isaml) {
2146 /* the samples are laid out in x dimension as
2147 * 0 1 2 3
2148 * x_ms = (x << ms) + sample_index;
2149 */
2150 struct ir3_instruction *ms;
2151 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2152
2153 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2154 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2155
2156 opc = OPC_ISAML;
2157 } else {
2158 src0[nsrc0++] = sample_index;
2159 }
2160 }
2161
2162 /*
2163 * second argument (if applicable):
2164 * - offsets
2165 * - lod
2166 * - bias
2167 */
2168 if (has_off | has_lod | has_bias) {
2169 if (has_off) {
2170 unsigned off_coords = coords;
2171 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2172 off_coords--;
2173 for (i = 0; i < off_coords; i++)
2174 src1[nsrc1++] = off[i];
2175 if (off_coords < 2)
2176 src1[nsrc1++] = create_immed(b, fui(0.0));
2177 flags |= IR3_INSTR_O;
2178 }
2179
2180 if (has_lod | has_bias)
2181 src1[nsrc1++] = lod;
2182 }
2183
2184 type = get_tex_dest_type(tex);
2185
2186 if (opc == OPC_GETLOD)
2187 type = TYPE_S32;
2188
2189 struct ir3_instruction *samp_tex;
2190
2191 if (tex->op == nir_texop_txf_ms_fb) {
2192 /* only expect a single txf_ms_fb per shader: */
2193 compile_assert(ctx, !ctx->so->fb_read);
2194 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2195
2196 ctx->so->fb_read = true;
2197 samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2198 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2199 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2200 }, 2);
2201
2202 ctx->so->num_samp++;
2203 } else {
2204 samp_tex = get_tex_samp_tex_src(ctx, tex);
2205 }
2206
2207 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2208 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2209
2210 if (opc == OPC_META_TEX_PREFETCH) {
2211 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2212
2213 compile_assert(ctx, tex->src[idx].src.is_ssa);
2214
2215 sam = ir3_META_TEX_PREFETCH(b);
2216 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2217 sam->prefetch.input_offset =
2218 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2219 sam->prefetch.tex = tex->texture_index;
2220 sam->prefetch.samp = tex->sampler_index;
2221 } else {
2222 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
2223 samp_tex, col0, col1);
2224 }
2225
2226 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2227 assert(opc != OPC_META_TEX_PREFETCH);
2228
2229 /* only need first 3 components: */
2230 sam->regs[0]->wrmask = 0x7;
2231 ir3_split_dest(b, dst, sam, 0, 3);
2232
2233 /* we need to sample the alpha separately with a non-ASTC
2234 * texture state:
2235 */
2236 sam = ir3_SAM(b, opc, type, 0b1000, flags,
2237 samp_tex, col0, col1);
2238
2239 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2240
2241 /* fixup .w component: */
2242 ir3_split_dest(b, &dst[3], sam, 3, 1);
2243 } else {
2244 /* normal (non-workaround) case: */
2245 ir3_split_dest(b, dst, sam, 0, ncomp);
2246 }
2247
2248 /* GETLOD returns results in 4.8 fixed point */
2249 if (opc == OPC_GETLOD) {
2250 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2251
2252 compile_assert(ctx, tex->dest_type == nir_type_float);
2253 for (i = 0; i < 2; i++) {
2254 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2255 factor, 0);
2256 }
2257 }
2258
2259 ir3_put_dst(ctx, &tex->dest);
2260 }
2261
2262 static void
2263 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2264 {
2265 struct ir3_block *b = ctx->block;
2266 struct ir3_instruction **dst, *sam;
2267 type_t dst_type = get_tex_dest_type(tex);
2268
2269 dst = ir3_get_dst(ctx, &tex->dest, 1);
2270
2271 sam = ir3_SAM(b, OPC_GETINFO, dst_type, 1 << idx, 0,
2272 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
2273
2274 /* even though there is only one component, since it ends
2275 * up in .y/.z/.w rather than .x, we need a split_dest()
2276 */
2277 if (idx)
2278 ir3_split_dest(b, dst, sam, 0, idx + 1);
2279
2280 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2281 * the value in TEX_CONST_0 is zero-based.
2282 */
2283 if (ctx->compiler->levels_add_one)
2284 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2285
2286 ir3_put_dst(ctx, &tex->dest);
2287 }
2288
2289 static void
2290 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2291 {
2292 struct ir3_block *b = ctx->block;
2293 struct ir3_instruction **dst, *sam;
2294 struct ir3_instruction *lod;
2295 unsigned flags, coords;
2296 type_t dst_type = get_tex_dest_type(tex);
2297
2298 tex_info(tex, &flags, &coords);
2299
2300 /* Actually we want the number of dimensions, not coordinates. This
2301 * distinction only matters for cubes.
2302 */
2303 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2304 coords = 2;
2305
2306 dst = ir3_get_dst(ctx, &tex->dest, 4);
2307
2308 compile_assert(ctx, tex->num_srcs == 1);
2309 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2310
2311 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2312
2313 sam = ir3_SAM(b, OPC_GETSIZE, dst_type, 0b1111, flags,
2314 get_tex_samp_tex_src(ctx, tex), lod, NULL);
2315
2316 ir3_split_dest(b, dst, sam, 0, 4);
2317
2318 /* Array size actually ends up in .w rather than .z. This doesn't
2319 * matter for miplevel 0, but for higher mips the value in z is
2320 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2321 * returned, which means that we have to add 1 to it for arrays.
2322 */
2323 if (tex->is_array) {
2324 if (ctx->compiler->levels_add_one) {
2325 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2326 } else {
2327 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2328 }
2329 }
2330
2331 ir3_put_dst(ctx, &tex->dest);
2332 }
2333
2334 static void
2335 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2336 {
2337 switch (jump->type) {
2338 case nir_jump_break:
2339 case nir_jump_continue:
2340 case nir_jump_return:
2341 /* I *think* we can simply just ignore this, and use the
2342 * successor block link to figure out where we need to
2343 * jump to for break/continue
2344 */
2345 break;
2346 default:
2347 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2348 break;
2349 }
2350 }
2351
2352 static void
2353 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2354 {
2355 switch (instr->type) {
2356 case nir_instr_type_alu:
2357 emit_alu(ctx, nir_instr_as_alu(instr));
2358 break;
2359 case nir_instr_type_deref:
2360 /* ignored, handled as part of the intrinsic they are src to */
2361 break;
2362 case nir_instr_type_intrinsic:
2363 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2364 break;
2365 case nir_instr_type_load_const:
2366 emit_load_const(ctx, nir_instr_as_load_const(instr));
2367 break;
2368 case nir_instr_type_ssa_undef:
2369 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2370 break;
2371 case nir_instr_type_tex: {
2372 nir_tex_instr *tex = nir_instr_as_tex(instr);
2373 /* couple tex instructions get special-cased:
2374 */
2375 switch (tex->op) {
2376 case nir_texop_txs:
2377 emit_tex_txs(ctx, tex);
2378 break;
2379 case nir_texop_query_levels:
2380 emit_tex_info(ctx, tex, 2);
2381 break;
2382 case nir_texop_texture_samples:
2383 emit_tex_info(ctx, tex, 3);
2384 break;
2385 default:
2386 emit_tex(ctx, tex);
2387 break;
2388 }
2389 break;
2390 }
2391 case nir_instr_type_jump:
2392 emit_jump(ctx, nir_instr_as_jump(instr));
2393 break;
2394 case nir_instr_type_phi:
2395 /* we have converted phi webs to regs in NIR by now */
2396 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2397 break;
2398 case nir_instr_type_call:
2399 case nir_instr_type_parallel_copy:
2400 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2401 break;
2402 }
2403 }
2404
2405 static struct ir3_block *
2406 get_block(struct ir3_context *ctx, const nir_block *nblock)
2407 {
2408 struct ir3_block *block;
2409 struct hash_entry *hentry;
2410
2411 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2412 if (hentry)
2413 return hentry->data;
2414
2415 block = ir3_block_create(ctx->ir);
2416 block->nblock = nblock;
2417 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2418
2419 block->predecessors = _mesa_pointer_set_create(block);
2420 set_foreach(nblock->predecessors, sentry) {
2421 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2422 }
2423
2424 return block;
2425 }
2426
2427 static void
2428 emit_block(struct ir3_context *ctx, nir_block *nblock)
2429 {
2430 struct ir3_block *block = get_block(ctx, nblock);
2431
2432 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2433 if (nblock->successors[i]) {
2434 block->successors[i] =
2435 get_block(ctx, nblock->successors[i]);
2436 }
2437 }
2438
2439 ctx->block = block;
2440 list_addtail(&block->node, &ctx->ir->block_list);
2441
2442 /* re-emit addr register in each block if needed: */
2443 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2444 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2445 ctx->addr_ht[i] = NULL;
2446 }
2447
2448 nir_foreach_instr(instr, nblock) {
2449 ctx->cur_instr = instr;
2450 emit_instr(ctx, instr);
2451 ctx->cur_instr = NULL;
2452 if (ctx->error)
2453 return;
2454 }
2455 }
2456
2457 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2458
2459 static void
2460 emit_if(struct ir3_context *ctx, nir_if *nif)
2461 {
2462 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2463
2464 ctx->block->condition =
2465 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2466
2467 emit_cf_list(ctx, &nif->then_list);
2468 emit_cf_list(ctx, &nif->else_list);
2469 }
2470
2471 static void
2472 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2473 {
2474 emit_cf_list(ctx, &nloop->body);
2475 ctx->so->loops++;
2476 }
2477
2478 static void
2479 stack_push(struct ir3_context *ctx)
2480 {
2481 ctx->stack++;
2482 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2483 }
2484
2485 static void
2486 stack_pop(struct ir3_context *ctx)
2487 {
2488 compile_assert(ctx, ctx->stack > 0);
2489 ctx->stack--;
2490 }
2491
2492 static void
2493 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2494 {
2495 foreach_list_typed(nir_cf_node, node, node, list) {
2496 switch (node->type) {
2497 case nir_cf_node_block:
2498 emit_block(ctx, nir_cf_node_as_block(node));
2499 break;
2500 case nir_cf_node_if:
2501 stack_push(ctx);
2502 emit_if(ctx, nir_cf_node_as_if(node));
2503 stack_pop(ctx);
2504 break;
2505 case nir_cf_node_loop:
2506 stack_push(ctx);
2507 emit_loop(ctx, nir_cf_node_as_loop(node));
2508 stack_pop(ctx);
2509 break;
2510 case nir_cf_node_function:
2511 ir3_context_error(ctx, "TODO\n");
2512 break;
2513 }
2514 }
2515 }
2516
2517 /* emit stream-out code. At this point, the current block is the original
2518 * (nir) end block, and nir ensures that all flow control paths terminate
2519 * into the end block. We re-purpose the original end block to generate
2520 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2521 * block holding stream-out write instructions, followed by the new end
2522 * block:
2523 *
2524 * blockOrigEnd {
2525 * p0.x = (vtxcnt < maxvtxcnt)
2526 * // succs: blockStreamOut, blockNewEnd
2527 * }
2528 * blockStreamOut {
2529 * ... stream-out instructions ...
2530 * // succs: blockNewEnd
2531 * }
2532 * blockNewEnd {
2533 * }
2534 */
2535 static void
2536 emit_stream_out(struct ir3_context *ctx)
2537 {
2538 struct ir3 *ir = ctx->ir;
2539 struct ir3_stream_output_info *strmout =
2540 &ctx->so->shader->stream_output;
2541 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2542 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2543 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2544
2545 /* create vtxcnt input in input block at top of shader,
2546 * so that it is seen as live over the entire duration
2547 * of the shader:
2548 */
2549 vtxcnt = create_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, 0x1);
2550 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2551
2552 /* at this point, we are at the original 'end' block,
2553 * re-purpose this block to stream-out condition, then
2554 * append stream-out block and new-end block
2555 */
2556 orig_end_block = ctx->block;
2557
2558 // TODO these blocks need to update predecessors..
2559 // maybe w/ store_global intrinsic, we could do this
2560 // stuff in nir->nir pass
2561
2562 stream_out_block = ir3_block_create(ir);
2563 list_addtail(&stream_out_block->node, &ir->block_list);
2564
2565 new_end_block = ir3_block_create(ir);
2566 list_addtail(&new_end_block->node, &ir->block_list);
2567
2568 orig_end_block->successors[0] = stream_out_block;
2569 orig_end_block->successors[1] = new_end_block;
2570 stream_out_block->successors[0] = new_end_block;
2571
2572 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2573 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2574 cond->regs[0]->num = regid(REG_P0, 0);
2575 cond->regs[0]->flags &= ~IR3_REG_SSA;
2576 cond->cat2.condition = IR3_COND_LT;
2577
2578 /* condition goes on previous block to the conditional,
2579 * since it is used to pick which of the two successor
2580 * paths to take:
2581 */
2582 orig_end_block->condition = cond;
2583
2584 /* switch to stream_out_block to generate the stream-out
2585 * instructions:
2586 */
2587 ctx->block = stream_out_block;
2588
2589 /* Calculate base addresses based on vtxcnt. Instructions
2590 * generated for bases not used in following loop will be
2591 * stripped out in the backend.
2592 */
2593 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2594 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2595 unsigned stride = strmout->stride[i];
2596 struct ir3_instruction *base, *off;
2597
2598 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2599
2600 /* 24-bit should be enough: */
2601 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2602 create_immed(ctx->block, stride * 4), 0);
2603
2604 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2605 }
2606
2607 /* Generate the per-output store instructions: */
2608 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2609 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2610 unsigned c = j + strmout->output[i].start_component;
2611 struct ir3_instruction *base, *out, *stg;
2612
2613 base = bases[strmout->output[i].output_buffer];
2614 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2615
2616 stg = ir3_STG(ctx->block, base, 0, out, 0,
2617 create_immed(ctx->block, 1), 0);
2618 stg->cat6.type = TYPE_U32;
2619 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2620
2621 array_insert(ctx->block, ctx->block->keeps, stg);
2622 }
2623 }
2624
2625 /* and finally switch to the new_end_block: */
2626 ctx->block = new_end_block;
2627 }
2628
2629 static void
2630 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2631 {
2632 nir_metadata_require(impl, nir_metadata_block_index);
2633
2634 compile_assert(ctx, ctx->stack == 0);
2635
2636 emit_cf_list(ctx, &impl->body);
2637 emit_block(ctx, impl->end_block);
2638
2639 compile_assert(ctx, ctx->stack == 0);
2640
2641 /* at this point, we should have a single empty block,
2642 * into which we emit the 'end' instruction.
2643 */
2644 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2645
2646 /* If stream-out (aka transform-feedback) enabled, emit the
2647 * stream-out instructions, followed by a new empty block (into
2648 * which the 'end' instruction lands).
2649 *
2650 * NOTE: it is done in this order, rather than inserting before
2651 * we emit end_block, because NIR guarantees that all blocks
2652 * flow into end_block, and that end_block has no successors.
2653 * So by re-purposing end_block as the first block of stream-
2654 * out, we guarantee that all exit paths flow into the stream-
2655 * out instructions.
2656 */
2657 if ((ctx->compiler->gpu_id < 500) &&
2658 (ctx->so->shader->stream_output.num_outputs > 0) &&
2659 !ctx->so->binning_pass) {
2660 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2661 emit_stream_out(ctx);
2662 }
2663
2664 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2665 * NOP and has an epilogue that writes the VS outputs to local storage, to
2666 * be read by the HS. Then it resets execution mask (chmask) and chains
2667 * to the next shader (chsh).
2668 */
2669 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2670 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2671 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2672 struct ir3_instruction *chmask =
2673 ir3_CHMASK(ctx->block);
2674 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2675 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2676
2677 struct ir3_instruction *chsh =
2678 ir3_CHSH(ctx->block);
2679 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2680 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2681 } else {
2682 ir3_END(ctx->block);
2683 }
2684 }
2685
2686 static void
2687 setup_input(struct ir3_context *ctx, nir_variable *in)
2688 {
2689 struct ir3_shader_variant *so = ctx->so;
2690 unsigned ncomp = glsl_get_components(in->type);
2691 unsigned n = in->data.driver_location;
2692 unsigned frac = in->data.location_frac;
2693 unsigned slot = in->data.location;
2694
2695 /* Inputs are loaded using ldlw or ldg for these stages. */
2696 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2697 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2698 ctx->so->type == MESA_SHADER_GEOMETRY)
2699 return;
2700
2701 /* skip unread inputs, we could end up with (for example), unsplit
2702 * matrix/etc inputs in the case they are not read, so just silently
2703 * skip these.
2704 */
2705 if (ncomp > 4)
2706 return;
2707
2708 so->inputs[n].slot = slot;
2709 so->inputs[n].compmask = (1 << (ncomp + frac)) - 1;
2710 so->inputs_count = MAX2(so->inputs_count, n + 1);
2711 so->inputs[n].interpolate = in->data.interpolation;
2712
2713 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2714
2715 /* if any varyings have 'sample' qualifer, that triggers us
2716 * to run in per-sample mode:
2717 */
2718 so->per_samp |= in->data.sample;
2719
2720 for (int i = 0; i < ncomp; i++) {
2721 struct ir3_instruction *instr = NULL;
2722 unsigned idx = (n * 4) + i + frac;
2723
2724 if (slot == VARYING_SLOT_POS) {
2725 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2726 } else if (slot == VARYING_SLOT_PNTC) {
2727 /* see for example st_nir_fixup_varying_slots().. this is
2728 * maybe a bit mesa/st specific. But we need things to line
2729 * up for this in fdN_program:
2730 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2731 * if (emit->sprite_coord_enable & texmask) {
2732 * ...
2733 * }
2734 */
2735 so->inputs[n].slot = VARYING_SLOT_VAR8;
2736 so->inputs[n].bary = true;
2737 instr = create_frag_input(ctx, false, idx);
2738 } else {
2739 /* detect the special case for front/back colors where
2740 * we need to do flat vs smooth shading depending on
2741 * rast state:
2742 */
2743 if (in->data.interpolation == INTERP_MODE_NONE) {
2744 switch (slot) {
2745 case VARYING_SLOT_COL0:
2746 case VARYING_SLOT_COL1:
2747 case VARYING_SLOT_BFC0:
2748 case VARYING_SLOT_BFC1:
2749 so->inputs[n].rasterflat = true;
2750 break;
2751 default:
2752 break;
2753 }
2754 }
2755
2756 if (ctx->compiler->flat_bypass) {
2757 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2758 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2759 so->inputs[n].use_ldlv = true;
2760 }
2761
2762 so->inputs[n].bary = true;
2763
2764 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2765 }
2766
2767 compile_assert(ctx, idx < ctx->ninputs);
2768
2769 ctx->inputs[idx] = instr;
2770 }
2771 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2772 /* We shouldn't have fractional input for VS input.. that only shows
2773 * up with varying packing
2774 */
2775 assert(frac == 0);
2776
2777 struct ir3_instruction *input = create_input(ctx, (1 << ncomp) - 1);
2778 struct ir3_instruction *components[ncomp];
2779
2780 input->input.inidx = n;
2781
2782 ir3_split_dest(ctx->block, components, input, 0, ncomp);
2783
2784 for (int i = 0; i < ncomp; i++) {
2785 unsigned idx = (n * 4) + i + frac;
2786 compile_assert(ctx, idx < ctx->ninputs);
2787 ctx->inputs[idx] = components[i];
2788 }
2789 } else {
2790 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2791 }
2792
2793 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2794 so->total_in += ncomp;
2795 }
2796 }
2797
2798 /* Initially we assign non-packed inloc's for varyings, as we don't really
2799 * know up-front which components will be unused. After all the compilation
2800 * stages we scan the shader to see which components are actually used, and
2801 * re-pack the inlocs to eliminate unneeded varyings.
2802 */
2803 static void
2804 pack_inlocs(struct ir3_context *ctx)
2805 {
2806 struct ir3_shader_variant *so = ctx->so;
2807 uint8_t used_components[so->inputs_count];
2808
2809 memset(used_components, 0, sizeof(used_components));
2810
2811 /*
2812 * First Step: scan shader to find which bary.f/ldlv remain:
2813 */
2814
2815 foreach_block (block, &ctx->ir->block_list) {
2816 foreach_instr (instr, &block->instr_list) {
2817 if (is_input(instr)) {
2818 unsigned inloc = instr->regs[1]->iim_val;
2819 unsigned i = inloc / 4;
2820 unsigned j = inloc % 4;
2821
2822 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
2823 compile_assert(ctx, i < so->inputs_count);
2824
2825 used_components[i] |= 1 << j;
2826 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
2827 for (int n = 0; n < 2; n++) {
2828 unsigned inloc = instr->prefetch.input_offset + n;
2829 unsigned i = inloc / 4;
2830 unsigned j = inloc % 4;
2831
2832 compile_assert(ctx, i < so->inputs_count);
2833
2834 used_components[i] |= 1 << j;
2835 }
2836 }
2837 }
2838 }
2839
2840 /*
2841 * Second Step: reassign varying inloc/slots:
2842 */
2843
2844 unsigned actual_in = 0;
2845 unsigned inloc = 0;
2846
2847 for (unsigned i = 0; i < so->inputs_count; i++) {
2848 unsigned compmask = 0, maxcomp = 0;
2849
2850 so->inputs[i].inloc = inloc;
2851 so->inputs[i].bary = false;
2852
2853 for (unsigned j = 0; j < 4; j++) {
2854 if (!(used_components[i] & (1 << j)))
2855 continue;
2856
2857 compmask |= (1 << j);
2858 actual_in++;
2859 maxcomp = j + 1;
2860
2861 /* at this point, since used_components[i] mask is only
2862 * considering varyings (ie. not sysvals) we know this
2863 * is a varying:
2864 */
2865 so->inputs[i].bary = true;
2866 }
2867
2868 if (so->inputs[i].bary) {
2869 so->varying_in++;
2870 so->inputs[i].compmask = (1 << maxcomp) - 1;
2871 inloc += maxcomp;
2872 }
2873 }
2874
2875 /*
2876 * Third Step: reassign packed inloc's:
2877 */
2878
2879 foreach_block (block, &ctx->ir->block_list) {
2880 foreach_instr (instr, &block->instr_list) {
2881 if (is_input(instr)) {
2882 unsigned inloc = instr->regs[1]->iim_val;
2883 unsigned i = inloc / 4;
2884 unsigned j = inloc % 4;
2885
2886 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
2887 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
2888 unsigned i = instr->prefetch.input_offset / 4;
2889 unsigned j = instr->prefetch.input_offset % 4;
2890 instr->prefetch.input_offset = so->inputs[i].inloc + j;
2891 }
2892 }
2893 }
2894 }
2895
2896 static void
2897 setup_output(struct ir3_context *ctx, nir_variable *out)
2898 {
2899 struct ir3_shader_variant *so = ctx->so;
2900 unsigned ncomp = glsl_get_components(out->type);
2901 unsigned n = out->data.driver_location;
2902 unsigned frac = out->data.location_frac;
2903 unsigned slot = out->data.location;
2904 unsigned comp = 0;
2905
2906 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2907 switch (slot) {
2908 case FRAG_RESULT_DEPTH:
2909 comp = 2; /* tgsi will write to .z component */
2910 so->writes_pos = true;
2911 break;
2912 case FRAG_RESULT_COLOR:
2913 so->color0_mrt = 1;
2914 break;
2915 case FRAG_RESULT_SAMPLE_MASK:
2916 so->writes_smask = true;
2917 break;
2918 default:
2919 if (slot >= FRAG_RESULT_DATA0)
2920 break;
2921 ir3_context_error(ctx, "unknown FS output name: %s\n",
2922 gl_frag_result_name(slot));
2923 }
2924 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
2925 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2926 ctx->so->type == MESA_SHADER_GEOMETRY) {
2927 switch (slot) {
2928 case VARYING_SLOT_POS:
2929 so->writes_pos = true;
2930 break;
2931 case VARYING_SLOT_PSIZ:
2932 so->writes_psize = true;
2933 break;
2934 case VARYING_SLOT_PRIMITIVE_ID:
2935 case VARYING_SLOT_LAYER:
2936 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
2937 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
2938 /* fall through */
2939 case VARYING_SLOT_COL0:
2940 case VARYING_SLOT_COL1:
2941 case VARYING_SLOT_BFC0:
2942 case VARYING_SLOT_BFC1:
2943 case VARYING_SLOT_FOGC:
2944 case VARYING_SLOT_CLIP_DIST0:
2945 case VARYING_SLOT_CLIP_DIST1:
2946 case VARYING_SLOT_CLIP_VERTEX:
2947 break;
2948 default:
2949 if (slot >= VARYING_SLOT_VAR0)
2950 break;
2951 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2952 break;
2953 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
2954 _mesa_shader_stage_to_string(ctx->so->type),
2955 gl_varying_slot_name(slot));
2956 }
2957 } else if (ctx->so->type == MESA_SHADER_TESS_CTRL) {
2958 /* output lowered to buffer writes. */
2959 return;
2960 } else {
2961 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2962 }
2963
2964 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2965
2966 so->outputs[n].slot = slot;
2967 so->outputs[n].regid = regid(n, comp);
2968 so->outputs_count = MAX2(so->outputs_count, n + 1);
2969
2970 for (int i = 0; i < ncomp; i++) {
2971 unsigned idx = (n * 4) + i + frac;
2972 compile_assert(ctx, idx < ctx->noutputs);
2973 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
2974 }
2975
2976 /* if varying packing doesn't happen, we could end up in a situation
2977 * with "holes" in the output, and since the per-generation code that
2978 * sets up varying linkage registers doesn't expect to have more than
2979 * one varying per vec4 slot, pad the holes.
2980 *
2981 * Note that this should probably generate a performance warning of
2982 * some sort.
2983 */
2984 for (int i = 0; i < frac; i++) {
2985 unsigned idx = (n * 4) + i;
2986 if (!ctx->outputs[idx]) {
2987 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
2988 }
2989 }
2990 }
2991
2992 static int
2993 max_drvloc(struct exec_list *vars)
2994 {
2995 int drvloc = -1;
2996 nir_foreach_variable(var, vars) {
2997 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2998 }
2999 return drvloc;
3000 }
3001
3002 static void
3003 emit_instructions(struct ir3_context *ctx)
3004 {
3005 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
3006
3007 ctx->ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
3008 ctx->noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
3009
3010 ctx->inputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->ninputs);
3011 ctx->outputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->noutputs);
3012
3013 ctx->ir = ir3_create(ctx->compiler, ctx->so->type);
3014
3015 /* Create inputs in first block: */
3016 ctx->block = get_block(ctx, nir_start_block(fxn));
3017 ctx->in_block = ctx->block;
3018 list_addtail(&ctx->block->node, &ctx->ir->block_list);
3019
3020 /* for fragment shader, the vcoord input register is used as the
3021 * base for bary.f varying fetch instrs:
3022 *
3023 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3024 * until emit_intrinsic when we know they are actually needed.
3025 * For now, we defer creating ctx->ij_centroid, etc, since we
3026 * only need ij_pixel for "old style" varying inputs (ie.
3027 * tgsi_to_nir)
3028 */
3029 struct ir3_instruction *vcoord = NULL;
3030 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3031 struct ir3_instruction *xy[2];
3032
3033 vcoord = create_input(ctx, 0x3);
3034 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
3035
3036 ctx->ij_pixel = ir3_create_collect(ctx, xy, 2);
3037 }
3038
3039 /* Setup inputs: */
3040 nir_foreach_variable(var, &ctx->s->inputs) {
3041 setup_input(ctx, var);
3042 }
3043
3044 /* Defer add_sysval_input() stuff until after setup_inputs(),
3045 * because sysvals need to be appended after varyings:
3046 */
3047 if (vcoord) {
3048 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PIXEL,
3049 0x3, vcoord);
3050 }
3051
3052
3053 /* Tesselation shaders always need primitive ID for indexing the
3054 * BO. Geometry shaders don't always need it but when they do it has be
3055 * delivered and unclobbered in the VS. To make things easy, we always
3056 * make room for it in VS/DS.
3057 */
3058 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
3059 bool has_gs = ctx->so->key.has_gs;
3060 switch (ctx->so->type) {
3061 case MESA_SHADER_VERTEX:
3062 if (has_tess) {
3063 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3064 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3065 } else if (has_gs) {
3066 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3067 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3068 }
3069 break;
3070 case MESA_SHADER_TESS_CTRL:
3071 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3072 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3073 break;
3074 case MESA_SHADER_TESS_EVAL:
3075 if (has_gs)
3076 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3077 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3078 break;
3079 case MESA_SHADER_GEOMETRY:
3080 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3081 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3082 break;
3083 default:
3084 break;
3085 }
3086
3087 /* Setup outputs: */
3088 nir_foreach_variable(var, &ctx->s->outputs) {
3089 setup_output(ctx, var);
3090 }
3091
3092 /* Find # of samplers: */
3093 nir_foreach_variable(var, &ctx->s->uniforms) {
3094 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
3095 /* just assume that we'll be reading from images.. if it
3096 * is write-only we don't have to count it, but not sure
3097 * if there is a good way to know?
3098 */
3099 ctx->so->num_samp += glsl_type_get_image_count(var->type);
3100 }
3101
3102 /* NOTE: need to do something more clever when we support >1 fxn */
3103 nir_foreach_register(reg, &fxn->registers) {
3104 ir3_declare_array(ctx, reg);
3105 }
3106 /* And emit the body: */
3107 ctx->impl = fxn;
3108 emit_function(ctx, fxn);
3109 }
3110
3111 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3112 * need to assign the tex state indexes for these after we know the
3113 * max tex index.
3114 */
3115 static void
3116 fixup_astc_srgb(struct ir3_context *ctx)
3117 {
3118 struct ir3_shader_variant *so = ctx->so;
3119 /* indexed by original tex idx, value is newly assigned alpha sampler
3120 * state tex idx. Zero is invalid since there is at least one sampler
3121 * if we get here.
3122 */
3123 unsigned alt_tex_state[16] = {0};
3124 unsigned tex_idx = ctx->max_texture_index + 1;
3125 unsigned idx = 0;
3126
3127 so->astc_srgb.base = tex_idx;
3128
3129 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3130 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3131
3132 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3133
3134 if (alt_tex_state[sam->cat5.tex] == 0) {
3135 /* assign new alternate/alpha tex state slot: */
3136 alt_tex_state[sam->cat5.tex] = tex_idx++;
3137 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3138 so->astc_srgb.count++;
3139 }
3140
3141 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3142 }
3143 }
3144
3145 static void
3146 fixup_binning_pass(struct ir3_context *ctx)
3147 {
3148 struct ir3_shader_variant *so = ctx->so;
3149 struct ir3 *ir = ctx->ir;
3150 unsigned i, j;
3151
3152 /* first pass, remove unused outputs from the IR level outputs: */
3153 for (i = 0, j = 0; i < ir->outputs_count; i++) {
3154 struct ir3_instruction *out = ir->outputs[i];
3155 assert(out->opc == OPC_META_COLLECT);
3156 unsigned outidx = out->collect.outidx;
3157 unsigned slot = so->outputs[outidx].slot;
3158
3159 /* throw away everything but first position/psize */
3160 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3161 ir->outputs[j] = ir->outputs[i];
3162 j++;
3163 }
3164 }
3165 ir->outputs_count = j;
3166
3167 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3168 * table:
3169 */
3170 for (i = 0, j = 0; i < so->outputs_count; i++) {
3171 unsigned slot = so->outputs[i].slot;
3172
3173 /* throw away everything but first position/psize */
3174 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3175 so->outputs[j] = so->outputs[i];
3176
3177 /* fixup outidx to point to new output table entry: */
3178 struct ir3_instruction *out;
3179 foreach_output(out, ir) {
3180 if (out->collect.outidx == i) {
3181 out->collect.outidx = j;
3182 break;
3183 }
3184 }
3185
3186 j++;
3187 }
3188 }
3189 so->outputs_count = j;
3190 }
3191
3192 static void
3193 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3194 {
3195 unsigned idx = 0;
3196
3197 /* Collect sampling instructions eligible for pre-dispatch. */
3198 foreach_block (block, &ir->block_list) {
3199 foreach_instr_safe (instr, &block->instr_list) {
3200 if (instr->opc == OPC_META_TEX_PREFETCH) {
3201 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3202 struct ir3_sampler_prefetch *fetch =
3203 &ctx->so->sampler_prefetch[idx];
3204 idx++;
3205
3206 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3207 fetch->wrmask = instr->regs[0]->wrmask;
3208 fetch->tex_id = instr->prefetch.tex;
3209 fetch->samp_id = instr->prefetch.samp;
3210 fetch->dst = instr->regs[0]->num;
3211 fetch->src = instr->prefetch.input_offset;
3212
3213 ctx->so->total_in =
3214 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3215
3216 /* Disable half precision until supported. */
3217 fetch->half_precision = !!(instr->regs[0]->flags & IR3_REG_HALF);
3218
3219 /* Remove the prefetch placeholder instruction: */
3220 list_delinit(&instr->node);
3221 }
3222 }
3223 }
3224 }
3225
3226 int
3227 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3228 struct ir3_shader_variant *so)
3229 {
3230 struct ir3_context *ctx;
3231 struct ir3 *ir;
3232 int ret = 0, max_bary;
3233
3234 assert(!so->ir);
3235
3236 ctx = ir3_context_init(compiler, so);
3237 if (!ctx) {
3238 DBG("INIT failed!");
3239 ret = -1;
3240 goto out;
3241 }
3242
3243 emit_instructions(ctx);
3244
3245 if (ctx->error) {
3246 DBG("EMIT failed!");
3247 ret = -1;
3248 goto out;
3249 }
3250
3251 ir = so->ir = ctx->ir;
3252
3253 assert((ctx->noutputs % 4) == 0);
3254
3255 /* Setup IR level outputs, which are "collects" that gather
3256 * the scalar components of outputs.
3257 */
3258 for (unsigned i = 0; i < ctx->noutputs; i += 4) {
3259 unsigned ncomp = 0;
3260 /* figure out the # of components written:
3261 *
3262 * TODO do we need to handle holes, ie. if .x and .z
3263 * components written, but .y component not written?
3264 */
3265 for (unsigned j = 0; j < 4; j++) {
3266 if (!ctx->outputs[i + j])
3267 break;
3268 ncomp++;
3269 }
3270
3271 /* Note that in some stages, like TCS, store_output is
3272 * lowered to memory writes, so no components of the
3273 * are "written" from the PoV of traditional store-
3274 * output instructions:
3275 */
3276 if (!ncomp)
3277 continue;
3278
3279 struct ir3_instruction *out =
3280 ir3_create_collect(ctx, &ctx->outputs[i], ncomp);
3281
3282 int outidx = i / 4;
3283 assert(outidx < so->outputs_count);
3284
3285 /* stash index into so->outputs[] so we can map the
3286 * output back to slot/etc later:
3287 */
3288 out->collect.outidx = outidx;
3289
3290 array_insert(ir, ir->outputs, out);
3291 }
3292
3293 /* Set up the gs header as an output for the vertex shader so it won't
3294 * clobber it for the tess ctrl shader.
3295 *
3296 * TODO this could probably be done more cleanly in a nir pass.
3297 */
3298 if (ctx->so->type == MESA_SHADER_VERTEX ||
3299 (ctx->so->key.has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3300 if (ctx->primitive_id) {
3301 unsigned n = so->outputs_count++;
3302 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3303
3304 struct ir3_instruction *out =
3305 ir3_create_collect(ctx, &ctx->primitive_id, 1);
3306 out->collect.outidx = n;
3307 array_insert(ir, ir->outputs, out);
3308 }
3309
3310 if (ctx->gs_header) {
3311 unsigned n = so->outputs_count++;
3312 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3313 struct ir3_instruction *out =
3314 ir3_create_collect(ctx, &ctx->gs_header, 1);
3315 out->collect.outidx = n;
3316 array_insert(ir, ir->outputs, out);
3317 }
3318
3319 if (ctx->tcs_header) {
3320 unsigned n = so->outputs_count++;
3321 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3322 struct ir3_instruction *out =
3323 ir3_create_collect(ctx, &ctx->tcs_header, 1);
3324 out->collect.outidx = n;
3325 array_insert(ir, ir->outputs, out);
3326 }
3327 }
3328
3329 /* at this point, for binning pass, throw away unneeded outputs: */
3330 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3331 fixup_binning_pass(ctx);
3332
3333 ir3_debug_print(ir, "BEFORE CP");
3334
3335 ir3_cp(ir, so);
3336
3337 /* at this point, for binning pass, throw away unneeded outputs:
3338 * Note that for a6xx and later, we do this after ir3_cp to ensure
3339 * that the uniform/constant layout for BS and VS matches, so that
3340 * we can re-use same VS_CONST state group.
3341 */
3342 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
3343 fixup_binning_pass(ctx);
3344
3345 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3346 * need to make sure not to remove any inputs that are used by
3347 * the nonbinning VS.
3348 */
3349 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3350 so->type == MESA_SHADER_VERTEX) {
3351 for (int i = 0; i < ctx->ninputs; i++) {
3352 struct ir3_instruction *in = ctx->inputs[i];
3353
3354 if (!in)
3355 continue;
3356
3357 unsigned n = i / 4;
3358 unsigned c = i % 4;
3359
3360 debug_assert(n < so->nonbinning->inputs_count);
3361
3362 if (so->nonbinning->inputs[n].sysval)
3363 continue;
3364
3365 /* be sure to keep inputs, even if only used in VS */
3366 if (so->nonbinning->inputs[n].compmask & (1 << c))
3367 array_insert(in->block, in->block->keeps, in);
3368 }
3369 }
3370
3371 ir3_debug_print(ir, "BEFORE GROUPING");
3372
3373 ir3_sched_add_deps(ir);
3374
3375 /* Group left/right neighbors, inserting mov's where needed to
3376 * solve conflicts:
3377 */
3378 ir3_group(ir);
3379
3380 ir3_debug_print(ir, "AFTER GROUPING");
3381
3382 ir3_depth(ir, so);
3383
3384 ir3_debug_print(ir, "AFTER DEPTH");
3385
3386 /* do Sethi–Ullman numbering before scheduling: */
3387 ir3_sun(ir);
3388
3389 ret = ir3_sched(ir);
3390 if (ret) {
3391 DBG("SCHED failed!");
3392 goto out;
3393 }
3394
3395 if (compiler->gpu_id >= 600) {
3396 ir3_a6xx_fixup_atomic_dests(ir, so);
3397 }
3398
3399 ir3_debug_print(ir, "AFTER SCHED");
3400
3401 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3402 * with draw pass VS, so binning and draw pass can both use the
3403 * same VBO state.
3404 *
3405 * Note that VS inputs are expected to be full precision.
3406 */
3407 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3408 (ir->type == MESA_SHADER_VERTEX) &&
3409 so->binning_pass;
3410
3411 if (pre_assign_inputs) {
3412 for (unsigned i = 0; i < ctx->ninputs; i++) {
3413 struct ir3_instruction *instr = ctx->inputs[i];
3414
3415 if (!instr)
3416 continue;
3417
3418 unsigned n = i / 4;
3419 unsigned c = i % 4;
3420 unsigned regid = so->nonbinning->inputs[n].regid + c;
3421
3422 instr->regs[0]->num = regid;
3423 }
3424
3425 ret = ir3_ra(so, ctx->inputs, ctx->ninputs);
3426 } else if (ctx->tcs_header) {
3427 /* We need to have these values in the same registers between VS and TCS
3428 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3429 */
3430
3431 ctx->tcs_header->regs[0]->num = regid(0, 0);
3432 ctx->primitive_id->regs[0]->num = regid(0, 1);
3433 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3434 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3435 } else if (ctx->gs_header) {
3436 /* We need to have these values in the same registers between producer
3437 * (VS or DS) and GS since the producer chains to GS and doesn't get
3438 * the sysvals redelivered.
3439 */
3440
3441 ctx->gs_header->regs[0]->num = regid(0, 0);
3442 ctx->primitive_id->regs[0]->num = regid(0, 1);
3443 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3444 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3445 } else if (so->num_sampler_prefetch) {
3446 assert(so->type == MESA_SHADER_FRAGMENT);
3447 struct ir3_instruction *instr, *precolor[2];
3448 int idx = 0;
3449
3450 foreach_input(instr, ir) {
3451 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PIXEL)
3452 continue;
3453
3454 assert(idx < ARRAY_SIZE(precolor));
3455
3456 precolor[idx] = instr;
3457 instr->regs[0]->num = idx;
3458
3459 idx++;
3460 }
3461 ret = ir3_ra(so, precolor, idx);
3462 } else {
3463 ret = ir3_ra(so, NULL, 0);
3464 }
3465
3466 if (ret) {
3467 DBG("RA failed!");
3468 goto out;
3469 }
3470
3471 ir3_debug_print(ir, "AFTER RA");
3472
3473 if (so->type == MESA_SHADER_FRAGMENT)
3474 pack_inlocs(ctx);
3475
3476 /*
3477 * Fixup inputs/outputs to point to the actual registers assigned:
3478 *
3479 * 1) initialize to r63.x (invalid/unused)
3480 * 2) iterate IR level inputs/outputs and update the variants
3481 * inputs/outputs table based on the assigned registers for
3482 * the remaining inputs/outputs.
3483 */
3484
3485 for (unsigned i = 0; i < so->inputs_count; i++)
3486 so->inputs[i].regid = INVALID_REG;
3487 for (unsigned i = 0; i < so->outputs_count; i++)
3488 so->outputs[i].regid = INVALID_REG;
3489
3490 struct ir3_instruction *out;
3491 foreach_output(out, ir) {
3492 assert(out->opc == OPC_META_COLLECT);
3493 unsigned outidx = out->collect.outidx;
3494
3495 so->outputs[outidx].regid = out->regs[0]->num;
3496 so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF);
3497 }
3498
3499 struct ir3_instruction *in;
3500 foreach_input(in, ir) {
3501 assert(in->opc == OPC_META_INPUT);
3502 unsigned inidx = in->input.inidx;
3503
3504 if (pre_assign_inputs && !so->inputs[inidx].sysval) {
3505 if (VALIDREG(so->nonbinning->inputs[inidx].regid)) {
3506 compile_assert(ctx, in->regs[0]->num ==
3507 so->nonbinning->inputs[inidx].regid);
3508 compile_assert(ctx, !!(in->regs[0]->flags & IR3_REG_HALF) ==
3509 so->nonbinning->inputs[inidx].half);
3510 }
3511 so->inputs[inidx].regid = so->nonbinning->inputs[inidx].regid;
3512 so->inputs[inidx].half = so->nonbinning->inputs[inidx].half;
3513 } else {
3514 so->inputs[inidx].regid = in->regs[0]->num;
3515 so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
3516 }
3517 }
3518
3519 if (ctx->astc_srgb)
3520 fixup_astc_srgb(ctx);
3521
3522 /* We need to do legalize after (for frag shader's) the "bary.f"
3523 * offsets (inloc) have been assigned.
3524 */
3525 ir3_legalize(ir, &so->has_ssbo, &so->need_pixlod, &max_bary);
3526
3527 ir3_debug_print(ir, "AFTER LEGALIZE");
3528
3529 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3530 * know what we might have to wait on when coming in from VS chsh.
3531 */
3532 if (so->type == MESA_SHADER_TESS_CTRL ||
3533 so->type == MESA_SHADER_GEOMETRY ) {
3534 foreach_block (block, &ir->block_list) {
3535 foreach_instr (instr, &block->instr_list) {
3536 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3537 break;
3538 }
3539 }
3540 }
3541
3542 so->branchstack = ctx->max_stack;
3543
3544 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3545 if (so->type == MESA_SHADER_FRAGMENT)
3546 so->total_in = max_bary + 1;
3547
3548 so->max_sun = ir->max_sun;
3549
3550 /* Collect sampling instructions eligible for pre-dispatch. */
3551 collect_tex_prefetches(ctx, ir);
3552
3553 out:
3554 if (ret) {
3555 if (so->ir)
3556 ir3_destroy(so->ir);
3557 so->ir = NULL;
3558 }
3559 ir3_context_free(ctx);
3560
3561 return ret;
3562 }