2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
38 #include "instr-a3xx.h"
40 #include "ir3_context.h"
43 ir3_handle_bindless_cat6(struct ir3_instruction
*instr
, nir_src rsrc
)
45 nir_intrinsic_instr
*intrin
= ir3_bindless_resource(rsrc
);
49 instr
->flags
|= IR3_INSTR_B
;
50 instr
->cat6
.base
= nir_intrinsic_desc_set(intrin
);
53 static struct ir3_instruction
*
54 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
55 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
57 struct ir3_block
*block
= ctx
->block
;
58 struct ir3_instruction
*mov
;
59 struct ir3_register
*src
;
61 mov
= ir3_instr_create(block
, OPC_MOV
);
62 mov
->cat1
.src_type
= TYPE_U32
;
63 mov
->cat1
.dst_type
= TYPE_U32
;
65 src
= __ssa_src(mov
, collect
, IR3_REG_RELATIV
);
67 src
->array
.offset
= n
;
69 ir3_instr_set_address(mov
, address
);
74 static struct ir3_instruction
*
75 create_input(struct ir3_context
*ctx
, unsigned compmask
)
77 struct ir3_instruction
*in
;
79 in
= ir3_instr_create(ctx
->in_block
, OPC_META_INPUT
);
80 in
->input
.sysval
= ~0;
81 __ssa_dst(in
)->wrmask
= compmask
;
83 array_insert(ctx
->ir
, ctx
->ir
->inputs
, in
);
88 static struct ir3_instruction
*
89 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
, unsigned n
)
91 struct ir3_block
*block
= ctx
->block
;
92 struct ir3_instruction
*instr
;
93 /* packed inloc is fixed up later: */
94 struct ir3_instruction
*inloc
= create_immed(block
, n
);
97 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
98 instr
->cat6
.type
= TYPE_U32
;
99 instr
->cat6
.iim_val
= 1;
101 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->ij
[IJ_PERSP_PIXEL
], 0);
102 instr
->regs
[2]->wrmask
= 0x3;
108 static struct ir3_instruction
*
109 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
111 /* first four vec4 sysval's reserved for UBOs: */
112 /* NOTE: dp is in scalar, but there can be >4 dp components: */
113 struct ir3_const_state
*const_state
= ir3_const_state(ctx
->so
);
114 unsigned n
= const_state
->offsets
.driver_param
;
115 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
116 return create_uniform(ctx
->block
, r
);
120 * Adreno's comparisons produce a 1 for true and 0 for false, in either 16 or
121 * 32-bit registers. We use NIR's 1-bit integers to represent bools, and
122 * trust that we will only see and/or/xor on those 1-bit values, so we can
123 * safely store NIR i1s in a 32-bit reg while always containing either a 1 or
128 * alu/sfu instructions:
131 static struct ir3_instruction
*
132 create_cov(struct ir3_context
*ctx
, struct ir3_instruction
*src
,
133 unsigned src_bitsize
, nir_op op
)
135 type_t src_type
, dst_type
;
139 case nir_op_f2f16_rtne
:
140 case nir_op_f2f16_rtz
:
148 switch (src_bitsize
) {
156 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
165 switch (src_bitsize
) {
176 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
185 switch (src_bitsize
) {
196 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
209 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
220 case nir_op_f2f16_rtne
:
221 case nir_op_f2f16_rtz
:
263 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
266 if (src_type
== dst_type
)
269 struct ir3_instruction
*cov
=
270 ir3_COV(ctx
->block
, src
, src_type
, dst_type
);
272 if (op
== nir_op_f2f16_rtne
)
273 cov
->regs
[0]->flags
|= IR3_REG_EVEN
;
279 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
281 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
282 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
283 unsigned bs
[info
->num_inputs
]; /* bit size */
284 struct ir3_block
*b
= ctx
->block
;
285 unsigned dst_sz
, wrmask
;
286 type_t dst_type
= nir_dest_bit_size(alu
->dest
.dest
) == 16 ?
289 if (alu
->dest
.dest
.is_ssa
) {
290 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
291 wrmask
= (1 << dst_sz
) - 1;
293 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
294 wrmask
= alu
->dest
.write_mask
;
297 dst
= ir3_get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
299 /* Vectors are special in that they have non-scalarized writemasks,
300 * and just take the first swizzle channel for each argument in
301 * order into each writemask channel.
303 if ((alu
->op
== nir_op_vec2
) ||
304 (alu
->op
== nir_op_vec3
) ||
305 (alu
->op
== nir_op_vec4
)) {
307 for (int i
= 0; i
< info
->num_inputs
; i
++) {
308 nir_alu_src
*asrc
= &alu
->src
[i
];
310 compile_assert(ctx
, !asrc
->abs
);
311 compile_assert(ctx
, !asrc
->negate
);
313 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
315 src
[i
] = create_immed_typed(ctx
->block
, 0, dst_type
);
316 dst
[i
] = ir3_MOV(b
, src
[i
], dst_type
);
319 ir3_put_dst(ctx
, &alu
->dest
.dest
);
323 /* We also get mov's with more than one component for mov's so
324 * handle those specially:
326 if (alu
->op
== nir_op_mov
) {
327 nir_alu_src
*asrc
= &alu
->src
[0];
328 struct ir3_instruction
*const *src0
= ir3_get_src(ctx
, &asrc
->src
);
330 for (unsigned i
= 0; i
< dst_sz
; i
++) {
331 if (wrmask
& (1 << i
)) {
332 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], dst_type
);
338 ir3_put_dst(ctx
, &alu
->dest
.dest
);
342 /* General case: We can just grab the one used channel per src. */
343 for (int i
= 0; i
< info
->num_inputs
; i
++) {
344 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
345 nir_alu_src
*asrc
= &alu
->src
[i
];
347 compile_assert(ctx
, !asrc
->abs
);
348 compile_assert(ctx
, !asrc
->negate
);
350 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
351 bs
[i
] = nir_src_bit_size(asrc
->src
);
353 compile_assert(ctx
, src
[i
]);
358 case nir_op_f2f16_rtne
:
359 case nir_op_f2f16_rtz
:
382 dst
[0] = create_cov(ctx
, src
[0], bs
[0], alu
->op
);
385 case nir_op_fquantize2f16
:
386 dst
[0] = create_cov(ctx
,
387 create_cov(ctx
, src
[0], 32, nir_op_f2f16
),
391 dst
[0] = ir3_CMPS_F(b
,
393 create_immed_typed(b
, 0, bs
[0] == 16 ? TYPE_F16
: TYPE_F32
), 0);
394 dst
[0]->cat2
.condition
= IR3_COND_NE
;
398 /* i2b1 will appear when translating from nir_load_ubo or
399 * nir_intrinsic_load_ssbo, where any non-zero value is true.
401 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
402 dst
[0]->cat2
.condition
= IR3_COND_NE
;
406 /* b2b1 will appear when translating from
408 * - nir_intrinsic_load_shared of a 32-bit 0/~0 value.
409 * - nir_intrinsic_load_constant of a 32-bit 0/~0 value
411 * A negate can turn those into a 1 or 0 for us.
413 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
417 /* b2b32 will appear when converting our 1-bit bools to a store_shared
420 * A negate can turn those into a ~0 for us.
422 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
426 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
429 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
432 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
435 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
438 /* if there is just a single use of the src, and it supports
439 * (sat) bit, we can just fold the (sat) flag back to the
440 * src instruction and create a mov. This is easier for cp
443 * NOTE: a3xx definitely seen not working with flat bary.f. Same test
444 * uses ldlv on a4xx+, so not definitive. Seems rare enough to apply
447 * TODO probably opc_cat==4 is ok too
449 if (alu
->src
[0].src
.is_ssa
&&
450 src
[0]->opc
!= OPC_BARY_F
&&
451 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
452 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
453 src
[0]->flags
|= IR3_INSTR_SAT
;
454 dst
[0] = ir3_MOV(b
, src
[0], dst_type
);
456 /* otherwise generate a max.f that saturates.. blob does
457 * similar (generating a cat2 mov using max.f)
459 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
460 dst
[0]->flags
|= IR3_INSTR_SAT
;
464 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
467 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
470 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
473 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
476 case nir_op_fddx_coarse
:
477 dst
[0] = ir3_DSX(b
, src
[0], 0);
478 dst
[0]->cat5
.type
= TYPE_F32
;
480 case nir_op_fddx_fine
:
481 dst
[0] = ir3_DSXPP_MACRO(b
, src
[0], 0);
482 dst
[0]->cat5
.type
= TYPE_F32
;
485 case nir_op_fddy_coarse
:
486 dst
[0] = ir3_DSY(b
, src
[0], 0);
487 dst
[0]->cat5
.type
= TYPE_F32
;
490 case nir_op_fddy_fine
:
491 dst
[0] = ir3_DSYPP_MACRO(b
, src
[0], 0);
492 dst
[0]->cat5
.type
= TYPE_F32
;
495 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
496 dst
[0]->cat2
.condition
= IR3_COND_LT
;
499 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
500 dst
[0]->cat2
.condition
= IR3_COND_GE
;
503 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
504 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
507 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
508 dst
[0]->cat2
.condition
= IR3_COND_NE
;
511 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
514 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
517 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
519 case nir_op_fround_even
:
520 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
523 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
527 dst
[0] = ir3_SIN(b
, src
[0], 0);
530 dst
[0] = ir3_COS(b
, src
[0], 0);
533 dst
[0] = ir3_RSQ(b
, src
[0], 0);
536 dst
[0] = ir3_RCP(b
, src
[0], 0);
539 dst
[0] = ir3_LOG2(b
, src
[0], 0);
542 dst
[0] = ir3_EXP2(b
, src
[0], 0);
545 dst
[0] = ir3_SQRT(b
, src
[0], 0);
549 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
552 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
555 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
558 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
561 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
564 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
567 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
569 case nir_op_umul_low
:
570 dst
[0] = ir3_MULL_U(b
, src
[0], 0, src
[1], 0);
572 case nir_op_imadsh_mix16
:
573 dst
[0] = ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0, src
[2], 0);
575 case nir_op_imad24_ir3
:
576 dst
[0] = ir3_MAD_S24(b
, src
[0], 0, src
[1], 0, src
[2], 0);
579 dst
[0] = ir3_MUL_S24(b
, src
[0], 0, src
[1], 0);
582 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
586 dst
[0] = ir3_SUB_U(b
, create_immed(ctx
->block
, 1), 0, src
[0], 0);
588 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
592 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
595 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
598 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
601 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
604 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
607 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
610 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
611 dst
[0]->cat2
.condition
= IR3_COND_LT
;
614 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
615 dst
[0]->cat2
.condition
= IR3_COND_GE
;
618 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
619 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
622 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
623 dst
[0]->cat2
.condition
= IR3_COND_NE
;
626 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
627 dst
[0]->cat2
.condition
= IR3_COND_LT
;
630 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
631 dst
[0]->cat2
.condition
= IR3_COND_GE
;
635 struct ir3_instruction
*cond
= src
[0];
637 /* If src[0] is a negation (likely as a result of an ir3_b2n(cond)),
638 * we can ignore that and use original cond, since the nonzero-ness of
639 * cond stays the same.
641 if (cond
->opc
== OPC_ABSNEG_S
&&
643 (cond
->regs
[1]->flags
& (IR3_REG_SNEG
| IR3_REG_SABS
)) == IR3_REG_SNEG
) {
644 cond
= cond
->regs
[1]->instr
;
647 compile_assert(ctx
, bs
[1] == bs
[2]);
648 /* The condition's size has to match the other two arguments' size, so
649 * convert down if necessary.
652 struct hash_entry
*prev_entry
=
653 _mesa_hash_table_search(ctx
->sel_cond_conversions
, src
[0]);
655 cond
= prev_entry
->data
;
657 cond
= ir3_COV(b
, cond
, TYPE_U32
, TYPE_U16
);
658 _mesa_hash_table_insert(ctx
->sel_cond_conversions
, src
[0], cond
);
663 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, cond
, 0, src
[2], 0);
665 dst
[0] = ir3_SEL_B16(b
, src
[1], 0, cond
, 0, src
[2], 0);
668 case nir_op_bit_count
: {
669 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
670 // double check on earlier gen's. Once half-precision support is
671 // in place, this should probably move to a NIR lowering pass:
672 struct ir3_instruction
*hi
, *lo
;
674 hi
= ir3_COV(b
, ir3_SHR_B(b
, src
[0], 0, create_immed(b
, 16), 0),
676 lo
= ir3_COV(b
, src
[0], TYPE_U32
, TYPE_U16
);
678 hi
= ir3_CBITS_B(b
, hi
, 0);
679 lo
= ir3_CBITS_B(b
, lo
, 0);
681 // TODO maybe the builders should default to making dst half-precision
682 // if the src's were half precision, to make this less awkward.. otoh
683 // we should probably just do this lowering in NIR.
684 hi
->regs
[0]->flags
|= IR3_REG_HALF
;
685 lo
->regs
[0]->flags
|= IR3_REG_HALF
;
687 dst
[0] = ir3_ADD_S(b
, hi
, 0, lo
, 0);
688 dst
[0]->regs
[0]->flags
|= IR3_REG_HALF
;
689 dst
[0] = ir3_COV(b
, dst
[0], TYPE_U16
, TYPE_U32
);
692 case nir_op_ifind_msb
: {
693 struct ir3_instruction
*cmp
;
694 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
695 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
696 cmp
->cat2
.condition
= IR3_COND_GE
;
697 dst
[0] = ir3_SEL_B32(b
,
698 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
702 case nir_op_ufind_msb
:
703 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
704 dst
[0] = ir3_SEL_B32(b
,
705 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
706 src
[0], 0, dst
[0], 0);
708 case nir_op_find_lsb
:
709 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
710 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
712 case nir_op_bitfield_reverse
:
713 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
717 ir3_context_error(ctx
, "Unhandled ALU op: %s\n",
718 nir_op_infos
[alu
->op
].name
);
722 if (nir_alu_type_get_base_type(info
->output_type
) == nir_type_bool
) {
723 assert(nir_dest_bit_size(alu
->dest
.dest
) == 1 ||
724 alu
->op
== nir_op_b2b32
);
727 /* 1-bit values stored in 32-bit registers are only valid for certain
738 compile_assert(ctx
, nir_dest_bit_size(alu
->dest
.dest
) != 1);
742 ir3_put_dst(ctx
, &alu
->dest
.dest
);
746 emit_intrinsic_load_ubo_ldc(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
747 struct ir3_instruction
**dst
)
749 struct ir3_block
*b
= ctx
->block
;
751 unsigned ncomp
= intr
->num_components
;
752 struct ir3_instruction
*offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
753 struct ir3_instruction
*idx
= ir3_get_src(ctx
, &intr
->src
[0])[0];
754 struct ir3_instruction
*ldc
= ir3_LDC(b
, idx
, 0, offset
, 0);
755 ldc
->regs
[0]->wrmask
= MASK(ncomp
);
756 ldc
->cat6
.iim_val
= ncomp
;
757 ldc
->cat6
.d
= nir_intrinsic_base(intr
);
758 ldc
->cat6
.type
= TYPE_U32
;
760 ir3_handle_bindless_cat6(ldc
, intr
->src
[0]);
761 if (ldc
->flags
& IR3_INSTR_B
)
762 ctx
->so
->bindless_ubo
= true;
764 ir3_split_dest(b
, dst
, ldc
, 0, ncomp
);
768 /* handles direct/indirect UBO reads: */
770 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
771 struct ir3_instruction
**dst
)
773 struct ir3_block
*b
= ctx
->block
;
774 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
775 const struct ir3_const_state
*const_state
= ir3_const_state(ctx
->so
);
776 unsigned ubo
= regid(const_state
->offsets
.ubo
, 0);
777 const unsigned ptrsz
= ir3_pointer_size(ctx
->compiler
);
781 /* First src is ubo index, which could either be an immed or not: */
782 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0];
783 if (is_same_type_mov(src0
) &&
784 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
785 base_lo
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
786 base_hi
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
788 base_lo
= create_uniform_indirect(b
, ubo
, TYPE_U32
, ir3_get_addr0(ctx
, src0
, ptrsz
));
789 base_hi
= create_uniform_indirect(b
, ubo
+ 1, TYPE_U32
, ir3_get_addr0(ctx
, src0
, ptrsz
));
791 /* NOTE: since relative addressing is used, make sure constlen is
792 * at least big enough to cover all the UBO addresses, since the
793 * assembler won't know what the max address reg is.
795 ctx
->so
->constlen
= MAX2(ctx
->so
->constlen
,
796 const_state
->offsets
.ubo
+ (ctx
->s
->info
.num_ubos
* ptrsz
));
799 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
802 if (nir_src_is_const(intr
->src
[1])) {
803 off
+= nir_src_as_uint(intr
->src
[1]);
805 /* For load_ubo_indirect, second src is indirect offset: */
806 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0];
808 /* and add offset to addr: */
809 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
812 /* if offset is to large to encode in the ldg, split it out: */
813 if ((off
+ (intr
->num_components
* 4)) > 1024) {
814 /* split out the minimal amount to improve the odds that
815 * cp can fit the immediate in the add.s instruction:
817 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
818 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
823 struct ir3_instruction
*carry
;
825 /* handle 32b rollover, ie:
826 * if (addr < base_lo)
829 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
830 carry
->cat2
.condition
= IR3_COND_LT
;
831 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
833 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
836 for (int i
= 0; i
< intr
->num_components
; i
++) {
837 struct ir3_instruction
*load
=
838 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0, /* num components */
839 create_immed(b
, off
+ i
* 4), 0);
840 load
->cat6
.type
= TYPE_U32
;
845 /* src[] = { block_index } */
847 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
848 struct ir3_instruction
**dst
)
850 if (ir3_bindless_resource(intr
->src
[0])) {
851 struct ir3_block
*b
= ctx
->block
;
852 struct ir3_instruction
*ibo
= ir3_ssbo_to_ibo(ctx
, intr
->src
[0]);
853 struct ir3_instruction
*resinfo
= ir3_RESINFO(b
, ibo
, 0);
854 resinfo
->cat6
.iim_val
= 1;
856 resinfo
->cat6
.type
= TYPE_U32
;
857 resinfo
->cat6
.typed
= false;
858 /* resinfo has no writemask and always writes out 3 components */
859 resinfo
->regs
[0]->wrmask
= MASK(3);
860 ir3_handle_bindless_cat6(resinfo
, intr
->src
[0]);
861 struct ir3_instruction
*resinfo_dst
;
862 ir3_split_dest(b
, &resinfo_dst
, resinfo
, 0, 1);
863 /* Unfortunately resinfo returns the array length, i.e. in dwords,
864 * while NIR expects us to return the size in bytes.
866 * TODO: fix this in NIR.
868 *dst
= ir3_SHL_B(b
, resinfo_dst
, 0, create_immed(b
, 2), 0);
872 /* SSBO size stored as a const starting at ssbo_sizes: */
873 const struct ir3_const_state
*const_state
= ir3_const_state(ctx
->so
);
874 unsigned blk_idx
= nir_src_as_uint(intr
->src
[0]);
875 unsigned idx
= regid(const_state
->offsets
.ssbo_sizes
, 0) +
876 const_state
->ssbo_size
.off
[blk_idx
];
878 debug_assert(const_state
->ssbo_size
.mask
& (1 << blk_idx
));
880 dst
[0] = create_uniform(ctx
->block
, idx
);
883 /* src[] = { offset }. const_index[] = { base } */
885 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
886 struct ir3_instruction
**dst
)
888 struct ir3_block
*b
= ctx
->block
;
889 struct ir3_instruction
*ldl
, *offset
;
892 offset
= ir3_get_src(ctx
, &intr
->src
[0])[0];
893 base
= nir_intrinsic_base(intr
);
895 ldl
= ir3_LDL(b
, offset
, 0,
896 create_immed(b
, intr
->num_components
), 0,
897 create_immed(b
, base
), 0);
899 ldl
->cat6
.type
= utype_dst(intr
->dest
);
900 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
902 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
903 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
905 ir3_split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
908 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
910 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
912 struct ir3_block
*b
= ctx
->block
;
913 struct ir3_instruction
*stl
, *offset
;
914 struct ir3_instruction
* const *value
;
915 unsigned base
, wrmask
, ncomp
;
917 value
= ir3_get_src(ctx
, &intr
->src
[0]);
918 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
920 base
= nir_intrinsic_base(intr
);
921 wrmask
= nir_intrinsic_write_mask(intr
);
922 ncomp
= ffs(~wrmask
) - 1;
924 assert(wrmask
== BITFIELD_MASK(intr
->num_components
));
926 stl
= ir3_STL(b
, offset
, 0,
927 ir3_create_collect(ctx
, value
, ncomp
), 0,
928 create_immed(b
, ncomp
), 0);
929 stl
->cat6
.dst_offset
= base
;
930 stl
->cat6
.type
= utype_src(intr
->src
[0]);
931 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
932 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
934 array_insert(b
, b
->keeps
, stl
);
937 /* src[] = { offset }. const_index[] = { base } */
939 emit_intrinsic_load_shared_ir3(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
940 struct ir3_instruction
**dst
)
942 struct ir3_block
*b
= ctx
->block
;
943 struct ir3_instruction
*load
, *offset
;
946 offset
= ir3_get_src(ctx
, &intr
->src
[0])[0];
947 base
= nir_intrinsic_base(intr
);
949 load
= ir3_LDLW(b
, offset
, 0,
950 create_immed(b
, intr
->num_components
), 0,
951 create_immed(b
, base
), 0);
953 /* for a650, use LDL for tess ctrl inputs: */
954 if (ctx
->so
->type
== MESA_SHADER_TESS_CTRL
&& ctx
->compiler
->tess_use_shared
)
957 load
->cat6
.type
= utype_dst(intr
->dest
);
958 load
->regs
[0]->wrmask
= MASK(intr
->num_components
);
960 load
->barrier_class
= IR3_BARRIER_SHARED_R
;
961 load
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
963 ir3_split_dest(b
, dst
, load
, 0, intr
->num_components
);
966 /* src[] = { value, offset }. const_index[] = { base } */
968 emit_intrinsic_store_shared_ir3(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
970 struct ir3_block
*b
= ctx
->block
;
971 struct ir3_instruction
*store
, *offset
;
972 struct ir3_instruction
* const *value
;
974 value
= ir3_get_src(ctx
, &intr
->src
[0]);
975 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
977 store
= ir3_STLW(b
, offset
, 0,
978 ir3_create_collect(ctx
, value
, intr
->num_components
), 0,
979 create_immed(b
, intr
->num_components
), 0);
981 /* for a650, use STL for vertex outputs used by tess ctrl shader: */
982 if (ctx
->so
->type
== MESA_SHADER_VERTEX
&& ctx
->so
->key
.tessellation
&&
983 ctx
->compiler
->tess_use_shared
)
984 store
->opc
= OPC_STL
;
986 store
->cat6
.dst_offset
= nir_intrinsic_base(intr
);
987 store
->cat6
.type
= utype_src(intr
->src
[0]);
988 store
->barrier_class
= IR3_BARRIER_SHARED_W
;
989 store
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
991 array_insert(b
, b
->keeps
, store
);
995 * CS shared variable atomic intrinsics
997 * All of the shared variable atomic memory operations read a value from
998 * memory, compute a new value using one of the operations below, write the
999 * new value to memory, and return the original value read.
1001 * All operations take 2 sources except CompSwap that takes 3. These
1002 * sources represent:
1004 * 0: The offset into the shared variable storage region that the atomic
1005 * operation will operate on.
1006 * 1: The data parameter to the atomic function (i.e. the value to add
1007 * in shared_atomic_add, etc).
1008 * 2: For CompSwap only: the second data parameter.
1010 static struct ir3_instruction
*
1011 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1013 struct ir3_block
*b
= ctx
->block
;
1014 struct ir3_instruction
*atomic
, *src0
, *src1
;
1015 type_t type
= TYPE_U32
;
1017 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0]; /* offset */
1018 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0]; /* value */
1020 switch (intr
->intrinsic
) {
1021 case nir_intrinsic_shared_atomic_add
:
1022 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
1024 case nir_intrinsic_shared_atomic_imin
:
1025 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1028 case nir_intrinsic_shared_atomic_umin
:
1029 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1031 case nir_intrinsic_shared_atomic_imax
:
1032 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1035 case nir_intrinsic_shared_atomic_umax
:
1036 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1038 case nir_intrinsic_shared_atomic_and
:
1039 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
1041 case nir_intrinsic_shared_atomic_or
:
1042 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
1044 case nir_intrinsic_shared_atomic_xor
:
1045 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1047 case nir_intrinsic_shared_atomic_exchange
:
1048 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1050 case nir_intrinsic_shared_atomic_comp_swap
:
1051 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1052 src1
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1053 ir3_get_src(ctx
, &intr
->src
[2])[0],
1056 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1062 atomic
->cat6
.iim_val
= 1;
1064 atomic
->cat6
.type
= type
;
1065 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1066 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1068 /* even if nothing consume the result, we can't DCE the instruction: */
1069 array_insert(b
, b
->keeps
, atomic
);
1074 struct tex_src_info
{
1076 unsigned tex_base
, samp_base
, tex_idx
, samp_idx
;
1077 /* For normal tex instructions */
1078 unsigned base
, combined_idx
, a1_val
, flags
;
1079 struct ir3_instruction
*samp_tex
;
1082 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1083 * to handle with the image_mapping table..
1085 static struct tex_src_info
1086 get_image_samp_tex_src(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1088 struct ir3_block
*b
= ctx
->block
;
1089 struct tex_src_info info
= { 0 };
1090 nir_intrinsic_instr
*bindless_tex
= ir3_bindless_resource(intr
->src
[0]);
1091 ctx
->so
->bindless_tex
= true;
1095 info
.flags
|= IR3_INSTR_B
;
1097 /* Gather information required to determine which encoding to
1098 * choose as well as for prefetch.
1100 info
.tex_base
= nir_intrinsic_desc_set(bindless_tex
);
1101 bool tex_const
= nir_src_is_const(bindless_tex
->src
[0]);
1103 info
.tex_idx
= nir_src_as_uint(bindless_tex
->src
[0]);
1106 /* Choose encoding. */
1107 if (tex_const
&& info
.tex_idx
< 256) {
1108 if (info
.tex_idx
< 16) {
1109 /* Everything fits within the instruction */
1110 info
.base
= info
.tex_base
;
1111 info
.combined_idx
= info
.samp_idx
| (info
.tex_idx
<< 4);
1113 info
.base
= info
.tex_base
;
1114 info
.a1_val
= info
.tex_idx
<< 3;
1115 info
.combined_idx
= 0;
1116 info
.flags
|= IR3_INSTR_A1EN
;
1118 info
.samp_tex
= NULL
;
1120 info
.flags
|= IR3_INSTR_S2EN
;
1121 info
.base
= info
.tex_base
;
1123 /* Note: the indirect source is now a vec2 instead of hvec2 */
1124 struct ir3_instruction
*texture
, *sampler
;
1126 texture
= ir3_get_src(ctx
, &intr
->src
[0])[0];
1127 sampler
= create_immed(b
, 0);
1128 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1134 info
.flags
|= IR3_INSTR_S2EN
;
1135 unsigned slot
= nir_src_as_uint(intr
->src
[0]);
1136 unsigned tex_idx
= ir3_image_to_tex(&ctx
->so
->image_mapping
, slot
);
1137 struct ir3_instruction
*texture
, *sampler
;
1139 texture
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
1140 sampler
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
1142 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1151 static struct ir3_instruction
*
1152 emit_sam(struct ir3_context
*ctx
, opc_t opc
, struct tex_src_info info
,
1153 type_t type
, unsigned wrmask
, struct ir3_instruction
*src0
,
1154 struct ir3_instruction
*src1
)
1156 struct ir3_instruction
*sam
, *addr
;
1157 if (info
.flags
& IR3_INSTR_A1EN
) {
1158 addr
= ir3_get_addr1(ctx
, info
.a1_val
);
1160 sam
= ir3_SAM(ctx
->block
, opc
, type
, 0b1111, info
.flags
,
1161 info
.samp_tex
, src0
, src1
);
1162 if (info
.flags
& IR3_INSTR_A1EN
) {
1163 ir3_instr_set_address(sam
, addr
);
1165 if (info
.flags
& IR3_INSTR_B
) {
1166 sam
->cat5
.tex_base
= info
.base
;
1167 sam
->cat5
.samp
= info
.combined_idx
;
1172 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1174 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1175 struct ir3_instruction
**dst
)
1177 struct ir3_block
*b
= ctx
->block
;
1178 struct tex_src_info info
= get_image_samp_tex_src(ctx
, intr
);
1179 struct ir3_instruction
*sam
;
1180 struct ir3_instruction
* const *src0
= ir3_get_src(ctx
, &intr
->src
[1]);
1181 struct ir3_instruction
*coords
[4];
1182 unsigned flags
, ncoords
= ir3_get_image_coords(intr
, &flags
);
1183 type_t type
= ir3_get_type_for_image_intrinsic(intr
);
1185 /* hmm, this seems a bit odd, but it is what blob does and (at least
1186 * a5xx) just faults on bogus addresses otherwise:
1188 if (flags
& IR3_INSTR_3D
) {
1189 flags
&= ~IR3_INSTR_3D
;
1190 flags
|= IR3_INSTR_A
;
1192 info
.flags
|= flags
;
1194 for (unsigned i
= 0; i
< ncoords
; i
++)
1195 coords
[i
] = src0
[i
];
1198 coords
[ncoords
++] = create_immed(b
, 0);
1200 sam
= emit_sam(ctx
, OPC_ISAM
, info
, type
, 0b1111,
1201 ir3_create_collect(ctx
, coords
, ncoords
), NULL
);
1203 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
1204 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
1206 ir3_split_dest(b
, dst
, sam
, 0, 4);
1209 /* A4xx version of image_size, see ir3_a6xx.c for newer resinfo version. */
1211 emit_intrinsic_image_size_tex(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1212 struct ir3_instruction
**dst
)
1214 struct ir3_block
*b
= ctx
->block
;
1215 struct tex_src_info info
= get_image_samp_tex_src(ctx
, intr
);
1216 struct ir3_instruction
*sam
, *lod
;
1217 unsigned flags
, ncoords
= ir3_get_image_coords(intr
, &flags
);
1218 type_t dst_type
= nir_dest_bit_size(intr
->dest
) == 16 ?
1219 TYPE_U16
: TYPE_U32
;
1221 info
.flags
|= flags
;
1222 assert(nir_src_as_uint(intr
->src
[1]) == 0);
1223 lod
= create_immed(b
, 0);
1224 sam
= emit_sam(ctx
, OPC_GETSIZE
, info
, dst_type
, 0b1111, lod
, NULL
);
1226 /* Array size actually ends up in .w rather than .z. This doesn't
1227 * matter for miplevel 0, but for higher mips the value in z is
1228 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1229 * returned, which means that we have to add 1 to it for arrays for
1232 * Note use a temporary dst and then copy, since the size of the dst
1233 * array that is passed in is based on nir's understanding of the
1234 * result size, not the hardware's
1236 struct ir3_instruction
*tmp
[4];
1238 ir3_split_dest(b
, tmp
, sam
, 0, 4);
1240 /* get_size instruction returns size in bytes instead of texels
1241 * for imageBuffer, so we need to divide it by the pixel size
1242 * of the image format.
1244 * TODO: This is at least true on a5xx. Check other gens.
1246 if (nir_intrinsic_image_dim(intr
) == GLSL_SAMPLER_DIM_BUF
) {
1247 /* Since all the possible values the divisor can take are
1248 * power-of-two (4, 8, or 16), the division is implemented
1250 * During shader setup, the log2 of the image format's
1251 * bytes-per-pixel should have been emitted in 2nd slot of
1252 * image_dims. See ir3_shader::emit_image_dims().
1254 const struct ir3_const_state
*const_state
=
1255 ir3_const_state(ctx
->so
);
1256 unsigned cb
= regid(const_state
->offsets
.image_dims
, 0) +
1257 const_state
->image_dims
.off
[nir_src_as_uint(intr
->src
[0])];
1258 struct ir3_instruction
*aux
= create_uniform(b
, cb
+ 1);
1260 tmp
[0] = ir3_SHR_B(b
, tmp
[0], 0, aux
, 0);
1263 for (unsigned i
= 0; i
< ncoords
; i
++)
1266 if (flags
& IR3_INSTR_A
) {
1267 if (ctx
->compiler
->levels_add_one
) {
1268 dst
[ncoords
-1] = ir3_ADD_U(b
, tmp
[3], 0, create_immed(b
, 1), 0);
1270 dst
[ncoords
-1] = ir3_MOV(b
, tmp
[3], TYPE_U32
);
1276 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1278 struct ir3_block
*b
= ctx
->block
;
1279 struct ir3_instruction
*barrier
;
1281 switch (intr
->intrinsic
) {
1282 case nir_intrinsic_control_barrier
:
1283 barrier
= ir3_BAR(b
);
1284 barrier
->cat7
.g
= true;
1285 barrier
->cat7
.l
= true;
1286 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
1287 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1289 case nir_intrinsic_memory_barrier
:
1290 barrier
= ir3_FENCE(b
);
1291 barrier
->cat7
.g
= true;
1292 barrier
->cat7
.r
= true;
1293 barrier
->cat7
.w
= true;
1294 barrier
->cat7
.l
= true;
1295 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
1296 IR3_BARRIER_BUFFER_W
;
1297 barrier
->barrier_conflict
=
1298 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1299 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1301 case nir_intrinsic_memory_barrier_buffer
:
1302 barrier
= ir3_FENCE(b
);
1303 barrier
->cat7
.g
= true;
1304 barrier
->cat7
.r
= true;
1305 barrier
->cat7
.w
= true;
1306 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1307 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
1308 IR3_BARRIER_BUFFER_W
;
1310 case nir_intrinsic_memory_barrier_image
:
1311 // TODO double check if this should have .g set
1312 barrier
= ir3_FENCE(b
);
1313 barrier
->cat7
.g
= true;
1314 barrier
->cat7
.r
= true;
1315 barrier
->cat7
.w
= true;
1316 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1317 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
1318 IR3_BARRIER_IMAGE_W
;
1320 case nir_intrinsic_memory_barrier_shared
:
1321 barrier
= ir3_FENCE(b
);
1322 barrier
->cat7
.g
= true;
1323 barrier
->cat7
.l
= true;
1324 barrier
->cat7
.r
= true;
1325 barrier
->cat7
.w
= true;
1326 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
1327 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
1328 IR3_BARRIER_SHARED_W
;
1330 case nir_intrinsic_group_memory_barrier
:
1331 barrier
= ir3_FENCE(b
);
1332 barrier
->cat7
.g
= true;
1333 barrier
->cat7
.l
= true;
1334 barrier
->cat7
.r
= true;
1335 barrier
->cat7
.w
= true;
1336 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
1337 IR3_BARRIER_IMAGE_W
|
1338 IR3_BARRIER_BUFFER_W
;
1339 barrier
->barrier_conflict
=
1340 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
1341 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1342 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1348 /* make sure barrier doesn't get DCE'd */
1349 array_insert(b
, b
->keeps
, barrier
);
1352 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
1353 gl_system_value slot
, unsigned compmask
,
1354 struct ir3_instruction
*instr
)
1356 struct ir3_shader_variant
*so
= ctx
->so
;
1357 unsigned n
= so
->inputs_count
++;
1359 assert(instr
->opc
== OPC_META_INPUT
);
1360 instr
->input
.inidx
= n
;
1361 instr
->input
.sysval
= slot
;
1363 so
->inputs
[n
].sysval
= true;
1364 so
->inputs
[n
].slot
= slot
;
1365 so
->inputs
[n
].compmask
= compmask
;
1366 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1370 static struct ir3_instruction
*
1371 create_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
1375 struct ir3_instruction
*sysval
= create_input(ctx
, compmask
);
1376 add_sysval_input_compmask(ctx
, slot
, compmask
, sysval
);
1380 static struct ir3_instruction
*
1381 get_barycentric(struct ir3_context
*ctx
, enum ir3_bary bary
)
1383 static const gl_system_value sysval_base
= SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
;
1385 STATIC_ASSERT(sysval_base
+ IJ_PERSP_PIXEL
== SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
);
1386 STATIC_ASSERT(sysval_base
+ IJ_PERSP_SAMPLE
== SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE
);
1387 STATIC_ASSERT(sysval_base
+ IJ_PERSP_CENTROID
== SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
);
1388 STATIC_ASSERT(sysval_base
+ IJ_PERSP_SIZE
== SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE
);
1389 STATIC_ASSERT(sysval_base
+ IJ_LINEAR_PIXEL
== SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL
);
1390 STATIC_ASSERT(sysval_base
+ IJ_LINEAR_CENTROID
== SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID
);
1391 STATIC_ASSERT(sysval_base
+ IJ_LINEAR_SAMPLE
== SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE
);
1393 if (!ctx
->ij
[bary
]) {
1394 struct ir3_instruction
*xy
[2];
1395 struct ir3_instruction
*ij
;
1397 ij
= create_sysval_input(ctx
, sysval_base
+ bary
, 0x3);
1398 ir3_split_dest(ctx
->block
, xy
, ij
, 0, 2);
1400 ctx
->ij
[bary
] = ir3_create_collect(ctx
, xy
, 2);
1403 return ctx
->ij
[bary
];
1406 /* TODO: make this a common NIR helper?
1407 * there is a nir_system_value_from_intrinsic but it takes nir_intrinsic_op so it
1408 * can't be extended to work with this
1410 static gl_system_value
1411 nir_intrinsic_barycentric_sysval(nir_intrinsic_instr
*intr
)
1413 enum glsl_interp_mode interp_mode
= nir_intrinsic_interp_mode(intr
);
1414 gl_system_value sysval
;
1416 switch (intr
->intrinsic
) {
1417 case nir_intrinsic_load_barycentric_pixel
:
1418 if (interp_mode
== INTERP_MODE_NOPERSPECTIVE
)
1419 sysval
= SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL
;
1421 sysval
= SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
;
1423 case nir_intrinsic_load_barycentric_centroid
:
1424 if (interp_mode
== INTERP_MODE_NOPERSPECTIVE
)
1425 sysval
= SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID
;
1427 sysval
= SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
;
1429 case nir_intrinsic_load_barycentric_sample
:
1430 if (interp_mode
== INTERP_MODE_NOPERSPECTIVE
)
1431 sysval
= SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE
;
1433 sysval
= SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE
;
1436 unreachable("invalid barycentric intrinsic");
1443 emit_intrinsic_barycentric(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1444 struct ir3_instruction
**dst
)
1446 gl_system_value sysval
= nir_intrinsic_barycentric_sysval(intr
);
1448 if (!ctx
->so
->key
.msaa
) {
1449 if (sysval
== SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE
)
1450 sysval
= SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
;
1451 if (sysval
== SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE
)
1452 sysval
= SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL
;
1455 enum ir3_bary bary
= sysval
- SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
;
1457 struct ir3_instruction
*ij
= get_barycentric(ctx
, bary
);
1458 ir3_split_dest(ctx
->block
, dst
, ij
, 0, 2);
1461 static struct ir3_instruction
*
1462 get_frag_coord(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1464 if (!ctx
->frag_coord
) {
1465 struct ir3_block
*b
= ctx
->in_block
;
1466 struct ir3_instruction
*xyzw
[4];
1467 struct ir3_instruction
*hw_frag_coord
;
1469 hw_frag_coord
= create_sysval_input(ctx
, SYSTEM_VALUE_FRAG_COORD
, 0xf);
1470 ir3_split_dest(b
, xyzw
, hw_frag_coord
, 0, 4);
1472 /* for frag_coord.xy, we get unsigned values.. we need
1473 * to subtract (integer) 8 and divide by 16 (right-
1474 * shift by 4) then convert to float:
1478 * mov.u32f32 dst, tmp
1481 for (int i
= 0; i
< 2; i
++) {
1482 xyzw
[i
] = ir3_COV(b
, xyzw
[i
], TYPE_U32
, TYPE_F32
);
1483 xyzw
[i
] = ir3_MUL_F(b
, xyzw
[i
], 0, create_immed(b
, fui(1.0 / 16.0)), 0);
1486 ctx
->frag_coord
= ir3_create_collect(ctx
, xyzw
, 4);
1489 ctx
->so
->fragcoord_compmask
|=
1490 nir_ssa_def_components_read(&intr
->dest
.ssa
);
1492 return ctx
->frag_coord
;
1496 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1498 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1499 struct ir3_instruction
**dst
;
1500 struct ir3_instruction
* const *src
;
1501 struct ir3_block
*b
= ctx
->block
;
1502 unsigned dest_components
= nir_intrinsic_dest_components(intr
);
1505 if (info
->has_dest
) {
1506 dst
= ir3_get_dst(ctx
, &intr
->dest
, dest_components
);
1511 const struct ir3_const_state
*const_state
= ir3_const_state(ctx
->so
);
1512 const unsigned primitive_param
= const_state
->offsets
.primitive_param
* 4;
1513 const unsigned primitive_map
= const_state
->offsets
.primitive_map
* 4;
1515 switch (intr
->intrinsic
) {
1516 case nir_intrinsic_load_uniform
:
1517 idx
= nir_intrinsic_base(intr
);
1518 if (nir_src_is_const(intr
->src
[0])) {
1519 idx
+= nir_src_as_uint(intr
->src
[0]);
1520 for (int i
= 0; i
< dest_components
; i
++) {
1521 dst
[i
] = create_uniform_typed(b
, idx
+ i
,
1522 nir_dest_bit_size(intr
->dest
) == 16 ? TYPE_F16
: TYPE_F32
);
1525 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1526 for (int i
= 0; i
< dest_components
; i
++) {
1527 dst
[i
] = create_uniform_indirect(b
, idx
+ i
,
1528 nir_dest_bit_size(intr
->dest
) == 16 ? TYPE_F16
: TYPE_F32
,
1529 ir3_get_addr0(ctx
, src
[0], 1));
1531 /* NOTE: if relative addressing is used, we set
1532 * constlen in the compiler (to worst-case value)
1533 * since we don't know in the assembler what the max
1534 * addr reg value can be:
1536 ctx
->so
->constlen
= MAX2(ctx
->so
->constlen
,
1537 const_state
->ubo_state
.size
/ 16);
1541 case nir_intrinsic_load_vs_primitive_stride_ir3
:
1542 dst
[0] = create_uniform(b
, primitive_param
+ 0);
1544 case nir_intrinsic_load_vs_vertex_stride_ir3
:
1545 dst
[0] = create_uniform(b
, primitive_param
+ 1);
1547 case nir_intrinsic_load_hs_patch_stride_ir3
:
1548 dst
[0] = create_uniform(b
, primitive_param
+ 2);
1550 case nir_intrinsic_load_patch_vertices_in
:
1551 dst
[0] = create_uniform(b
, primitive_param
+ 3);
1553 case nir_intrinsic_load_tess_param_base_ir3
:
1554 dst
[0] = create_uniform(b
, primitive_param
+ 4);
1555 dst
[1] = create_uniform(b
, primitive_param
+ 5);
1557 case nir_intrinsic_load_tess_factor_base_ir3
:
1558 dst
[0] = create_uniform(b
, primitive_param
+ 6);
1559 dst
[1] = create_uniform(b
, primitive_param
+ 7);
1562 case nir_intrinsic_load_primitive_location_ir3
:
1563 idx
= nir_intrinsic_driver_location(intr
);
1564 dst
[0] = create_uniform(b
, primitive_map
+ idx
);
1567 case nir_intrinsic_load_gs_header_ir3
:
1568 dst
[0] = ctx
->gs_header
;
1570 case nir_intrinsic_load_tcs_header_ir3
:
1571 dst
[0] = ctx
->tcs_header
;
1574 case nir_intrinsic_load_primitive_id
:
1575 dst
[0] = ctx
->primitive_id
;
1578 case nir_intrinsic_load_tess_coord
:
1579 if (!ctx
->tess_coord
) {
1581 create_sysval_input(ctx
, SYSTEM_VALUE_TESS_COORD
, 0x3);
1583 ir3_split_dest(b
, dst
, ctx
->tess_coord
, 0, 2);
1585 /* Unused, but ir3_put_dst() below wants to free something */
1586 dst
[2] = create_immed(b
, 0);
1589 case nir_intrinsic_end_patch_ir3
:
1590 assert(ctx
->so
->type
== MESA_SHADER_TESS_CTRL
);
1591 struct ir3_instruction
*end
= ir3_PREDE(b
);
1592 array_insert(b
, b
->keeps
, end
);
1594 end
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1595 end
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
1598 case nir_intrinsic_store_global_ir3
: {
1599 struct ir3_instruction
*value
, *addr
, *offset
;
1600 unsigned ncomp
= nir_intrinsic_src_components(intr
, 0);
1602 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1603 ir3_get_src(ctx
, &intr
->src
[1])[0],
1604 ir3_get_src(ctx
, &intr
->src
[1])[1]
1607 offset
= ir3_get_src(ctx
, &intr
->src
[2])[0];
1609 value
= ir3_create_collect(ctx
, ir3_get_src(ctx
, &intr
->src
[0]), ncomp
);
1611 struct ir3_instruction
*stg
=
1612 ir3_STG_G(ctx
->block
, addr
, 0, value
, 0,
1613 create_immed(ctx
->block
, ncomp
), 0, offset
, 0);
1614 stg
->cat6
.type
= TYPE_U32
;
1615 stg
->cat6
.iim_val
= 1;
1617 array_insert(b
, b
->keeps
, stg
);
1619 stg
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1620 stg
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1624 case nir_intrinsic_load_global_ir3
: {
1625 struct ir3_instruction
*addr
, *offset
;
1627 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1628 ir3_get_src(ctx
, &intr
->src
[0])[0],
1629 ir3_get_src(ctx
, &intr
->src
[0])[1]
1632 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
1634 struct ir3_instruction
*load
=
1635 ir3_LDG(b
, addr
, 0, create_immed(ctx
->block
, dest_components
),
1637 load
->cat6
.type
= TYPE_U32
;
1638 load
->regs
[0]->wrmask
= MASK(dest_components
);
1640 load
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1641 load
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1643 ir3_split_dest(b
, dst
, load
, 0, dest_components
);
1647 case nir_intrinsic_load_ubo
:
1648 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1650 case nir_intrinsic_load_ubo_ir3
:
1651 emit_intrinsic_load_ubo_ldc(ctx
, intr
, dst
);
1653 case nir_intrinsic_load_frag_coord
:
1654 ir3_split_dest(b
, dst
, get_frag_coord(ctx
, intr
), 0, 4);
1656 case nir_intrinsic_load_sample_pos_from_id
: {
1657 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1658 * but that doesn't seem necessary.
1660 struct ir3_instruction
*offset
=
1661 ir3_RGETPOS(b
, ir3_get_src(ctx
, &intr
->src
[0])[0], 0);
1662 offset
->regs
[0]->wrmask
= 0x3;
1663 offset
->cat5
.type
= TYPE_F32
;
1665 ir3_split_dest(b
, dst
, offset
, 0, 2);
1669 case nir_intrinsic_load_size_ir3
:
1670 if (!ctx
->ij
[IJ_PERSP_SIZE
]) {
1671 ctx
->ij
[IJ_PERSP_SIZE
] =
1672 create_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE
, 0x1);
1674 dst
[0] = ctx
->ij
[IJ_PERSP_SIZE
];
1676 case nir_intrinsic_load_barycentric_centroid
:
1677 case nir_intrinsic_load_barycentric_sample
:
1678 case nir_intrinsic_load_barycentric_pixel
:
1679 emit_intrinsic_barycentric(ctx
, intr
, dst
);
1681 case nir_intrinsic_load_interpolated_input
:
1682 idx
= nir_intrinsic_base(intr
);
1683 comp
= nir_intrinsic_component(intr
);
1684 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1685 if (nir_src_is_const(intr
->src
[1])) {
1686 struct ir3_instruction
*coord
= ir3_create_collect(ctx
, src
, 2);
1687 idx
+= nir_src_as_uint(intr
->src
[1]);
1688 for (int i
= 0; i
< dest_components
; i
++) {
1689 unsigned inloc
= idx
* 4 + i
+ comp
;
1690 if (ctx
->so
->inputs
[idx
].bary
&&
1691 !ctx
->so
->inputs
[idx
].use_ldlv
) {
1692 dst
[i
] = ir3_BARY_F(b
, create_immed(b
, inloc
), 0, coord
, 0);
1694 /* for non-varyings use the pre-setup input, since
1695 * that is easier than mapping things back to a
1696 * nir_variable to figure out what it is.
1698 dst
[i
] = ctx
->inputs
[inloc
];
1699 compile_assert(ctx
, dst
[i
]);
1703 ir3_context_error(ctx
, "unhandled");
1706 case nir_intrinsic_load_input
:
1707 idx
= nir_intrinsic_base(intr
);
1708 comp
= nir_intrinsic_component(intr
);
1709 if (nir_src_is_const(intr
->src
[0])) {
1710 idx
+= nir_src_as_uint(intr
->src
[0]);
1711 for (int i
= 0; i
< dest_components
; i
++) {
1712 unsigned n
= idx
* 4 + i
+ comp
;
1713 dst
[i
] = ctx
->inputs
[n
];
1714 compile_assert(ctx
, ctx
->inputs
[n
]);
1717 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1718 struct ir3_instruction
*collect
=
1719 ir3_create_collect(ctx
, ctx
->ir
->inputs
, ctx
->ninputs
);
1720 struct ir3_instruction
*addr
= ir3_get_addr0(ctx
, src
[0], 4);
1721 for (int i
= 0; i
< dest_components
; i
++) {
1722 unsigned n
= idx
* 4 + i
+ comp
;
1723 dst
[i
] = create_indirect_load(ctx
, ctx
->ninputs
,
1728 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1729 * pass and replaced by an ir3-specifc version that adds the
1730 * dword-offset in the last source.
1732 case nir_intrinsic_load_ssbo_ir3
:
1733 ctx
->funcs
->emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
1735 case nir_intrinsic_store_ssbo_ir3
:
1736 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1737 !ctx
->s
->info
.fs
.early_fragment_tests
)
1738 ctx
->so
->no_earlyz
= true;
1739 ctx
->funcs
->emit_intrinsic_store_ssbo(ctx
, intr
);
1741 case nir_intrinsic_get_buffer_size
:
1742 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
1744 case nir_intrinsic_ssbo_atomic_add_ir3
:
1745 case nir_intrinsic_ssbo_atomic_imin_ir3
:
1746 case nir_intrinsic_ssbo_atomic_umin_ir3
:
1747 case nir_intrinsic_ssbo_atomic_imax_ir3
:
1748 case nir_intrinsic_ssbo_atomic_umax_ir3
:
1749 case nir_intrinsic_ssbo_atomic_and_ir3
:
1750 case nir_intrinsic_ssbo_atomic_or_ir3
:
1751 case nir_intrinsic_ssbo_atomic_xor_ir3
:
1752 case nir_intrinsic_ssbo_atomic_exchange_ir3
:
1753 case nir_intrinsic_ssbo_atomic_comp_swap_ir3
:
1754 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1755 !ctx
->s
->info
.fs
.early_fragment_tests
)
1756 ctx
->so
->no_earlyz
= true;
1757 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_ssbo(ctx
, intr
);
1759 case nir_intrinsic_load_shared
:
1760 emit_intrinsic_load_shared(ctx
, intr
, dst
);
1762 case nir_intrinsic_store_shared
:
1763 emit_intrinsic_store_shared(ctx
, intr
);
1765 case nir_intrinsic_shared_atomic_add
:
1766 case nir_intrinsic_shared_atomic_imin
:
1767 case nir_intrinsic_shared_atomic_umin
:
1768 case nir_intrinsic_shared_atomic_imax
:
1769 case nir_intrinsic_shared_atomic_umax
:
1770 case nir_intrinsic_shared_atomic_and
:
1771 case nir_intrinsic_shared_atomic_or
:
1772 case nir_intrinsic_shared_atomic_xor
:
1773 case nir_intrinsic_shared_atomic_exchange
:
1774 case nir_intrinsic_shared_atomic_comp_swap
:
1775 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
1777 case nir_intrinsic_image_load
:
1778 emit_intrinsic_load_image(ctx
, intr
, dst
);
1780 case nir_intrinsic_bindless_image_load
:
1781 /* Bindless uses the IBO state, which doesn't have swizzle filled out,
1782 * so using isam doesn't work.
1784 * TODO: can we use isam if we fill out more fields?
1786 ctx
->funcs
->emit_intrinsic_load_image(ctx
, intr
, dst
);
1788 case nir_intrinsic_image_store
:
1789 case nir_intrinsic_bindless_image_store
:
1790 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1791 !ctx
->s
->info
.fs
.early_fragment_tests
)
1792 ctx
->so
->no_earlyz
= true;
1793 ctx
->funcs
->emit_intrinsic_store_image(ctx
, intr
);
1795 case nir_intrinsic_image_size
:
1796 case nir_intrinsic_bindless_image_size
:
1797 ctx
->funcs
->emit_intrinsic_image_size(ctx
, intr
, dst
);
1799 case nir_intrinsic_image_atomic_add
:
1800 case nir_intrinsic_bindless_image_atomic_add
:
1801 case nir_intrinsic_image_atomic_imin
:
1802 case nir_intrinsic_bindless_image_atomic_imin
:
1803 case nir_intrinsic_image_atomic_umin
:
1804 case nir_intrinsic_bindless_image_atomic_umin
:
1805 case nir_intrinsic_image_atomic_imax
:
1806 case nir_intrinsic_bindless_image_atomic_imax
:
1807 case nir_intrinsic_image_atomic_umax
:
1808 case nir_intrinsic_bindless_image_atomic_umax
:
1809 case nir_intrinsic_image_atomic_and
:
1810 case nir_intrinsic_bindless_image_atomic_and
:
1811 case nir_intrinsic_image_atomic_or
:
1812 case nir_intrinsic_bindless_image_atomic_or
:
1813 case nir_intrinsic_image_atomic_xor
:
1814 case nir_intrinsic_bindless_image_atomic_xor
:
1815 case nir_intrinsic_image_atomic_exchange
:
1816 case nir_intrinsic_bindless_image_atomic_exchange
:
1817 case nir_intrinsic_image_atomic_comp_swap
:
1818 case nir_intrinsic_bindless_image_atomic_comp_swap
:
1819 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1820 !ctx
->s
->info
.fs
.early_fragment_tests
)
1821 ctx
->so
->no_earlyz
= true;
1822 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_image(ctx
, intr
);
1824 case nir_intrinsic_control_barrier
:
1825 case nir_intrinsic_memory_barrier
:
1826 case nir_intrinsic_group_memory_barrier
:
1827 case nir_intrinsic_memory_barrier_buffer
:
1828 case nir_intrinsic_memory_barrier_image
:
1829 case nir_intrinsic_memory_barrier_shared
:
1830 emit_intrinsic_barrier(ctx
, intr
);
1831 /* note that blk ptr no longer valid, make that obvious: */
1834 case nir_intrinsic_store_output
:
1835 idx
= nir_intrinsic_base(intr
);
1836 comp
= nir_intrinsic_component(intr
);
1837 compile_assert(ctx
, nir_src_is_const(intr
->src
[1]));
1838 idx
+= nir_src_as_uint(intr
->src
[1]);
1840 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1841 for (int i
= 0; i
< nir_intrinsic_src_components(intr
, 0); i
++) {
1842 unsigned n
= idx
* 4 + i
+ comp
;
1843 ctx
->outputs
[n
] = src
[i
];
1846 case nir_intrinsic_load_base_vertex
:
1847 case nir_intrinsic_load_first_vertex
:
1848 if (!ctx
->basevertex
) {
1849 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1851 dst
[0] = ctx
->basevertex
;
1853 case nir_intrinsic_load_draw_id
:
1854 if (!ctx
->draw_id
) {
1855 ctx
->draw_id
= create_driver_param(ctx
, IR3_DP_DRAWID
);
1857 dst
[0] = ctx
->draw_id
;
1859 case nir_intrinsic_load_base_instance
:
1860 if (!ctx
->base_instance
) {
1861 ctx
->base_instance
= create_driver_param(ctx
, IR3_DP_INSTID_BASE
);
1863 dst
[0] = ctx
->base_instance
;
1865 case nir_intrinsic_load_view_index
:
1866 if (!ctx
->view_index
) {
1867 ctx
->view_index
= create_sysval_input(ctx
, SYSTEM_VALUE_VIEW_INDEX
, 0x1);
1869 dst
[0] = ctx
->view_index
;
1871 case nir_intrinsic_load_vertex_id_zero_base
:
1872 case nir_intrinsic_load_vertex_id
:
1873 if (!ctx
->vertex_id
) {
1874 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
1875 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
1876 ctx
->vertex_id
= create_sysval_input(ctx
, sv
, 0x1);
1878 dst
[0] = ctx
->vertex_id
;
1880 case nir_intrinsic_load_instance_id
:
1881 if (!ctx
->instance_id
) {
1882 ctx
->instance_id
= create_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
, 0x1);
1884 dst
[0] = ctx
->instance_id
;
1886 case nir_intrinsic_load_sample_id
:
1887 ctx
->so
->per_samp
= true;
1889 case nir_intrinsic_load_sample_id_no_per_sample
:
1890 if (!ctx
->samp_id
) {
1891 ctx
->samp_id
= create_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_ID
, 0x1);
1892 ctx
->samp_id
->regs
[0]->flags
|= IR3_REG_HALF
;
1894 dst
[0] = ir3_COV(b
, ctx
->samp_id
, TYPE_U16
, TYPE_U32
);
1896 case nir_intrinsic_load_sample_mask_in
:
1897 if (!ctx
->samp_mask_in
) {
1898 ctx
->samp_mask_in
= create_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_MASK_IN
, 0x1);
1900 dst
[0] = ctx
->samp_mask_in
;
1902 case nir_intrinsic_load_user_clip_plane
:
1903 idx
= nir_intrinsic_ucp_id(intr
);
1904 for (int i
= 0; i
< dest_components
; i
++) {
1905 unsigned n
= idx
* 4 + i
;
1906 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1909 case nir_intrinsic_load_front_face
:
1910 if (!ctx
->frag_face
) {
1911 ctx
->so
->frag_face
= true;
1912 ctx
->frag_face
= create_sysval_input(ctx
, SYSTEM_VALUE_FRONT_FACE
, 0x1);
1913 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
1915 /* for fragface, we get -1 for back and 0 for front. However this is
1916 * the inverse of what nir expects (where ~0 is true).
1918 dst
[0] = ir3_CMPS_S(b
,
1920 create_immed_typed(b
, 0, TYPE_U16
), 0);
1921 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1923 case nir_intrinsic_load_local_invocation_id
:
1924 if (!ctx
->local_invocation_id
) {
1925 ctx
->local_invocation_id
=
1926 create_sysval_input(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
, 0x7);
1928 ir3_split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
1930 case nir_intrinsic_load_work_group_id
:
1931 if (!ctx
->work_group_id
) {
1932 ctx
->work_group_id
=
1933 create_sysval_input(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
, 0x7);
1934 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
1936 ir3_split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
1938 case nir_intrinsic_load_num_work_groups
:
1939 for (int i
= 0; i
< dest_components
; i
++) {
1940 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
1943 case nir_intrinsic_load_local_group_size
:
1944 for (int i
= 0; i
< dest_components
; i
++) {
1945 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
1948 case nir_intrinsic_discard_if
:
1949 case nir_intrinsic_discard
: {
1950 struct ir3_instruction
*cond
, *kill
;
1952 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1953 /* conditional discard: */
1954 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1957 /* unconditional discard: */
1958 cond
= create_immed(b
, 1);
1961 /* NOTE: only cmps.*.* can write p0.x: */
1962 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1963 cond
->cat2
.condition
= IR3_COND_NE
;
1965 /* condition always goes in predicate register: */
1966 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1967 cond
->regs
[0]->flags
&= ~IR3_REG_SSA
;
1969 kill
= ir3_KILL(b
, cond
, 0);
1970 kill
->regs
[1]->num
= regid(REG_P0
, 0);
1971 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1973 array_insert(b
, b
->keeps
, kill
);
1974 ctx
->so
->has_kill
= true;
1979 case nir_intrinsic_cond_end_ir3
: {
1980 struct ir3_instruction
*cond
, *kill
;
1982 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1985 /* NOTE: only cmps.*.* can write p0.x: */
1986 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1987 cond
->cat2
.condition
= IR3_COND_NE
;
1989 /* condition always goes in predicate register: */
1990 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1992 kill
= ir3_PREDT(b
, cond
, 0);
1994 kill
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1995 kill
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
1997 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1998 array_insert(b
, b
->keeps
, kill
);
2002 case nir_intrinsic_load_shared_ir3
:
2003 emit_intrinsic_load_shared_ir3(ctx
, intr
, dst
);
2005 case nir_intrinsic_store_shared_ir3
:
2006 emit_intrinsic_store_shared_ir3(ctx
, intr
);
2008 case nir_intrinsic_bindless_resource_ir3
:
2009 dst
[0] = ir3_get_src(ctx
, &intr
->src
[0])[0];
2012 ir3_context_error(ctx
, "Unhandled intrinsic type: %s\n",
2013 nir_intrinsic_infos
[intr
->intrinsic
].name
);
2018 ir3_put_dst(ctx
, &intr
->dest
);
2022 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
2024 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &instr
->def
,
2025 instr
->def
.num_components
);
2027 if (instr
->def
.bit_size
== 16) {
2028 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
2029 dst
[i
] = create_immed_typed(ctx
->block
,
2030 instr
->value
[i
].u16
,
2033 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
2034 dst
[i
] = create_immed_typed(ctx
->block
,
2035 instr
->value
[i
].u32
,
2042 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
2044 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &undef
->def
,
2045 undef
->def
.num_components
);
2046 type_t type
= (undef
->def
.bit_size
== 16) ? TYPE_U16
: TYPE_U32
;
2048 /* backend doesn't want undefined instructions, so just plug
2051 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
2052 dst
[i
] = create_immed_typed(ctx
->block
, fui(0.0), type
);
2056 * texture fetch/sample instructions:
2060 get_tex_dest_type(nir_tex_instr
*tex
)
2064 switch (nir_alu_type_get_base_type(tex
->dest_type
)) {
2065 case nir_type_invalid
:
2066 case nir_type_float
:
2067 type
= nir_dest_bit_size(tex
->dest
) == 16 ? TYPE_F16
: TYPE_F32
;
2070 type
= nir_dest_bit_size(tex
->dest
) == 16 ? TYPE_S16
: TYPE_S32
;
2074 type
= nir_dest_bit_size(tex
->dest
) == 16 ? TYPE_U16
: TYPE_U32
;
2077 unreachable("bad dest_type");
2084 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
2086 unsigned coords
= glsl_get_sampler_dim_coordinate_components(tex
->sampler_dim
);
2089 /* note: would use tex->coord_components.. except txs.. also,
2090 * since array index goes after shadow ref, we don't want to
2094 flags
|= IR3_INSTR_3D
;
2096 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2097 flags
|= IR3_INSTR_S
;
2099 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
2100 flags
|= IR3_INSTR_A
;
2106 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
2107 * or immediate (in which case it will get lowered later to a non .s2en
2108 * version of the tex instruction which encode tex/samp as immediates:
2110 static struct tex_src_info
2111 get_tex_samp_tex_src(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2113 struct ir3_block
*b
= ctx
->block
;
2114 struct tex_src_info info
= { 0 };
2115 int texture_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_texture_handle
);
2116 int sampler_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_sampler_handle
);
2117 struct ir3_instruction
*texture
, *sampler
;
2119 if (texture_idx
>= 0 || sampler_idx
>= 0) {
2121 info
.flags
|= IR3_INSTR_B
;
2123 /* Gather information required to determine which encoding to
2124 * choose as well as for prefetch.
2126 nir_intrinsic_instr
*bindless_tex
= NULL
;
2128 if (texture_idx
>= 0) {
2129 ctx
->so
->bindless_tex
= true;
2130 bindless_tex
= ir3_bindless_resource(tex
->src
[texture_idx
].src
);
2131 assert(bindless_tex
);
2132 info
.tex_base
= nir_intrinsic_desc_set(bindless_tex
);
2133 tex_const
= nir_src_is_const(bindless_tex
->src
[0]);
2135 info
.tex_idx
= nir_src_as_uint(bindless_tex
->src
[0]);
2137 /* To simplify some of the logic below, assume the index is
2138 * constant 0 when it's not enabled.
2143 nir_intrinsic_instr
*bindless_samp
= NULL
;
2145 if (sampler_idx
>= 0) {
2146 ctx
->so
->bindless_samp
= true;
2147 bindless_samp
= ir3_bindless_resource(tex
->src
[sampler_idx
].src
);
2148 assert(bindless_samp
);
2149 info
.samp_base
= nir_intrinsic_desc_set(bindless_samp
);
2150 samp_const
= nir_src_is_const(bindless_samp
->src
[0]);
2152 info
.samp_idx
= nir_src_as_uint(bindless_samp
->src
[0]);
2158 /* Choose encoding. */
2159 if (tex_const
&& samp_const
&& info
.tex_idx
< 256 && info
.samp_idx
< 256) {
2160 if (info
.tex_idx
< 16 && info
.samp_idx
< 16 &&
2161 (!bindless_tex
|| !bindless_samp
|| info
.tex_base
== info
.samp_base
)) {
2162 /* Everything fits within the instruction */
2163 info
.base
= info
.tex_base
;
2164 info
.combined_idx
= info
.samp_idx
| (info
.tex_idx
<< 4);
2166 info
.base
= info
.tex_base
;
2167 info
.a1_val
= info
.tex_idx
<< 3 | info
.samp_base
;
2168 info
.combined_idx
= info
.samp_idx
;
2169 info
.flags
|= IR3_INSTR_A1EN
;
2171 info
.samp_tex
= NULL
;
2173 info
.flags
|= IR3_INSTR_S2EN
;
2174 /* In the indirect case, we only use a1.x to store the sampler
2175 * base if it differs from the texture base.
2177 if (!bindless_tex
|| !bindless_samp
|| info
.tex_base
== info
.samp_base
) {
2178 info
.base
= info
.tex_base
;
2180 info
.base
= info
.tex_base
;
2181 info
.a1_val
= info
.samp_base
;
2182 info
.flags
|= IR3_INSTR_A1EN
;
2185 /* Note: the indirect source is now a vec2 instead of hvec2, and
2186 * for some reason the texture and sampler are swapped.
2188 struct ir3_instruction
*texture
, *sampler
;
2191 texture
= ir3_get_src(ctx
, &tex
->src
[texture_idx
].src
)[0];
2193 texture
= create_immed(b
, 0);
2196 if (bindless_samp
) {
2197 sampler
= ir3_get_src(ctx
, &tex
->src
[sampler_idx
].src
)[0];
2199 sampler
= create_immed(b
, 0);
2201 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2207 info
.flags
|= IR3_INSTR_S2EN
;
2208 texture_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_texture_offset
);
2209 sampler_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_sampler_offset
);
2210 if (texture_idx
>= 0) {
2211 texture
= ir3_get_src(ctx
, &tex
->src
[texture_idx
].src
)[0];
2212 texture
= ir3_COV(ctx
->block
, texture
, TYPE_U32
, TYPE_U16
);
2214 /* TODO what to do for dynamic case? I guess we only need the
2215 * max index for astc srgb workaround so maybe not a problem
2216 * to worry about if we don't enable indirect samplers for
2219 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex
->texture_index
);
2220 texture
= create_immed_typed(ctx
->block
, tex
->texture_index
, TYPE_U16
);
2221 info
.tex_idx
= tex
->texture_index
;
2224 if (sampler_idx
>= 0) {
2225 sampler
= ir3_get_src(ctx
, &tex
->src
[sampler_idx
].src
)[0];
2226 sampler
= ir3_COV(ctx
->block
, sampler
, TYPE_U32
, TYPE_U16
);
2228 sampler
= create_immed_typed(ctx
->block
, tex
->sampler_index
, TYPE_U16
);
2229 info
.samp_idx
= tex
->texture_index
;
2232 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2242 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2244 struct ir3_block
*b
= ctx
->block
;
2245 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
2246 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
2247 struct ir3_instruction
*lod
, *compare
, *proj
, *sample_index
;
2248 struct tex_src_info info
= { 0 };
2249 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
2250 unsigned i
, coords
, flags
, ncomp
;
2251 unsigned nsrc0
= 0, nsrc1
= 0;
2255 ncomp
= nir_dest_num_components(tex
->dest
);
2257 coord
= off
= ddx
= ddy
= NULL
;
2258 lod
= proj
= compare
= sample_index
= NULL
;
2260 dst
= ir3_get_dst(ctx
, &tex
->dest
, ncomp
);
2262 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
2263 switch (tex
->src
[i
].src_type
) {
2264 case nir_tex_src_coord
:
2265 coord
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2267 case nir_tex_src_bias
:
2268 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2271 case nir_tex_src_lod
:
2272 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2275 case nir_tex_src_comparator
: /* shadow comparator */
2276 compare
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2278 case nir_tex_src_projector
:
2279 proj
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2282 case nir_tex_src_offset
:
2283 off
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2286 case nir_tex_src_ddx
:
2287 ddx
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2289 case nir_tex_src_ddy
:
2290 ddy
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2292 case nir_tex_src_ms_index
:
2293 sample_index
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2295 case nir_tex_src_texture_offset
:
2296 case nir_tex_src_sampler_offset
:
2297 case nir_tex_src_texture_handle
:
2298 case nir_tex_src_sampler_handle
:
2299 /* handled in get_tex_samp_src() */
2302 ir3_context_error(ctx
, "Unhandled NIR tex src type: %d\n",
2303 tex
->src
[i
].src_type
);
2309 case nir_texop_tex_prefetch
:
2310 compile_assert(ctx
, !has_bias
);
2311 compile_assert(ctx
, !has_lod
);
2312 compile_assert(ctx
, !compare
);
2313 compile_assert(ctx
, !has_proj
);
2314 compile_assert(ctx
, !has_off
);
2315 compile_assert(ctx
, !ddx
);
2316 compile_assert(ctx
, !ddy
);
2317 compile_assert(ctx
, !sample_index
);
2318 compile_assert(ctx
, nir_tex_instr_src_index(tex
, nir_tex_src_texture_offset
) < 0);
2319 compile_assert(ctx
, nir_tex_instr_src_index(tex
, nir_tex_src_sampler_offset
) < 0);
2321 if (ctx
->so
->num_sampler_prefetch
< ctx
->prefetch_limit
) {
2322 opc
= OPC_META_TEX_PREFETCH
;
2323 ctx
->so
->num_sampler_prefetch
++;
2327 case nir_texop_tex
: opc
= has_lod
? OPC_SAML
: OPC_SAM
; break;
2328 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2329 case nir_texop_txl
: opc
= OPC_SAML
; break;
2330 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2331 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2332 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2334 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2335 * what blob does, seems gather is broken?), and a3xx did
2336 * not support it (but probably could also emulate).
2338 switch (tex
->component
) {
2339 case 0: opc
= OPC_GATHER4R
; break;
2340 case 1: opc
= OPC_GATHER4G
; break;
2341 case 2: opc
= OPC_GATHER4B
; break;
2342 case 3: opc
= OPC_GATHER4A
; break;
2345 case nir_texop_txf_ms_fb
:
2346 case nir_texop_txf_ms
: opc
= OPC_ISAMM
; break;
2348 ir3_context_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2352 tex_info(tex
, &flags
, &coords
);
2355 * lay out the first argument in the proper order:
2356 * - actual coordinates first
2357 * - shadow reference
2360 * - starting at offset 4, dpdx.xy, dpdy.xy
2362 * bias/lod go into the second arg
2365 /* insert tex coords: */
2366 for (i
= 0; i
< coords
; i
++)
2371 /* scale up integer coords for TXF based on the LOD */
2372 if (ctx
->compiler
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2374 for (i
= 0; i
< coords
; i
++)
2375 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2379 /* hw doesn't do 1d, so we treat it as 2d with
2380 * height of 1, and patch up the y coord.
2383 src0
[nsrc0
++] = create_immed(b
, 0);
2385 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2389 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2390 src0
[nsrc0
++] = compare
;
2392 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2393 struct ir3_instruction
*idx
= coord
[coords
];
2395 /* the array coord for cube arrays needs 0.5 added to it */
2396 if (ctx
->compiler
->array_index_add_half
&& !is_isam(opc
))
2397 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2399 src0
[nsrc0
++] = idx
;
2403 src0
[nsrc0
++] = proj
;
2404 flags
|= IR3_INSTR_P
;
2407 /* pad to 4, then ddx/ddy: */
2408 if (tex
->op
== nir_texop_txd
) {
2410 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2411 for (i
= 0; i
< coords
; i
++)
2412 src0
[nsrc0
++] = ddx
[i
];
2414 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2415 for (i
= 0; i
< coords
; i
++)
2416 src0
[nsrc0
++] = ddy
[i
];
2418 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2421 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2422 * with scaled x coord according to requested sample:
2424 if (opc
== OPC_ISAMM
) {
2425 if (ctx
->compiler
->txf_ms_with_isaml
) {
2426 /* the samples are laid out in x dimension as
2428 * x_ms = (x << ms) + sample_index;
2430 struct ir3_instruction
*ms
;
2431 ms
= create_immed(b
, (ctx
->samples
>> (2 * tex
->texture_index
)) & 3);
2433 src0
[0] = ir3_SHL_B(b
, src0
[0], 0, ms
, 0);
2434 src0
[0] = ir3_ADD_U(b
, src0
[0], 0, sample_index
, 0);
2438 src0
[nsrc0
++] = sample_index
;
2443 * second argument (if applicable):
2448 if (has_off
| has_lod
| has_bias
) {
2450 unsigned off_coords
= coords
;
2451 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2453 for (i
= 0; i
< off_coords
; i
++)
2454 src1
[nsrc1
++] = off
[i
];
2456 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2457 flags
|= IR3_INSTR_O
;
2460 if (has_lod
| has_bias
)
2461 src1
[nsrc1
++] = lod
;
2464 type
= get_tex_dest_type(tex
);
2466 if (opc
== OPC_GETLOD
)
2470 if (tex
->op
== nir_texop_txf_ms_fb
) {
2471 /* only expect a single txf_ms_fb per shader: */
2472 compile_assert(ctx
, !ctx
->so
->fb_read
);
2473 compile_assert(ctx
, ctx
->so
->type
== MESA_SHADER_FRAGMENT
);
2475 ctx
->so
->fb_read
= true;
2476 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2477 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
2478 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
2480 info
.flags
= IR3_INSTR_S2EN
;
2482 ctx
->so
->num_samp
++;
2484 info
= get_tex_samp_tex_src(ctx
, tex
);
2487 struct ir3_instruction
*col0
= ir3_create_collect(ctx
, src0
, nsrc0
);
2488 struct ir3_instruction
*col1
= ir3_create_collect(ctx
, src1
, nsrc1
);
2490 if (opc
== OPC_META_TEX_PREFETCH
) {
2491 int idx
= nir_tex_instr_src_index(tex
, nir_tex_src_coord
);
2493 compile_assert(ctx
, tex
->src
[idx
].src
.is_ssa
);
2495 sam
= ir3_META_TEX_PREFETCH(b
);
2496 __ssa_dst(sam
)->wrmask
= MASK(ncomp
); /* dst */
2497 __ssa_src(sam
, get_barycentric(ctx
, IJ_PERSP_PIXEL
), 0);
2498 sam
->prefetch
.input_offset
=
2499 ir3_nir_coord_offset(tex
->src
[idx
].src
.ssa
);
2500 /* make sure not to add irrelevant flags like S2EN */
2501 sam
->flags
= flags
| (info
.flags
& IR3_INSTR_B
);
2502 sam
->prefetch
.tex
= info
.tex_idx
;
2503 sam
->prefetch
.samp
= info
.samp_idx
;
2504 sam
->prefetch
.tex_base
= info
.tex_base
;
2505 sam
->prefetch
.samp_base
= info
.samp_base
;
2507 info
.flags
|= flags
;
2508 sam
= emit_sam(ctx
, opc
, info
, type
, MASK(ncomp
), col0
, col1
);
2511 if ((ctx
->astc_srgb
& (1 << tex
->texture_index
)) && !nir_tex_instr_is_query(tex
)) {
2512 assert(opc
!= OPC_META_TEX_PREFETCH
);
2514 /* only need first 3 components: */
2515 sam
->regs
[0]->wrmask
= 0x7;
2516 ir3_split_dest(b
, dst
, sam
, 0, 3);
2518 /* we need to sample the alpha separately with a non-ASTC
2521 sam
= ir3_SAM(b
, opc
, type
, 0b1000, flags
| info
.flags
,
2522 info
.samp_tex
, col0
, col1
);
2524 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2526 /* fixup .w component: */
2527 ir3_split_dest(b
, &dst
[3], sam
, 3, 1);
2529 /* normal (non-workaround) case: */
2530 ir3_split_dest(b
, dst
, sam
, 0, ncomp
);
2533 /* GETLOD returns results in 4.8 fixed point */
2534 if (opc
== OPC_GETLOD
) {
2535 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2537 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2538 for (i
= 0; i
< 2; i
++) {
2539 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_S32
, TYPE_F32
), 0,
2544 ir3_put_dst(ctx
, &tex
->dest
);
2548 emit_tex_info(struct ir3_context
*ctx
, nir_tex_instr
*tex
, unsigned idx
)
2550 struct ir3_block
*b
= ctx
->block
;
2551 struct ir3_instruction
**dst
, *sam
;
2552 type_t dst_type
= get_tex_dest_type(tex
);
2553 struct tex_src_info info
= get_tex_samp_tex_src(ctx
, tex
);
2555 dst
= ir3_get_dst(ctx
, &tex
->dest
, 1);
2557 sam
= emit_sam(ctx
, OPC_GETINFO
, info
, dst_type
, 1 << idx
, NULL
, NULL
);
2559 /* even though there is only one component, since it ends
2560 * up in .y/.z/.w rather than .x, we need a split_dest()
2562 ir3_split_dest(b
, dst
, sam
, idx
, 1);
2564 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2565 * the value in TEX_CONST_0 is zero-based.
2567 if (ctx
->compiler
->levels_add_one
)
2568 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2570 ir3_put_dst(ctx
, &tex
->dest
);
2574 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2576 struct ir3_block
*b
= ctx
->block
;
2577 struct ir3_instruction
**dst
, *sam
;
2578 struct ir3_instruction
*lod
;
2579 unsigned flags
, coords
;
2580 type_t dst_type
= get_tex_dest_type(tex
);
2581 struct tex_src_info info
= get_tex_samp_tex_src(ctx
, tex
);
2583 tex_info(tex
, &flags
, &coords
);
2584 info
.flags
|= flags
;
2586 /* Actually we want the number of dimensions, not coordinates. This
2587 * distinction only matters for cubes.
2589 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2592 dst
= ir3_get_dst(ctx
, &tex
->dest
, 4);
2594 int lod_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_lod
);
2595 compile_assert(ctx
, lod_idx
>= 0);
2597 lod
= ir3_get_src(ctx
, &tex
->src
[lod_idx
].src
)[0];
2599 sam
= emit_sam(ctx
, OPC_GETSIZE
, info
, dst_type
, 0b1111, lod
, NULL
);
2600 ir3_split_dest(b
, dst
, sam
, 0, 4);
2602 /* Array size actually ends up in .w rather than .z. This doesn't
2603 * matter for miplevel 0, but for higher mips the value in z is
2604 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2605 * returned, which means that we have to add 1 to it for arrays.
2607 if (tex
->is_array
) {
2608 if (ctx
->compiler
->levels_add_one
) {
2609 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2611 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2615 ir3_put_dst(ctx
, &tex
->dest
);
2619 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2621 switch (jump
->type
) {
2622 case nir_jump_break
:
2623 case nir_jump_continue
:
2624 case nir_jump_return
:
2625 /* I *think* we can simply just ignore this, and use the
2626 * successor block link to figure out where we need to
2627 * jump to for break/continue
2631 ir3_context_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2637 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2639 switch (instr
->type
) {
2640 case nir_instr_type_alu
:
2641 emit_alu(ctx
, nir_instr_as_alu(instr
));
2643 case nir_instr_type_deref
:
2644 /* ignored, handled as part of the intrinsic they are src to */
2646 case nir_instr_type_intrinsic
:
2647 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2649 case nir_instr_type_load_const
:
2650 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2652 case nir_instr_type_ssa_undef
:
2653 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2655 case nir_instr_type_tex
: {
2656 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2657 /* couple tex instructions get special-cased:
2661 emit_tex_txs(ctx
, tex
);
2663 case nir_texop_query_levels
:
2664 emit_tex_info(ctx
, tex
, 2);
2666 case nir_texop_texture_samples
:
2667 emit_tex_info(ctx
, tex
, 3);
2675 case nir_instr_type_jump
:
2676 emit_jump(ctx
, nir_instr_as_jump(instr
));
2678 case nir_instr_type_phi
:
2679 /* we have converted phi webs to regs in NIR by now */
2680 ir3_context_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
2682 case nir_instr_type_call
:
2683 case nir_instr_type_parallel_copy
:
2684 ir3_context_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2689 static struct ir3_block
*
2690 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
2692 struct ir3_block
*block
;
2693 struct hash_entry
*hentry
;
2695 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2697 return hentry
->data
;
2699 block
= ir3_block_create(ctx
->ir
);
2700 block
->nblock
= nblock
;
2701 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2703 set_foreach(nblock
->predecessors
, sentry
) {
2704 _mesa_set_add(block
->predecessors
, get_block(ctx
, sentry
->key
));
2711 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2713 struct ir3_block
*block
= get_block(ctx
, nblock
);
2715 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2716 if (nblock
->successors
[i
]) {
2717 block
->successors
[i
] =
2718 get_block(ctx
, nblock
->successors
[i
]);
2723 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2725 /* re-emit addr register in each block if needed: */
2726 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr0_ht
); i
++) {
2727 _mesa_hash_table_destroy(ctx
->addr0_ht
[i
], NULL
);
2728 ctx
->addr0_ht
[i
] = NULL
;
2731 _mesa_hash_table_u64_destroy(ctx
->addr1_ht
, NULL
);
2732 ctx
->addr1_ht
= NULL
;
2734 nir_foreach_instr (instr
, nblock
) {
2735 ctx
->cur_instr
= instr
;
2736 emit_instr(ctx
, instr
);
2737 ctx
->cur_instr
= NULL
;
2742 _mesa_hash_table_clear(ctx
->sel_cond_conversions
, NULL
);
2745 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
2748 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
2750 struct ir3_instruction
*condition
= ir3_get_src(ctx
, &nif
->condition
)[0];
2752 ctx
->block
->condition
= ir3_get_predicate(ctx
, condition
);
2754 emit_cf_list(ctx
, &nif
->then_list
);
2755 emit_cf_list(ctx
, &nif
->else_list
);
2759 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
2761 emit_cf_list(ctx
, &nloop
->body
);
2766 stack_push(struct ir3_context
*ctx
)
2769 ctx
->max_stack
= MAX2(ctx
->max_stack
, ctx
->stack
);
2773 stack_pop(struct ir3_context
*ctx
)
2775 compile_assert(ctx
, ctx
->stack
> 0);
2780 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
2782 foreach_list_typed (nir_cf_node
, node
, node
, list
) {
2783 switch (node
->type
) {
2784 case nir_cf_node_block
:
2785 emit_block(ctx
, nir_cf_node_as_block(node
));
2787 case nir_cf_node_if
:
2789 emit_if(ctx
, nir_cf_node_as_if(node
));
2792 case nir_cf_node_loop
:
2794 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2797 case nir_cf_node_function
:
2798 ir3_context_error(ctx
, "TODO\n");
2804 /* emit stream-out code. At this point, the current block is the original
2805 * (nir) end block, and nir ensures that all flow control paths terminate
2806 * into the end block. We re-purpose the original end block to generate
2807 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2808 * block holding stream-out write instructions, followed by the new end
2812 * p0.x = (vtxcnt < maxvtxcnt)
2813 * // succs: blockStreamOut, blockNewEnd
2816 * // preds: blockOrigEnd
2817 * ... stream-out instructions ...
2818 * // succs: blockNewEnd
2821 * // preds: blockOrigEnd, blockStreamOut
2825 emit_stream_out(struct ir3_context
*ctx
)
2827 struct ir3
*ir
= ctx
->ir
;
2828 struct ir3_stream_output_info
*strmout
=
2829 &ctx
->so
->shader
->stream_output
;
2830 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2831 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2832 struct ir3_instruction
*bases
[IR3_MAX_SO_BUFFERS
];
2834 /* create vtxcnt input in input block at top of shader,
2835 * so that it is seen as live over the entire duration
2838 vtxcnt
= create_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, 0x1);
2839 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2841 /* at this point, we are at the original 'end' block,
2842 * re-purpose this block to stream-out condition, then
2843 * append stream-out block and new-end block
2845 orig_end_block
= ctx
->block
;
2847 // maybe w/ store_global intrinsic, we could do this
2848 // stuff in nir->nir pass
2850 stream_out_block
= ir3_block_create(ir
);
2851 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2853 new_end_block
= ir3_block_create(ir
);
2854 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2856 orig_end_block
->successors
[0] = stream_out_block
;
2857 orig_end_block
->successors
[1] = new_end_block
;
2859 stream_out_block
->successors
[0] = new_end_block
;
2860 _mesa_set_add(stream_out_block
->predecessors
, orig_end_block
);
2862 _mesa_set_add(new_end_block
->predecessors
, orig_end_block
);
2863 _mesa_set_add(new_end_block
->predecessors
, stream_out_block
);
2865 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2866 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2867 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2868 cond
->regs
[0]->flags
&= ~IR3_REG_SSA
;
2869 cond
->cat2
.condition
= IR3_COND_LT
;
2871 /* condition goes on previous block to the conditional,
2872 * since it is used to pick which of the two successor
2875 orig_end_block
->condition
= cond
;
2877 /* switch to stream_out_block to generate the stream-out
2880 ctx
->block
= stream_out_block
;
2882 /* Calculate base addresses based on vtxcnt. Instructions
2883 * generated for bases not used in following loop will be
2884 * stripped out in the backend.
2886 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
2887 const struct ir3_const_state
*const_state
=
2888 ir3_const_state(ctx
->so
);
2889 unsigned stride
= strmout
->stride
[i
];
2890 struct ir3_instruction
*base
, *off
;
2892 base
= create_uniform(ctx
->block
, regid(const_state
->offsets
.tfbo
, i
));
2894 /* 24-bit should be enough: */
2895 off
= ir3_MUL_U24(ctx
->block
, vtxcnt
, 0,
2896 create_immed(ctx
->block
, stride
* 4), 0);
2898 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2901 /* Generate the per-output store instructions: */
2902 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2903 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2904 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2905 struct ir3_instruction
*base
, *out
, *stg
;
2907 base
= bases
[strmout
->output
[i
].output_buffer
];
2908 out
= ctx
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2910 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2911 create_immed(ctx
->block
, 1), 0);
2912 stg
->cat6
.type
= TYPE_U32
;
2913 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2915 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2919 /* and finally switch to the new_end_block: */
2920 ctx
->block
= new_end_block
;
2924 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
2926 nir_metadata_require(impl
, nir_metadata_block_index
);
2928 compile_assert(ctx
, ctx
->stack
== 0);
2930 emit_cf_list(ctx
, &impl
->body
);
2931 emit_block(ctx
, impl
->end_block
);
2933 compile_assert(ctx
, ctx
->stack
== 0);
2935 /* at this point, we should have a single empty block,
2936 * into which we emit the 'end' instruction.
2938 compile_assert(ctx
, list_is_empty(&ctx
->block
->instr_list
));
2940 /* If stream-out (aka transform-feedback) enabled, emit the
2941 * stream-out instructions, followed by a new empty block (into
2942 * which the 'end' instruction lands).
2944 * NOTE: it is done in this order, rather than inserting before
2945 * we emit end_block, because NIR guarantees that all blocks
2946 * flow into end_block, and that end_block has no successors.
2947 * So by re-purposing end_block as the first block of stream-
2948 * out, we guarantee that all exit paths flow into the stream-
2951 if ((ctx
->compiler
->gpu_id
< 500) &&
2952 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2953 !ctx
->so
->binning_pass
) {
2954 debug_assert(ctx
->so
->type
== MESA_SHADER_VERTEX
);
2955 emit_stream_out(ctx
);
2958 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2959 * NOP and has an epilogue that writes the VS outputs to local storage, to
2960 * be read by the HS. Then it resets execution mask (chmask) and chains
2961 * to the next shader (chsh).
2963 if ((ctx
->so
->type
== MESA_SHADER_VERTEX
&&
2964 (ctx
->so
->key
.has_gs
|| ctx
->so
->key
.tessellation
)) ||
2965 (ctx
->so
->type
== MESA_SHADER_TESS_EVAL
&& ctx
->so
->key
.has_gs
)) {
2966 struct ir3_instruction
*chmask
=
2967 ir3_CHMASK(ctx
->block
);
2968 chmask
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2969 chmask
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
2971 struct ir3_instruction
*chsh
=
2972 ir3_CHSH(ctx
->block
);
2973 chsh
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2974 chsh
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
2976 ir3_END(ctx
->block
);
2981 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
2983 struct ir3_shader_variant
*so
= ctx
->so
;
2984 unsigned ncomp
= glsl_get_components(in
->type
);
2985 unsigned n
= in
->data
.driver_location
;
2986 unsigned frac
= in
->data
.location_frac
;
2987 unsigned slot
= in
->data
.location
;
2989 /* Inputs are loaded using ldlw or ldg for these stages. */
2990 if (ctx
->so
->type
== MESA_SHADER_TESS_CTRL
||
2991 ctx
->so
->type
== MESA_SHADER_TESS_EVAL
||
2992 ctx
->so
->type
== MESA_SHADER_GEOMETRY
)
2995 /* skip unread inputs, we could end up with (for example), unsplit
2996 * matrix/etc inputs in the case they are not read, so just silently
3002 so
->inputs
[n
].slot
= slot
;
3003 so
->inputs
[n
].compmask
|= (1 << (ncomp
+ frac
)) - 1;
3004 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
3005 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
3007 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
3009 /* if any varyings have 'sample' qualifer, that triggers us
3010 * to run in per-sample mode:
3012 so
->per_samp
|= in
->data
.sample
;
3014 for (int i
= 0; i
< ncomp
; i
++) {
3015 struct ir3_instruction
*instr
= NULL
;
3016 unsigned idx
= (n
* 4) + i
+ frac
;
3018 if (slot
== VARYING_SLOT_POS
) {
3019 ir3_context_error(ctx
, "fragcoord should be a sysval!\n");
3021 /* detect the special case for front/back colors where
3022 * we need to do flat vs smooth shading depending on
3025 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
3027 case VARYING_SLOT_COL0
:
3028 case VARYING_SLOT_COL1
:
3029 case VARYING_SLOT_BFC0
:
3030 case VARYING_SLOT_BFC1
:
3031 so
->inputs
[n
].rasterflat
= true;
3038 if (ctx
->compiler
->flat_bypass
) {
3039 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
3040 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
3041 so
->inputs
[n
].use_ldlv
= true;
3044 so
->inputs
[n
].bary
= true;
3046 instr
= create_frag_input(ctx
, so
->inputs
[n
].use_ldlv
, idx
);
3049 compile_assert(ctx
, idx
< ctx
->ninputs
);
3051 ctx
->inputs
[idx
] = instr
;
3053 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
) {
3054 struct ir3_instruction
*input
= NULL
;
3055 struct ir3_instruction
*components
[4];
3056 /* input as setup as frac=0 with "ncomp + frac" components,
3057 * this avoids getting a sparse writemask
3059 unsigned mask
= (1 << (ncomp
+ frac
)) - 1;
3061 foreach_input (in
, ctx
->ir
) {
3062 if (in
->input
.inidx
== n
) {
3069 input
= create_input(ctx
, mask
);
3070 input
->input
.inidx
= n
;
3072 /* For aliased inputs, just append to the wrmask.. ie. if we
3073 * first see a vec2 index at slot N, and then later a vec4,
3074 * the wrmask of the resulting overlapped vec2 and vec4 is 0xf
3076 * If the new input that aliases a previously processed input
3077 * sets no new bits, then just bail as there is nothing to see
3080 if (!(mask
& ~input
->regs
[0]->wrmask
))
3082 input
->regs
[0]->wrmask
|= mask
;
3085 ir3_split_dest(ctx
->block
, components
, input
, 0, ncomp
+ frac
);
3087 for (int i
= 0; i
< ncomp
+ frac
; i
++) {
3088 unsigned idx
= (n
* 4) + i
;
3089 compile_assert(ctx
, idx
< ctx
->ninputs
);
3091 /* With aliased inputs, since we add to the wrmask above, we
3092 * can end up with stale meta:split instructions in the inputs
3093 * table. This is basically harmless, since eventually they
3094 * will get swept away by DCE, but the mismatch wrmask (since
3095 * they would be using the previous wrmask before we OR'd in
3096 * more bits) angers ir3_validate. So just preemptively clean
3099 * dEQP-GLES2.functional.attribute_location.bind_aliasing.cond_vec2
3101 * Note however that split_dest() will return the src if it is
3102 * scalar, so the previous ctx->inputs[idx] could be the input
3103 * itself (which we don't want to remove)
3105 if (ctx
->inputs
[idx
] && (ctx
->inputs
[idx
] != input
)) {
3106 list_del(&ctx
->inputs
[idx
]->node
);
3109 ctx
->inputs
[idx
] = components
[i
];
3112 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3115 /* note: this can be wrong for sparse vertex inputs, this happens with
3116 * vulkan, only a3xx/a4xx use this value for VS, so it shouldn't matter
3118 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== MESA_SHADER_VERTEX
)) {
3119 so
->total_in
+= ncomp
;
3123 /* Initially we assign non-packed inloc's for varyings, as we don't really
3124 * know up-front which components will be unused. After all the compilation
3125 * stages we scan the shader to see which components are actually used, and
3126 * re-pack the inlocs to eliminate unneeded varyings.
3129 pack_inlocs(struct ir3_context
*ctx
)
3131 struct ir3_shader_variant
*so
= ctx
->so
;
3132 uint8_t used_components
[so
->inputs_count
];
3134 memset(used_components
, 0, sizeof(used_components
));
3137 * First Step: scan shader to find which bary.f/ldlv remain:
3140 foreach_block (block
, &ctx
->ir
->block_list
) {
3141 foreach_instr (instr
, &block
->instr_list
) {
3142 if (is_input(instr
)) {
3143 unsigned inloc
= instr
->regs
[1]->iim_val
;
3144 unsigned i
= inloc
/ 4;
3145 unsigned j
= inloc
% 4;
3147 compile_assert(ctx
, instr
->regs
[1]->flags
& IR3_REG_IMMED
);
3148 compile_assert(ctx
, i
< so
->inputs_count
);
3150 used_components
[i
] |= 1 << j
;
3151 } else if (instr
->opc
== OPC_META_TEX_PREFETCH
) {
3152 for (int n
= 0; n
< 2; n
++) {
3153 unsigned inloc
= instr
->prefetch
.input_offset
+ n
;
3154 unsigned i
= inloc
/ 4;
3155 unsigned j
= inloc
% 4;
3157 compile_assert(ctx
, i
< so
->inputs_count
);
3159 used_components
[i
] |= 1 << j
;
3166 * Second Step: reassign varying inloc/slots:
3169 unsigned actual_in
= 0;
3172 for (unsigned i
= 0; i
< so
->inputs_count
; i
++) {
3173 unsigned compmask
= 0, maxcomp
= 0;
3175 so
->inputs
[i
].inloc
= inloc
;
3176 so
->inputs
[i
].bary
= false;
3178 for (unsigned j
= 0; j
< 4; j
++) {
3179 if (!(used_components
[i
] & (1 << j
)))
3182 compmask
|= (1 << j
);
3186 /* at this point, since used_components[i] mask is only
3187 * considering varyings (ie. not sysvals) we know this
3190 so
->inputs
[i
].bary
= true;
3193 if (so
->inputs
[i
].bary
) {
3195 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
3201 * Third Step: reassign packed inloc's:
3204 foreach_block (block
, &ctx
->ir
->block_list
) {
3205 foreach_instr (instr
, &block
->instr_list
) {
3206 if (is_input(instr
)) {
3207 unsigned inloc
= instr
->regs
[1]->iim_val
;
3208 unsigned i
= inloc
/ 4;
3209 unsigned j
= inloc
% 4;
3211 instr
->regs
[1]->iim_val
= so
->inputs
[i
].inloc
+ j
;
3212 } else if (instr
->opc
== OPC_META_TEX_PREFETCH
) {
3213 unsigned i
= instr
->prefetch
.input_offset
/ 4;
3214 unsigned j
= instr
->prefetch
.input_offset
% 4;
3215 instr
->prefetch
.input_offset
= so
->inputs
[i
].inloc
+ j
;
3222 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
3224 struct ir3_shader_variant
*so
= ctx
->so
;
3225 unsigned slots
= glsl_count_vec4_slots(out
->type
, false, false);
3226 unsigned ncomp
= glsl_get_components(glsl_without_array(out
->type
));
3227 unsigned n
= out
->data
.driver_location
;
3228 unsigned frac
= out
->data
.location_frac
;
3229 unsigned slot
= out
->data
.location
;
3231 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
3233 case FRAG_RESULT_DEPTH
:
3234 so
->writes_pos
= true;
3236 case FRAG_RESULT_COLOR
:
3239 case FRAG_RESULT_SAMPLE_MASK
:
3240 so
->writes_smask
= true;
3242 case FRAG_RESULT_STENCIL
:
3243 so
->writes_stencilref
= true;
3246 slot
+= out
->data
.index
; /* For dual-src blend */
3247 if (slot
>= FRAG_RESULT_DATA0
)
3249 ir3_context_error(ctx
, "unknown FS output name: %s\n",
3250 gl_frag_result_name(slot
));
3252 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
||
3253 ctx
->so
->type
== MESA_SHADER_TESS_EVAL
||
3254 ctx
->so
->type
== MESA_SHADER_GEOMETRY
) {
3256 case VARYING_SLOT_POS
:
3257 so
->writes_pos
= true;
3259 case VARYING_SLOT_PSIZ
:
3260 so
->writes_psize
= true;
3262 case VARYING_SLOT_PRIMITIVE_ID
:
3263 case VARYING_SLOT_LAYER
:
3264 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3
:
3265 debug_assert(ctx
->so
->type
== MESA_SHADER_GEOMETRY
);
3267 case VARYING_SLOT_COL0
:
3268 case VARYING_SLOT_COL1
:
3269 case VARYING_SLOT_BFC0
:
3270 case VARYING_SLOT_BFC1
:
3271 case VARYING_SLOT_FOGC
:
3272 case VARYING_SLOT_CLIP_DIST0
:
3273 case VARYING_SLOT_CLIP_DIST1
:
3274 case VARYING_SLOT_CLIP_VERTEX
:
3277 if (slot
>= VARYING_SLOT_VAR0
)
3279 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
3281 ir3_context_error(ctx
, "unknown %s shader output name: %s\n",
3282 _mesa_shader_stage_to_string(ctx
->so
->type
),
3283 gl_varying_slot_name(slot
));
3285 } else if (ctx
->so
->type
== MESA_SHADER_TESS_CTRL
) {
3286 /* output lowered to buffer writes. */
3289 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3293 so
->outputs_count
= out
->data
.driver_location
+ slots
;
3294 compile_assert(ctx
, so
->outputs_count
< ARRAY_SIZE(so
->outputs
));
3296 for (int i
= 0; i
< slots
; i
++) {
3297 int slot_base
= n
+ i
;
3298 so
->outputs
[slot_base
].slot
= slot
+ i
;
3300 for (int i
= 0; i
< ncomp
; i
++) {
3301 unsigned idx
= (slot_base
* 4) + i
+ frac
;
3302 compile_assert(ctx
, idx
< ctx
->noutputs
);
3303 ctx
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3306 /* if varying packing doesn't happen, we could end up in a situation
3307 * with "holes" in the output, and since the per-generation code that
3308 * sets up varying linkage registers doesn't expect to have more than
3309 * one varying per vec4 slot, pad the holes.
3311 * Note that this should probably generate a performance warning of
3314 for (int i
= 0; i
< frac
; i
++) {
3315 unsigned idx
= (slot_base
* 4) + i
;
3316 if (!ctx
->outputs
[idx
]) {
3317 ctx
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3324 emit_instructions(struct ir3_context
*ctx
)
3326 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
3328 ctx
->ninputs
= ctx
->s
->num_inputs
* 4;
3329 ctx
->noutputs
= ctx
->s
->num_outputs
* 4;
3330 ctx
->inputs
= rzalloc_array(ctx
, struct ir3_instruction
*, ctx
->ninputs
);
3331 ctx
->outputs
= rzalloc_array(ctx
, struct ir3_instruction
*, ctx
->noutputs
);
3333 ctx
->ir
= ir3_create(ctx
->compiler
, ctx
->so
);
3335 /* Create inputs in first block: */
3336 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3337 ctx
->in_block
= ctx
->block
;
3339 /* for fragment shader, the vcoord input register is used as the
3340 * base for bary.f varying fetch instrs:
3342 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3343 * until emit_intrinsic when we know they are actually needed.
3344 * For now, we defer creating ctx->ij_centroid, etc, since we
3345 * only need ij_pixel for "old style" varying inputs (ie.
3348 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
3349 ctx
->ij
[IJ_PERSP_PIXEL
] = create_input(ctx
, 0x3);
3353 nir_foreach_shader_in_variable (var
, ctx
->s
) {
3354 setup_input(ctx
, var
);
3357 /* Defer add_sysval_input() stuff until after setup_inputs(),
3358 * because sysvals need to be appended after varyings:
3360 if (ctx
->ij
[IJ_PERSP_PIXEL
]) {
3361 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
,
3362 0x3, ctx
->ij
[IJ_PERSP_PIXEL
]);
3366 /* Tesselation shaders always need primitive ID for indexing the
3367 * BO. Geometry shaders don't always need it but when they do it has be
3368 * delivered and unclobbered in the VS. To make things easy, we always
3369 * make room for it in VS/DS.
3371 bool has_tess
= ctx
->so
->key
.tessellation
!= IR3_TESS_NONE
;
3372 bool has_gs
= ctx
->so
->key
.has_gs
;
3373 switch (ctx
->so
->type
) {
3374 case MESA_SHADER_VERTEX
:
3376 ctx
->tcs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_TCS_HEADER_IR3
, 0x1);
3377 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3378 } else if (has_gs
) {
3379 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3380 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3383 case MESA_SHADER_TESS_CTRL
:
3384 ctx
->tcs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_TCS_HEADER_IR3
, 0x1);
3385 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3387 case MESA_SHADER_TESS_EVAL
:
3389 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3390 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3392 case MESA_SHADER_GEOMETRY
:
3393 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3394 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3400 /* Setup outputs: */
3401 nir_foreach_shader_out_variable (var
, ctx
->s
) {
3402 setup_output(ctx
, var
);
3405 /* Find # of samplers. Just assume that we'll be reading from images.. if
3406 * it is write-only we don't have to count it, but after lowering derefs
3407 * is too late to compact indices for that.
3409 ctx
->so
->num_samp
= util_last_bit(ctx
->s
->info
.textures_used
) + ctx
->s
->info
.num_images
;
3411 /* NOTE: need to do something more clever when we support >1 fxn */
3412 nir_foreach_register (reg
, &fxn
->registers
) {
3413 ir3_declare_array(ctx
, reg
);
3415 /* And emit the body: */
3417 emit_function(ctx
, fxn
);
3420 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3421 * need to assign the tex state indexes for these after we know the
3425 fixup_astc_srgb(struct ir3_context
*ctx
)
3427 struct ir3_shader_variant
*so
= ctx
->so
;
3428 /* indexed by original tex idx, value is newly assigned alpha sampler
3429 * state tex idx. Zero is invalid since there is at least one sampler
3432 unsigned alt_tex_state
[16] = {0};
3433 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3436 so
->astc_srgb
.base
= tex_idx
;
3438 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3439 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3441 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3443 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3444 /* assign new alternate/alpha tex state slot: */
3445 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3446 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3447 so
->astc_srgb
.count
++;
3450 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3455 fixup_binning_pass(struct ir3_context
*ctx
)
3457 struct ir3_shader_variant
*so
= ctx
->so
;
3458 struct ir3
*ir
= ctx
->ir
;
3461 /* first pass, remove unused outputs from the IR level outputs: */
3462 for (i
= 0, j
= 0; i
< ir
->outputs_count
; i
++) {
3463 struct ir3_instruction
*out
= ir
->outputs
[i
];
3464 assert(out
->opc
== OPC_META_COLLECT
);
3465 unsigned outidx
= out
->collect
.outidx
;
3466 unsigned slot
= so
->outputs
[outidx
].slot
;
3468 /* throw away everything but first position/psize */
3469 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3470 ir
->outputs
[j
] = ir
->outputs
[i
];
3474 ir
->outputs_count
= j
;
3476 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3479 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3480 unsigned slot
= so
->outputs
[i
].slot
;
3482 /* throw away everything but first position/psize */
3483 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3484 so
->outputs
[j
] = so
->outputs
[i
];
3486 /* fixup outidx to point to new output table entry: */
3487 foreach_output (out
, ir
) {
3488 if (out
->collect
.outidx
== i
) {
3489 out
->collect
.outidx
= j
;
3497 so
->outputs_count
= j
;
3501 collect_tex_prefetches(struct ir3_context
*ctx
, struct ir3
*ir
)
3505 /* Collect sampling instructions eligible for pre-dispatch. */
3506 foreach_block (block
, &ir
->block_list
) {
3507 foreach_instr_safe (instr
, &block
->instr_list
) {
3508 if (instr
->opc
== OPC_META_TEX_PREFETCH
) {
3509 assert(idx
< ARRAY_SIZE(ctx
->so
->sampler_prefetch
));
3510 struct ir3_sampler_prefetch
*fetch
=
3511 &ctx
->so
->sampler_prefetch
[idx
];
3514 if (instr
->flags
& IR3_INSTR_B
) {
3515 fetch
->cmd
= IR3_SAMPLER_BINDLESS_PREFETCH_CMD
;
3516 /* In bindless mode, the index is actually the base */
3517 fetch
->tex_id
= instr
->prefetch
.tex_base
;
3518 fetch
->samp_id
= instr
->prefetch
.samp_base
;
3519 fetch
->tex_bindless_id
= instr
->prefetch
.tex
;
3520 fetch
->samp_bindless_id
= instr
->prefetch
.samp
;
3522 fetch
->cmd
= IR3_SAMPLER_PREFETCH_CMD
;
3523 fetch
->tex_id
= instr
->prefetch
.tex
;
3524 fetch
->samp_id
= instr
->prefetch
.samp
;
3526 fetch
->wrmask
= instr
->regs
[0]->wrmask
;
3527 fetch
->dst
= instr
->regs
[0]->num
;
3528 fetch
->src
= instr
->prefetch
.input_offset
;
3530 /* These are the limits on a5xx/a6xx, we might need to
3531 * revisit if SP_FS_PREFETCH[n] changes on later gens:
3533 assert(fetch
->dst
<= 0x3f);
3534 assert(fetch
->tex_id
<= 0x1f);
3535 assert(fetch
->samp_id
< 0xf);
3538 MAX2(ctx
->so
->total_in
, instr
->prefetch
.input_offset
+ 2);
3540 fetch
->half_precision
= !!(instr
->regs
[0]->flags
& IR3_REG_HALF
);
3542 /* Remove the prefetch placeholder instruction: */
3543 list_delinit(&instr
->node
);
3550 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3551 struct ir3_shader_variant
*so
)
3553 struct ir3_context
*ctx
;
3555 int ret
= 0, max_bary
;
3560 ctx
= ir3_context_init(compiler
, so
);
3562 DBG("INIT failed!");
3567 emit_instructions(ctx
);
3570 DBG("EMIT failed!");
3575 ir
= so
->ir
= ctx
->ir
;
3577 assert((ctx
->noutputs
% 4) == 0);
3579 /* Setup IR level outputs, which are "collects" that gather
3580 * the scalar components of outputs.
3582 for (unsigned i
= 0; i
< ctx
->noutputs
; i
+= 4) {
3584 /* figure out the # of components written:
3586 * TODO do we need to handle holes, ie. if .x and .z
3587 * components written, but .y component not written?
3589 for (unsigned j
= 0; j
< 4; j
++) {
3590 if (!ctx
->outputs
[i
+ j
])
3595 /* Note that in some stages, like TCS, store_output is
3596 * lowered to memory writes, so no components of the
3597 * are "written" from the PoV of traditional store-
3598 * output instructions:
3603 struct ir3_instruction
*out
=
3604 ir3_create_collect(ctx
, &ctx
->outputs
[i
], ncomp
);
3607 assert(outidx
< so
->outputs_count
);
3609 /* stash index into so->outputs[] so we can map the
3610 * output back to slot/etc later:
3612 out
->collect
.outidx
= outidx
;
3614 array_insert(ir
, ir
->outputs
, out
);
3617 /* Set up the gs header as an output for the vertex shader so it won't
3618 * clobber it for the tess ctrl shader.
3620 * TODO this could probably be done more cleanly in a nir pass.
3622 if (ctx
->so
->type
== MESA_SHADER_VERTEX
||
3623 (ctx
->so
->key
.has_gs
&& ctx
->so
->type
== MESA_SHADER_TESS_EVAL
)) {
3624 if (ctx
->primitive_id
) {
3625 unsigned n
= so
->outputs_count
++;
3626 so
->outputs
[n
].slot
= VARYING_SLOT_PRIMITIVE_ID
;
3628 struct ir3_instruction
*out
=
3629 ir3_create_collect(ctx
, &ctx
->primitive_id
, 1);
3630 out
->collect
.outidx
= n
;
3631 array_insert(ir
, ir
->outputs
, out
);
3634 if (ctx
->gs_header
) {
3635 unsigned n
= so
->outputs_count
++;
3636 so
->outputs
[n
].slot
= VARYING_SLOT_GS_HEADER_IR3
;
3637 struct ir3_instruction
*out
=
3638 ir3_create_collect(ctx
, &ctx
->gs_header
, 1);
3639 out
->collect
.outidx
= n
;
3640 array_insert(ir
, ir
->outputs
, out
);
3643 if (ctx
->tcs_header
) {
3644 unsigned n
= so
->outputs_count
++;
3645 so
->outputs
[n
].slot
= VARYING_SLOT_TCS_HEADER_IR3
;
3646 struct ir3_instruction
*out
=
3647 ir3_create_collect(ctx
, &ctx
->tcs_header
, 1);
3648 out
->collect
.outidx
= n
;
3649 array_insert(ir
, ir
->outputs
, out
);
3653 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3654 * need to make sure not to remove any inputs that are used by
3655 * the nonbinning VS.
3657 if (ctx
->compiler
->gpu_id
>= 600 && so
->binning_pass
&&
3658 so
->type
== MESA_SHADER_VERTEX
) {
3659 for (int i
= 0; i
< ctx
->ninputs
; i
++) {
3660 struct ir3_instruction
*in
= ctx
->inputs
[i
];
3668 debug_assert(n
< so
->nonbinning
->inputs_count
);
3670 if (so
->nonbinning
->inputs
[n
].sysval
)
3673 /* be sure to keep inputs, even if only used in VS */
3674 if (so
->nonbinning
->inputs
[n
].compmask
& (1 << c
))
3675 array_insert(in
->block
, in
->block
->keeps
, in
);
3679 /* at this point, for binning pass, throw away unneeded outputs: */
3680 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
< 600))
3681 fixup_binning_pass(ctx
);
3683 ir3_debug_print(ir
, "AFTER: nir->ir3");
3689 progress
|= IR3_PASS(ir
, ir3_cf
);
3690 progress
|= IR3_PASS(ir
, ir3_cp
, so
);
3691 progress
|= IR3_PASS(ir
, ir3_dce
, so
);
3694 /* at this point, for binning pass, throw away unneeded outputs:
3695 * Note that for a6xx and later, we do this after ir3_cp to ensure
3696 * that the uniform/constant layout for BS and VS matches, so that
3697 * we can re-use same VS_CONST state group.
3699 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
>= 600)) {
3700 fixup_binning_pass(ctx
);
3701 /* cleanup the result of removing unneeded outputs: */
3702 while (IR3_PASS(ir
, ir3_dce
, so
)) {}
3705 IR3_PASS(ir
, ir3_sched_add_deps
);
3707 /* Group left/right neighbors, inserting mov's where needed to
3710 IR3_PASS(ir
, ir3_group
);
3712 /* At this point, all the dead code should be long gone: */
3713 assert(!IR3_PASS(ir
, ir3_dce
, so
));
3715 ret
= ir3_sched(ir
);
3717 DBG("SCHED failed!");
3721 ir3_debug_print(ir
, "AFTER: ir3_sched");
3723 if (IR3_PASS(ir
, ir3_cp_postsched
)) {
3724 /* cleanup the result of removing unneeded mov's: */
3725 while (IR3_PASS(ir
, ir3_dce
, so
)) {}
3728 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3729 * with draw pass VS, so binning and draw pass can both use the
3732 * Note that VS inputs are expected to be full precision.
3734 bool pre_assign_inputs
= (ir
->compiler
->gpu_id
>= 600) &&
3735 (ir
->type
== MESA_SHADER_VERTEX
) &&
3738 if (pre_assign_inputs
) {
3739 for (unsigned i
= 0; i
< ctx
->ninputs
; i
++) {
3740 struct ir3_instruction
*instr
= ctx
->inputs
[i
];
3747 unsigned regid
= so
->nonbinning
->inputs
[n
].regid
+ c
;
3749 instr
->regs
[0]->num
= regid
;
3752 ret
= ir3_ra(so
, ctx
->inputs
, ctx
->ninputs
);
3753 } else if (ctx
->tcs_header
) {
3754 /* We need to have these values in the same registers between VS and TCS
3755 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3758 ctx
->tcs_header
->regs
[0]->num
= regid(0, 0);
3759 ctx
->primitive_id
->regs
[0]->num
= regid(0, 1);
3760 struct ir3_instruction
*precolor
[] = { ctx
->tcs_header
, ctx
->primitive_id
};
3761 ret
= ir3_ra(so
, precolor
, ARRAY_SIZE(precolor
));
3762 } else if (ctx
->gs_header
) {
3763 /* We need to have these values in the same registers between producer
3764 * (VS or DS) and GS since the producer chains to GS and doesn't get
3765 * the sysvals redelivered.
3768 ctx
->gs_header
->regs
[0]->num
= regid(0, 0);
3769 ctx
->primitive_id
->regs
[0]->num
= regid(0, 1);
3770 struct ir3_instruction
*precolor
[] = { ctx
->gs_header
, ctx
->primitive_id
};
3771 ret
= ir3_ra(so
, precolor
, ARRAY_SIZE(precolor
));
3772 } else if (so
->num_sampler_prefetch
) {
3773 assert(so
->type
== MESA_SHADER_FRAGMENT
);
3774 struct ir3_instruction
*precolor
[2];
3777 foreach_input (instr
, ir
) {
3778 if (instr
->input
.sysval
!= SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
)
3781 assert(idx
< ARRAY_SIZE(precolor
));
3783 precolor
[idx
] = instr
;
3784 instr
->regs
[0]->num
= idx
;
3788 ret
= ir3_ra(so
, precolor
, idx
);
3790 ret
= ir3_ra(so
, NULL
, 0);
3798 IR3_PASS(ir
, ir3_postsched
, so
);
3800 if (compiler
->gpu_id
>= 600) {
3801 IR3_PASS(ir
, ir3_a6xx_fixup_atomic_dests
, so
);
3804 if (so
->type
== MESA_SHADER_FRAGMENT
)
3808 * Fixup inputs/outputs to point to the actual registers assigned:
3810 * 1) initialize to r63.x (invalid/unused)
3811 * 2) iterate IR level inputs/outputs and update the variants
3812 * inputs/outputs table based on the assigned registers for
3813 * the remaining inputs/outputs.
3816 for (unsigned i
= 0; i
< so
->inputs_count
; i
++)
3817 so
->inputs
[i
].regid
= INVALID_REG
;
3818 for (unsigned i
= 0; i
< so
->outputs_count
; i
++)
3819 so
->outputs
[i
].regid
= INVALID_REG
;
3821 foreach_output (out
, ir
) {
3822 assert(out
->opc
== OPC_META_COLLECT
);
3823 unsigned outidx
= out
->collect
.outidx
;
3825 so
->outputs
[outidx
].regid
= out
->regs
[0]->num
;
3826 so
->outputs
[outidx
].half
= !!(out
->regs
[0]->flags
& IR3_REG_HALF
);
3829 foreach_input (in
, ir
) {
3830 assert(in
->opc
== OPC_META_INPUT
);
3831 unsigned inidx
= in
->input
.inidx
;
3833 if (pre_assign_inputs
&& !so
->inputs
[inidx
].sysval
) {
3834 if (VALIDREG(so
->nonbinning
->inputs
[inidx
].regid
)) {
3835 compile_assert(ctx
, in
->regs
[0]->num
==
3836 so
->nonbinning
->inputs
[inidx
].regid
);
3837 compile_assert(ctx
, !!(in
->regs
[0]->flags
& IR3_REG_HALF
) ==
3838 so
->nonbinning
->inputs
[inidx
].half
);
3840 so
->inputs
[inidx
].regid
= so
->nonbinning
->inputs
[inidx
].regid
;
3841 so
->inputs
[inidx
].half
= so
->nonbinning
->inputs
[inidx
].half
;
3843 so
->inputs
[inidx
].regid
= in
->regs
[0]->num
;
3844 so
->inputs
[inidx
].half
= !!(in
->regs
[0]->flags
& IR3_REG_HALF
);
3849 fixup_astc_srgb(ctx
);
3851 /* We need to do legalize after (for frag shader's) the "bary.f"
3852 * offsets (inloc) have been assigned.
3854 IR3_PASS(ir
, ir3_legalize
, so
, &max_bary
);
3856 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3857 * know what we might have to wait on when coming in from VS chsh.
3859 if (so
->type
== MESA_SHADER_TESS_CTRL
||
3860 so
->type
== MESA_SHADER_GEOMETRY
) {
3861 foreach_block (block
, &ir
->block_list
) {
3862 foreach_instr (instr
, &block
->instr_list
) {
3863 instr
->flags
|= IR3_INSTR_SS
| IR3_INSTR_SY
;
3869 so
->branchstack
= ctx
->max_stack
;
3871 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3872 if (so
->type
== MESA_SHADER_FRAGMENT
)
3873 so
->total_in
= max_bary
+ 1;
3875 /* Collect sampling instructions eligible for pre-dispatch. */
3876 collect_tex_prefetches(ctx
, ir
);
3878 if (so
->type
== MESA_SHADER_FRAGMENT
&&
3879 ctx
->s
->info
.fs
.needs_helper_invocations
)
3880 so
->need_pixlod
= true;
3885 ir3_destroy(so
->ir
);
3888 ir3_context_free(ctx
);