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freedreno/ir3: set more barrier bits
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 ir3_reg_create(mov, 0, 0);
55 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
56 src->instr = collect;
57 src->size = arrsz;
58 src->array.offset = n;
59
60 ir3_instr_set_address(mov, address);
61
62 return mov;
63 }
64
65 static struct ir3_instruction *
66 create_input_compmask(struct ir3_context *ctx, unsigned n, unsigned compmask)
67 {
68 struct ir3_instruction *in;
69
70 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
71 in->inout.block = ctx->in_block;
72 ir3_reg_create(in, n, 0);
73
74 in->regs[0]->wrmask = compmask;
75
76 return in;
77 }
78
79 static struct ir3_instruction *
80 create_input(struct ir3_context *ctx, unsigned n)
81 {
82 return create_input_compmask(ctx, n, 0x1);
83 }
84
85 static struct ir3_instruction *
86 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
87 {
88 struct ir3_block *block = ctx->block;
89 struct ir3_instruction *instr;
90 /* packed inloc is fixed up later: */
91 struct ir3_instruction *inloc = create_immed(block, n);
92
93 if (use_ldlv) {
94 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
95 instr->cat6.type = TYPE_U32;
96 instr->cat6.iim_val = 1;
97 } else {
98 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
99 instr->regs[2]->wrmask = 0x3;
100 }
101
102 return instr;
103 }
104
105 static struct ir3_instruction *
106 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
107 {
108 /* first four vec4 sysval's reserved for UBOs: */
109 /* NOTE: dp is in scalar, but there can be >4 dp components: */
110 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
111 unsigned n = const_state->offsets.driver_param;
112 unsigned r = regid(n + dp / 4, dp % 4);
113 return create_uniform(ctx->block, r);
114 }
115
116 /*
117 * Adreno uses uint rather than having dedicated bool type,
118 * which (potentially) requires some conversion, in particular
119 * when using output of an bool instr to int input, or visa
120 * versa.
121 *
122 * | Adreno | NIR |
123 * -------+---------+-------+-
124 * true | 1 | ~0 |
125 * false | 0 | 0 |
126 *
127 * To convert from an adreno bool (uint) to nir, use:
128 *
129 * absneg.s dst, (neg)src
130 *
131 * To convert back in the other direction:
132 *
133 * absneg.s dst, (abs)arc
134 *
135 * The CP step can clean up the absneg.s that cancel each other
136 * out, and with a slight bit of extra cleverness (to recognize
137 * the instructions which produce either a 0 or 1) can eliminate
138 * the absneg.s's completely when an instruction that wants
139 * 0/1 consumes the result. For example, when a nir 'bcsel'
140 * consumes the result of 'feq'. So we should be able to get by
141 * without a boolean resolve step, and without incuring any
142 * extra penalty in instruction count.
143 */
144
145 /* NIR bool -> native (adreno): */
146 static struct ir3_instruction *
147 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
148 {
149 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
150 }
151
152 /* native (adreno) -> NIR bool: */
153 static struct ir3_instruction *
154 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
155 {
156 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
157 }
158
159 /*
160 * alu/sfu instructions:
161 */
162
163 static struct ir3_instruction *
164 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
165 unsigned src_bitsize, nir_op op)
166 {
167 type_t src_type, dst_type;
168
169 switch (op) {
170 case nir_op_f2f32:
171 case nir_op_f2f16_rtne:
172 case nir_op_f2f16_rtz:
173 case nir_op_f2f16:
174 case nir_op_f2i32:
175 case nir_op_f2i16:
176 case nir_op_f2i8:
177 case nir_op_f2u32:
178 case nir_op_f2u16:
179 case nir_op_f2u8:
180 switch (src_bitsize) {
181 case 32:
182 src_type = TYPE_F32;
183 break;
184 case 16:
185 src_type = TYPE_F16;
186 break;
187 default:
188 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
189 }
190 break;
191
192 case nir_op_i2f32:
193 case nir_op_i2f16:
194 case nir_op_i2i32:
195 case nir_op_i2i16:
196 case nir_op_i2i8:
197 switch (src_bitsize) {
198 case 32:
199 src_type = TYPE_S32;
200 break;
201 case 16:
202 src_type = TYPE_S16;
203 break;
204 case 8:
205 src_type = TYPE_S8;
206 break;
207 default:
208 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
209 }
210 break;
211
212 case nir_op_u2f32:
213 case nir_op_u2f16:
214 case nir_op_u2u32:
215 case nir_op_u2u16:
216 case nir_op_u2u8:
217 switch (src_bitsize) {
218 case 32:
219 src_type = TYPE_U32;
220 break;
221 case 16:
222 src_type = TYPE_U16;
223 break;
224 case 8:
225 src_type = TYPE_U8;
226 break;
227 default:
228 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
229 }
230 break;
231
232 default:
233 ir3_context_error(ctx, "invalid conversion op: %u", op);
234 }
235
236 switch (op) {
237 case nir_op_f2f32:
238 case nir_op_i2f32:
239 case nir_op_u2f32:
240 dst_type = TYPE_F32;
241 break;
242
243 case nir_op_f2f16_rtne:
244 case nir_op_f2f16_rtz:
245 case nir_op_f2f16:
246 /* TODO how to handle rounding mode? */
247 case nir_op_i2f16:
248 case nir_op_u2f16:
249 dst_type = TYPE_F16;
250 break;
251
252 case nir_op_f2i32:
253 case nir_op_i2i32:
254 dst_type = TYPE_S32;
255 break;
256
257 case nir_op_f2i16:
258 case nir_op_i2i16:
259 dst_type = TYPE_S16;
260 break;
261
262 case nir_op_f2i8:
263 case nir_op_i2i8:
264 dst_type = TYPE_S8;
265 break;
266
267 case nir_op_f2u32:
268 case nir_op_u2u32:
269 dst_type = TYPE_U32;
270 break;
271
272 case nir_op_f2u16:
273 case nir_op_u2u16:
274 dst_type = TYPE_U16;
275 break;
276
277 case nir_op_f2u8:
278 case nir_op_u2u8:
279 dst_type = TYPE_U8;
280 break;
281
282 default:
283 ir3_context_error(ctx, "invalid conversion op: %u", op);
284 }
285
286 return ir3_COV(ctx->block, src, src_type, dst_type);
287 }
288
289 static void
290 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
291 {
292 const nir_op_info *info = &nir_op_infos[alu->op];
293 struct ir3_instruction **dst, *src[info->num_inputs];
294 unsigned bs[info->num_inputs]; /* bit size */
295 struct ir3_block *b = ctx->block;
296 unsigned dst_sz, wrmask;
297
298 if (alu->dest.dest.is_ssa) {
299 dst_sz = alu->dest.dest.ssa.num_components;
300 wrmask = (1 << dst_sz) - 1;
301 } else {
302 dst_sz = alu->dest.dest.reg.reg->num_components;
303 wrmask = alu->dest.write_mask;
304 }
305
306 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
307
308 /* Vectors are special in that they have non-scalarized writemasks,
309 * and just take the first swizzle channel for each argument in
310 * order into each writemask channel.
311 */
312 if ((alu->op == nir_op_vec2) ||
313 (alu->op == nir_op_vec3) ||
314 (alu->op == nir_op_vec4)) {
315
316 for (int i = 0; i < info->num_inputs; i++) {
317 nir_alu_src *asrc = &alu->src[i];
318
319 compile_assert(ctx, !asrc->abs);
320 compile_assert(ctx, !asrc->negate);
321
322 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
323 if (!src[i])
324 src[i] = create_immed(ctx->block, 0);
325 dst[i] = ir3_MOV(b, src[i], TYPE_U32);
326 }
327
328 ir3_put_dst(ctx, &alu->dest.dest);
329 return;
330 }
331
332 /* We also get mov's with more than one component for mov's so
333 * handle those specially:
334 */
335 if (alu->op == nir_op_mov) {
336 type_t type = TYPE_U32;
337 nir_alu_src *asrc = &alu->src[0];
338 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
339
340 for (unsigned i = 0; i < dst_sz; i++) {
341 if (wrmask & (1 << i)) {
342 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], type);
343 } else {
344 dst[i] = NULL;
345 }
346 }
347
348 ir3_put_dst(ctx, &alu->dest.dest);
349 return;
350 }
351
352 /* General case: We can just grab the one used channel per src. */
353 for (int i = 0; i < info->num_inputs; i++) {
354 unsigned chan = ffs(alu->dest.write_mask) - 1;
355 nir_alu_src *asrc = &alu->src[i];
356
357 compile_assert(ctx, !asrc->abs);
358 compile_assert(ctx, !asrc->negate);
359
360 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
361 bs[i] = nir_src_bit_size(asrc->src);
362
363 compile_assert(ctx, src[i]);
364 }
365
366 switch (alu->op) {
367 case nir_op_f2f32:
368 case nir_op_f2f16_rtne:
369 case nir_op_f2f16_rtz:
370 case nir_op_f2f16:
371 case nir_op_f2i32:
372 case nir_op_f2i16:
373 case nir_op_f2i8:
374 case nir_op_f2u32:
375 case nir_op_f2u16:
376 case nir_op_f2u8:
377 case nir_op_i2f32:
378 case nir_op_i2f16:
379 case nir_op_i2i32:
380 case nir_op_i2i16:
381 case nir_op_i2i8:
382 case nir_op_u2f32:
383 case nir_op_u2f16:
384 case nir_op_u2u32:
385 case nir_op_u2u16:
386 case nir_op_u2u8:
387 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
388 break;
389 case nir_op_f2b32:
390 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
391 dst[0]->cat2.condition = IR3_COND_NE;
392 dst[0] = ir3_n2b(b, dst[0]);
393 break;
394 case nir_op_b2f16:
395 case nir_op_b2f32:
396 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
397 break;
398 case nir_op_b2i8:
399 case nir_op_b2i16:
400 case nir_op_b2i32:
401 dst[0] = ir3_b2n(b, src[0]);
402 break;
403 case nir_op_i2b32:
404 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
405 dst[0]->cat2.condition = IR3_COND_NE;
406 dst[0] = ir3_n2b(b, dst[0]);
407 break;
408
409 case nir_op_fneg:
410 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
411 break;
412 case nir_op_fabs:
413 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
414 break;
415 case nir_op_fmax:
416 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
417 break;
418 case nir_op_fmin:
419 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
420 break;
421 case nir_op_fsat:
422 /* if there is just a single use of the src, and it supports
423 * (sat) bit, we can just fold the (sat) flag back to the
424 * src instruction and create a mov. This is easier for cp
425 * to eliminate.
426 *
427 * TODO probably opc_cat==4 is ok too
428 */
429 if (alu->src[0].src.is_ssa &&
430 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
431 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
432 src[0]->flags |= IR3_INSTR_SAT;
433 dst[0] = ir3_MOV(b, src[0], TYPE_U32);
434 } else {
435 /* otherwise generate a max.f that saturates.. blob does
436 * similar (generating a cat2 mov using max.f)
437 */
438 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
439 dst[0]->flags |= IR3_INSTR_SAT;
440 }
441 break;
442 case nir_op_fmul:
443 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
444 break;
445 case nir_op_fadd:
446 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
447 break;
448 case nir_op_fsub:
449 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
450 break;
451 case nir_op_ffma:
452 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
453 break;
454 case nir_op_fddx:
455 dst[0] = ir3_DSX(b, src[0], 0);
456 dst[0]->cat5.type = TYPE_F32;
457 break;
458 case nir_op_fddy:
459 dst[0] = ir3_DSY(b, src[0], 0);
460 dst[0]->cat5.type = TYPE_F32;
461 break;
462 break;
463 case nir_op_flt32:
464 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
465 dst[0]->cat2.condition = IR3_COND_LT;
466 dst[0] = ir3_n2b(b, dst[0]);
467 break;
468 case nir_op_fge32:
469 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
470 dst[0]->cat2.condition = IR3_COND_GE;
471 dst[0] = ir3_n2b(b, dst[0]);
472 break;
473 case nir_op_feq32:
474 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
475 dst[0]->cat2.condition = IR3_COND_EQ;
476 dst[0] = ir3_n2b(b, dst[0]);
477 break;
478 case nir_op_fne32:
479 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
480 dst[0]->cat2.condition = IR3_COND_NE;
481 dst[0] = ir3_n2b(b, dst[0]);
482 break;
483 case nir_op_fceil:
484 dst[0] = ir3_CEIL_F(b, src[0], 0);
485 break;
486 case nir_op_ffloor:
487 dst[0] = ir3_FLOOR_F(b, src[0], 0);
488 break;
489 case nir_op_ftrunc:
490 dst[0] = ir3_TRUNC_F(b, src[0], 0);
491 break;
492 case nir_op_fround_even:
493 dst[0] = ir3_RNDNE_F(b, src[0], 0);
494 break;
495 case nir_op_fsign:
496 dst[0] = ir3_SIGN_F(b, src[0], 0);
497 break;
498
499 case nir_op_fsin:
500 dst[0] = ir3_SIN(b, src[0], 0);
501 break;
502 case nir_op_fcos:
503 dst[0] = ir3_COS(b, src[0], 0);
504 break;
505 case nir_op_frsq:
506 dst[0] = ir3_RSQ(b, src[0], 0);
507 break;
508 case nir_op_frcp:
509 dst[0] = ir3_RCP(b, src[0], 0);
510 break;
511 case nir_op_flog2:
512 dst[0] = ir3_LOG2(b, src[0], 0);
513 break;
514 case nir_op_fexp2:
515 dst[0] = ir3_EXP2(b, src[0], 0);
516 break;
517 case nir_op_fsqrt:
518 dst[0] = ir3_SQRT(b, src[0], 0);
519 break;
520
521 case nir_op_iabs:
522 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
523 break;
524 case nir_op_iadd:
525 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
526 break;
527 case nir_op_iand:
528 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
529 break;
530 case nir_op_imax:
531 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
532 break;
533 case nir_op_umax:
534 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
535 break;
536 case nir_op_imin:
537 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
538 break;
539 case nir_op_umin:
540 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
541 break;
542 case nir_op_imul:
543 /*
544 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
545 * mull.u tmp0, a, b ; mul low, i.e. al * bl
546 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
547 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
548 */
549 dst[0] = ir3_MADSH_M16(b, src[1], 0, src[0], 0,
550 ir3_MADSH_M16(b, src[0], 0, src[1], 0,
551 ir3_MULL_U(b, src[0], 0, src[1], 0), 0), 0);
552 break;
553 case nir_op_ineg:
554 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
555 break;
556 case nir_op_inot:
557 dst[0] = ir3_NOT_B(b, src[0], 0);
558 break;
559 case nir_op_ior:
560 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
561 break;
562 case nir_op_ishl:
563 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
564 break;
565 case nir_op_ishr:
566 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
567 break;
568 case nir_op_isub:
569 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
570 break;
571 case nir_op_ixor:
572 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
573 break;
574 case nir_op_ushr:
575 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
576 break;
577 case nir_op_ilt32:
578 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
579 dst[0]->cat2.condition = IR3_COND_LT;
580 dst[0] = ir3_n2b(b, dst[0]);
581 break;
582 case nir_op_ige32:
583 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
584 dst[0]->cat2.condition = IR3_COND_GE;
585 dst[0] = ir3_n2b(b, dst[0]);
586 break;
587 case nir_op_ieq32:
588 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
589 dst[0]->cat2.condition = IR3_COND_EQ;
590 dst[0] = ir3_n2b(b, dst[0]);
591 break;
592 case nir_op_ine32:
593 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
594 dst[0]->cat2.condition = IR3_COND_NE;
595 dst[0] = ir3_n2b(b, dst[0]);
596 break;
597 case nir_op_ult32:
598 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
599 dst[0]->cat2.condition = IR3_COND_LT;
600 dst[0] = ir3_n2b(b, dst[0]);
601 break;
602 case nir_op_uge32:
603 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
604 dst[0]->cat2.condition = IR3_COND_GE;
605 dst[0] = ir3_n2b(b, dst[0]);
606 break;
607
608 case nir_op_b32csel: {
609 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
610 compile_assert(ctx, bs[1] == bs[2]);
611 /* the boolean condition is 32b even if src[1] and src[2] are
612 * half-precision, but sel.b16 wants all three src's to be the
613 * same type.
614 */
615 if (bs[1] < 32)
616 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
617 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
618 break;
619 }
620 case nir_op_bit_count: {
621 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
622 // double check on earlier gen's. Once half-precision support is
623 // in place, this should probably move to a NIR lowering pass:
624 struct ir3_instruction *hi, *lo;
625
626 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
627 TYPE_U32, TYPE_U16);
628 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
629
630 hi = ir3_CBITS_B(b, hi, 0);
631 lo = ir3_CBITS_B(b, lo, 0);
632
633 // TODO maybe the builders should default to making dst half-precision
634 // if the src's were half precision, to make this less awkward.. otoh
635 // we should probably just do this lowering in NIR.
636 hi->regs[0]->flags |= IR3_REG_HALF;
637 lo->regs[0]->flags |= IR3_REG_HALF;
638
639 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
640 dst[0]->regs[0]->flags |= IR3_REG_HALF;
641 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
642 break;
643 }
644 case nir_op_ifind_msb: {
645 struct ir3_instruction *cmp;
646 dst[0] = ir3_CLZ_S(b, src[0], 0);
647 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
648 cmp->cat2.condition = IR3_COND_GE;
649 dst[0] = ir3_SEL_B32(b,
650 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
651 cmp, 0, dst[0], 0);
652 break;
653 }
654 case nir_op_ufind_msb:
655 dst[0] = ir3_CLZ_B(b, src[0], 0);
656 dst[0] = ir3_SEL_B32(b,
657 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
658 src[0], 0, dst[0], 0);
659 break;
660 case nir_op_find_lsb:
661 dst[0] = ir3_BFREV_B(b, src[0], 0);
662 dst[0] = ir3_CLZ_B(b, dst[0], 0);
663 break;
664 case nir_op_bitfield_reverse:
665 dst[0] = ir3_BFREV_B(b, src[0], 0);
666 break;
667
668 default:
669 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
670 nir_op_infos[alu->op].name);
671 break;
672 }
673
674 ir3_put_dst(ctx, &alu->dest.dest);
675 }
676
677 /* handles direct/indirect UBO reads: */
678 static void
679 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
680 struct ir3_instruction **dst)
681 {
682 struct ir3_block *b = ctx->block;
683 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
684 /* UBO addresses are the first driver params, but subtract 2 here to
685 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
686 * is the uniforms: */
687 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
688 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
689 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
690
691 int off = 0;
692
693 /* First src is ubo index, which could either be an immed or not: */
694 src0 = ir3_get_src(ctx, &intr->src[0])[0];
695 if (is_same_type_mov(src0) &&
696 (src0->regs[1]->flags & IR3_REG_IMMED)) {
697 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
698 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
699 } else {
700 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
701 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
702 }
703
704 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
705 addr = base_lo;
706
707 if (nir_src_is_const(intr->src[1])) {
708 off += nir_src_as_uint(intr->src[1]);
709 } else {
710 /* For load_ubo_indirect, second src is indirect offset: */
711 src1 = ir3_get_src(ctx, &intr->src[1])[0];
712
713 /* and add offset to addr: */
714 addr = ir3_ADD_S(b, addr, 0, src1, 0);
715 }
716
717 /* if offset is to large to encode in the ldg, split it out: */
718 if ((off + (intr->num_components * 4)) > 1024) {
719 /* split out the minimal amount to improve the odds that
720 * cp can fit the immediate in the add.s instruction:
721 */
722 unsigned off2 = off + (intr->num_components * 4) - 1024;
723 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
724 off -= off2;
725 }
726
727 if (ptrsz == 2) {
728 struct ir3_instruction *carry;
729
730 /* handle 32b rollover, ie:
731 * if (addr < base_lo)
732 * base_hi++
733 */
734 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
735 carry->cat2.condition = IR3_COND_LT;
736 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
737
738 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
739 }
740
741 for (int i = 0; i < intr->num_components; i++) {
742 struct ir3_instruction *load =
743 ir3_LDG(b, addr, 0, create_immed(b, 1), 0);
744 load->cat6.type = TYPE_U32;
745 load->cat6.src_offset = off + i * 4; /* byte offset */
746 dst[i] = load;
747 }
748 }
749
750 /* src[] = { block_index } */
751 static void
752 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
753 struct ir3_instruction **dst)
754 {
755 /* SSBO size stored as a const starting at ssbo_sizes: */
756 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
757 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
758 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
759 const_state->ssbo_size.off[blk_idx];
760
761 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
762
763 dst[0] = create_uniform(ctx->block, idx);
764 }
765
766 /* src[] = { offset }. const_index[] = { base } */
767 static void
768 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
769 struct ir3_instruction **dst)
770 {
771 struct ir3_block *b = ctx->block;
772 struct ir3_instruction *ldl, *offset;
773 unsigned base;
774
775 offset = ir3_get_src(ctx, &intr->src[0])[0];
776 base = nir_intrinsic_base(intr);
777
778 ldl = ir3_LDL(b, offset, 0, create_immed(b, intr->num_components), 0);
779 ldl->cat6.src_offset = base;
780 ldl->cat6.type = utype_dst(intr->dest);
781 ldl->regs[0]->wrmask = MASK(intr->num_components);
782
783 ldl->barrier_class = IR3_BARRIER_SHARED_R;
784 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
785
786 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
787 }
788
789 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
790 static void
791 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
792 {
793 struct ir3_block *b = ctx->block;
794 struct ir3_instruction *stl, *offset;
795 struct ir3_instruction * const *value;
796 unsigned base, wrmask;
797
798 value = ir3_get_src(ctx, &intr->src[0]);
799 offset = ir3_get_src(ctx, &intr->src[1])[0];
800
801 base = nir_intrinsic_base(intr);
802 wrmask = nir_intrinsic_write_mask(intr);
803
804 /* Combine groups of consecutive enabled channels in one write
805 * message. We use ffs to find the first enabled channel and then ffs on
806 * the bit-inverse, down-shifted writemask to determine the length of
807 * the block of enabled bits.
808 *
809 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
810 */
811 while (wrmask) {
812 unsigned first_component = ffs(wrmask) - 1;
813 unsigned length = ffs(~(wrmask >> first_component)) - 1;
814
815 stl = ir3_STL(b, offset, 0,
816 ir3_create_collect(ctx, &value[first_component], length), 0,
817 create_immed(b, length), 0);
818 stl->cat6.dst_offset = first_component + base;
819 stl->cat6.type = utype_src(intr->src[0]);
820 stl->barrier_class = IR3_BARRIER_SHARED_W;
821 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
822
823 array_insert(b, b->keeps, stl);
824
825 /* Clear the bits in the writemask that we just wrote, then try
826 * again to see if more channels are left.
827 */
828 wrmask &= (15 << (first_component + length));
829 }
830 }
831
832 /*
833 * CS shared variable atomic intrinsics
834 *
835 * All of the shared variable atomic memory operations read a value from
836 * memory, compute a new value using one of the operations below, write the
837 * new value to memory, and return the original value read.
838 *
839 * All operations take 2 sources except CompSwap that takes 3. These
840 * sources represent:
841 *
842 * 0: The offset into the shared variable storage region that the atomic
843 * operation will operate on.
844 * 1: The data parameter to the atomic function (i.e. the value to add
845 * in shared_atomic_add, etc).
846 * 2: For CompSwap only: the second data parameter.
847 */
848 static struct ir3_instruction *
849 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
850 {
851 struct ir3_block *b = ctx->block;
852 struct ir3_instruction *atomic, *src0, *src1;
853 type_t type = TYPE_U32;
854
855 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
856 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
857
858 switch (intr->intrinsic) {
859 case nir_intrinsic_shared_atomic_add:
860 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
861 break;
862 case nir_intrinsic_shared_atomic_imin:
863 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
864 type = TYPE_S32;
865 break;
866 case nir_intrinsic_shared_atomic_umin:
867 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
868 break;
869 case nir_intrinsic_shared_atomic_imax:
870 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
871 type = TYPE_S32;
872 break;
873 case nir_intrinsic_shared_atomic_umax:
874 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
875 break;
876 case nir_intrinsic_shared_atomic_and:
877 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
878 break;
879 case nir_intrinsic_shared_atomic_or:
880 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
881 break;
882 case nir_intrinsic_shared_atomic_xor:
883 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
884 break;
885 case nir_intrinsic_shared_atomic_exchange:
886 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
887 break;
888 case nir_intrinsic_shared_atomic_comp_swap:
889 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
890 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
891 ir3_get_src(ctx, &intr->src[2])[0],
892 src1,
893 }, 2);
894 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
895 break;
896 default:
897 unreachable("boo");
898 }
899
900 atomic->cat6.iim_val = 1;
901 atomic->cat6.d = 1;
902 atomic->cat6.type = type;
903 atomic->barrier_class = IR3_BARRIER_SHARED_W;
904 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
905
906 /* even if nothing consume the result, we can't DCE the instruction: */
907 array_insert(b, b->keeps, atomic);
908
909 return atomic;
910 }
911
912 /* TODO handle actual indirect/dynamic case.. which is going to be weird
913 * to handle with the image_mapping table..
914 */
915 static struct ir3_instruction *
916 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
917 {
918 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
919 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
920 struct ir3_instruction *texture, *sampler;
921
922 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
923 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
924
925 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
926 sampler,
927 texture,
928 }, 2);
929 }
930
931 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
932 static void
933 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
934 struct ir3_instruction **dst)
935 {
936 struct ir3_block *b = ctx->block;
937 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
938 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
939 struct ir3_instruction *sam;
940 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
941 struct ir3_instruction *coords[4];
942 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
943 type_t type = ir3_get_image_type(var);
944
945 /* hmm, this seems a bit odd, but it is what blob does and (at least
946 * a5xx) just faults on bogus addresses otherwise:
947 */
948 if (flags & IR3_INSTR_3D) {
949 flags &= ~IR3_INSTR_3D;
950 flags |= IR3_INSTR_A;
951 }
952
953 for (unsigned i = 0; i < ncoords; i++)
954 coords[i] = src0[i];
955
956 if (ncoords == 1)
957 coords[ncoords++] = create_immed(b, 0);
958
959 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
960 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
961
962 sam->barrier_class = IR3_BARRIER_IMAGE_R;
963 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
964
965 ir3_split_dest(b, dst, sam, 0, 4);
966 }
967
968 static void
969 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
970 struct ir3_instruction **dst)
971 {
972 struct ir3_block *b = ctx->block;
973 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
974 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
975 struct ir3_instruction *sam, *lod;
976 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
977
978 lod = create_immed(b, 0);
979 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
980 samp_tex, lod, NULL);
981
982 /* Array size actually ends up in .w rather than .z. This doesn't
983 * matter for miplevel 0, but for higher mips the value in z is
984 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
985 * returned, which means that we have to add 1 to it for arrays for
986 * a3xx.
987 *
988 * Note use a temporary dst and then copy, since the size of the dst
989 * array that is passed in is based on nir's understanding of the
990 * result size, not the hardware's
991 */
992 struct ir3_instruction *tmp[4];
993
994 ir3_split_dest(b, tmp, sam, 0, 4);
995
996 /* get_size instruction returns size in bytes instead of texels
997 * for imageBuffer, so we need to divide it by the pixel size
998 * of the image format.
999 *
1000 * TODO: This is at least true on a5xx. Check other gens.
1001 */
1002 enum glsl_sampler_dim dim =
1003 glsl_get_sampler_dim(glsl_without_array(var->type));
1004 if (dim == GLSL_SAMPLER_DIM_BUF) {
1005 /* Since all the possible values the divisor can take are
1006 * power-of-two (4, 8, or 16), the division is implemented
1007 * as a shift-right.
1008 * During shader setup, the log2 of the image format's
1009 * bytes-per-pixel should have been emitted in 2nd slot of
1010 * image_dims. See ir3_shader::emit_image_dims().
1011 */
1012 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1013 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1014 const_state->image_dims.off[var->data.driver_location];
1015 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1016
1017 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1018 }
1019
1020 for (unsigned i = 0; i < ncoords; i++)
1021 dst[i] = tmp[i];
1022
1023 if (flags & IR3_INSTR_A) {
1024 if (ctx->compiler->levels_add_one) {
1025 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1026 } else {
1027 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1028 }
1029 }
1030 }
1031
1032 static void
1033 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1034 {
1035 struct ir3_block *b = ctx->block;
1036 struct ir3_instruction *barrier;
1037
1038 switch (intr->intrinsic) {
1039 case nir_intrinsic_barrier:
1040 barrier = ir3_BAR(b);
1041 barrier->cat7.g = true;
1042 barrier->cat7.l = true;
1043 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1044 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1045 break;
1046 case nir_intrinsic_memory_barrier:
1047 barrier = ir3_FENCE(b);
1048 barrier->cat7.g = true;
1049 barrier->cat7.r = true;
1050 barrier->cat7.w = true;
1051 barrier->cat7.l = true;
1052 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1053 IR3_BARRIER_BUFFER_W;
1054 barrier->barrier_conflict =
1055 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1056 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1057 break;
1058 case nir_intrinsic_memory_barrier_atomic_counter:
1059 case nir_intrinsic_memory_barrier_buffer:
1060 barrier = ir3_FENCE(b);
1061 barrier->cat7.g = true;
1062 barrier->cat7.r = true;
1063 barrier->cat7.w = true;
1064 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1065 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1066 IR3_BARRIER_BUFFER_W;
1067 break;
1068 case nir_intrinsic_memory_barrier_image:
1069 // TODO double check if this should have .g set
1070 barrier = ir3_FENCE(b);
1071 barrier->cat7.g = true;
1072 barrier->cat7.r = true;
1073 barrier->cat7.w = true;
1074 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1075 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1076 IR3_BARRIER_IMAGE_W;
1077 break;
1078 case nir_intrinsic_memory_barrier_shared:
1079 barrier = ir3_FENCE(b);
1080 barrier->cat7.g = true;
1081 barrier->cat7.l = true;
1082 barrier->cat7.r = true;
1083 barrier->cat7.w = true;
1084 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1085 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1086 IR3_BARRIER_SHARED_W;
1087 break;
1088 case nir_intrinsic_group_memory_barrier:
1089 barrier = ir3_FENCE(b);
1090 barrier->cat7.g = true;
1091 barrier->cat7.l = true;
1092 barrier->cat7.r = true;
1093 barrier->cat7.w = true;
1094 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1095 IR3_BARRIER_IMAGE_W |
1096 IR3_BARRIER_BUFFER_W;
1097 barrier->barrier_conflict =
1098 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1099 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1100 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1101 break;
1102 default:
1103 unreachable("boo");
1104 }
1105
1106 /* make sure barrier doesn't get DCE'd */
1107 array_insert(b, b->keeps, barrier);
1108 }
1109
1110 static void add_sysval_input_compmask(struct ir3_context *ctx,
1111 gl_system_value slot, unsigned compmask,
1112 struct ir3_instruction *instr)
1113 {
1114 struct ir3_shader_variant *so = ctx->so;
1115 unsigned r = regid(so->inputs_count, 0);
1116 unsigned n = so->inputs_count++;
1117
1118 so->inputs[n].sysval = true;
1119 so->inputs[n].slot = slot;
1120 so->inputs[n].compmask = compmask;
1121 so->inputs[n].regid = r;
1122 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1123 so->total_in++;
1124
1125 ctx->ir->ninputs = MAX2(ctx->ir->ninputs, r + 1);
1126 ctx->ir->inputs[r] = instr;
1127 }
1128
1129 static void add_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1130 struct ir3_instruction *instr)
1131 {
1132 add_sysval_input_compmask(ctx, slot, 0x1, instr);
1133 }
1134
1135 static struct ir3_instruction *
1136 get_barycentric_centroid(struct ir3_context *ctx)
1137 {
1138 if (!ctx->ij_centroid) {
1139 struct ir3_instruction *xy[2];
1140 struct ir3_instruction *ij;
1141
1142 ij = create_input_compmask(ctx, 0, 0x3);
1143 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1144
1145 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1146
1147 add_sysval_input_compmask(ctx,
1148 SYSTEM_VALUE_BARYCENTRIC_CENTROID,
1149 0x3, ij);
1150 }
1151
1152 return ctx->ij_centroid;
1153 }
1154
1155 static struct ir3_instruction *
1156 get_barycentric_sample(struct ir3_context *ctx)
1157 {
1158 if (!ctx->ij_sample) {
1159 struct ir3_instruction *xy[2];
1160 struct ir3_instruction *ij;
1161
1162 ij = create_input_compmask(ctx, 0, 0x3);
1163 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1164
1165 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1166
1167 add_sysval_input_compmask(ctx,
1168 SYSTEM_VALUE_BARYCENTRIC_SAMPLE,
1169 0x3, ij);
1170 }
1171
1172 return ctx->ij_sample;
1173 }
1174
1175 static struct ir3_instruction *
1176 get_barycentric_pixel(struct ir3_context *ctx)
1177 {
1178 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1179 * this to create ij_pixel only on demand:
1180 */
1181 return ctx->ij_pixel;
1182 }
1183
1184 static struct ir3_instruction *
1185 get_frag_coord(struct ir3_context *ctx)
1186 {
1187 if (!ctx->frag_coord) {
1188 struct ir3_block *b = ctx->block;
1189 struct ir3_instruction *xyzw[4];
1190 struct ir3_instruction *hw_frag_coord;
1191
1192 hw_frag_coord = create_input_compmask(ctx, 0, 0xf);
1193 ir3_split_dest(ctx->block, xyzw, hw_frag_coord, 0, 4);
1194
1195 /* for frag_coord.xy, we get unsigned values.. we need
1196 * to subtract (integer) 8 and divide by 16 (right-
1197 * shift by 4) then convert to float:
1198 *
1199 * sub.s tmp, src, 8
1200 * shr.b tmp, tmp, 4
1201 * mov.u32f32 dst, tmp
1202 *
1203 */
1204 for (int i = 0; i < 2; i++) {
1205 xyzw[i] = ir3_SUB_S(b, xyzw[i], 0,
1206 create_immed(b, 8), 0);
1207 xyzw[i] = ir3_SHR_B(b, xyzw[i], 0,
1208 create_immed(b, 4), 0);
1209 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1210 }
1211
1212 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1213
1214 add_sysval_input_compmask(ctx,
1215 SYSTEM_VALUE_FRAG_COORD,
1216 0xf, hw_frag_coord);
1217
1218 ctx->so->frag_coord = true;
1219 }
1220
1221 return ctx->frag_coord;
1222 }
1223
1224 static void
1225 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1226 {
1227 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1228 struct ir3_instruction **dst;
1229 struct ir3_instruction * const *src;
1230 struct ir3_block *b = ctx->block;
1231 int idx, comp;
1232
1233 if (info->has_dest) {
1234 unsigned n = nir_intrinsic_dest_components(intr);
1235 dst = ir3_get_dst(ctx, &intr->dest, n);
1236 } else {
1237 dst = NULL;
1238 }
1239
1240 switch (intr->intrinsic) {
1241 case nir_intrinsic_load_uniform:
1242 idx = nir_intrinsic_base(intr);
1243 if (nir_src_is_const(intr->src[0])) {
1244 idx += nir_src_as_uint(intr->src[0]);
1245 for (int i = 0; i < intr->num_components; i++) {
1246 dst[i] = create_uniform(b, idx + i);
1247 }
1248 } else {
1249 src = ir3_get_src(ctx, &intr->src[0]);
1250 for (int i = 0; i < intr->num_components; i++) {
1251 dst[i] = create_uniform_indirect(b, idx + i,
1252 ir3_get_addr(ctx, src[0], 1));
1253 }
1254 /* NOTE: if relative addressing is used, we set
1255 * constlen in the compiler (to worst-case value)
1256 * since we don't know in the assembler what the max
1257 * addr reg value can be:
1258 */
1259 ctx->so->constlen = ctx->s->num_uniforms;
1260 }
1261 break;
1262 case nir_intrinsic_load_ubo:
1263 emit_intrinsic_load_ubo(ctx, intr, dst);
1264 break;
1265 case nir_intrinsic_load_frag_coord:
1266 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1267 break;
1268 case nir_intrinsic_load_sample_pos_from_id: {
1269 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1270 * but that doesn't seem necessary.
1271 */
1272 struct ir3_instruction *offset =
1273 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1274 offset->regs[0]->wrmask = 0x3;
1275 offset->cat5.type = TYPE_F32;
1276
1277 ir3_split_dest(b, dst, offset, 0, 2);
1278
1279 break;
1280 }
1281 case nir_intrinsic_load_size_ir3:
1282 if (!ctx->ij_size) {
1283 ctx->ij_size = create_input(ctx, 0);
1284
1285 add_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SIZE,
1286 ctx->ij_size);
1287 }
1288 dst[0] = ctx->ij_size;
1289 break;
1290 case nir_intrinsic_load_barycentric_centroid:
1291 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1292 break;
1293 case nir_intrinsic_load_barycentric_sample:
1294 if (ctx->so->key.msaa) {
1295 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1296 } else {
1297 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1298 }
1299 break;
1300 case nir_intrinsic_load_barycentric_pixel:
1301 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1302 break;
1303 case nir_intrinsic_load_interpolated_input:
1304 idx = nir_intrinsic_base(intr);
1305 comp = nir_intrinsic_component(intr);
1306 src = ir3_get_src(ctx, &intr->src[0]);
1307 if (nir_src_is_const(intr->src[1])) {
1308 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1309 idx += nir_src_as_uint(intr->src[1]);
1310 for (int i = 0; i < intr->num_components; i++) {
1311 unsigned inloc = idx * 4 + i + comp;
1312 if (ctx->so->inputs[idx].bary &&
1313 !ctx->so->inputs[idx].use_ldlv) {
1314 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1315 } else {
1316 /* for non-varyings use the pre-setup input, since
1317 * that is easier than mapping things back to a
1318 * nir_variable to figure out what it is.
1319 */
1320 dst[i] = ctx->ir->inputs[inloc];
1321 }
1322 }
1323 } else {
1324 ir3_context_error(ctx, "unhandled");
1325 }
1326 break;
1327 case nir_intrinsic_load_input:
1328 idx = nir_intrinsic_base(intr);
1329 comp = nir_intrinsic_component(intr);
1330 if (nir_src_is_const(intr->src[0])) {
1331 idx += nir_src_as_uint(intr->src[0]);
1332 for (int i = 0; i < intr->num_components; i++) {
1333 unsigned n = idx * 4 + i + comp;
1334 dst[i] = ctx->ir->inputs[n];
1335 compile_assert(ctx, ctx->ir->inputs[n]);
1336 }
1337 } else {
1338 src = ir3_get_src(ctx, &intr->src[0]);
1339 struct ir3_instruction *collect =
1340 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ir->ninputs);
1341 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1342 for (int i = 0; i < intr->num_components; i++) {
1343 unsigned n = idx * 4 + i + comp;
1344 dst[i] = create_indirect_load(ctx, ctx->ir->ninputs,
1345 n, addr, collect);
1346 }
1347 }
1348 break;
1349 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1350 * pass and replaced by an ir3-specifc version that adds the
1351 * dword-offset in the last source.
1352 */
1353 case nir_intrinsic_load_ssbo_ir3:
1354 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1355 break;
1356 case nir_intrinsic_store_ssbo_ir3:
1357 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1358 !ctx->s->info.fs.early_fragment_tests)
1359 ctx->so->no_earlyz = true;
1360 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1361 break;
1362 case nir_intrinsic_get_buffer_size:
1363 emit_intrinsic_ssbo_size(ctx, intr, dst);
1364 break;
1365 case nir_intrinsic_ssbo_atomic_add_ir3:
1366 case nir_intrinsic_ssbo_atomic_imin_ir3:
1367 case nir_intrinsic_ssbo_atomic_umin_ir3:
1368 case nir_intrinsic_ssbo_atomic_imax_ir3:
1369 case nir_intrinsic_ssbo_atomic_umax_ir3:
1370 case nir_intrinsic_ssbo_atomic_and_ir3:
1371 case nir_intrinsic_ssbo_atomic_or_ir3:
1372 case nir_intrinsic_ssbo_atomic_xor_ir3:
1373 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1374 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1375 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1376 !ctx->s->info.fs.early_fragment_tests)
1377 ctx->so->no_earlyz = true;
1378 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1379 break;
1380 case nir_intrinsic_load_shared:
1381 emit_intrinsic_load_shared(ctx, intr, dst);
1382 break;
1383 case nir_intrinsic_store_shared:
1384 emit_intrinsic_store_shared(ctx, intr);
1385 break;
1386 case nir_intrinsic_shared_atomic_add:
1387 case nir_intrinsic_shared_atomic_imin:
1388 case nir_intrinsic_shared_atomic_umin:
1389 case nir_intrinsic_shared_atomic_imax:
1390 case nir_intrinsic_shared_atomic_umax:
1391 case nir_intrinsic_shared_atomic_and:
1392 case nir_intrinsic_shared_atomic_or:
1393 case nir_intrinsic_shared_atomic_xor:
1394 case nir_intrinsic_shared_atomic_exchange:
1395 case nir_intrinsic_shared_atomic_comp_swap:
1396 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1397 break;
1398 case nir_intrinsic_image_deref_load:
1399 emit_intrinsic_load_image(ctx, intr, dst);
1400 break;
1401 case nir_intrinsic_image_deref_store:
1402 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1403 !ctx->s->info.fs.early_fragment_tests)
1404 ctx->so->no_earlyz = true;
1405 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1406 break;
1407 case nir_intrinsic_image_deref_size:
1408 emit_intrinsic_image_size(ctx, intr, dst);
1409 break;
1410 case nir_intrinsic_image_deref_atomic_add:
1411 case nir_intrinsic_image_deref_atomic_min:
1412 case nir_intrinsic_image_deref_atomic_max:
1413 case nir_intrinsic_image_deref_atomic_and:
1414 case nir_intrinsic_image_deref_atomic_or:
1415 case nir_intrinsic_image_deref_atomic_xor:
1416 case nir_intrinsic_image_deref_atomic_exchange:
1417 case nir_intrinsic_image_deref_atomic_comp_swap:
1418 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1419 !ctx->s->info.fs.early_fragment_tests)
1420 ctx->so->no_earlyz = true;
1421 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1422 break;
1423 case nir_intrinsic_barrier:
1424 case nir_intrinsic_memory_barrier:
1425 case nir_intrinsic_group_memory_barrier:
1426 case nir_intrinsic_memory_barrier_atomic_counter:
1427 case nir_intrinsic_memory_barrier_buffer:
1428 case nir_intrinsic_memory_barrier_image:
1429 case nir_intrinsic_memory_barrier_shared:
1430 emit_intrinsic_barrier(ctx, intr);
1431 /* note that blk ptr no longer valid, make that obvious: */
1432 b = NULL;
1433 break;
1434 case nir_intrinsic_store_output:
1435 idx = nir_intrinsic_base(intr);
1436 comp = nir_intrinsic_component(intr);
1437 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1438 idx += nir_src_as_uint(intr->src[1]);
1439
1440 src = ir3_get_src(ctx, &intr->src[0]);
1441 for (int i = 0; i < intr->num_components; i++) {
1442 unsigned n = idx * 4 + i + comp;
1443 ctx->ir->outputs[n] = src[i];
1444 }
1445 break;
1446 case nir_intrinsic_load_base_vertex:
1447 case nir_intrinsic_load_first_vertex:
1448 if (!ctx->basevertex) {
1449 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1450 add_sysval_input(ctx, SYSTEM_VALUE_FIRST_VERTEX, ctx->basevertex);
1451 }
1452 dst[0] = ctx->basevertex;
1453 break;
1454 case nir_intrinsic_load_vertex_id_zero_base:
1455 case nir_intrinsic_load_vertex_id:
1456 if (!ctx->vertex_id) {
1457 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1458 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1459 ctx->vertex_id = create_input(ctx, 0);
1460 add_sysval_input(ctx, sv, ctx->vertex_id);
1461 }
1462 dst[0] = ctx->vertex_id;
1463 break;
1464 case nir_intrinsic_load_instance_id:
1465 if (!ctx->instance_id) {
1466 ctx->instance_id = create_input(ctx, 0);
1467 add_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID,
1468 ctx->instance_id);
1469 }
1470 dst[0] = ctx->instance_id;
1471 break;
1472 case nir_intrinsic_load_sample_id:
1473 ctx->so->per_samp = true;
1474 /* fall-thru */
1475 case nir_intrinsic_load_sample_id_no_per_sample:
1476 if (!ctx->samp_id) {
1477 ctx->samp_id = create_input(ctx, 0);
1478 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1479 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID,
1480 ctx->samp_id);
1481 }
1482 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1483 break;
1484 case nir_intrinsic_load_sample_mask_in:
1485 if (!ctx->samp_mask_in) {
1486 ctx->samp_mask_in = create_input(ctx, 0);
1487 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN,
1488 ctx->samp_mask_in);
1489 }
1490 dst[0] = ctx->samp_mask_in;
1491 break;
1492 case nir_intrinsic_load_user_clip_plane:
1493 idx = nir_intrinsic_ucp_id(intr);
1494 for (int i = 0; i < intr->num_components; i++) {
1495 unsigned n = idx * 4 + i;
1496 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1497 }
1498 break;
1499 case nir_intrinsic_load_front_face:
1500 if (!ctx->frag_face) {
1501 ctx->so->frag_face = true;
1502 ctx->frag_face = create_input(ctx, 0);
1503 add_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, ctx->frag_face);
1504 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1505 }
1506 /* for fragface, we get -1 for back and 0 for front. However this is
1507 * the inverse of what nir expects (where ~0 is true).
1508 */
1509 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1510 dst[0] = ir3_NOT_B(b, dst[0], 0);
1511 break;
1512 case nir_intrinsic_load_local_invocation_id:
1513 if (!ctx->local_invocation_id) {
1514 ctx->local_invocation_id = create_input_compmask(ctx, 0, 0x7);
1515 add_sysval_input_compmask(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID,
1516 0x7, ctx->local_invocation_id);
1517 }
1518 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1519 break;
1520 case nir_intrinsic_load_work_group_id:
1521 if (!ctx->work_group_id) {
1522 ctx->work_group_id = create_input_compmask(ctx, 0, 0x7);
1523 add_sysval_input_compmask(ctx, SYSTEM_VALUE_WORK_GROUP_ID,
1524 0x7, ctx->work_group_id);
1525 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1526 }
1527 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1528 break;
1529 case nir_intrinsic_load_num_work_groups:
1530 for (int i = 0; i < intr->num_components; i++) {
1531 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1532 }
1533 break;
1534 case nir_intrinsic_load_local_group_size:
1535 for (int i = 0; i < intr->num_components; i++) {
1536 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1537 }
1538 break;
1539 case nir_intrinsic_discard_if:
1540 case nir_intrinsic_discard: {
1541 struct ir3_instruction *cond, *kill;
1542
1543 if (intr->intrinsic == nir_intrinsic_discard_if) {
1544 /* conditional discard: */
1545 src = ir3_get_src(ctx, &intr->src[0]);
1546 cond = ir3_b2n(b, src[0]);
1547 } else {
1548 /* unconditional discard: */
1549 cond = create_immed(b, 1);
1550 }
1551
1552 /* NOTE: only cmps.*.* can write p0.x: */
1553 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1554 cond->cat2.condition = IR3_COND_NE;
1555
1556 /* condition always goes in predicate register: */
1557 cond->regs[0]->num = regid(REG_P0, 0);
1558
1559 kill = ir3_KILL(b, cond, 0);
1560 array_insert(ctx->ir, ctx->ir->predicates, kill);
1561
1562 array_insert(b, b->keeps, kill);
1563 ctx->so->no_earlyz = true;
1564
1565 break;
1566 }
1567 default:
1568 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1569 nir_intrinsic_infos[intr->intrinsic].name);
1570 break;
1571 }
1572
1573 if (info->has_dest)
1574 ir3_put_dst(ctx, &intr->dest);
1575 }
1576
1577 static void
1578 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1579 {
1580 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1581 instr->def.num_components);
1582 type_t type = (instr->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1583
1584 for (int i = 0; i < instr->def.num_components; i++)
1585 dst[i] = create_immed_typed(ctx->block, instr->value[i].u32, type);
1586 }
1587
1588 static void
1589 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1590 {
1591 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1592 undef->def.num_components);
1593 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1594
1595 /* backend doesn't want undefined instructions, so just plug
1596 * in 0.0..
1597 */
1598 for (int i = 0; i < undef->def.num_components; i++)
1599 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1600 }
1601
1602 /*
1603 * texture fetch/sample instructions:
1604 */
1605
1606 static void
1607 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1608 {
1609 unsigned coords, flags = 0;
1610
1611 /* note: would use tex->coord_components.. except txs.. also,
1612 * since array index goes after shadow ref, we don't want to
1613 * count it:
1614 */
1615 switch (tex->sampler_dim) {
1616 case GLSL_SAMPLER_DIM_1D:
1617 case GLSL_SAMPLER_DIM_BUF:
1618 coords = 1;
1619 break;
1620 case GLSL_SAMPLER_DIM_2D:
1621 case GLSL_SAMPLER_DIM_RECT:
1622 case GLSL_SAMPLER_DIM_EXTERNAL:
1623 case GLSL_SAMPLER_DIM_MS:
1624 coords = 2;
1625 break;
1626 case GLSL_SAMPLER_DIM_3D:
1627 case GLSL_SAMPLER_DIM_CUBE:
1628 coords = 3;
1629 flags |= IR3_INSTR_3D;
1630 break;
1631 default:
1632 unreachable("bad sampler_dim");
1633 }
1634
1635 if (tex->is_shadow && tex->op != nir_texop_lod)
1636 flags |= IR3_INSTR_S;
1637
1638 if (tex->is_array && tex->op != nir_texop_lod)
1639 flags |= IR3_INSTR_A;
1640
1641 *flagsp = flags;
1642 *coordsp = coords;
1643 }
1644
1645 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1646 * or immediate (in which case it will get lowered later to a non .s2en
1647 * version of the tex instruction which encode tex/samp as immediates:
1648 */
1649 static struct ir3_instruction *
1650 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1651 {
1652 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1653 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1654 struct ir3_instruction *texture, *sampler;
1655
1656 if (texture_idx >= 0) {
1657 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1658 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1659 } else {
1660 /* TODO what to do for dynamic case? I guess we only need the
1661 * max index for astc srgb workaround so maybe not a problem
1662 * to worry about if we don't enable indirect samplers for
1663 * a4xx?
1664 */
1665 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1666 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1667 }
1668
1669 if (sampler_idx >= 0) {
1670 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1671 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1672 } else {
1673 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1674 }
1675
1676 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1677 sampler,
1678 texture,
1679 }, 2);
1680 }
1681
1682 static void
1683 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1684 {
1685 struct ir3_block *b = ctx->block;
1686 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1687 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1688 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1689 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1690 unsigned i, coords, flags, ncomp;
1691 unsigned nsrc0 = 0, nsrc1 = 0;
1692 type_t type;
1693 opc_t opc = 0;
1694
1695 ncomp = nir_dest_num_components(tex->dest);
1696
1697 coord = off = ddx = ddy = NULL;
1698 lod = proj = compare = sample_index = NULL;
1699
1700 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1701
1702 for (unsigned i = 0; i < tex->num_srcs; i++) {
1703 switch (tex->src[i].src_type) {
1704 case nir_tex_src_coord:
1705 coord = ir3_get_src(ctx, &tex->src[i].src);
1706 break;
1707 case nir_tex_src_bias:
1708 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1709 has_bias = true;
1710 break;
1711 case nir_tex_src_lod:
1712 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1713 has_lod = true;
1714 break;
1715 case nir_tex_src_comparator: /* shadow comparator */
1716 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1717 break;
1718 case nir_tex_src_projector:
1719 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1720 has_proj = true;
1721 break;
1722 case nir_tex_src_offset:
1723 off = ir3_get_src(ctx, &tex->src[i].src);
1724 has_off = true;
1725 break;
1726 case nir_tex_src_ddx:
1727 ddx = ir3_get_src(ctx, &tex->src[i].src);
1728 break;
1729 case nir_tex_src_ddy:
1730 ddy = ir3_get_src(ctx, &tex->src[i].src);
1731 break;
1732 case nir_tex_src_ms_index:
1733 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
1734 break;
1735 case nir_tex_src_texture_offset:
1736 case nir_tex_src_sampler_offset:
1737 /* handled in get_tex_samp_src() */
1738 break;
1739 default:
1740 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
1741 tex->src[i].src_type);
1742 return;
1743 }
1744 }
1745
1746 switch (tex->op) {
1747 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
1748 case nir_texop_txb: opc = OPC_SAMB; break;
1749 case nir_texop_txl: opc = OPC_SAML; break;
1750 case nir_texop_txd: opc = OPC_SAMGQ; break;
1751 case nir_texop_txf: opc = OPC_ISAML; break;
1752 case nir_texop_lod: opc = OPC_GETLOD; break;
1753 case nir_texop_tg4:
1754 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1755 * what blob does, seems gather is broken?), and a3xx did
1756 * not support it (but probably could also emulate).
1757 */
1758 switch (tex->component) {
1759 case 0: opc = OPC_GATHER4R; break;
1760 case 1: opc = OPC_GATHER4G; break;
1761 case 2: opc = OPC_GATHER4B; break;
1762 case 3: opc = OPC_GATHER4A; break;
1763 }
1764 break;
1765 case nir_texop_txf_ms_fb:
1766 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
1767 default:
1768 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
1769 return;
1770 }
1771
1772 tex_info(tex, &flags, &coords);
1773
1774 /*
1775 * lay out the first argument in the proper order:
1776 * - actual coordinates first
1777 * - shadow reference
1778 * - array index
1779 * - projection w
1780 * - starting at offset 4, dpdx.xy, dpdy.xy
1781 *
1782 * bias/lod go into the second arg
1783 */
1784
1785 /* insert tex coords: */
1786 for (i = 0; i < coords; i++)
1787 src0[i] = coord[i];
1788
1789 nsrc0 = i;
1790
1791 /* scale up integer coords for TXF based on the LOD */
1792 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
1793 assert(has_lod);
1794 for (i = 0; i < coords; i++)
1795 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
1796 }
1797
1798 if (coords == 1) {
1799 /* hw doesn't do 1d, so we treat it as 2d with
1800 * height of 1, and patch up the y coord.
1801 */
1802 if (is_isam(opc)) {
1803 src0[nsrc0++] = create_immed(b, 0);
1804 } else {
1805 src0[nsrc0++] = create_immed(b, fui(0.5));
1806 }
1807 }
1808
1809 if (tex->is_shadow && tex->op != nir_texop_lod)
1810 src0[nsrc0++] = compare;
1811
1812 if (tex->is_array && tex->op != nir_texop_lod) {
1813 struct ir3_instruction *idx = coord[coords];
1814
1815 /* the array coord for cube arrays needs 0.5 added to it */
1816 if (ctx->compiler->array_index_add_half && !is_isam(opc))
1817 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
1818
1819 src0[nsrc0++] = idx;
1820 }
1821
1822 if (has_proj) {
1823 src0[nsrc0++] = proj;
1824 flags |= IR3_INSTR_P;
1825 }
1826
1827 /* pad to 4, then ddx/ddy: */
1828 if (tex->op == nir_texop_txd) {
1829 while (nsrc0 < 4)
1830 src0[nsrc0++] = create_immed(b, fui(0.0));
1831 for (i = 0; i < coords; i++)
1832 src0[nsrc0++] = ddx[i];
1833 if (coords < 2)
1834 src0[nsrc0++] = create_immed(b, fui(0.0));
1835 for (i = 0; i < coords; i++)
1836 src0[nsrc0++] = ddy[i];
1837 if (coords < 2)
1838 src0[nsrc0++] = create_immed(b, fui(0.0));
1839 }
1840
1841 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
1842 * with scaled x coord according to requested sample:
1843 */
1844 if (opc == OPC_ISAMM) {
1845 if (ctx->compiler->txf_ms_with_isaml) {
1846 /* the samples are laid out in x dimension as
1847 * 0 1 2 3
1848 * x_ms = (x << ms) + sample_index;
1849 */
1850 struct ir3_instruction *ms;
1851 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
1852
1853 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
1854 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
1855
1856 opc = OPC_ISAML;
1857 } else {
1858 src0[nsrc0++] = sample_index;
1859 }
1860 }
1861
1862 /*
1863 * second argument (if applicable):
1864 * - offsets
1865 * - lod
1866 * - bias
1867 */
1868 if (has_off | has_lod | has_bias) {
1869 if (has_off) {
1870 unsigned off_coords = coords;
1871 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
1872 off_coords--;
1873 for (i = 0; i < off_coords; i++)
1874 src1[nsrc1++] = off[i];
1875 if (off_coords < 2)
1876 src1[nsrc1++] = create_immed(b, fui(0.0));
1877 flags |= IR3_INSTR_O;
1878 }
1879
1880 if (has_lod | has_bias)
1881 src1[nsrc1++] = lod;
1882 }
1883
1884 switch (tex->dest_type) {
1885 case nir_type_invalid:
1886 case nir_type_float:
1887 type = TYPE_F32;
1888 break;
1889 case nir_type_int:
1890 type = TYPE_S32;
1891 break;
1892 case nir_type_uint:
1893 case nir_type_bool:
1894 type = TYPE_U32;
1895 break;
1896 default:
1897 unreachable("bad dest_type");
1898 }
1899
1900 if (opc == OPC_GETLOD)
1901 type = TYPE_U32;
1902
1903 struct ir3_instruction *samp_tex;
1904
1905 if (tex->op == nir_texop_txf_ms_fb) {
1906 /* only expect a single txf_ms_fb per shader: */
1907 compile_assert(ctx, !ctx->so->fb_read);
1908 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
1909
1910 ctx->so->fb_read = true;
1911 samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1912 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
1913 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
1914 }, 2);
1915
1916 ctx->so->num_samp++;
1917 } else {
1918 samp_tex = get_tex_samp_tex_src(ctx, tex);
1919 }
1920
1921 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
1922 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
1923
1924 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
1925 samp_tex, col0, col1);
1926
1927 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
1928 /* only need first 3 components: */
1929 sam->regs[0]->wrmask = 0x7;
1930 ir3_split_dest(b, dst, sam, 0, 3);
1931
1932 /* we need to sample the alpha separately with a non-ASTC
1933 * texture state:
1934 */
1935 sam = ir3_SAM(b, opc, type, 0b1000, flags,
1936 samp_tex, col0, col1);
1937
1938 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
1939
1940 /* fixup .w component: */
1941 ir3_split_dest(b, &dst[3], sam, 3, 1);
1942 } else {
1943 /* normal (non-workaround) case: */
1944 ir3_split_dest(b, dst, sam, 0, ncomp);
1945 }
1946
1947 /* GETLOD returns results in 4.8 fixed point */
1948 if (opc == OPC_GETLOD) {
1949 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
1950
1951 compile_assert(ctx, tex->dest_type == nir_type_float);
1952 for (i = 0; i < 2; i++) {
1953 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_U32, TYPE_F32), 0,
1954 factor, 0);
1955 }
1956 }
1957
1958 ir3_put_dst(ctx, &tex->dest);
1959 }
1960
1961 static void
1962 emit_tex_query_levels(struct ir3_context *ctx, nir_tex_instr *tex)
1963 {
1964 struct ir3_block *b = ctx->block;
1965 struct ir3_instruction **dst, *sam;
1966
1967 dst = ir3_get_dst(ctx, &tex->dest, 1);
1968
1969 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, 0b0100, 0,
1970 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
1971
1972 /* even though there is only one component, since it ends
1973 * up in .z rather than .x, we need a split_dest()
1974 */
1975 ir3_split_dest(b, dst, sam, 0, 3);
1976
1977 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
1978 * the value in TEX_CONST_0 is zero-based.
1979 */
1980 if (ctx->compiler->levels_add_one)
1981 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
1982
1983 ir3_put_dst(ctx, &tex->dest);
1984 }
1985
1986 static void
1987 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
1988 {
1989 struct ir3_block *b = ctx->block;
1990 struct ir3_instruction **dst, *sam;
1991 struct ir3_instruction *lod;
1992 unsigned flags, coords;
1993
1994 tex_info(tex, &flags, &coords);
1995
1996 /* Actually we want the number of dimensions, not coordinates. This
1997 * distinction only matters for cubes.
1998 */
1999 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2000 coords = 2;
2001
2002 dst = ir3_get_dst(ctx, &tex->dest, 4);
2003
2004 compile_assert(ctx, tex->num_srcs == 1);
2005 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2006
2007 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2008
2009 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
2010 get_tex_samp_tex_src(ctx, tex), lod, NULL);
2011
2012 ir3_split_dest(b, dst, sam, 0, 4);
2013
2014 /* Array size actually ends up in .w rather than .z. This doesn't
2015 * matter for miplevel 0, but for higher mips the value in z is
2016 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2017 * returned, which means that we have to add 1 to it for arrays.
2018 */
2019 if (tex->is_array) {
2020 if (ctx->compiler->levels_add_one) {
2021 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2022 } else {
2023 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2024 }
2025 }
2026
2027 ir3_put_dst(ctx, &tex->dest);
2028 }
2029
2030 static void
2031 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2032 {
2033 switch (jump->type) {
2034 case nir_jump_break:
2035 case nir_jump_continue:
2036 case nir_jump_return:
2037 /* I *think* we can simply just ignore this, and use the
2038 * successor block link to figure out where we need to
2039 * jump to for break/continue
2040 */
2041 break;
2042 default:
2043 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2044 break;
2045 }
2046 }
2047
2048 static void
2049 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2050 {
2051 switch (instr->type) {
2052 case nir_instr_type_alu:
2053 emit_alu(ctx, nir_instr_as_alu(instr));
2054 break;
2055 case nir_instr_type_deref:
2056 /* ignored, handled as part of the intrinsic they are src to */
2057 break;
2058 case nir_instr_type_intrinsic:
2059 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2060 break;
2061 case nir_instr_type_load_const:
2062 emit_load_const(ctx, nir_instr_as_load_const(instr));
2063 break;
2064 case nir_instr_type_ssa_undef:
2065 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2066 break;
2067 case nir_instr_type_tex: {
2068 nir_tex_instr *tex = nir_instr_as_tex(instr);
2069 /* couple tex instructions get special-cased:
2070 */
2071 switch (tex->op) {
2072 case nir_texop_txs:
2073 emit_tex_txs(ctx, tex);
2074 break;
2075 case nir_texop_query_levels:
2076 emit_tex_query_levels(ctx, tex);
2077 break;
2078 default:
2079 emit_tex(ctx, tex);
2080 break;
2081 }
2082 break;
2083 }
2084 case nir_instr_type_jump:
2085 emit_jump(ctx, nir_instr_as_jump(instr));
2086 break;
2087 case nir_instr_type_phi:
2088 /* we have converted phi webs to regs in NIR by now */
2089 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2090 break;
2091 case nir_instr_type_call:
2092 case nir_instr_type_parallel_copy:
2093 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2094 break;
2095 }
2096 }
2097
2098 static struct ir3_block *
2099 get_block(struct ir3_context *ctx, const nir_block *nblock)
2100 {
2101 struct ir3_block *block;
2102 struct hash_entry *hentry;
2103 unsigned i;
2104
2105 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2106 if (hentry)
2107 return hentry->data;
2108
2109 block = ir3_block_create(ctx->ir);
2110 block->nblock = nblock;
2111 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2112
2113 block->predecessors_count = nblock->predecessors->entries;
2114 block->predecessors = ralloc_array_size(block,
2115 sizeof(block->predecessors[0]), block->predecessors_count);
2116 i = 0;
2117 set_foreach(nblock->predecessors, sentry) {
2118 block->predecessors[i++] = get_block(ctx, sentry->key);
2119 }
2120
2121 return block;
2122 }
2123
2124 static void
2125 emit_block(struct ir3_context *ctx, nir_block *nblock)
2126 {
2127 struct ir3_block *block = get_block(ctx, nblock);
2128
2129 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2130 if (nblock->successors[i]) {
2131 block->successors[i] =
2132 get_block(ctx, nblock->successors[i]);
2133 }
2134 }
2135
2136 ctx->block = block;
2137 list_addtail(&block->node, &ctx->ir->block_list);
2138
2139 /* re-emit addr register in each block if needed: */
2140 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2141 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2142 ctx->addr_ht[i] = NULL;
2143 }
2144
2145 nir_foreach_instr(instr, nblock) {
2146 ctx->cur_instr = instr;
2147 emit_instr(ctx, instr);
2148 ctx->cur_instr = NULL;
2149 if (ctx->error)
2150 return;
2151 }
2152 }
2153
2154 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2155
2156 static void
2157 emit_if(struct ir3_context *ctx, nir_if *nif)
2158 {
2159 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2160
2161 ctx->block->condition =
2162 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2163
2164 emit_cf_list(ctx, &nif->then_list);
2165 emit_cf_list(ctx, &nif->else_list);
2166 }
2167
2168 static void
2169 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2170 {
2171 emit_cf_list(ctx, &nloop->body);
2172 ctx->so->loops++;
2173 }
2174
2175 static void
2176 stack_push(struct ir3_context *ctx)
2177 {
2178 ctx->stack++;
2179 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2180 }
2181
2182 static void
2183 stack_pop(struct ir3_context *ctx)
2184 {
2185 compile_assert(ctx, ctx->stack > 0);
2186 ctx->stack--;
2187 }
2188
2189 static void
2190 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2191 {
2192 foreach_list_typed(nir_cf_node, node, node, list) {
2193 switch (node->type) {
2194 case nir_cf_node_block:
2195 emit_block(ctx, nir_cf_node_as_block(node));
2196 break;
2197 case nir_cf_node_if:
2198 stack_push(ctx);
2199 emit_if(ctx, nir_cf_node_as_if(node));
2200 stack_pop(ctx);
2201 break;
2202 case nir_cf_node_loop:
2203 stack_push(ctx);
2204 emit_loop(ctx, nir_cf_node_as_loop(node));
2205 stack_pop(ctx);
2206 break;
2207 case nir_cf_node_function:
2208 ir3_context_error(ctx, "TODO\n");
2209 break;
2210 }
2211 }
2212 }
2213
2214 /* emit stream-out code. At this point, the current block is the original
2215 * (nir) end block, and nir ensures that all flow control paths terminate
2216 * into the end block. We re-purpose the original end block to generate
2217 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2218 * block holding stream-out write instructions, followed by the new end
2219 * block:
2220 *
2221 * blockOrigEnd {
2222 * p0.x = (vtxcnt < maxvtxcnt)
2223 * // succs: blockStreamOut, blockNewEnd
2224 * }
2225 * blockStreamOut {
2226 * ... stream-out instructions ...
2227 * // succs: blockNewEnd
2228 * }
2229 * blockNewEnd {
2230 * }
2231 */
2232 static void
2233 emit_stream_out(struct ir3_context *ctx)
2234 {
2235 struct ir3 *ir = ctx->ir;
2236 struct ir3_stream_output_info *strmout =
2237 &ctx->so->shader->stream_output;
2238 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2239 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2240 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2241
2242 /* create vtxcnt input in input block at top of shader,
2243 * so that it is seen as live over the entire duration
2244 * of the shader:
2245 */
2246 vtxcnt = create_input(ctx, 0);
2247 add_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, vtxcnt);
2248
2249 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2250
2251 /* at this point, we are at the original 'end' block,
2252 * re-purpose this block to stream-out condition, then
2253 * append stream-out block and new-end block
2254 */
2255 orig_end_block = ctx->block;
2256
2257 // TODO these blocks need to update predecessors..
2258 // maybe w/ store_global intrinsic, we could do this
2259 // stuff in nir->nir pass
2260
2261 stream_out_block = ir3_block_create(ir);
2262 list_addtail(&stream_out_block->node, &ir->block_list);
2263
2264 new_end_block = ir3_block_create(ir);
2265 list_addtail(&new_end_block->node, &ir->block_list);
2266
2267 orig_end_block->successors[0] = stream_out_block;
2268 orig_end_block->successors[1] = new_end_block;
2269 stream_out_block->successors[0] = new_end_block;
2270
2271 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2272 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2273 cond->regs[0]->num = regid(REG_P0, 0);
2274 cond->cat2.condition = IR3_COND_LT;
2275
2276 /* condition goes on previous block to the conditional,
2277 * since it is used to pick which of the two successor
2278 * paths to take:
2279 */
2280 orig_end_block->condition = cond;
2281
2282 /* switch to stream_out_block to generate the stream-out
2283 * instructions:
2284 */
2285 ctx->block = stream_out_block;
2286
2287 /* Calculate base addresses based on vtxcnt. Instructions
2288 * generated for bases not used in following loop will be
2289 * stripped out in the backend.
2290 */
2291 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2292 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2293 unsigned stride = strmout->stride[i];
2294 struct ir3_instruction *base, *off;
2295
2296 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2297
2298 /* 24-bit should be enough: */
2299 off = ir3_MUL_U(ctx->block, vtxcnt, 0,
2300 create_immed(ctx->block, stride * 4), 0);
2301
2302 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2303 }
2304
2305 /* Generate the per-output store instructions: */
2306 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2307 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2308 unsigned c = j + strmout->output[i].start_component;
2309 struct ir3_instruction *base, *out, *stg;
2310
2311 base = bases[strmout->output[i].output_buffer];
2312 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2313
2314 stg = ir3_STG(ctx->block, base, 0, out, 0,
2315 create_immed(ctx->block, 1), 0);
2316 stg->cat6.type = TYPE_U32;
2317 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2318
2319 array_insert(ctx->block, ctx->block->keeps, stg);
2320 }
2321 }
2322
2323 /* and finally switch to the new_end_block: */
2324 ctx->block = new_end_block;
2325 }
2326
2327 static void
2328 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2329 {
2330 nir_metadata_require(impl, nir_metadata_block_index);
2331
2332 compile_assert(ctx, ctx->stack == 0);
2333
2334 emit_cf_list(ctx, &impl->body);
2335 emit_block(ctx, impl->end_block);
2336
2337 compile_assert(ctx, ctx->stack == 0);
2338
2339 /* at this point, we should have a single empty block,
2340 * into which we emit the 'end' instruction.
2341 */
2342 compile_assert(ctx, list_empty(&ctx->block->instr_list));
2343
2344 /* If stream-out (aka transform-feedback) enabled, emit the
2345 * stream-out instructions, followed by a new empty block (into
2346 * which the 'end' instruction lands).
2347 *
2348 * NOTE: it is done in this order, rather than inserting before
2349 * we emit end_block, because NIR guarantees that all blocks
2350 * flow into end_block, and that end_block has no successors.
2351 * So by re-purposing end_block as the first block of stream-
2352 * out, we guarantee that all exit paths flow into the stream-
2353 * out instructions.
2354 */
2355 if ((ctx->compiler->gpu_id < 500) &&
2356 (ctx->so->shader->stream_output.num_outputs > 0) &&
2357 !ctx->so->binning_pass) {
2358 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2359 emit_stream_out(ctx);
2360 }
2361
2362 ir3_END(ctx->block);
2363 }
2364
2365 static void
2366 setup_input(struct ir3_context *ctx, nir_variable *in)
2367 {
2368 struct ir3_shader_variant *so = ctx->so;
2369 unsigned ncomp = glsl_get_components(in->type);
2370 unsigned n = in->data.driver_location;
2371 unsigned frac = in->data.location_frac;
2372 unsigned slot = in->data.location;
2373
2374 /* skip unread inputs, we could end up with (for example), unsplit
2375 * matrix/etc inputs in the case they are not read, so just silently
2376 * skip these.
2377 */
2378 if (ncomp > 4)
2379 return;
2380
2381 so->inputs[n].slot = slot;
2382 so->inputs[n].compmask = (1 << (ncomp + frac)) - 1;
2383 so->inputs_count = MAX2(so->inputs_count, n + 1);
2384 so->inputs[n].interpolate = in->data.interpolation;
2385 so->inputs[n].ncomp = ncomp;
2386
2387 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2388
2389 /* if any varyings have 'sample' qualifer, that triggers us
2390 * to run in per-sample mode:
2391 */
2392 so->per_samp |= in->data.sample;
2393
2394 for (int i = 0; i < ncomp; i++) {
2395 struct ir3_instruction *instr = NULL;
2396 unsigned idx = (n * 4) + i + frac;
2397
2398 if (slot == VARYING_SLOT_POS) {
2399 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2400 } else if (slot == VARYING_SLOT_PNTC) {
2401 /* see for example st_nir_fixup_varying_slots().. this is
2402 * maybe a bit mesa/st specific. But we need things to line
2403 * up for this in fdN_program:
2404 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2405 * if (emit->sprite_coord_enable & texmask) {
2406 * ...
2407 * }
2408 */
2409 so->inputs[n].slot = VARYING_SLOT_VAR8;
2410 so->inputs[n].bary = true;
2411 instr = create_frag_input(ctx, false, idx);
2412 } else {
2413 /* detect the special case for front/back colors where
2414 * we need to do flat vs smooth shading depending on
2415 * rast state:
2416 */
2417 if (in->data.interpolation == INTERP_MODE_NONE) {
2418 switch (slot) {
2419 case VARYING_SLOT_COL0:
2420 case VARYING_SLOT_COL1:
2421 case VARYING_SLOT_BFC0:
2422 case VARYING_SLOT_BFC1:
2423 so->inputs[n].rasterflat = true;
2424 break;
2425 default:
2426 break;
2427 }
2428 }
2429
2430 if (ctx->compiler->flat_bypass) {
2431 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2432 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2433 so->inputs[n].use_ldlv = true;
2434 }
2435
2436 so->inputs[n].bary = true;
2437
2438 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2439 }
2440
2441 compile_assert(ctx, idx < ctx->ir->ninputs);
2442
2443 ctx->ir->inputs[idx] = instr;
2444 }
2445 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2446 for (int i = 0; i < ncomp; i++) {
2447 unsigned idx = (n * 4) + i + frac;
2448 compile_assert(ctx, idx < ctx->ir->ninputs);
2449 ctx->ir->inputs[idx] = create_input(ctx, idx);
2450 }
2451 } else {
2452 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2453 }
2454
2455 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2456 so->total_in += ncomp;
2457 }
2458 }
2459
2460 /* Initially we assign non-packed inloc's for varyings, as we don't really
2461 * know up-front which components will be unused. After all the compilation
2462 * stages we scan the shader to see which components are actually used, and
2463 * re-pack the inlocs to eliminate unneeded varyings.
2464 */
2465 static void
2466 pack_inlocs(struct ir3_context *ctx)
2467 {
2468 struct ir3_shader_variant *so = ctx->so;
2469 uint8_t used_components[so->inputs_count];
2470
2471 memset(used_components, 0, sizeof(used_components));
2472
2473 /*
2474 * First Step: scan shader to find which bary.f/ldlv remain:
2475 */
2476
2477 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2478 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2479 if (is_input(instr)) {
2480 unsigned inloc = instr->regs[1]->iim_val;
2481 unsigned i = inloc / 4;
2482 unsigned j = inloc % 4;
2483
2484 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
2485 compile_assert(ctx, i < so->inputs_count);
2486
2487 used_components[i] |= 1 << j;
2488 }
2489 }
2490 }
2491
2492 /*
2493 * Second Step: reassign varying inloc/slots:
2494 */
2495
2496 unsigned actual_in = 0;
2497 unsigned inloc = 0;
2498
2499 for (unsigned i = 0; i < so->inputs_count; i++) {
2500 unsigned compmask = 0, maxcomp = 0;
2501
2502 so->inputs[i].ncomp = 0;
2503 so->inputs[i].inloc = inloc;
2504 so->inputs[i].bary = false;
2505
2506 for (unsigned j = 0; j < 4; j++) {
2507 if (!(used_components[i] & (1 << j)))
2508 continue;
2509
2510 compmask |= (1 << j);
2511 actual_in++;
2512 so->inputs[i].ncomp++;
2513 maxcomp = j + 1;
2514
2515 /* at this point, since used_components[i] mask is only
2516 * considering varyings (ie. not sysvals) we know this
2517 * is a varying:
2518 */
2519 so->inputs[i].bary = true;
2520 }
2521
2522 if (so->inputs[i].bary) {
2523 so->varying_in++;
2524 so->inputs[i].compmask = (1 << maxcomp) - 1;
2525 inloc += maxcomp;
2526 }
2527 }
2528
2529 /*
2530 * Third Step: reassign packed inloc's:
2531 */
2532
2533 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2534 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2535 if (is_input(instr)) {
2536 unsigned inloc = instr->regs[1]->iim_val;
2537 unsigned i = inloc / 4;
2538 unsigned j = inloc % 4;
2539
2540 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
2541 }
2542 }
2543 }
2544 }
2545
2546 static void
2547 setup_output(struct ir3_context *ctx, nir_variable *out)
2548 {
2549 struct ir3_shader_variant *so = ctx->so;
2550 unsigned ncomp = glsl_get_components(out->type);
2551 unsigned n = out->data.driver_location;
2552 unsigned frac = out->data.location_frac;
2553 unsigned slot = out->data.location;
2554 unsigned comp = 0;
2555
2556 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2557 switch (slot) {
2558 case FRAG_RESULT_DEPTH:
2559 comp = 2; /* tgsi will write to .z component */
2560 so->writes_pos = true;
2561 break;
2562 case FRAG_RESULT_COLOR:
2563 so->color0_mrt = 1;
2564 break;
2565 case FRAG_RESULT_SAMPLE_MASK:
2566 so->writes_smask = true;
2567 break;
2568 default:
2569 if (slot >= FRAG_RESULT_DATA0)
2570 break;
2571 ir3_context_error(ctx, "unknown FS output name: %s\n",
2572 gl_frag_result_name(slot));
2573 }
2574 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2575 switch (slot) {
2576 case VARYING_SLOT_POS:
2577 so->writes_pos = true;
2578 break;
2579 case VARYING_SLOT_PSIZ:
2580 so->writes_psize = true;
2581 break;
2582 case VARYING_SLOT_COL0:
2583 case VARYING_SLOT_COL1:
2584 case VARYING_SLOT_BFC0:
2585 case VARYING_SLOT_BFC1:
2586 case VARYING_SLOT_FOGC:
2587 case VARYING_SLOT_CLIP_DIST0:
2588 case VARYING_SLOT_CLIP_DIST1:
2589 case VARYING_SLOT_CLIP_VERTEX:
2590 break;
2591 default:
2592 if (slot >= VARYING_SLOT_VAR0)
2593 break;
2594 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2595 break;
2596 ir3_context_error(ctx, "unknown VS output name: %s\n",
2597 gl_varying_slot_name(slot));
2598 }
2599 } else {
2600 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2601 }
2602
2603 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2604
2605 so->outputs[n].slot = slot;
2606 so->outputs[n].regid = regid(n, comp);
2607 so->outputs_count = MAX2(so->outputs_count, n + 1);
2608
2609 for (int i = 0; i < ncomp; i++) {
2610 unsigned idx = (n * 4) + i + frac;
2611 compile_assert(ctx, idx < ctx->ir->noutputs);
2612 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2613 }
2614
2615 /* if varying packing doesn't happen, we could end up in a situation
2616 * with "holes" in the output, and since the per-generation code that
2617 * sets up varying linkage registers doesn't expect to have more than
2618 * one varying per vec4 slot, pad the holes.
2619 *
2620 * Note that this should probably generate a performance warning of
2621 * some sort.
2622 */
2623 for (int i = 0; i < frac; i++) {
2624 unsigned idx = (n * 4) + i;
2625 if (!ctx->ir->outputs[idx]) {
2626 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2627 }
2628 }
2629 }
2630
2631 static int
2632 max_drvloc(struct exec_list *vars)
2633 {
2634 int drvloc = -1;
2635 nir_foreach_variable(var, vars) {
2636 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2637 }
2638 return drvloc;
2639 }
2640
2641 static const unsigned max_sysvals[] = {
2642 [MESA_SHADER_FRAGMENT] = 24, // TODO
2643 [MESA_SHADER_VERTEX] = 16,
2644 [MESA_SHADER_COMPUTE] = 16, // TODO how many do we actually need?
2645 [MESA_SHADER_KERNEL] = 16, // TODO how many do we actually need?
2646 };
2647
2648 static void
2649 emit_instructions(struct ir3_context *ctx)
2650 {
2651 unsigned ninputs, noutputs;
2652 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
2653
2654 ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
2655 noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
2656
2657 /* we need to leave room for sysvals:
2658 */
2659 ninputs += max_sysvals[ctx->so->type];
2660
2661 ctx->ir = ir3_create(ctx->compiler, ctx->so->type, ninputs, noutputs);
2662
2663 /* Create inputs in first block: */
2664 ctx->block = get_block(ctx, nir_start_block(fxn));
2665 ctx->in_block = ctx->block;
2666 list_addtail(&ctx->block->node, &ctx->ir->block_list);
2667
2668 ninputs -= max_sysvals[ctx->so->type];
2669
2670 /* for fragment shader, the vcoord input register is used as the
2671 * base for bary.f varying fetch instrs:
2672 *
2673 * TODO defer creating ctx->ij_pixel and corresponding sysvals
2674 * until emit_intrinsic when we know they are actually needed.
2675 * For now, we defer creating ctx->ij_centroid, etc, since we
2676 * only need ij_pixel for "old style" varying inputs (ie.
2677 * tgsi_to_nir)
2678 */
2679 struct ir3_instruction *vcoord = NULL;
2680 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2681 struct ir3_instruction *xy[2];
2682
2683 vcoord = create_input_compmask(ctx, 0, 0x3);
2684 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
2685
2686 ctx->ij_pixel = ir3_create_collect(ctx, xy, 2);
2687 }
2688
2689 /* Setup inputs: */
2690 nir_foreach_variable(var, &ctx->s->inputs) {
2691 setup_input(ctx, var);
2692 }
2693
2694 /* Defer add_sysval_input() stuff until after setup_inputs(),
2695 * because sysvals need to be appended after varyings:
2696 */
2697 if (vcoord) {
2698 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PIXEL,
2699 0x3, vcoord);
2700 }
2701
2702 /* Setup outputs: */
2703 nir_foreach_variable(var, &ctx->s->outputs) {
2704 setup_output(ctx, var);
2705 }
2706
2707 /* Find # of samplers: */
2708 nir_foreach_variable(var, &ctx->s->uniforms) {
2709 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
2710 /* just assume that we'll be reading from images.. if it
2711 * is write-only we don't have to count it, but not sure
2712 * if there is a good way to know?
2713 */
2714 ctx->so->num_samp += glsl_type_get_image_count(var->type);
2715 }
2716
2717 /* NOTE: need to do something more clever when we support >1 fxn */
2718 nir_foreach_register(reg, &fxn->registers) {
2719 ir3_declare_array(ctx, reg);
2720 }
2721 /* And emit the body: */
2722 ctx->impl = fxn;
2723 emit_function(ctx, fxn);
2724 }
2725
2726 /* from NIR perspective, we actually have varying inputs. But the varying
2727 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
2728 * only actual inputs are the sysvals.
2729 */
2730 static void
2731 fixup_frag_inputs(struct ir3_context *ctx)
2732 {
2733 struct ir3_shader_variant *so = ctx->so;
2734 struct ir3 *ir = ctx->ir;
2735 unsigned i = 0;
2736
2737 /* sysvals should appear at the end of the inputs, drop everything else: */
2738 while ((i < so->inputs_count) && !so->inputs[i].sysval)
2739 i++;
2740
2741 /* at IR level, inputs are always blocks of 4 scalars: */
2742 i *= 4;
2743
2744 ir->inputs = &ir->inputs[i];
2745 ir->ninputs -= i;
2746 }
2747
2748 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2749 * need to assign the tex state indexes for these after we know the
2750 * max tex index.
2751 */
2752 static void
2753 fixup_astc_srgb(struct ir3_context *ctx)
2754 {
2755 struct ir3_shader_variant *so = ctx->so;
2756 /* indexed by original tex idx, value is newly assigned alpha sampler
2757 * state tex idx. Zero is invalid since there is at least one sampler
2758 * if we get here.
2759 */
2760 unsigned alt_tex_state[16] = {0};
2761 unsigned tex_idx = ctx->max_texture_index + 1;
2762 unsigned idx = 0;
2763
2764 so->astc_srgb.base = tex_idx;
2765
2766 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
2767 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
2768
2769 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
2770
2771 if (alt_tex_state[sam->cat5.tex] == 0) {
2772 /* assign new alternate/alpha tex state slot: */
2773 alt_tex_state[sam->cat5.tex] = tex_idx++;
2774 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
2775 so->astc_srgb.count++;
2776 }
2777
2778 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
2779 }
2780 }
2781
2782 static void
2783 fixup_binning_pass(struct ir3_context *ctx)
2784 {
2785 struct ir3_shader_variant *so = ctx->so;
2786 struct ir3 *ir = ctx->ir;
2787 unsigned i, j;
2788
2789 for (i = 0, j = 0; i < so->outputs_count; i++) {
2790 unsigned slot = so->outputs[i].slot;
2791
2792 /* throw away everything but first position/psize */
2793 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
2794 if (i != j) {
2795 so->outputs[j] = so->outputs[i];
2796 ir->outputs[(j*4)+0] = ir->outputs[(i*4)+0];
2797 ir->outputs[(j*4)+1] = ir->outputs[(i*4)+1];
2798 ir->outputs[(j*4)+2] = ir->outputs[(i*4)+2];
2799 ir->outputs[(j*4)+3] = ir->outputs[(i*4)+3];
2800 }
2801 j++;
2802 }
2803 }
2804 so->outputs_count = j;
2805 ir->noutputs = j * 4;
2806 }
2807
2808 int
2809 ir3_compile_shader_nir(struct ir3_compiler *compiler,
2810 struct ir3_shader_variant *so)
2811 {
2812 struct ir3_context *ctx;
2813 struct ir3 *ir;
2814 struct ir3_instruction **inputs;
2815 unsigned i;
2816 int ret = 0, max_bary;
2817
2818 assert(!so->ir);
2819
2820 ctx = ir3_context_init(compiler, so);
2821 if (!ctx) {
2822 DBG("INIT failed!");
2823 ret = -1;
2824 goto out;
2825 }
2826
2827 emit_instructions(ctx);
2828
2829 if (ctx->error) {
2830 DBG("EMIT failed!");
2831 ret = -1;
2832 goto out;
2833 }
2834
2835 ir = so->ir = ctx->ir;
2836
2837 /* keep track of the inputs from TGSI perspective.. */
2838 inputs = ir->inputs;
2839
2840 /* but fixup actual inputs for frag shader: */
2841 if (so->type == MESA_SHADER_FRAGMENT)
2842 fixup_frag_inputs(ctx);
2843
2844 /* at this point, for binning pass, throw away unneeded outputs: */
2845 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
2846 fixup_binning_pass(ctx);
2847
2848 /* if we want half-precision outputs, mark the output registers
2849 * as half:
2850 */
2851 if (so->key.half_precision) {
2852 for (i = 0; i < ir->noutputs; i++) {
2853 struct ir3_instruction *out = ir->outputs[i];
2854
2855 if (!out)
2856 continue;
2857
2858 /* if frag shader writes z, that needs to be full precision: */
2859 if (so->outputs[i/4].slot == FRAG_RESULT_DEPTH)
2860 continue;
2861
2862 out->regs[0]->flags |= IR3_REG_HALF;
2863 /* output could be a fanout (ie. texture fetch output)
2864 * in which case we need to propagate the half-reg flag
2865 * up to the definer so that RA sees it:
2866 */
2867 if (out->opc == OPC_META_FO) {
2868 out = out->regs[1]->instr;
2869 out->regs[0]->flags |= IR3_REG_HALF;
2870 }
2871
2872 if (out->opc == OPC_MOV) {
2873 out->cat1.dst_type = half_type(out->cat1.dst_type);
2874 }
2875 }
2876 }
2877
2878 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2879 printf("BEFORE CP:\n");
2880 ir3_print(ir);
2881 }
2882
2883 ir3_cp(ir, so);
2884
2885 /* at this point, for binning pass, throw away unneeded outputs:
2886 * Note that for a6xx and later, we do this after ir3_cp to ensure
2887 * that the uniform/constant layout for BS and VS matches, so that
2888 * we can re-use same VS_CONST state group.
2889 */
2890 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
2891 fixup_binning_pass(ctx);
2892
2893 /* Insert mov if there's same instruction for each output.
2894 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
2895 */
2896 for (int i = ir->noutputs - 1; i >= 0; i--) {
2897 if (!ir->outputs[i])
2898 continue;
2899 for (unsigned j = 0; j < i; j++) {
2900 if (ir->outputs[i] == ir->outputs[j]) {
2901 ir->outputs[i] =
2902 ir3_MOV(ir->outputs[i]->block, ir->outputs[i], TYPE_F32);
2903 }
2904 }
2905 }
2906
2907 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2908 printf("BEFORE GROUPING:\n");
2909 ir3_print(ir);
2910 }
2911
2912 ir3_sched_add_deps(ir);
2913
2914 /* Group left/right neighbors, inserting mov's where needed to
2915 * solve conflicts:
2916 */
2917 ir3_group(ir);
2918
2919 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2920 printf("AFTER GROUPING:\n");
2921 ir3_print(ir);
2922 }
2923
2924 ir3_depth(ir);
2925
2926 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2927 printf("AFTER DEPTH:\n");
2928 ir3_print(ir);
2929 }
2930
2931 /* do Sethi–Ullman numbering before scheduling: */
2932 ir3_sun(ir);
2933
2934 ret = ir3_sched(ir);
2935 if (ret) {
2936 DBG("SCHED failed!");
2937 goto out;
2938 }
2939
2940 if (compiler->gpu_id >= 600) {
2941 ir3_a6xx_fixup_atomic_dests(ir, so);
2942 }
2943
2944 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2945 printf("AFTER SCHED:\n");
2946 ir3_print(ir);
2947 }
2948
2949 ret = ir3_ra(ir, so->type, so->frag_coord, so->frag_face);
2950 if (ret) {
2951 DBG("RA failed!");
2952 goto out;
2953 }
2954
2955 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2956 printf("AFTER RA:\n");
2957 ir3_print(ir);
2958 }
2959
2960 if (so->type == MESA_SHADER_FRAGMENT)
2961 pack_inlocs(ctx);
2962
2963 /* fixup input/outputs: */
2964 for (i = 0; i < so->outputs_count; i++) {
2965 /* sometimes we get outputs that don't write the .x coord, like:
2966 *
2967 * decl_var shader_out INTERP_MODE_NONE float Color (VARYING_SLOT_VAR9.z, 1, 0)
2968 *
2969 * Presumably the result of varying packing and then eliminating
2970 * some unneeded varyings? Just skip head to the first valid
2971 * component of the output.
2972 */
2973 for (unsigned j = 0; j < 4; j++) {
2974 struct ir3_instruction *instr = ir->outputs[(i*4) + j];
2975 if (instr) {
2976 so->outputs[i].regid = instr->regs[0]->num;
2977 so->outputs[i].half = !!(instr->regs[0]->flags & IR3_REG_HALF);
2978 break;
2979 }
2980 }
2981 }
2982
2983 /* Note that some or all channels of an input may be unused: */
2984 for (i = 0; i < so->inputs_count; i++) {
2985 unsigned j, reg = regid(63,0);
2986 bool half = false;
2987 for (j = 0; j < 4; j++) {
2988 struct ir3_instruction *in = inputs[(i*4) + j];
2989
2990 if (in && !(in->flags & IR3_INSTR_UNUSED)) {
2991 reg = in->regs[0]->num - j;
2992 if (half) {
2993 compile_assert(ctx, in->regs[0]->flags & IR3_REG_HALF);
2994 } else {
2995 half = !!(in->regs[0]->flags & IR3_REG_HALF);
2996 }
2997 }
2998 }
2999 so->inputs[i].regid = reg;
3000 so->inputs[i].half = half;
3001 }
3002
3003 if (ctx->astc_srgb)
3004 fixup_astc_srgb(ctx);
3005
3006 /* We need to do legalize after (for frag shader's) the "bary.f"
3007 * offsets (inloc) have been assigned.
3008 */
3009 ir3_legalize(ir, &so->has_ssbo, &so->need_pixlod, &max_bary);
3010
3011 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3012 printf("AFTER LEGALIZE:\n");
3013 ir3_print(ir);
3014 }
3015
3016 so->branchstack = ctx->max_stack;
3017
3018 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3019 if (so->type == MESA_SHADER_FRAGMENT)
3020 so->total_in = max_bary + 1;
3021
3022 so->max_sun = ir->max_sun;
3023
3024 out:
3025 if (ret) {
3026 if (so->ir)
3027 ir3_destroy(so->ir);
3028 so->ir = NULL;
3029 }
3030 ir3_context_free(ctx);
3031
3032 return ret;
3033 }