1aab7396c3e11593a4f7f8fe7dd6ce459a321d7b
2 * Copyright (C) 2015-2018 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "util/u_math.h"
29 #include "ir3_compiler.h"
30 #include "ir3_context.h"
31 #include "ir3_image.h"
32 #include "ir3_shader.h"
36 ir3_context_init(struct ir3_compiler
*compiler
,
37 struct ir3_shader_variant
*so
)
39 struct ir3_context
*ctx
= rzalloc(NULL
, struct ir3_context
);
41 if (compiler
->gpu_id
>= 400) {
42 if (so
->type
== MESA_SHADER_VERTEX
) {
43 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
44 } else if (so
->type
== MESA_SHADER_FRAGMENT
) {
45 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
49 if (so
->type
== MESA_SHADER_VERTEX
) {
50 ctx
->samples
= so
->key
.vsamples
;
51 } else if (so
->type
== MESA_SHADER_FRAGMENT
) {
52 ctx
->samples
= so
->key
.fsamples
;
56 if (compiler
->gpu_id
>= 600) {
57 ctx
->funcs
= &ir3_a6xx_funcs
;
58 } else if (compiler
->gpu_id
>= 400) {
59 ctx
->funcs
= &ir3_a4xx_funcs
;
62 ctx
->compiler
= compiler
;
64 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
65 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
66 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
67 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
69 /* TODO: maybe generate some sort of bitmask of what key
70 * lowers vs what shader has (ie. no need to lower
71 * texture clamp lowering if no texture sample instrs)..
72 * although should be done further up the stack to avoid
73 * creating duplicate variants..
76 if (ir3_key_lowers_nir(&so
->key
)) {
77 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
78 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
80 /* fast-path for shader key that lowers nothing in NIR: */
81 ctx
->s
= nir_shader_clone(ctx
, so
->shader
->nir
);
84 /* this needs to be the last pass run, so do this here instead of
85 * in ir3_optimize_nir():
87 NIR_PASS_V(ctx
->s
, nir_lower_bool_to_int32
);
88 NIR_PASS_V(ctx
->s
, nir_lower_locals_to_regs
);
89 NIR_PASS_V(ctx
->s
, nir_convert_from_ssa
, true);
91 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
92 DBG("dump nir%dv%d: type=%d, k={cts=%u,hp=%u}",
93 so
->shader
->id
, so
->id
, so
->type
,
94 so
->key
.color_two_side
, so
->key
.half_precision
);
95 nir_print_shader(ctx
->s
, stdout
);
98 if (shader_debug_enabled(so
->type
)) {
99 fprintf(stderr
, "NIR (final form) for %s shader:\n",
100 _mesa_shader_stage_to_string(so
->type
));
101 nir_print_shader(ctx
->s
, stderr
);
104 ir3_nir_scan_driver_consts(ctx
->s
, &so
->const_layout
);
106 so
->num_uniforms
= ctx
->s
->num_uniforms
;
107 so
->num_ubos
= ctx
->s
->info
.num_ubos
;
109 ir3_ibo_mapping_init(&so
->image_mapping
, ctx
->s
->info
.num_textures
);
111 /* Layout of constant registers, each section aligned to vec4. Note
112 * that pointer size (ubo, etc) changes depending on generation.
117 * if (vertex shader) {
118 * driver params (IR3_DP_*)
119 * if (stream_output.num_outputs > 0)
120 * stream-out addresses
124 * Immediates go last mostly because they are inserted in the CP pass
125 * after the nir -> ir3 frontend.
127 unsigned constoff
= align(ctx
->s
->num_uniforms
, 4);
128 unsigned ptrsz
= ir3_pointer_size(ctx
);
130 memset(&so
->constbase
, ~0, sizeof(so
->constbase
));
132 if (so
->num_ubos
> 0) {
133 so
->constbase
.ubo
= constoff
;
134 constoff
+= align(ctx
->s
->info
.num_ubos
* ptrsz
, 4) / 4;
137 if (so
->const_layout
.ssbo_size
.count
> 0) {
138 unsigned cnt
= so
->const_layout
.ssbo_size
.count
;
139 so
->constbase
.ssbo_sizes
= constoff
;
140 constoff
+= align(cnt
, 4) / 4;
143 if (so
->const_layout
.image_dims
.count
> 0) {
144 unsigned cnt
= so
->const_layout
.image_dims
.count
;
145 so
->constbase
.image_dims
= constoff
;
146 constoff
+= align(cnt
, 4) / 4;
149 unsigned num_driver_params
= 0;
150 if (so
->type
== MESA_SHADER_VERTEX
) {
151 num_driver_params
= IR3_DP_VS_COUNT
;
152 } else if (so
->type
== MESA_SHADER_COMPUTE
) {
153 num_driver_params
= IR3_DP_CS_COUNT
;
156 so
->constbase
.driver_param
= constoff
;
157 constoff
+= align(num_driver_params
, 4) / 4;
159 if ((so
->type
== MESA_SHADER_VERTEX
) &&
160 (compiler
->gpu_id
< 500) &&
161 so
->shader
->stream_output
.num_outputs
> 0) {
162 so
->constbase
.tfbo
= constoff
;
163 constoff
+= align(IR3_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
166 so
->constbase
.immediate
= constoff
;
172 ir3_context_free(struct ir3_context
*ctx
)
181 /* allocate a n element value array (to be populated by caller) and
184 struct ir3_instruction
**
185 ir3_get_dst_ssa(struct ir3_context
*ctx
, nir_ssa_def
*dst
, unsigned n
)
187 struct ir3_instruction
**value
=
188 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
189 _mesa_hash_table_insert(ctx
->def_ht
, dst
, value
);
193 struct ir3_instruction
**
194 ir3_get_dst(struct ir3_context
*ctx
, nir_dest
*dst
, unsigned n
)
196 struct ir3_instruction
**value
;
199 value
= ir3_get_dst_ssa(ctx
, &dst
->ssa
, n
);
201 value
= ralloc_array(ctx
, struct ir3_instruction
*, n
);
204 /* NOTE: in non-ssa case, we don't really need to store last_dst
205 * but this helps us catch cases where put_dst() call is forgotten
207 compile_assert(ctx
, !ctx
->last_dst
);
208 ctx
->last_dst
= value
;
214 struct ir3_instruction
* const *
215 ir3_get_src(struct ir3_context
*ctx
, nir_src
*src
)
218 struct hash_entry
*entry
;
219 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
220 compile_assert(ctx
, entry
);
223 nir_register
*reg
= src
->reg
.reg
;
224 struct ir3_array
*arr
= ir3_get_array(ctx
, reg
);
225 unsigned num_components
= arr
->r
->num_components
;
226 struct ir3_instruction
*addr
= NULL
;
227 struct ir3_instruction
**value
=
228 ralloc_array(ctx
, struct ir3_instruction
*, num_components
);
230 if (src
->reg
.indirect
)
231 addr
= ir3_get_addr(ctx
, ir3_get_src(ctx
, src
->reg
.indirect
)[0],
232 reg
->num_components
);
234 for (unsigned i
= 0; i
< num_components
; i
++) {
235 unsigned n
= src
->reg
.base_offset
* reg
->num_components
+ i
;
236 compile_assert(ctx
, n
< arr
->length
);
237 value
[i
] = ir3_create_array_load(ctx
, arr
, n
, addr
);
245 put_dst(struct ir3_context
*ctx
, nir_dest
*dst
)
247 unsigned bit_size
= nir_dest_bit_size(*dst
);
249 /* add extra mov if dst value is HIGH reg.. in some cases not all
250 * instructions can read from HIGH regs, in cases where they can
251 * ir3_cp will clean up the extra mov:
253 for (unsigned i
= 0; i
< ctx
->last_dst_n
; i
++) {
254 if (ctx
->last_dst
[i
]->regs
[0]->flags
& IR3_REG_HIGH
) {
255 ctx
->last_dst
[i
] = ir3_MOV(ctx
->block
, ctx
->last_dst
[i
], TYPE_U32
);
260 for (unsigned i
= 0; i
< ctx
->last_dst_n
; i
++) {
261 struct ir3_instruction
*dst
= ctx
->last_dst
[i
];
262 dst
->regs
[0]->flags
|= IR3_REG_HALF
;
263 if (ctx
->last_dst
[i
]->opc
== OPC_META_FO
)
264 dst
->regs
[1]->instr
->regs
[0]->flags
|= IR3_REG_HALF
;
269 nir_register
*reg
= dst
->reg
.reg
;
270 struct ir3_array
*arr
= ir3_get_array(ctx
, reg
);
271 unsigned num_components
= ctx
->last_dst_n
;
272 struct ir3_instruction
*addr
= NULL
;
274 if (dst
->reg
.indirect
)
275 addr
= ir3_get_addr(ctx
, ir3_get_src(ctx
, dst
->reg
.indirect
)[0],
276 reg
->num_components
);
278 for (unsigned i
= 0; i
< num_components
; i
++) {
279 unsigned n
= dst
->reg
.base_offset
* reg
->num_components
+ i
;
280 compile_assert(ctx
, n
< arr
->length
);
281 if (!ctx
->last_dst
[i
])
283 ir3_create_array_store(ctx
, arr
, n
, ctx
->last_dst
[i
], addr
);
286 ralloc_free(ctx
->last_dst
);
289 ctx
->last_dst
= NULL
;
293 struct ir3_instruction
*
294 ir3_create_collect(struct ir3_context
*ctx
, struct ir3_instruction
*const *arr
,
297 struct ir3_block
*block
= ctx
->block
;
298 struct ir3_instruction
*collect
;
303 unsigned flags
= arr
[0]->regs
[0]->flags
& IR3_REG_HALF
;
305 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
306 ir3_reg_create(collect
, 0, flags
); /* dst */
307 for (unsigned i
= 0; i
< arrsz
; i
++) {
308 struct ir3_instruction
*elem
= arr
[i
];
310 /* Since arrays are pre-colored in RA, we can't assume that
311 * things will end up in the right place. (Ie. if a collect
312 * joins elements from two different arrays.) So insert an
315 * We could possibly skip this if all the collected elements
316 * are contiguous elements in a single array.. not sure how
317 * likely that is to happen.
319 * Fixes a problem with glamor shaders, that in effect do
326 * color = texture2D(tex, texcoord);
328 * In this case, texcoord will end up as nir registers (which
329 * translate to ir3 array's of length 1. And we can't assume
330 * the two (or more) arrays will get allocated in consecutive
334 if (elem
->regs
[0]->flags
& IR3_REG_ARRAY
) {
335 type_t type
= (flags
& IR3_REG_HALF
) ? TYPE_U16
: TYPE_U32
;
336 elem
= ir3_MOV(block
, elem
, type
);
339 compile_assert(ctx
, (elem
->regs
[0]->flags
& IR3_REG_HALF
) == flags
);
340 ir3_reg_create(collect
, 0, IR3_REG_SSA
| flags
)->instr
= elem
;
346 /* helper for instructions that produce multiple consecutive scalar
347 * outputs which need to have a split/fanout meta instruction inserted
350 ir3_split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
351 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
353 struct ir3_instruction
*prev
= NULL
;
355 if ((n
== 1) && (src
->regs
[0]->wrmask
== 0x1)) {
360 unsigned flags
= src
->regs
[0]->flags
& (IR3_REG_HALF
| IR3_REG_HIGH
);
362 for (int i
= 0, j
= 0; i
< n
; i
++) {
363 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
364 ir3_reg_create(split
, 0, IR3_REG_SSA
| flags
);
365 ir3_reg_create(split
, 0, IR3_REG_SSA
| flags
)->instr
= src
;
366 split
->fo
.off
= i
+ base
;
369 split
->cp
.left
= prev
;
370 split
->cp
.left_cnt
++;
371 prev
->cp
.right
= split
;
372 prev
->cp
.right_cnt
++;
376 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
382 ir3_context_error(struct ir3_context
*ctx
, const char *format
, ...)
384 struct hash_table
*errors
= NULL
;
386 va_start(ap
, format
);
387 if (ctx
->cur_instr
) {
388 errors
= _mesa_hash_table_create(NULL
,
390 _mesa_key_pointer_equal
);
391 char *msg
= ralloc_vasprintf(errors
, format
, ap
);
392 _mesa_hash_table_insert(errors
, ctx
->cur_instr
, msg
);
394 _debug_vprintf(format
, ap
);
397 nir_print_shader_annotated(ctx
->s
, stdout
, errors
);
403 static struct ir3_instruction
*
404 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
, int align
)
406 struct ir3_instruction
*instr
, *immed
;
408 /* TODO in at least some cases, the backend could probably be
409 * made clever enough to propagate IR3_REG_HALF..
411 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
412 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
419 /* src *= 2 => src <<= 1: */
420 immed
= create_immed(block
, 1);
421 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
423 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
424 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
425 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
429 immed
= create_immed(block
, 3);
430 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
432 instr
= ir3_MULL_U(block
, instr
, 0, immed
, 0);
433 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
434 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
437 /* src *= 4 => src <<= 2: */
438 immed
= create_immed(block
, 2);
439 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
441 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
442 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
443 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
446 unreachable("bad align");
450 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
451 instr
->regs
[0]->num
= regid(REG_A0
, 0);
452 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
453 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
458 /* caches addr values to avoid generating multiple cov/shl/mova
459 * sequences for each use of a given NIR level src as address
461 struct ir3_instruction
*
462 ir3_get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
)
464 struct ir3_instruction
*addr
;
465 unsigned idx
= align
- 1;
467 compile_assert(ctx
, idx
< ARRAY_SIZE(ctx
->addr_ht
));
469 if (!ctx
->addr_ht
[idx
]) {
470 ctx
->addr_ht
[idx
] = _mesa_hash_table_create(ctx
,
471 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
473 struct hash_entry
*entry
;
474 entry
= _mesa_hash_table_search(ctx
->addr_ht
[idx
], src
);
479 addr
= create_addr(ctx
->block
, src
, align
);
480 _mesa_hash_table_insert(ctx
->addr_ht
[idx
], src
, addr
);
485 struct ir3_instruction
*
486 ir3_get_predicate(struct ir3_context
*ctx
, struct ir3_instruction
*src
)
488 struct ir3_block
*b
= ctx
->block
;
489 struct ir3_instruction
*cond
;
491 /* NOTE: only cmps.*.* can write p0.x: */
492 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
493 cond
->cat2
.condition
= IR3_COND_NE
;
495 /* condition always goes in predicate register: */
496 cond
->regs
[0]->num
= regid(REG_P0
, 0);
506 ir3_declare_array(struct ir3_context
*ctx
, nir_register
*reg
)
508 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
509 arr
->id
= ++ctx
->num_arrays
;
510 /* NOTE: sometimes we get non array regs, for example for arrays of
511 * length 1. See fs-const-array-of-struct-of-array.shader_test. So
512 * treat a non-array as if it was an array of length 1.
514 * It would be nice if there was a nir pass to convert arrays of
517 arr
->length
= reg
->num_components
* MAX2(1, reg
->num_array_elems
);
518 compile_assert(ctx
, arr
->length
> 0);
520 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
524 ir3_get_array(struct ir3_context
*ctx
, nir_register
*reg
)
526 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
530 ir3_context_error(ctx
, "bogus reg: %s\n", reg
->name
);
534 /* relative (indirect) if address!=NULL */
535 struct ir3_instruction
*
536 ir3_create_array_load(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
537 struct ir3_instruction
*address
)
539 struct ir3_block
*block
= ctx
->block
;
540 struct ir3_instruction
*mov
;
541 struct ir3_register
*src
;
543 mov
= ir3_instr_create(block
, OPC_MOV
);
544 mov
->cat1
.src_type
= TYPE_U32
;
545 mov
->cat1
.dst_type
= TYPE_U32
;
546 mov
->barrier_class
= IR3_BARRIER_ARRAY_R
;
547 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_W
;
548 ir3_reg_create(mov
, 0, 0);
549 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
550 COND(address
, IR3_REG_RELATIV
));
551 src
->instr
= arr
->last_write
;
552 src
->size
= arr
->length
;
553 src
->array
.id
= arr
->id
;
554 src
->array
.offset
= n
;
557 ir3_instr_set_address(mov
, address
);
562 /* relative (indirect) if address!=NULL */
564 ir3_create_array_store(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
565 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
567 struct ir3_block
*block
= ctx
->block
;
568 struct ir3_instruction
*mov
;
569 struct ir3_register
*dst
;
571 /* if not relative store, don't create an extra mov, since that
572 * ends up being difficult for cp to remove.
577 src
->barrier_class
|= IR3_BARRIER_ARRAY_W
;
578 src
->barrier_conflict
|= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
580 dst
->flags
|= IR3_REG_ARRAY
;
581 dst
->instr
= arr
->last_write
;
582 dst
->size
= arr
->length
;
583 dst
->array
.id
= arr
->id
;
584 dst
->array
.offset
= n
;
586 arr
->last_write
= src
;
588 array_insert(block
, block
->keeps
, src
);
593 mov
= ir3_instr_create(block
, OPC_MOV
);
594 mov
->cat1
.src_type
= TYPE_U32
;
595 mov
->cat1
.dst_type
= TYPE_U32
;
596 mov
->barrier_class
= IR3_BARRIER_ARRAY_W
;
597 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
598 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
599 COND(address
, IR3_REG_RELATIV
));
600 dst
->instr
= arr
->last_write
;
601 dst
->size
= arr
->length
;
602 dst
->array
.id
= arr
->id
;
603 dst
->array
.offset
= n
;
604 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
607 ir3_instr_set_address(mov
, address
);
609 arr
->last_write
= mov
;
611 /* the array store may only matter to something in an earlier
612 * block (ie. loops), but since arrays are not in SSA, depth
613 * pass won't know this.. so keep all array stores:
615 array_insert(block
, block
->keeps
, mov
);