2 * Copyright (C) 2015-2018 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "ir3_compiler.h"
28 #include "ir3_context.h"
29 #include "ir3_image.h"
30 #include "ir3_shader.h"
34 ir3_context_init(struct ir3_compiler
*compiler
,
35 struct ir3_shader_variant
*so
)
37 struct ir3_context
*ctx
= rzalloc(NULL
, struct ir3_context
);
39 if (compiler
->gpu_id
>= 400) {
40 if (so
->type
== MESA_SHADER_VERTEX
) {
41 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
42 } else if (so
->type
== MESA_SHADER_FRAGMENT
) {
43 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
47 if (so
->type
== MESA_SHADER_VERTEX
) {
48 ctx
->samples
= so
->key
.vsamples
;
49 } else if (so
->type
== MESA_SHADER_FRAGMENT
) {
50 ctx
->samples
= so
->key
.fsamples
;
54 if (compiler
->gpu_id
>= 600) {
55 ctx
->funcs
= &ir3_a6xx_funcs
;
56 } else if (compiler
->gpu_id
>= 400) {
57 ctx
->funcs
= &ir3_a4xx_funcs
;
60 ctx
->compiler
= compiler
;
62 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
63 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
64 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
65 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
66 ctx
->sel_cond_conversions
= _mesa_hash_table_create(ctx
,
67 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
69 /* TODO: maybe generate some sort of bitmask of what key
70 * lowers vs what shader has (ie. no need to lower
71 * texture clamp lowering if no texture sample instrs)..
72 * although should be done further up the stack to avoid
73 * creating duplicate variants..
76 ctx
->s
= nir_shader_clone(ctx
, so
->shader
->nir
);
77 if (ir3_key_lowers_nir(&so
->key
))
78 ir3_optimize_nir(so
->shader
, ctx
->s
, &so
->key
);
80 /* this needs to be the last pass run, so do this here instead of
81 * in ir3_optimize_nir():
83 bool progress
= false;
84 NIR_PASS(progress
, ctx
->s
, nir_lower_locals_to_regs
);
86 /* we could need cleanup after lower_locals_to_regs */
89 NIR_PASS(progress
, ctx
->s
, nir_opt_algebraic
);
90 NIR_PASS(progress
, ctx
->s
, nir_opt_constant_folding
);
93 /* We want to lower nir_op_imul as late as possible, to catch also
94 * those generated by earlier passes (e.g, nir_lower_locals_to_regs).
95 * However, we want a final swing of a few passes to have a chance
96 * at optimizing the result.
99 NIR_PASS(progress
, ctx
->s
, ir3_nir_lower_imul
);
102 NIR_PASS(progress
, ctx
->s
, nir_opt_algebraic
);
103 NIR_PASS(progress
, ctx
->s
, nir_opt_copy_prop_vars
);
104 NIR_PASS(progress
, ctx
->s
, nir_opt_dead_write_vars
);
105 NIR_PASS(progress
, ctx
->s
, nir_opt_dce
);
106 NIR_PASS(progress
, ctx
->s
, nir_opt_constant_folding
);
109 /* Enable the texture pre-fetch feature only a4xx onwards. But
110 * only enable it on generations that have been tested:
112 if ((so
->type
== MESA_SHADER_FRAGMENT
) && (compiler
->gpu_id
>= 600))
113 NIR_PASS_V(ctx
->s
, ir3_nir_lower_tex_prefetch
);
115 NIR_PASS_V(ctx
->s
, nir_convert_from_ssa
, true);
117 /* Super crude heuristic to limit # of tex prefetch in small
118 * shaders. This completely ignores loops.. but that's really
119 * not the worst of it's problems. (A frag shader that has
120 * loops is probably going to be big enough to not trigger a
123 * 1) probably want to do this in terms of ir3 instructions
124 * 2) probably really want to decide this after scheduling
125 * (or at least pre-RA sched) so we have a rough idea about
126 * nops, and don't count things that get cp'd away
127 * 3) blob seems to use higher thresholds with a mix of more
128 * SFU instructions. Which partly makes sense, more SFU
129 * instructions probably means you want to get the real
130 * shader started sooner, but that considers where in the
131 * shader the SFU instructions are, which blob doesn't seem
134 * This uses more conservative thresholds assuming a more alu
135 * than sfu heavy instruction mix.
137 if (so
->type
== MESA_SHADER_FRAGMENT
) {
138 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
140 unsigned instruction_count
= 0;
141 nir_foreach_block (block
, fxn
) {
142 instruction_count
+= exec_list_length(&block
->instr_list
);
145 if (instruction_count
< 50) {
146 ctx
->prefetch_limit
= 2;
147 } else if (instruction_count
< 70) {
148 ctx
->prefetch_limit
= 3;
150 ctx
->prefetch_limit
= IR3_MAX_SAMPLER_PREFETCH
;
154 if (shader_debug_enabled(so
->type
)) {
155 fprintf(stdout
, "NIR (final form) for %s shader %s:\n",
156 ir3_shader_stage(so
), so
->shader
->nir
->info
.name
);
157 nir_print_shader(ctx
->s
, stdout
);
160 ir3_ibo_mapping_init(&so
->image_mapping
, ctx
->s
->info
.num_textures
);
166 ir3_context_free(struct ir3_context
*ctx
)
175 /* allocate a n element value array (to be populated by caller) and
178 struct ir3_instruction
**
179 ir3_get_dst_ssa(struct ir3_context
*ctx
, nir_ssa_def
*dst
, unsigned n
)
181 struct ir3_instruction
**value
=
182 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
183 _mesa_hash_table_insert(ctx
->def_ht
, dst
, value
);
187 struct ir3_instruction
**
188 ir3_get_dst(struct ir3_context
*ctx
, nir_dest
*dst
, unsigned n
)
190 struct ir3_instruction
**value
;
193 value
= ir3_get_dst_ssa(ctx
, &dst
->ssa
, n
);
195 value
= ralloc_array(ctx
, struct ir3_instruction
*, n
);
198 /* NOTE: in non-ssa case, we don't really need to store last_dst
199 * but this helps us catch cases where put_dst() call is forgotten
201 compile_assert(ctx
, !ctx
->last_dst
);
202 ctx
->last_dst
= value
;
208 struct ir3_instruction
* const *
209 ir3_get_src(struct ir3_context
*ctx
, nir_src
*src
)
212 struct hash_entry
*entry
;
213 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
214 compile_assert(ctx
, entry
);
217 nir_register
*reg
= src
->reg
.reg
;
218 struct ir3_array
*arr
= ir3_get_array(ctx
, reg
);
219 unsigned num_components
= arr
->r
->num_components
;
220 struct ir3_instruction
*addr
= NULL
;
221 struct ir3_instruction
**value
=
222 ralloc_array(ctx
, struct ir3_instruction
*, num_components
);
224 if (src
->reg
.indirect
)
225 addr
= ir3_get_addr0(ctx
, ir3_get_src(ctx
, src
->reg
.indirect
)[0],
226 reg
->num_components
);
228 for (unsigned i
= 0; i
< num_components
; i
++) {
229 unsigned n
= src
->reg
.base_offset
* reg
->num_components
+ i
;
230 compile_assert(ctx
, n
< arr
->length
);
231 value
[i
] = ir3_create_array_load(ctx
, arr
, n
, addr
, reg
->bit_size
);
239 ir3_put_dst(struct ir3_context
*ctx
, nir_dest
*dst
)
241 unsigned bit_size
= nir_dest_bit_size(*dst
);
243 /* add extra mov if dst value is HIGH reg.. in some cases not all
244 * instructions can read from HIGH regs, in cases where they can
245 * ir3_cp will clean up the extra mov:
247 for (unsigned i
= 0; i
< ctx
->last_dst_n
; i
++) {
248 if (!ctx
->last_dst
[i
])
250 if (ctx
->last_dst
[i
]->regs
[0]->flags
& IR3_REG_HIGH
) {
251 ctx
->last_dst
[i
] = ir3_MOV(ctx
->block
, ctx
->last_dst
[i
], TYPE_U32
);
255 /* Note: 1-bit bools are stored in 32-bit regs */
256 if (bit_size
== 16) {
257 for (unsigned i
= 0; i
< ctx
->last_dst_n
; i
++) {
258 struct ir3_instruction
*dst
= ctx
->last_dst
[i
];
259 dst
->regs
[0]->flags
|= IR3_REG_HALF
;
260 if (dst
->opc
== OPC_META_SPLIT
) {
261 dst
->regs
[1]->instr
->regs
[0]->flags
|= IR3_REG_HALF
;
262 dst
->regs
[1]->flags
|= IR3_REG_HALF
;
268 nir_register
*reg
= dst
->reg
.reg
;
269 struct ir3_array
*arr
= ir3_get_array(ctx
, reg
);
270 unsigned num_components
= ctx
->last_dst_n
;
271 struct ir3_instruction
*addr
= NULL
;
273 if (dst
->reg
.indirect
)
274 addr
= ir3_get_addr0(ctx
, ir3_get_src(ctx
, dst
->reg
.indirect
)[0],
275 reg
->num_components
);
277 for (unsigned i
= 0; i
< num_components
; i
++) {
278 unsigned n
= dst
->reg
.base_offset
* reg
->num_components
+ i
;
279 compile_assert(ctx
, n
< arr
->length
);
280 if (!ctx
->last_dst
[i
])
282 ir3_create_array_store(ctx
, arr
, n
, ctx
->last_dst
[i
], addr
);
285 ralloc_free(ctx
->last_dst
);
288 ctx
->last_dst
= NULL
;
293 dest_flags(struct ir3_instruction
*instr
)
295 return instr
->regs
[0]->flags
& (IR3_REG_HALF
| IR3_REG_HIGH
);
298 struct ir3_instruction
*
299 ir3_create_collect(struct ir3_context
*ctx
, struct ir3_instruction
*const *arr
,
302 struct ir3_block
*block
= ctx
->block
;
303 struct ir3_instruction
*collect
;
308 unsigned flags
= dest_flags(arr
[0]);
310 collect
= ir3_instr_create2(block
, OPC_META_COLLECT
, 1 + arrsz
);
311 __ssa_dst(collect
)->flags
|= flags
;
312 for (unsigned i
= 0; i
< arrsz
; i
++) {
313 struct ir3_instruction
*elem
= arr
[i
];
315 /* Since arrays are pre-colored in RA, we can't assume that
316 * things will end up in the right place. (Ie. if a collect
317 * joins elements from two different arrays.) So insert an
320 * We could possibly skip this if all the collected elements
321 * are contiguous elements in a single array.. not sure how
322 * likely that is to happen.
324 * Fixes a problem with glamor shaders, that in effect do
331 * color = texture2D(tex, texcoord);
333 * In this case, texcoord will end up as nir registers (which
334 * translate to ir3 array's of length 1. And we can't assume
335 * the two (or more) arrays will get allocated in consecutive
339 if (elem
->regs
[0]->flags
& IR3_REG_ARRAY
) {
340 type_t type
= (flags
& IR3_REG_HALF
) ? TYPE_U16
: TYPE_U32
;
341 elem
= ir3_MOV(block
, elem
, type
);
344 compile_assert(ctx
, dest_flags(elem
) == flags
);
345 __ssa_src(collect
, elem
, flags
);
348 collect
->regs
[0]->wrmask
= MASK(arrsz
);
353 /* helper for instructions that produce multiple consecutive scalar
354 * outputs which need to have a split meta instruction inserted
357 ir3_split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
358 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
360 struct ir3_instruction
*prev
= NULL
;
362 if ((n
== 1) && (src
->regs
[0]->wrmask
== 0x1)) {
367 if (src
->opc
== OPC_META_COLLECT
) {
368 debug_assert((base
+ n
) < src
->regs_count
);
370 for (int i
= 0; i
< n
; i
++) {
371 dst
[i
] = ssa(src
->regs
[i
+ base
+ 1]);
377 unsigned flags
= dest_flags(src
);
379 for (int i
= 0, j
= 0; i
< n
; i
++) {
380 struct ir3_instruction
*split
=
381 ir3_instr_create(block
, OPC_META_SPLIT
);
382 __ssa_dst(split
)->flags
|= flags
;
383 __ssa_src(split
, src
, flags
);
384 split
->split
.off
= i
+ base
;
387 split
->cp
.left
= prev
;
388 split
->cp
.left_cnt
++;
389 prev
->cp
.right
= split
;
390 prev
->cp
.right_cnt
++;
394 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
400 ir3_context_error(struct ir3_context
*ctx
, const char *format
, ...)
402 struct hash_table
*errors
= NULL
;
404 va_start(ap
, format
);
405 if (ctx
->cur_instr
) {
406 errors
= _mesa_hash_table_create(NULL
,
408 _mesa_key_pointer_equal
);
409 char *msg
= ralloc_vasprintf(errors
, format
, ap
);
410 _mesa_hash_table_insert(errors
, ctx
->cur_instr
, msg
);
412 _debug_vprintf(format
, ap
);
415 nir_print_shader_annotated(ctx
->s
, stdout
, errors
);
421 static struct ir3_instruction
*
422 create_addr0(struct ir3_block
*block
, struct ir3_instruction
*src
, int align
)
424 struct ir3_instruction
*instr
, *immed
;
426 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
433 /* src *= 2 => src <<= 1: */
434 immed
= create_immed_typed(block
, 1, TYPE_S16
);
435 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
439 immed
= create_immed_typed(block
, 3, TYPE_S16
);
440 instr
= ir3_MULL_U(block
, instr
, 0, immed
, 0);
443 /* src *= 4 => src <<= 2: */
444 immed
= create_immed_typed(block
, 2, TYPE_S16
);
445 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
448 unreachable("bad align");
452 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
454 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
455 instr
->regs
[0]->num
= regid(REG_A0
, 0);
456 instr
->regs
[0]->flags
&= ~IR3_REG_SSA
;
461 static struct ir3_instruction
*
462 create_addr1(struct ir3_block
*block
, unsigned const_val
)
465 struct ir3_instruction
*immed
= create_immed_typed(block
, const_val
, TYPE_S16
);
466 struct ir3_instruction
*instr
= ir3_MOV(block
, immed
, TYPE_S16
);
467 instr
->regs
[0]->num
= regid(REG_A0
, 1);
468 instr
->regs
[0]->flags
&= ~IR3_REG_SSA
;
472 /* caches addr values to avoid generating multiple cov/shl/mova
473 * sequences for each use of a given NIR level src as address
475 struct ir3_instruction
*
476 ir3_get_addr0(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
)
478 struct ir3_instruction
*addr
;
479 unsigned idx
= align
- 1;
481 compile_assert(ctx
, idx
< ARRAY_SIZE(ctx
->addr0_ht
));
483 if (!ctx
->addr0_ht
[idx
]) {
484 ctx
->addr0_ht
[idx
] = _mesa_hash_table_create(ctx
,
485 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
487 struct hash_entry
*entry
;
488 entry
= _mesa_hash_table_search(ctx
->addr0_ht
[idx
], src
);
493 addr
= create_addr0(ctx
->block
, src
, align
);
494 _mesa_hash_table_insert(ctx
->addr0_ht
[idx
], src
, addr
);
499 /* Similar to ir3_get_addr0, but for a1.x. */
500 struct ir3_instruction
*
501 ir3_get_addr1(struct ir3_context
*ctx
, unsigned const_val
)
503 struct ir3_instruction
*addr
;
505 if (!ctx
->addr1_ht
) {
506 ctx
->addr1_ht
= _mesa_hash_table_u64_create(ctx
);
508 addr
= _mesa_hash_table_u64_search(ctx
->addr1_ht
, const_val
);
513 addr
= create_addr1(ctx
->block
, const_val
);
514 _mesa_hash_table_u64_insert(ctx
->addr1_ht
, const_val
, addr
);
519 struct ir3_instruction
*
520 ir3_get_predicate(struct ir3_context
*ctx
, struct ir3_instruction
*src
)
522 struct ir3_block
*b
= ctx
->block
;
523 struct ir3_instruction
*cond
;
525 /* NOTE: only cmps.*.* can write p0.x: */
526 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
527 cond
->cat2
.condition
= IR3_COND_NE
;
529 /* condition always goes in predicate register: */
530 cond
->regs
[0]->num
= regid(REG_P0
, 0);
531 cond
->regs
[0]->flags
&= ~IR3_REG_SSA
;
541 ir3_declare_array(struct ir3_context
*ctx
, nir_register
*reg
)
543 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
544 arr
->id
= ++ctx
->num_arrays
;
545 /* NOTE: sometimes we get non array regs, for example for arrays of
546 * length 1. See fs-const-array-of-struct-of-array.shader_test. So
547 * treat a non-array as if it was an array of length 1.
549 * It would be nice if there was a nir pass to convert arrays of
552 arr
->length
= reg
->num_components
* MAX2(1, reg
->num_array_elems
);
553 compile_assert(ctx
, arr
->length
> 0);
555 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
559 ir3_get_array(struct ir3_context
*ctx
, nir_register
*reg
)
561 foreach_array (arr
, &ctx
->ir
->array_list
) {
565 ir3_context_error(ctx
, "bogus reg: %s\n", reg
->name
);
569 /* relative (indirect) if address!=NULL */
570 struct ir3_instruction
*
571 ir3_create_array_load(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
572 struct ir3_instruction
*address
, unsigned bitsize
)
574 struct ir3_block
*block
= ctx
->block
;
575 struct ir3_instruction
*mov
;
576 struct ir3_register
*src
;
579 mov
= ir3_instr_create(block
, OPC_MOV
);
581 mov
->cat1
.src_type
= TYPE_U16
;
582 mov
->cat1
.dst_type
= TYPE_U16
;
583 flags
|= IR3_REG_HALF
;
586 mov
->cat1
.src_type
= TYPE_U32
;
587 mov
->cat1
.dst_type
= TYPE_U32
;
590 mov
->barrier_class
= IR3_BARRIER_ARRAY_R
;
591 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_W
;
592 __ssa_dst(mov
)->flags
|= flags
;
593 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
594 COND(address
, IR3_REG_RELATIV
) | flags
);
595 src
->instr
= arr
->last_write
;
596 src
->size
= arr
->length
;
597 src
->array
.id
= arr
->id
;
598 src
->array
.offset
= n
;
601 ir3_instr_set_address(mov
, address
);
606 /* relative (indirect) if address!=NULL */
608 ir3_create_array_store(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
609 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
611 struct ir3_block
*block
= ctx
->block
;
612 struct ir3_instruction
*mov
;
613 struct ir3_register
*dst
;
615 /* if not relative store, don't create an extra mov, since that
616 * ends up being difficult for cp to remove.
618 * Also, don't skip the mov if the src is meta (like fanout/split),
619 * since that creates a situation that RA can't really handle properly.
621 if (!address
&& !is_meta(src
)) {
624 src
->barrier_class
|= IR3_BARRIER_ARRAY_W
;
625 src
->barrier_conflict
|= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
627 dst
->flags
|= IR3_REG_ARRAY
;
628 dst
->instr
= arr
->last_write
;
629 dst
->size
= arr
->length
;
630 dst
->array
.id
= arr
->id
;
631 dst
->array
.offset
= n
;
633 arr
->last_write
= src
;
635 array_insert(block
, block
->keeps
, src
);
640 mov
= ir3_instr_create(block
, OPC_MOV
);
641 mov
->cat1
.src_type
= TYPE_U32
;
642 mov
->cat1
.dst_type
= TYPE_U32
;
643 mov
->barrier_class
= IR3_BARRIER_ARRAY_W
;
644 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
645 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
646 COND(address
, IR3_REG_RELATIV
));
647 dst
->instr
= arr
->last_write
;
648 dst
->size
= arr
->length
;
649 dst
->array
.id
= arr
->id
;
650 dst
->array
.offset
= n
;
651 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
654 ir3_instr_set_address(mov
, address
);
656 arr
->last_write
= mov
;
658 /* the array store may only matter to something in an earlier
659 * block (ie. loops), but since arrays are not in SSA, depth
660 * pass won't know this.. so keep all array stores:
662 array_insert(block
, block
->keeps
, mov
);