2 * Copyright (C) 2015-2018 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "util/u_math.h"
29 #include "ir3_compiler.h"
30 #include "ir3_context.h"
31 #include "ir3_image.h"
32 #include "ir3_shader.h"
36 ir3_context_init(struct ir3_compiler
*compiler
,
37 struct ir3_shader_variant
*so
)
39 struct ir3_context
*ctx
= rzalloc(NULL
, struct ir3_context
);
41 if (compiler
->gpu_id
>= 400) {
42 if (so
->type
== MESA_SHADER_VERTEX
) {
43 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
44 } else if (so
->type
== MESA_SHADER_FRAGMENT
) {
45 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
49 if (so
->type
== MESA_SHADER_VERTEX
) {
50 ctx
->samples
= so
->key
.vsamples
;
51 } else if (so
->type
== MESA_SHADER_FRAGMENT
) {
52 ctx
->samples
= so
->key
.fsamples
;
56 if (compiler
->gpu_id
>= 400) {
57 ctx
->funcs
= &ir3_a4xx_funcs
;
60 ctx
->compiler
= compiler
;
62 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
63 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
64 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
65 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
67 /* TODO: maybe generate some sort of bitmask of what key
68 * lowers vs what shader has (ie. no need to lower
69 * texture clamp lowering if no texture sample instrs)..
70 * although should be done further up the stack to avoid
71 * creating duplicate variants..
74 if (ir3_key_lowers_nir(&so
->key
)) {
75 nir_shader
*s
= nir_shader_clone(ctx
, so
->shader
->nir
);
76 ctx
->s
= ir3_optimize_nir(so
->shader
, s
, &so
->key
);
78 /* fast-path for shader key that lowers nothing in NIR: */
79 ctx
->s
= nir_shader_clone(ctx
, so
->shader
->nir
);
82 /* this needs to be the last pass run, so do this here instead of
83 * in ir3_optimize_nir():
85 NIR_PASS_V(ctx
->s
, nir_lower_bool_to_int32
);
86 NIR_PASS_V(ctx
->s
, nir_lower_locals_to_regs
);
87 NIR_PASS_V(ctx
->s
, nir_convert_from_ssa
, true);
89 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
90 DBG("dump nir%dv%d: type=%d, k={cts=%u,hp=%u}",
91 so
->shader
->id
, so
->id
, so
->type
,
92 so
->key
.color_two_side
, so
->key
.half_precision
);
93 nir_print_shader(ctx
->s
, stdout
);
96 if (shader_debug_enabled(so
->type
)) {
97 fprintf(stderr
, "NIR (final form) for %s shader:\n",
98 _mesa_shader_stage_to_string(so
->type
));
99 nir_print_shader(ctx
->s
, stderr
);
102 ir3_nir_scan_driver_consts(ctx
->s
, &so
->const_layout
);
104 so
->num_uniforms
= ctx
->s
->num_uniforms
;
105 so
->num_ubos
= ctx
->s
->info
.num_ubos
;
107 ir3_ibo_mapping_init(&so
->image_mapping
, ctx
->s
->info
.num_textures
);
109 /* Layout of constant registers, each section aligned to vec4. Note
110 * that pointer size (ubo, etc) changes depending on generation.
115 * if (vertex shader) {
116 * driver params (IR3_DP_*)
117 * if (stream_output.num_outputs > 0)
118 * stream-out addresses
122 * Immediates go last mostly because they are inserted in the CP pass
123 * after the nir -> ir3 frontend.
125 unsigned constoff
= align(ctx
->s
->num_uniforms
, 4);
126 unsigned ptrsz
= ir3_pointer_size(ctx
);
128 memset(&so
->constbase
, ~0, sizeof(so
->constbase
));
130 if (so
->num_ubos
> 0) {
131 so
->constbase
.ubo
= constoff
;
132 constoff
+= align(ctx
->s
->info
.num_ubos
* ptrsz
, 4) / 4;
135 if (so
->const_layout
.ssbo_size
.count
> 0) {
136 unsigned cnt
= so
->const_layout
.ssbo_size
.count
;
137 so
->constbase
.ssbo_sizes
= constoff
;
138 constoff
+= align(cnt
, 4) / 4;
141 if (so
->const_layout
.image_dims
.count
> 0) {
142 unsigned cnt
= so
->const_layout
.image_dims
.count
;
143 so
->constbase
.image_dims
= constoff
;
144 constoff
+= align(cnt
, 4) / 4;
147 unsigned num_driver_params
= 0;
148 if (so
->type
== MESA_SHADER_VERTEX
) {
149 num_driver_params
= IR3_DP_VS_COUNT
;
150 } else if (so
->type
== MESA_SHADER_COMPUTE
) {
151 num_driver_params
= IR3_DP_CS_COUNT
;
154 so
->constbase
.driver_param
= constoff
;
155 constoff
+= align(num_driver_params
, 4) / 4;
157 if ((so
->type
== MESA_SHADER_VERTEX
) &&
158 (compiler
->gpu_id
< 500) &&
159 so
->shader
->stream_output
.num_outputs
> 0) {
160 so
->constbase
.tfbo
= constoff
;
161 constoff
+= align(IR3_MAX_SO_BUFFERS
* ptrsz
, 4) / 4;
164 so
->constbase
.immediate
= constoff
;
170 ir3_context_free(struct ir3_context
*ctx
)
179 /* allocate a n element value array (to be populated by caller) and
182 struct ir3_instruction
**
183 ir3_get_dst_ssa(struct ir3_context
*ctx
, nir_ssa_def
*dst
, unsigned n
)
185 struct ir3_instruction
**value
=
186 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
187 _mesa_hash_table_insert(ctx
->def_ht
, dst
, value
);
191 struct ir3_instruction
**
192 ir3_get_dst(struct ir3_context
*ctx
, nir_dest
*dst
, unsigned n
)
194 struct ir3_instruction
**value
;
197 value
= ir3_get_dst_ssa(ctx
, &dst
->ssa
, n
);
199 value
= ralloc_array(ctx
, struct ir3_instruction
*, n
);
202 /* NOTE: in non-ssa case, we don't really need to store last_dst
203 * but this helps us catch cases where put_dst() call is forgotten
205 compile_assert(ctx
, !ctx
->last_dst
);
206 ctx
->last_dst
= value
;
212 struct ir3_instruction
* const *
213 ir3_get_src(struct ir3_context
*ctx
, nir_src
*src
)
216 struct hash_entry
*entry
;
217 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
218 compile_assert(ctx
, entry
);
221 nir_register
*reg
= src
->reg
.reg
;
222 struct ir3_array
*arr
= ir3_get_array(ctx
, reg
);
223 unsigned num_components
= arr
->r
->num_components
;
224 struct ir3_instruction
*addr
= NULL
;
225 struct ir3_instruction
**value
=
226 ralloc_array(ctx
, struct ir3_instruction
*, num_components
);
228 if (src
->reg
.indirect
)
229 addr
= ir3_get_addr(ctx
, ir3_get_src(ctx
, src
->reg
.indirect
)[0],
230 reg
->num_components
);
232 for (unsigned i
= 0; i
< num_components
; i
++) {
233 unsigned n
= src
->reg
.base_offset
* reg
->num_components
+ i
;
234 compile_assert(ctx
, n
< arr
->length
);
235 value
[i
] = ir3_create_array_load(ctx
, arr
, n
, addr
);
243 put_dst(struct ir3_context
*ctx
, nir_dest
*dst
)
245 unsigned bit_size
= nir_dest_bit_size(*dst
);
248 for (unsigned i
= 0; i
< ctx
->last_dst_n
; i
++) {
249 struct ir3_instruction
*dst
= ctx
->last_dst
[i
];
250 dst
->regs
[0]->flags
|= IR3_REG_HALF
;
251 if (ctx
->last_dst
[i
]->opc
== OPC_META_FO
)
252 dst
->regs
[1]->instr
->regs
[0]->flags
|= IR3_REG_HALF
;
257 nir_register
*reg
= dst
->reg
.reg
;
258 struct ir3_array
*arr
= ir3_get_array(ctx
, reg
);
259 unsigned num_components
= ctx
->last_dst_n
;
260 struct ir3_instruction
*addr
= NULL
;
262 if (dst
->reg
.indirect
)
263 addr
= ir3_get_addr(ctx
, ir3_get_src(ctx
, dst
->reg
.indirect
)[0],
264 reg
->num_components
);
266 for (unsigned i
= 0; i
< num_components
; i
++) {
267 unsigned n
= dst
->reg
.base_offset
* reg
->num_components
+ i
;
268 compile_assert(ctx
, n
< arr
->length
);
269 if (!ctx
->last_dst
[i
])
271 ir3_create_array_store(ctx
, arr
, n
, ctx
->last_dst
[i
], addr
);
274 ralloc_free(ctx
->last_dst
);
276 ctx
->last_dst
= NULL
;
280 struct ir3_instruction
*
281 ir3_create_collect(struct ir3_context
*ctx
, struct ir3_instruction
*const *arr
,
284 struct ir3_block
*block
= ctx
->block
;
285 struct ir3_instruction
*collect
;
290 unsigned flags
= arr
[0]->regs
[0]->flags
& IR3_REG_HALF
;
292 collect
= ir3_instr_create2(block
, OPC_META_FI
, 1 + arrsz
);
293 ir3_reg_create(collect
, 0, flags
); /* dst */
294 for (unsigned i
= 0; i
< arrsz
; i
++) {
295 struct ir3_instruction
*elem
= arr
[i
];
297 /* Since arrays are pre-colored in RA, we can't assume that
298 * things will end up in the right place. (Ie. if a collect
299 * joins elements from two different arrays.) So insert an
302 * We could possibly skip this if all the collected elements
303 * are contiguous elements in a single array.. not sure how
304 * likely that is to happen.
306 * Fixes a problem with glamor shaders, that in effect do
313 * color = texture2D(tex, texcoord);
315 * In this case, texcoord will end up as nir registers (which
316 * translate to ir3 array's of length 1. And we can't assume
317 * the two (or more) arrays will get allocated in consecutive
321 if (elem
->regs
[0]->flags
& IR3_REG_ARRAY
) {
322 type_t type
= (flags
& IR3_REG_HALF
) ? TYPE_U16
: TYPE_U32
;
323 elem
= ir3_MOV(block
, elem
, type
);
326 compile_assert(ctx
, (elem
->regs
[0]->flags
& IR3_REG_HALF
) == flags
);
327 ir3_reg_create(collect
, 0, IR3_REG_SSA
| flags
)->instr
= elem
;
333 /* helper for instructions that produce multiple consecutive scalar
334 * outputs which need to have a split/fanout meta instruction inserted
337 ir3_split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
338 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
340 struct ir3_instruction
*prev
= NULL
;
342 if ((n
== 1) && (src
->regs
[0]->wrmask
== 0x1)) {
347 for (int i
= 0, j
= 0; i
< n
; i
++) {
348 struct ir3_instruction
*split
= ir3_instr_create(block
, OPC_META_FO
);
349 ir3_reg_create(split
, 0, IR3_REG_SSA
);
350 ir3_reg_create(split
, 0, IR3_REG_SSA
)->instr
= src
;
351 split
->fo
.off
= i
+ base
;
354 split
->cp
.left
= prev
;
355 split
->cp
.left_cnt
++;
356 prev
->cp
.right
= split
;
357 prev
->cp
.right_cnt
++;
361 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
367 ir3_context_error(struct ir3_context
*ctx
, const char *format
, ...)
369 struct hash_table
*errors
= NULL
;
371 va_start(ap
, format
);
372 if (ctx
->cur_instr
) {
373 errors
= _mesa_hash_table_create(NULL
,
375 _mesa_key_pointer_equal
);
376 char *msg
= ralloc_vasprintf(errors
, format
, ap
);
377 _mesa_hash_table_insert(errors
, ctx
->cur_instr
, msg
);
379 _debug_vprintf(format
, ap
);
382 nir_print_shader_annotated(ctx
->s
, stdout
, errors
);
388 static struct ir3_instruction
*
389 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
, int align
)
391 struct ir3_instruction
*instr
, *immed
;
393 /* TODO in at least some cases, the backend could probably be
394 * made clever enough to propagate IR3_REG_HALF..
396 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
397 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
404 /* src *= 2 => src <<= 1: */
405 immed
= create_immed(block
, 1);
406 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
408 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
409 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
410 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
414 immed
= create_immed(block
, 3);
415 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
417 instr
= ir3_MULL_U(block
, instr
, 0, immed
, 0);
418 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
419 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
422 /* src *= 4 => src <<= 2: */
423 immed
= create_immed(block
, 2);
424 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
426 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
427 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
428 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
431 unreachable("bad align");
435 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
436 instr
->regs
[0]->num
= regid(REG_A0
, 0);
437 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
438 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
443 /* caches addr values to avoid generating multiple cov/shl/mova
444 * sequences for each use of a given NIR level src as address
446 struct ir3_instruction
*
447 ir3_get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
)
449 struct ir3_instruction
*addr
;
450 unsigned idx
= align
- 1;
452 compile_assert(ctx
, idx
< ARRAY_SIZE(ctx
->addr_ht
));
454 if (!ctx
->addr_ht
[idx
]) {
455 ctx
->addr_ht
[idx
] = _mesa_hash_table_create(ctx
,
456 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
458 struct hash_entry
*entry
;
459 entry
= _mesa_hash_table_search(ctx
->addr_ht
[idx
], src
);
464 addr
= create_addr(ctx
->block
, src
, align
);
465 _mesa_hash_table_insert(ctx
->addr_ht
[idx
], src
, addr
);
470 struct ir3_instruction
*
471 ir3_get_predicate(struct ir3_context
*ctx
, struct ir3_instruction
*src
)
473 struct ir3_block
*b
= ctx
->block
;
474 struct ir3_instruction
*cond
;
476 /* NOTE: only cmps.*.* can write p0.x: */
477 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
478 cond
->cat2
.condition
= IR3_COND_NE
;
480 /* condition always goes in predicate register: */
481 cond
->regs
[0]->num
= regid(REG_P0
, 0);
491 ir3_declare_array(struct ir3_context
*ctx
, nir_register
*reg
)
493 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
494 arr
->id
= ++ctx
->num_arrays
;
495 /* NOTE: sometimes we get non array regs, for example for arrays of
496 * length 1. See fs-const-array-of-struct-of-array.shader_test. So
497 * treat a non-array as if it was an array of length 1.
499 * It would be nice if there was a nir pass to convert arrays of
502 arr
->length
= reg
->num_components
* MAX2(1, reg
->num_array_elems
);
503 compile_assert(ctx
, arr
->length
> 0);
505 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
509 ir3_get_array(struct ir3_context
*ctx
, nir_register
*reg
)
511 list_for_each_entry (struct ir3_array
, arr
, &ctx
->ir
->array_list
, node
) {
515 ir3_context_error(ctx
, "bogus reg: %s\n", reg
->name
);
519 /* relative (indirect) if address!=NULL */
520 struct ir3_instruction
*
521 ir3_create_array_load(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
522 struct ir3_instruction
*address
)
524 struct ir3_block
*block
= ctx
->block
;
525 struct ir3_instruction
*mov
;
526 struct ir3_register
*src
;
528 mov
= ir3_instr_create(block
, OPC_MOV
);
529 mov
->cat1
.src_type
= TYPE_U32
;
530 mov
->cat1
.dst_type
= TYPE_U32
;
531 mov
->barrier_class
= IR3_BARRIER_ARRAY_R
;
532 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_W
;
533 ir3_reg_create(mov
, 0, 0);
534 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
535 COND(address
, IR3_REG_RELATIV
));
536 src
->instr
= arr
->last_write
;
537 src
->size
= arr
->length
;
538 src
->array
.id
= arr
->id
;
539 src
->array
.offset
= n
;
542 ir3_instr_set_address(mov
, address
);
547 /* relative (indirect) if address!=NULL */
549 ir3_create_array_store(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
550 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
552 struct ir3_block
*block
= ctx
->block
;
553 struct ir3_instruction
*mov
;
554 struct ir3_register
*dst
;
556 /* if not relative store, don't create an extra mov, since that
557 * ends up being difficult for cp to remove.
562 src
->barrier_class
|= IR3_BARRIER_ARRAY_W
;
563 src
->barrier_conflict
|= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
565 dst
->flags
|= IR3_REG_ARRAY
;
566 dst
->instr
= arr
->last_write
;
567 dst
->size
= arr
->length
;
568 dst
->array
.id
= arr
->id
;
569 dst
->array
.offset
= n
;
571 arr
->last_write
= src
;
573 array_insert(block
, block
->keeps
, src
);
578 mov
= ir3_instr_create(block
, OPC_MOV
);
579 mov
->cat1
.src_type
= TYPE_U32
;
580 mov
->cat1
.dst_type
= TYPE_U32
;
581 mov
->barrier_class
= IR3_BARRIER_ARRAY_W
;
582 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
583 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
584 COND(address
, IR3_REG_RELATIV
));
585 dst
->instr
= arr
->last_write
;
586 dst
->size
= arr
->length
;
587 dst
->array
.id
= arr
->id
;
588 dst
->array
.offset
= n
;
589 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
592 ir3_instr_set_address(mov
, address
);
594 arr
->last_write
= mov
;
596 /* the array store may only matter to something in an earlier
597 * block (ie. loops), but since arrays are not in SSA, depth
598 * pass won't know this.. so keep all array stores:
600 array_insert(block
, block
->keeps
, mov
);