2 * Copyright (C) 2015-2018 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "ir3_compiler.h"
28 #include "ir3_context.h"
29 #include "ir3_image.h"
30 #include "ir3_shader.h"
34 ir3_context_init(struct ir3_compiler
*compiler
,
35 struct ir3_shader_variant
*so
)
37 struct ir3_context
*ctx
= rzalloc(NULL
, struct ir3_context
);
39 if (compiler
->gpu_id
>= 400) {
40 if (so
->type
== MESA_SHADER_VERTEX
) {
41 ctx
->astc_srgb
= so
->key
.vastc_srgb
;
42 } else if (so
->type
== MESA_SHADER_FRAGMENT
) {
43 ctx
->astc_srgb
= so
->key
.fastc_srgb
;
47 if (so
->type
== MESA_SHADER_VERTEX
) {
48 ctx
->samples
= so
->key
.vsamples
;
49 } else if (so
->type
== MESA_SHADER_FRAGMENT
) {
50 ctx
->samples
= so
->key
.fsamples
;
54 if (compiler
->gpu_id
>= 600) {
55 ctx
->funcs
= &ir3_a6xx_funcs
;
56 } else if (compiler
->gpu_id
>= 400) {
57 ctx
->funcs
= &ir3_a4xx_funcs
;
60 ctx
->compiler
= compiler
;
62 ctx
->def_ht
= _mesa_hash_table_create(ctx
,
63 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
64 ctx
->block_ht
= _mesa_hash_table_create(ctx
,
65 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
67 /* TODO: maybe generate some sort of bitmask of what key
68 * lowers vs what shader has (ie. no need to lower
69 * texture clamp lowering if no texture sample instrs)..
70 * although should be done further up the stack to avoid
71 * creating duplicate variants..
74 ctx
->s
= nir_shader_clone(ctx
, so
->shader
->nir
);
75 if (ir3_key_lowers_nir(&so
->key
))
76 ir3_optimize_nir(so
->shader
, ctx
->s
, &so
->key
);
78 /* this needs to be the last pass run, so do this here instead of
79 * in ir3_optimize_nir():
81 NIR_PASS_V(ctx
->s
, nir_lower_bool_to_int32
);
82 bool progress
= false;
83 NIR_PASS(progress
, ctx
->s
, nir_lower_locals_to_regs
);
85 /* we could need cleanup after lower_locals_to_regs */
88 NIR_PASS(progress
, ctx
->s
, nir_opt_algebraic
);
89 NIR_PASS(progress
, ctx
->s
, nir_opt_constant_folding
);
92 /* We want to lower nir_op_imul as late as possible, to catch also
93 * those generated by earlier passes (e.g, nir_lower_locals_to_regs).
94 * However, we want a final swing of a few passes to have a chance
95 * at optimizing the result.
98 NIR_PASS(progress
, ctx
->s
, ir3_nir_lower_imul
);
101 NIR_PASS(progress
, ctx
->s
, nir_opt_algebraic
);
102 NIR_PASS(progress
, ctx
->s
, nir_opt_copy_prop_vars
);
103 NIR_PASS(progress
, ctx
->s
, nir_opt_dead_write_vars
);
104 NIR_PASS(progress
, ctx
->s
, nir_opt_dce
);
105 NIR_PASS(progress
, ctx
->s
, nir_opt_constant_folding
);
108 /* Enable the texture pre-fetch feature only a4xx onwards. But
109 * only enable it on generations that have been tested:
111 if ((so
->type
== MESA_SHADER_FRAGMENT
) && (compiler
->gpu_id
>= 600))
112 NIR_PASS_V(ctx
->s
, ir3_nir_lower_tex_prefetch
);
114 NIR_PASS_V(ctx
->s
, nir_convert_from_ssa
, true);
116 if (shader_debug_enabled(so
->type
)) {
117 fprintf(stdout
, "NIR (final form) for %s shader %s:\n",
118 ir3_shader_stage(so
), so
->shader
->nir
->info
.name
);
119 nir_print_shader(ctx
->s
, stdout
);
122 ir3_ibo_mapping_init(&so
->image_mapping
, ctx
->s
->info
.num_textures
);
128 ir3_context_free(struct ir3_context
*ctx
)
137 /* allocate a n element value array (to be populated by caller) and
140 struct ir3_instruction
**
141 ir3_get_dst_ssa(struct ir3_context
*ctx
, nir_ssa_def
*dst
, unsigned n
)
143 struct ir3_instruction
**value
=
144 ralloc_array(ctx
->def_ht
, struct ir3_instruction
*, n
);
145 _mesa_hash_table_insert(ctx
->def_ht
, dst
, value
);
149 struct ir3_instruction
**
150 ir3_get_dst(struct ir3_context
*ctx
, nir_dest
*dst
, unsigned n
)
152 struct ir3_instruction
**value
;
155 value
= ir3_get_dst_ssa(ctx
, &dst
->ssa
, n
);
157 value
= ralloc_array(ctx
, struct ir3_instruction
*, n
);
160 /* NOTE: in non-ssa case, we don't really need to store last_dst
161 * but this helps us catch cases where put_dst() call is forgotten
163 compile_assert(ctx
, !ctx
->last_dst
);
164 ctx
->last_dst
= value
;
170 struct ir3_instruction
* const *
171 ir3_get_src(struct ir3_context
*ctx
, nir_src
*src
)
174 struct hash_entry
*entry
;
175 entry
= _mesa_hash_table_search(ctx
->def_ht
, src
->ssa
);
176 compile_assert(ctx
, entry
);
179 nir_register
*reg
= src
->reg
.reg
;
180 struct ir3_array
*arr
= ir3_get_array(ctx
, reg
);
181 unsigned num_components
= arr
->r
->num_components
;
182 struct ir3_instruction
*addr
= NULL
;
183 struct ir3_instruction
**value
=
184 ralloc_array(ctx
, struct ir3_instruction
*, num_components
);
186 if (src
->reg
.indirect
)
187 addr
= ir3_get_addr(ctx
, ir3_get_src(ctx
, src
->reg
.indirect
)[0],
188 reg
->num_components
);
190 for (unsigned i
= 0; i
< num_components
; i
++) {
191 unsigned n
= src
->reg
.base_offset
* reg
->num_components
+ i
;
192 compile_assert(ctx
, n
< arr
->length
);
193 value
[i
] = ir3_create_array_load(ctx
, arr
, n
, addr
, reg
->bit_size
);
201 ir3_put_dst(struct ir3_context
*ctx
, nir_dest
*dst
)
203 unsigned bit_size
= nir_dest_bit_size(*dst
);
205 /* add extra mov if dst value is HIGH reg.. in some cases not all
206 * instructions can read from HIGH regs, in cases where they can
207 * ir3_cp will clean up the extra mov:
209 for (unsigned i
= 0; i
< ctx
->last_dst_n
; i
++) {
210 if (!ctx
->last_dst
[i
])
212 if (ctx
->last_dst
[i
]->regs
[0]->flags
& IR3_REG_HIGH
) {
213 ctx
->last_dst
[i
] = ir3_MOV(ctx
->block
, ctx
->last_dst
[i
], TYPE_U32
);
218 for (unsigned i
= 0; i
< ctx
->last_dst_n
; i
++) {
219 struct ir3_instruction
*dst
= ctx
->last_dst
[i
];
220 dst
->regs
[0]->flags
|= IR3_REG_HALF
;
221 if (ctx
->last_dst
[i
]->opc
== OPC_META_SPLIT
)
222 dst
->regs
[1]->instr
->regs
[0]->flags
|= IR3_REG_HALF
;
227 nir_register
*reg
= dst
->reg
.reg
;
228 struct ir3_array
*arr
= ir3_get_array(ctx
, reg
);
229 unsigned num_components
= ctx
->last_dst_n
;
230 struct ir3_instruction
*addr
= NULL
;
232 if (dst
->reg
.indirect
)
233 addr
= ir3_get_addr(ctx
, ir3_get_src(ctx
, dst
->reg
.indirect
)[0],
234 reg
->num_components
);
236 for (unsigned i
= 0; i
< num_components
; i
++) {
237 unsigned n
= dst
->reg
.base_offset
* reg
->num_components
+ i
;
238 compile_assert(ctx
, n
< arr
->length
);
239 if (!ctx
->last_dst
[i
])
241 ir3_create_array_store(ctx
, arr
, n
, ctx
->last_dst
[i
], addr
);
244 ralloc_free(ctx
->last_dst
);
247 ctx
->last_dst
= NULL
;
252 dest_flags(struct ir3_instruction
*instr
)
254 return instr
->regs
[0]->flags
& (IR3_REG_HALF
| IR3_REG_HIGH
);
257 struct ir3_instruction
*
258 ir3_create_collect(struct ir3_context
*ctx
, struct ir3_instruction
*const *arr
,
261 struct ir3_block
*block
= ctx
->block
;
262 struct ir3_instruction
*collect
;
267 unsigned flags
= dest_flags(arr
[0]);
269 collect
= ir3_instr_create2(block
, OPC_META_COLLECT
, 1 + arrsz
);
270 __ssa_dst(collect
)->flags
|= flags
;
271 for (unsigned i
= 0; i
< arrsz
; i
++) {
272 struct ir3_instruction
*elem
= arr
[i
];
274 /* Since arrays are pre-colored in RA, we can't assume that
275 * things will end up in the right place. (Ie. if a collect
276 * joins elements from two different arrays.) So insert an
279 * We could possibly skip this if all the collected elements
280 * are contiguous elements in a single array.. not sure how
281 * likely that is to happen.
283 * Fixes a problem with glamor shaders, that in effect do
290 * color = texture2D(tex, texcoord);
292 * In this case, texcoord will end up as nir registers (which
293 * translate to ir3 array's of length 1. And we can't assume
294 * the two (or more) arrays will get allocated in consecutive
298 if (elem
->regs
[0]->flags
& IR3_REG_ARRAY
) {
299 type_t type
= (flags
& IR3_REG_HALF
) ? TYPE_U16
: TYPE_U32
;
300 elem
= ir3_MOV(block
, elem
, type
);
303 compile_assert(ctx
, dest_flags(elem
) == flags
);
304 __ssa_src(collect
, elem
, flags
);
307 collect
->regs
[0]->wrmask
= MASK(arrsz
);
312 /* helper for instructions that produce multiple consecutive scalar
313 * outputs which need to have a split meta instruction inserted
316 ir3_split_dest(struct ir3_block
*block
, struct ir3_instruction
**dst
,
317 struct ir3_instruction
*src
, unsigned base
, unsigned n
)
319 struct ir3_instruction
*prev
= NULL
;
321 if ((n
== 1) && (src
->regs
[0]->wrmask
== 0x1)) {
326 if (src
->opc
== OPC_META_COLLECT
) {
327 debug_assert((base
+ n
) < src
->regs_count
);
329 for (int i
= 0; i
< n
; i
++) {
330 dst
[i
] = ssa(src
->regs
[i
+ base
+ 1]);
336 unsigned flags
= dest_flags(src
);
338 for (int i
= 0, j
= 0; i
< n
; i
++) {
339 struct ir3_instruction
*split
=
340 ir3_instr_create(block
, OPC_META_SPLIT
);
341 __ssa_dst(split
)->flags
|= flags
;
342 __ssa_src(split
, src
, flags
);
343 split
->split
.off
= i
+ base
;
346 split
->cp
.left
= prev
;
347 split
->cp
.left_cnt
++;
348 prev
->cp
.right
= split
;
349 prev
->cp
.right_cnt
++;
353 if (src
->regs
[0]->wrmask
& (1 << (i
+ base
)))
359 ir3_context_error(struct ir3_context
*ctx
, const char *format
, ...)
361 struct hash_table
*errors
= NULL
;
363 va_start(ap
, format
);
364 if (ctx
->cur_instr
) {
365 errors
= _mesa_hash_table_create(NULL
,
367 _mesa_key_pointer_equal
);
368 char *msg
= ralloc_vasprintf(errors
, format
, ap
);
369 _mesa_hash_table_insert(errors
, ctx
->cur_instr
, msg
);
371 _debug_vprintf(format
, ap
);
374 nir_print_shader_annotated(ctx
->s
, stdout
, errors
);
380 static struct ir3_instruction
*
381 create_addr(struct ir3_block
*block
, struct ir3_instruction
*src
, int align
)
383 struct ir3_instruction
*instr
, *immed
;
385 /* TODO in at least some cases, the backend could probably be
386 * made clever enough to propagate IR3_REG_HALF..
388 instr
= ir3_COV(block
, src
, TYPE_U32
, TYPE_S16
);
389 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
396 /* src *= 2 => src <<= 1: */
397 immed
= create_immed(block
, 1);
398 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
400 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
401 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
402 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
406 immed
= create_immed(block
, 3);
407 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
409 instr
= ir3_MULL_U(block
, instr
, 0, immed
, 0);
410 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
411 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
414 /* src *= 4 => src <<= 2: */
415 immed
= create_immed(block
, 2);
416 immed
->regs
[0]->flags
|= IR3_REG_HALF
;
418 instr
= ir3_SHL_B(block
, instr
, 0, immed
, 0);
419 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
420 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
423 unreachable("bad align");
427 instr
= ir3_MOV(block
, instr
, TYPE_S16
);
428 instr
->regs
[0]->num
= regid(REG_A0
, 0);
429 instr
->regs
[0]->flags
&= ~IR3_REG_SSA
;
430 instr
->regs
[0]->flags
|= IR3_REG_HALF
;
431 instr
->regs
[1]->flags
|= IR3_REG_HALF
;
436 /* caches addr values to avoid generating multiple cov/shl/mova
437 * sequences for each use of a given NIR level src as address
439 struct ir3_instruction
*
440 ir3_get_addr(struct ir3_context
*ctx
, struct ir3_instruction
*src
, int align
)
442 struct ir3_instruction
*addr
;
443 unsigned idx
= align
- 1;
445 compile_assert(ctx
, idx
< ARRAY_SIZE(ctx
->addr_ht
));
447 if (!ctx
->addr_ht
[idx
]) {
448 ctx
->addr_ht
[idx
] = _mesa_hash_table_create(ctx
,
449 _mesa_hash_pointer
, _mesa_key_pointer_equal
);
451 struct hash_entry
*entry
;
452 entry
= _mesa_hash_table_search(ctx
->addr_ht
[idx
], src
);
457 addr
= create_addr(ctx
->block
, src
, align
);
458 _mesa_hash_table_insert(ctx
->addr_ht
[idx
], src
, addr
);
463 struct ir3_instruction
*
464 ir3_get_predicate(struct ir3_context
*ctx
, struct ir3_instruction
*src
)
466 struct ir3_block
*b
= ctx
->block
;
467 struct ir3_instruction
*cond
;
469 /* NOTE: only cmps.*.* can write p0.x: */
470 cond
= ir3_CMPS_S(b
, src
, 0, create_immed(b
, 0), 0);
471 cond
->cat2
.condition
= IR3_COND_NE
;
473 /* condition always goes in predicate register: */
474 cond
->regs
[0]->num
= regid(REG_P0
, 0);
475 cond
->regs
[0]->flags
&= ~IR3_REG_SSA
;
485 ir3_declare_array(struct ir3_context
*ctx
, nir_register
*reg
)
487 struct ir3_array
*arr
= rzalloc(ctx
, struct ir3_array
);
488 arr
->id
= ++ctx
->num_arrays
;
489 /* NOTE: sometimes we get non array regs, for example for arrays of
490 * length 1. See fs-const-array-of-struct-of-array.shader_test. So
491 * treat a non-array as if it was an array of length 1.
493 * It would be nice if there was a nir pass to convert arrays of
496 arr
->length
= reg
->num_components
* MAX2(1, reg
->num_array_elems
);
497 compile_assert(ctx
, arr
->length
> 0);
499 list_addtail(&arr
->node
, &ctx
->ir
->array_list
);
503 ir3_get_array(struct ir3_context
*ctx
, nir_register
*reg
)
505 foreach_array (arr
, &ctx
->ir
->array_list
) {
509 ir3_context_error(ctx
, "bogus reg: %s\n", reg
->name
);
513 /* relative (indirect) if address!=NULL */
514 struct ir3_instruction
*
515 ir3_create_array_load(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
516 struct ir3_instruction
*address
, unsigned bitsize
)
518 struct ir3_block
*block
= ctx
->block
;
519 struct ir3_instruction
*mov
;
520 struct ir3_register
*src
;
523 mov
= ir3_instr_create(block
, OPC_MOV
);
525 mov
->cat1
.src_type
= TYPE_U16
;
526 mov
->cat1
.dst_type
= TYPE_U16
;
527 flags
|= IR3_REG_HALF
;
529 mov
->cat1
.src_type
= TYPE_U32
;
530 mov
->cat1
.dst_type
= TYPE_U32
;
533 mov
->barrier_class
= IR3_BARRIER_ARRAY_R
;
534 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_W
;
535 __ssa_dst(mov
)->flags
|= flags
;
536 src
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
537 COND(address
, IR3_REG_RELATIV
) | flags
);
538 src
->instr
= arr
->last_write
;
539 src
->size
= arr
->length
;
540 src
->array
.id
= arr
->id
;
541 src
->array
.offset
= n
;
544 ir3_instr_set_address(mov
, address
);
549 /* relative (indirect) if address!=NULL */
551 ir3_create_array_store(struct ir3_context
*ctx
, struct ir3_array
*arr
, int n
,
552 struct ir3_instruction
*src
, struct ir3_instruction
*address
)
554 struct ir3_block
*block
= ctx
->block
;
555 struct ir3_instruction
*mov
;
556 struct ir3_register
*dst
;
558 /* if not relative store, don't create an extra mov, since that
559 * ends up being difficult for cp to remove.
561 * Also, don't skip the mov if the src is meta (like fanout/split),
562 * since that creates a situation that RA can't really handle properly.
564 if (!address
&& !is_meta(src
)) {
567 src
->barrier_class
|= IR3_BARRIER_ARRAY_W
;
568 src
->barrier_conflict
|= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
570 dst
->flags
|= IR3_REG_ARRAY
;
571 dst
->instr
= arr
->last_write
;
572 dst
->size
= arr
->length
;
573 dst
->array
.id
= arr
->id
;
574 dst
->array
.offset
= n
;
576 arr
->last_write
= src
;
578 array_insert(block
, block
->keeps
, src
);
583 mov
= ir3_instr_create(block
, OPC_MOV
);
584 mov
->cat1
.src_type
= TYPE_U32
;
585 mov
->cat1
.dst_type
= TYPE_U32
;
586 mov
->barrier_class
= IR3_BARRIER_ARRAY_W
;
587 mov
->barrier_conflict
= IR3_BARRIER_ARRAY_R
| IR3_BARRIER_ARRAY_W
;
588 dst
= ir3_reg_create(mov
, 0, IR3_REG_ARRAY
|
589 COND(address
, IR3_REG_RELATIV
));
590 dst
->instr
= arr
->last_write
;
591 dst
->size
= arr
->length
;
592 dst
->array
.id
= arr
->id
;
593 dst
->array
.offset
= n
;
594 ir3_reg_create(mov
, 0, IR3_REG_SSA
)->instr
= src
;
597 ir3_instr_set_address(mov
, address
);
599 arr
->last_write
= mov
;
601 /* the array store may only matter to something in an earlier
602 * block (ie. loops), but since arrays are not in SSA, depth
603 * pass won't know this.. so keep all array stores:
605 array_insert(block
, block
->keeps
, mov
);