2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
28 #include "util/half_float.h"
29 #include "util/u_math.h"
32 #include "ir3_compiler.h"
33 #include "ir3_shader.h"
36 do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
44 struct ir3_shader_variant
*so
;
47 /* is it a type preserving mov, with ok flags? */
48 static bool is_eligible_mov(struct ir3_instruction
*instr
, bool allow_flags
)
50 if (is_same_type_mov(instr
)) {
51 struct ir3_register
*dst
= instr
->regs
[0];
52 struct ir3_register
*src
= instr
->regs
[1];
53 struct ir3_instruction
*src_instr
= ssa(src
);
55 /* only if mov src is SSA (not const/immed): */
60 if (dst
->flags
& IR3_REG_RELATIV
)
62 if (src
->flags
& IR3_REG_RELATIV
)
65 if (src
->flags
& IR3_REG_ARRAY
)
69 if (src
->flags
& (IR3_REG_FABS
| IR3_REG_FNEG
|
70 IR3_REG_SABS
| IR3_REG_SNEG
| IR3_REG_BNOT
))
73 /* TODO: remove this hack: */
74 if (src_instr
->opc
== OPC_META_FO
)
82 static unsigned cp_flags(unsigned flags
)
84 /* only considering these flags (at least for now): */
85 flags
&= (IR3_REG_CONST
| IR3_REG_IMMED
|
86 IR3_REG_FNEG
| IR3_REG_FABS
|
87 IR3_REG_SNEG
| IR3_REG_SABS
|
88 IR3_REG_BNOT
| IR3_REG_RELATIV
);
92 static bool valid_flags(struct ir3_instruction
*instr
, unsigned n
,
95 struct ir3_compiler
*compiler
= instr
->block
->shader
->compiler
;
98 if ((flags
& IR3_REG_HIGH
) &&
99 (opc_cat(instr
->opc
) > 1) &&
100 (compiler
->gpu_id
>= 600))
103 flags
= cp_flags(flags
);
105 /* If destination is indirect, then source cannot be.. at least
108 if ((instr
->regs
[0]->flags
& IR3_REG_RELATIV
) &&
109 (flags
& IR3_REG_RELATIV
))
112 if (flags
& IR3_REG_RELATIV
) {
113 /* TODO need to test on earlier gens.. pretty sure the earlier
114 * problem was just that we didn't check that the src was from
115 * same block (since we can't propagate address register values
116 * across blocks currently)
118 if (compiler
->gpu_id
< 600)
121 /* NOTE in the special try_swap_mad_two_srcs() case we can be
122 * called on a src that has already had an indirect load folded
123 * in, in which case ssa() returns NULL
125 struct ir3_instruction
*src
= ssa(instr
->regs
[n
+1]);
126 if (src
&& src
->address
->block
!= instr
->block
)
130 switch (opc_cat(instr
->opc
)) {
132 valid_flags
= IR3_REG_IMMED
| IR3_REG_CONST
| IR3_REG_RELATIV
;
133 if (flags
& ~valid_flags
)
137 valid_flags
= ir3_cat2_absneg(instr
->opc
) |
138 IR3_REG_CONST
| IR3_REG_RELATIV
;
140 if (ir3_cat2_int(instr
->opc
))
141 valid_flags
|= IR3_REG_IMMED
;
143 if (flags
& ~valid_flags
)
146 if (flags
& (IR3_REG_CONST
| IR3_REG_IMMED
)) {
147 unsigned m
= (n
^ 1) + 1;
148 /* cannot deal w/ const in both srcs:
149 * (note that some cat2 actually only have a single src)
151 if (m
< instr
->regs_count
) {
152 struct ir3_register
*reg
= instr
->regs
[m
];
153 if ((flags
& IR3_REG_CONST
) && (reg
->flags
& IR3_REG_CONST
))
155 if ((flags
& IR3_REG_IMMED
) && (reg
->flags
& IR3_REG_IMMED
))
158 /* cannot be const + ABS|NEG: */
159 if (flags
& (IR3_REG_FABS
| IR3_REG_FNEG
|
160 IR3_REG_SABS
| IR3_REG_SNEG
| IR3_REG_BNOT
))
165 valid_flags
= ir3_cat3_absneg(instr
->opc
) |
166 IR3_REG_CONST
| IR3_REG_RELATIV
;
168 if (flags
& ~valid_flags
)
171 if (flags
& (IR3_REG_CONST
| IR3_REG_RELATIV
)) {
172 /* cannot deal w/ const/relativ in 2nd src: */
177 if (flags
& IR3_REG_CONST
) {
178 /* cannot be const + ABS|NEG: */
179 if (flags
& (IR3_REG_FABS
| IR3_REG_FNEG
|
180 IR3_REG_SABS
| IR3_REG_SNEG
| IR3_REG_BNOT
))
185 /* seems like blob compiler avoids const as src.. */
186 /* TODO double check if this is still the case on a4xx */
187 if (flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
189 if (flags
& (IR3_REG_SABS
| IR3_REG_SNEG
))
193 /* no flags allowed */
198 valid_flags
= IR3_REG_IMMED
;
199 if (flags
& ~valid_flags
)
202 if (flags
& IR3_REG_IMMED
) {
203 /* doesn't seem like we can have immediate src for store
206 * TODO this restriction could also apply to load instructions,
207 * but for load instructions this arg is the address (and not
208 * really sure any good way to test a hard-coded immed addr src)
210 if (is_store(instr
) && (n
== 1))
213 if ((instr
->opc
== OPC_LDL
) && (n
!= 1))
216 if ((instr
->opc
== OPC_STL
) && (n
!= 2))
219 /* disallow CP into anything but the SSBO slot argument for
222 if (is_atomic(instr
->opc
) && (n
!= 0))
225 if (is_atomic(instr
->opc
) && !(instr
->flags
& IR3_INSTR_G
))
228 /* as with atomics, ldib on a6xx can only have immediate for
231 if ((instr
->opc
== OPC_LDIB
) && (n
!= 0))
241 /* propagate register flags from src to dst.. negates need special
242 * handling to cancel each other out.
244 static void combine_flags(unsigned *dstflags
, struct ir3_instruction
*src
)
246 unsigned srcflags
= src
->regs
[1]->flags
;
248 /* if what we are combining into already has (abs) flags,
249 * we can drop (neg) from src:
251 if (*dstflags
& IR3_REG_FABS
)
252 srcflags
&= ~IR3_REG_FNEG
;
253 if (*dstflags
& IR3_REG_SABS
)
254 srcflags
&= ~IR3_REG_SNEG
;
256 if (srcflags
& IR3_REG_FABS
)
257 *dstflags
|= IR3_REG_FABS
;
258 if (srcflags
& IR3_REG_SABS
)
259 *dstflags
|= IR3_REG_SABS
;
260 if (srcflags
& IR3_REG_FNEG
)
261 *dstflags
^= IR3_REG_FNEG
;
262 if (srcflags
& IR3_REG_SNEG
)
263 *dstflags
^= IR3_REG_SNEG
;
264 if (srcflags
& IR3_REG_BNOT
)
265 *dstflags
^= IR3_REG_BNOT
;
267 *dstflags
&= ~IR3_REG_SSA
;
268 *dstflags
|= srcflags
& IR3_REG_SSA
;
269 *dstflags
|= srcflags
& IR3_REG_CONST
;
270 *dstflags
|= srcflags
& IR3_REG_IMMED
;
271 *dstflags
|= srcflags
& IR3_REG_RELATIV
;
272 *dstflags
|= srcflags
& IR3_REG_ARRAY
;
273 *dstflags
|= srcflags
& IR3_REG_HIGH
;
275 /* if src of the src is boolean we can drop the (abs) since we know
276 * the source value is already a postitive integer. This cleans
277 * up the absnegs that get inserted when converting between nir and
278 * native boolean (see ir3_b2n/n2b)
280 struct ir3_instruction
*srcsrc
= ssa(src
->regs
[1]);
281 if (srcsrc
&& is_bool(srcsrc
))
282 *dstflags
&= ~IR3_REG_SABS
;
285 static struct ir3_register
*
286 lower_immed(struct ir3_cp_ctx
*ctx
, struct ir3_register
*reg
, unsigned new_flags
, bool f_opcode
)
288 unsigned swiz
, idx
, i
;
290 reg
= ir3_reg_clone(ctx
->shader
, reg
);
292 /* in some cases, there are restrictions on (abs)/(neg) plus const..
293 * so just evaluate those and clear the flags:
295 if (new_flags
& IR3_REG_SABS
) {
296 reg
->iim_val
= abs(reg
->iim_val
);
297 new_flags
&= ~IR3_REG_SABS
;
300 if (new_flags
& IR3_REG_FABS
) {
301 reg
->fim_val
= fabs(reg
->fim_val
);
302 new_flags
&= ~IR3_REG_FABS
;
305 if (new_flags
& IR3_REG_SNEG
) {
306 reg
->iim_val
= -reg
->iim_val
;
307 new_flags
&= ~IR3_REG_SNEG
;
310 if (new_flags
& IR3_REG_FNEG
) {
311 reg
->fim_val
= -reg
->fim_val
;
312 new_flags
&= ~IR3_REG_FNEG
;
315 /* Reallocate for 4 more elements whenever it's necessary */
316 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
317 if (const_state
->immediate_idx
== const_state
->immediates_size
* 4) {
318 const_state
->immediates_size
+= 4;
319 const_state
->immediates
= realloc (const_state
->immediates
,
320 const_state
->immediates_size
* sizeof(const_state
->immediates
[0]));
323 for (i
= 0; i
< const_state
->immediate_idx
; i
++) {
327 if (const_state
->immediates
[idx
].val
[swiz
] == reg
->uim_val
) {
332 if (i
== const_state
->immediate_idx
) {
333 /* need to generate a new immediate: */
337 /* Half constant registers seems to handle only 32-bit values
338 * within floating-point opcodes. So convert back to 32-bit values. */
339 if (f_opcode
&& (new_flags
& IR3_REG_HALF
)) {
340 reg
->uim_val
= fui(_mesa_half_to_float(reg
->uim_val
));
343 const_state
->immediates
[idx
].val
[swiz
] = reg
->uim_val
;
344 const_state
->immediates_count
= idx
+ 1;
345 const_state
->immediate_idx
++;
348 new_flags
&= ~IR3_REG_IMMED
;
349 new_flags
|= IR3_REG_CONST
;
350 reg
->flags
= new_flags
;
351 reg
->num
= i
+ (4 * const_state
->offsets
.immediate
);
357 unuse(struct ir3_instruction
*instr
)
359 debug_assert(instr
->use_count
> 0);
361 if (--instr
->use_count
== 0) {
362 struct ir3_block
*block
= instr
->block
;
364 instr
->barrier_class
= 0;
365 instr
->barrier_conflict
= 0;
367 /* we don't want to remove anything in keeps (which could
368 * be things like array store's)
370 for (unsigned i
= 0; i
< block
->keeps_count
; i
++) {
371 debug_assert(block
->keeps
[i
] != instr
);
377 * Handles the special case of the 2nd src (n == 1) to "normal" mad
378 * instructions, which cannot reference a constant. See if it is
379 * possible to swap the 1st and 2nd sources.
382 try_swap_mad_two_srcs(struct ir3_instruction
*instr
, unsigned new_flags
)
384 if (!is_mad(instr
->opc
))
387 /* NOTE: pre-swap first two src's before valid_flags(),
388 * which might try to dereference the n'th src:
390 swap(instr
->regs
[0 + 1], instr
->regs
[1 + 1]);
393 /* can we propagate mov if we move 2nd src to first? */
394 valid_flags(instr
, 0, new_flags
) &&
395 /* and does first src fit in second slot? */
396 valid_flags(instr
, 1, instr
->regs
[1 + 1]->flags
);
399 /* put things back the way they were: */
400 swap(instr
->regs
[0 + 1], instr
->regs
[1 + 1]);
401 } /* otherwise leave things swapped */
407 * Handle cp for a given src register. This additionally handles
408 * the cases of collapsing immedate/const (which replace the src
409 * register with a non-ssa src) or collapsing mov's from relative
410 * src (which needs to also fixup the address src reference by the
414 reg_cp(struct ir3_cp_ctx
*ctx
, struct ir3_instruction
*instr
,
415 struct ir3_register
*reg
, unsigned n
)
417 struct ir3_instruction
*src
= ssa(reg
);
419 if (is_eligible_mov(src
, true)) {
420 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */
421 struct ir3_register
*src_reg
= src
->regs
[1];
422 unsigned new_flags
= reg
->flags
;
424 combine_flags(&new_flags
, src
);
426 if (valid_flags(instr
, n
, new_flags
)) {
427 if (new_flags
& IR3_REG_ARRAY
) {
428 debug_assert(!(reg
->flags
& IR3_REG_ARRAY
));
429 reg
->array
= src_reg
->array
;
431 reg
->flags
= new_flags
;
432 reg
->instr
= ssa(src_reg
);
434 instr
->barrier_class
|= src
->barrier_class
;
435 instr
->barrier_conflict
|= src
->barrier_conflict
;
438 reg
->instr
->use_count
++;
441 } else if (is_same_type_mov(src
) &&
442 /* cannot collapse const/immed/etc into meta instrs: */
444 /* immed/const/etc cases, which require some special handling: */
445 struct ir3_register
*src_reg
= src
->regs
[1];
446 unsigned new_flags
= reg
->flags
;
448 combine_flags(&new_flags
, src
);
450 if (!valid_flags(instr
, n
, new_flags
)) {
451 /* See if lowering an immediate to const would help. */
452 if (valid_flags(instr
, n
, (new_flags
& ~IR3_REG_IMMED
) | IR3_REG_CONST
)) {
453 bool f_opcode
= (ir3_cat2_float(instr
->opc
) ||
454 ir3_cat3_float(instr
->opc
)) ? true : false;
456 debug_assert(new_flags
& IR3_REG_IMMED
);
458 instr
->regs
[n
+ 1] = lower_immed(ctx
, src_reg
, new_flags
, f_opcode
);
462 /* special case for "normal" mad instructions, we can
463 * try swapping the first two args if that fits better.
465 * the "plain" MAD's (ie. the ones that don't shift first
466 * src prior to multiply) can swap their first two srcs if
467 * src[0] is !CONST and src[1] is CONST:
469 if ((n
== 1) && try_swap_mad_two_srcs(instr
, new_flags
)) {
470 /* we swapped, so now we are dealing with 1st src: */
477 /* Here we handle the special case of mov from
478 * CONST and/or RELATIV. These need to be handled
479 * specially, because in the case of move from CONST
480 * there is no src ir3_instruction so we need to
481 * replace the ir3_register. And in the case of
482 * RELATIV we need to handle the address register
485 if (src_reg
->flags
& IR3_REG_CONST
) {
486 /* an instruction cannot reference two different
489 if ((src_reg
->flags
& IR3_REG_RELATIV
) &&
490 conflicts(instr
->address
, reg
->instr
->address
))
493 /* This seems to be a hw bug, or something where the timings
494 * just somehow don't work out. This restriction may only
495 * apply if the first src is also CONST.
497 if ((opc_cat(instr
->opc
) == 3) && (n
== 2) &&
498 (src_reg
->flags
& IR3_REG_RELATIV
) &&
499 (src_reg
->array
.offset
== 0))
502 src_reg
= ir3_reg_clone(instr
->block
->shader
, src_reg
);
503 src_reg
->flags
= new_flags
;
504 instr
->regs
[n
+1] = src_reg
;
506 if (src_reg
->flags
& IR3_REG_RELATIV
)
507 ir3_instr_set_address(instr
, reg
->instr
->address
);
512 if ((src_reg
->flags
& IR3_REG_RELATIV
) &&
513 !conflicts(instr
->address
, reg
->instr
->address
)) {
514 src_reg
= ir3_reg_clone(instr
->block
->shader
, src_reg
);
515 src_reg
->flags
= new_flags
;
516 instr
->regs
[n
+1] = src_reg
;
517 ir3_instr_set_address(instr
, reg
->instr
->address
);
522 /* NOTE: seems we can only do immed integers, so don't
523 * need to care about float. But we do need to handle
524 * abs/neg *before* checking that the immediate requires
525 * few enough bits to encode:
527 * TODO: do we need to do something to avoid accidentally
528 * catching a float immed?
530 if (src_reg
->flags
& IR3_REG_IMMED
) {
531 int32_t iim_val
= src_reg
->iim_val
;
533 debug_assert((opc_cat(instr
->opc
) == 1) ||
534 (opc_cat(instr
->opc
) == 6) ||
535 ir3_cat2_int(instr
->opc
) ||
536 (is_mad(instr
->opc
) && (n
== 0)));
538 if (new_flags
& IR3_REG_SABS
)
539 iim_val
= abs(iim_val
);
541 if (new_flags
& IR3_REG_SNEG
)
544 if (new_flags
& IR3_REG_BNOT
)
547 /* other than category 1 (mov) we can only encode up to 10 bits: */
548 if ((instr
->opc
== OPC_MOV
) ||
549 !((iim_val
& ~0x3ff) && (-iim_val
& ~0x3ff))) {
550 new_flags
&= ~(IR3_REG_SABS
| IR3_REG_SNEG
| IR3_REG_BNOT
);
551 src_reg
= ir3_reg_clone(instr
->block
->shader
, src_reg
);
552 src_reg
->flags
= new_flags
;
553 src_reg
->iim_val
= iim_val
;
554 instr
->regs
[n
+1] = src_reg
;
555 } else if (valid_flags(instr
, n
, (new_flags
& ~IR3_REG_IMMED
) | IR3_REG_CONST
)) {
556 bool f_opcode
= (ir3_cat2_float(instr
->opc
) ||
557 ir3_cat3_float(instr
->opc
)) ? true : false;
559 /* See if lowering an immediate to const would help. */
560 instr
->regs
[n
+1] = lower_immed(ctx
, src_reg
, new_flags
, f_opcode
);
567 /* Handle special case of eliminating output mov, and similar cases where
568 * there isn't a normal "consuming" instruction. In this case we cannot
569 * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
572 static struct ir3_instruction
*
573 eliminate_output_mov(struct ir3_instruction
*instr
)
575 if (is_eligible_mov(instr
, false)) {
576 struct ir3_register
*reg
= instr
->regs
[1];
577 if (!(reg
->flags
& IR3_REG_ARRAY
)) {
578 struct ir3_instruction
*src_instr
= ssa(reg
);
579 debug_assert(src_instr
);
587 * Find instruction src's which are mov's that can be collapsed, replacing
588 * the mov dst with the mov src
591 instr_cp(struct ir3_cp_ctx
*ctx
, struct ir3_instruction
*instr
)
593 struct ir3_register
*reg
;
595 if (instr
->regs_count
== 0)
598 if (ir3_instr_check_mark(instr
))
601 /* walk down the graph from each src: */
602 foreach_src_n(reg
, n
, instr
) {
603 struct ir3_instruction
*src
= ssa(reg
);
610 /* TODO non-indirect access we could figure out which register
611 * we actually want and allow cp..
613 if (reg
->flags
& IR3_REG_ARRAY
)
616 /* Don't CP absneg into meta instructions, that won't end well: */
617 if (is_meta(instr
) && (src
->opc
!= OPC_MOV
))
620 reg_cp(ctx
, instr
, reg
, n
);
623 if (instr
->regs
[0]->flags
& IR3_REG_ARRAY
) {
624 struct ir3_instruction
*src
= ssa(instr
->regs
[0]);
629 if (instr
->address
) {
630 instr_cp(ctx
, instr
->address
);
631 ir3_instr_set_address(instr
, eliminate_output_mov(instr
->address
));
634 /* we can end up with extra cmps.s from frontend, which uses a
636 * cmps.s p0.x, cond, 0
638 * as a way to mov into the predicate register. But frequently 'cond'
639 * is itself a cmps.s/cmps.f/cmps.u. So detect this special case and
640 * just re-write the instruction writing predicate register to get rid
641 * of the double cmps.
643 if ((instr
->opc
== OPC_CMPS_S
) &&
644 (instr
->regs
[0]->num
== regid(REG_P0
, 0)) &&
645 ssa(instr
->regs
[1]) &&
646 (instr
->regs
[2]->flags
& IR3_REG_IMMED
) &&
647 (instr
->regs
[2]->iim_val
== 0)) {
648 struct ir3_instruction
*cond
= ssa(instr
->regs
[1]);
653 instr
->opc
= cond
->opc
;
654 instr
->flags
= cond
->flags
;
655 instr
->cat2
= cond
->cat2
;
656 ir3_instr_set_address(instr
, cond
->address
);
657 instr
->regs
[1] = cond
->regs
[1];
658 instr
->regs
[2] = cond
->regs
[2];
659 instr
->barrier_class
|= cond
->barrier_class
;
660 instr
->barrier_conflict
|= cond
->barrier_conflict
;
668 /* Handle converting a sam.s2en (taking samp/tex idx params via
669 * register) into a normal sam (encoding immediate samp/tex idx)
670 * if they are immediate. This saves some instructions and regs
671 * in the common case where we know samp/tex at compile time:
673 if (is_tex(instr
) && (instr
->flags
& IR3_INSTR_S2EN
) &&
674 !(ir3_shader_debug
& IR3_DBG_FORCES2EN
)) {
675 /* The first src will be a fan-in (collect), if both of it's
676 * two sources are mov from imm, then we can
678 struct ir3_instruction
*samp_tex
= ssa(instr
->regs
[1]);
680 debug_assert(samp_tex
->opc
== OPC_META_FI
);
682 struct ir3_instruction
*samp
= ssa(samp_tex
->regs
[1]);
683 struct ir3_instruction
*tex
= ssa(samp_tex
->regs
[2]);
685 if ((samp
->opc
== OPC_MOV
) &&
686 (samp
->regs
[1]->flags
& IR3_REG_IMMED
) &&
687 (tex
->opc
== OPC_MOV
) &&
688 (tex
->regs
[1]->flags
& IR3_REG_IMMED
)) {
689 instr
->flags
&= ~IR3_INSTR_S2EN
;
690 instr
->cat5
.samp
= samp
->regs
[1]->iim_val
;
691 instr
->cat5
.tex
= tex
->regs
[1]->iim_val
;
692 instr
->regs
[1]->instr
= NULL
;
698 ir3_cp(struct ir3
*ir
, struct ir3_shader_variant
*so
)
700 struct ir3_cp_ctx ctx
= {
705 /* This is a bit annoying, and probably wouldn't be necessary if we
706 * tracked a reverse link from producing instruction to consumer.
707 * But we need to know when we've eliminated the last consumer of
708 * a mov, so we need to do a pass to first count consumers of a
711 list_for_each_entry (struct ir3_block
, block
, &ir
->block_list
, node
) {
712 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
713 struct ir3_instruction
*src
;
715 /* by the way, we don't account for false-dep's, so the CP
716 * pass should always happen before false-dep's are inserted
718 debug_assert(instr
->deps_count
== 0);
720 foreach_ssa_src(src
, instr
) {
728 for (unsigned i
= 0; i
< ir
->noutputs
; i
++) {
729 if (ir
->outputs
[i
]) {
730 instr_cp(&ctx
, ir
->outputs
[i
]);
731 ir
->outputs
[i
] = eliminate_output_mov(ir
->outputs
[i
]);
735 list_for_each_entry (struct ir3_block
, block
, &ir
->block_list
, node
) {
736 if (block
->condition
) {
737 instr_cp(&ctx
, block
->condition
);
738 block
->condition
= eliminate_output_mov(block
->condition
);
741 for (unsigned i
= 0; i
< block
->keeps_count
; i
++) {
742 instr_cp(&ctx
, block
->keeps
[i
]);
743 block
->keeps
[i
] = eliminate_output_mov(block
->keeps
[i
]);