2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
28 #include "util/half_float.h"
29 #include "util/u_math.h"
32 #include "ir3_compiler.h"
33 #include "ir3_shader.h"
36 do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
44 struct ir3_shader_variant
*so
;
48 /* is it a type preserving mov, with ok flags?
50 * @instr: the mov to consider removing
51 * @dst_instr: the instruction consuming the mov (instr)
53 * TODO maybe drop allow_flags since this is only false when dst is
56 static bool is_eligible_mov(struct ir3_instruction
*instr
,
57 struct ir3_instruction
*dst_instr
, bool allow_flags
)
59 if (is_same_type_mov(instr
)) {
60 struct ir3_register
*dst
= instr
->regs
[0];
61 struct ir3_register
*src
= instr
->regs
[1];
62 struct ir3_instruction
*src_instr
= ssa(src
);
64 /* only if mov src is SSA (not const/immed): */
69 if (dst
->flags
& IR3_REG_RELATIV
)
71 if (src
->flags
& IR3_REG_RELATIV
)
74 if (src
->flags
& IR3_REG_ARRAY
)
78 if (src
->flags
& (IR3_REG_FABS
| IR3_REG_FNEG
|
79 IR3_REG_SABS
| IR3_REG_SNEG
| IR3_REG_BNOT
))
82 /* If src is coming from fanout/split (ie. one component of a
83 * texture fetch, etc) and we have constraints on swizzle of
84 * destination, then skip it.
86 * We could possibly do a bit better, and copy-propagation if
87 * we can CP all components that are being fanned out.
89 if (src_instr
->opc
== OPC_META_SPLIT
) {
92 if (dst_instr
->opc
== OPC_META_COLLECT
)
94 if (dst_instr
->cp
.left
|| dst_instr
->cp
.right
)
103 /* propagate register flags from src to dst.. negates need special
104 * handling to cancel each other out.
106 static void combine_flags(unsigned *dstflags
, struct ir3_instruction
*src
)
108 unsigned srcflags
= src
->regs
[1]->flags
;
110 /* if what we are combining into already has (abs) flags,
111 * we can drop (neg) from src:
113 if (*dstflags
& IR3_REG_FABS
)
114 srcflags
&= ~IR3_REG_FNEG
;
115 if (*dstflags
& IR3_REG_SABS
)
116 srcflags
&= ~IR3_REG_SNEG
;
118 if (srcflags
& IR3_REG_FABS
)
119 *dstflags
|= IR3_REG_FABS
;
120 if (srcflags
& IR3_REG_SABS
)
121 *dstflags
|= IR3_REG_SABS
;
122 if (srcflags
& IR3_REG_FNEG
)
123 *dstflags
^= IR3_REG_FNEG
;
124 if (srcflags
& IR3_REG_SNEG
)
125 *dstflags
^= IR3_REG_SNEG
;
126 if (srcflags
& IR3_REG_BNOT
)
127 *dstflags
^= IR3_REG_BNOT
;
129 *dstflags
&= ~IR3_REG_SSA
;
130 *dstflags
|= srcflags
& IR3_REG_SSA
;
131 *dstflags
|= srcflags
& IR3_REG_CONST
;
132 *dstflags
|= srcflags
& IR3_REG_IMMED
;
133 *dstflags
|= srcflags
& IR3_REG_RELATIV
;
134 *dstflags
|= srcflags
& IR3_REG_ARRAY
;
135 *dstflags
|= srcflags
& IR3_REG_HIGH
;
137 /* if src of the src is boolean we can drop the (abs) since we know
138 * the source value is already a postitive integer. This cleans
139 * up the absnegs that get inserted when converting between nir and
140 * native boolean (see ir3_b2n/n2b)
142 struct ir3_instruction
*srcsrc
= ssa(src
->regs
[1]);
143 if (srcsrc
&& is_bool(srcsrc
))
144 *dstflags
&= ~IR3_REG_SABS
;
147 /* Tries lowering an immediate register argument to a const buffer access by
148 * adding to the list of immediates to be pushed to the const buffer when
149 * switching to this shader.
152 lower_immed(struct ir3_cp_ctx
*ctx
, struct ir3_instruction
*instr
, unsigned n
,
153 struct ir3_register
*reg
, unsigned new_flags
)
155 if (!(new_flags
& IR3_REG_IMMED
))
158 new_flags
&= ~IR3_REG_IMMED
;
159 new_flags
|= IR3_REG_CONST
;
161 if (!ir3_valid_flags(instr
, n
, new_flags
))
164 unsigned swiz
, idx
, i
;
166 reg
= ir3_reg_clone(ctx
->shader
, reg
);
168 /* Half constant registers seems to handle only 32-bit values
169 * within floating-point opcodes. So convert back to 32-bit values.
171 bool f_opcode
= (is_cat2_float(instr
->opc
) ||
172 is_cat3_float(instr
->opc
)) ? true : false;
173 if (f_opcode
&& (new_flags
& IR3_REG_HALF
))
174 reg
->uim_val
= fui(_mesa_half_to_float(reg
->uim_val
));
176 /* in some cases, there are restrictions on (abs)/(neg) plus const..
177 * so just evaluate those and clear the flags:
179 if (new_flags
& IR3_REG_SABS
) {
180 reg
->iim_val
= abs(reg
->iim_val
);
181 new_flags
&= ~IR3_REG_SABS
;
184 if (new_flags
& IR3_REG_FABS
) {
185 reg
->fim_val
= fabs(reg
->fim_val
);
186 new_flags
&= ~IR3_REG_FABS
;
189 if (new_flags
& IR3_REG_SNEG
) {
190 reg
->iim_val
= -reg
->iim_val
;
191 new_flags
&= ~IR3_REG_SNEG
;
194 if (new_flags
& IR3_REG_FNEG
) {
195 reg
->fim_val
= -reg
->fim_val
;
196 new_flags
&= ~IR3_REG_FNEG
;
199 /* Reallocate for 4 more elements whenever it's necessary */
200 struct ir3_const_state
*const_state
= ir3_const_state(ctx
->so
);
201 if (const_state
->immediate_idx
== const_state
->immediates_size
* 4) {
202 const_state
->immediates
= rerzalloc(const_state
,
203 const_state
->immediates
,
204 __typeof__(const_state
->immediates
[0]),
205 const_state
->immediates_size
,
206 const_state
->immediates_size
+ 4);
207 const_state
->immediates_size
+= 4;
209 for (int i
= const_state
->immediate_idx
; i
< const_state
->immediates_size
* 4; i
++)
210 const_state
->immediates
[i
/ 4].val
[i
% 4] = 0xd0d0d0d0;
213 for (i
= 0; i
< const_state
->immediate_idx
; i
++) {
217 if (const_state
->immediates
[idx
].val
[swiz
] == reg
->uim_val
) {
222 if (i
== const_state
->immediate_idx
) {
223 /* Add on a new immediate to be pushed, if we have space left in the
226 if (const_state
->offsets
.immediate
+ const_state
->immediate_idx
/ 4 >=
227 ir3_max_const(ctx
->so
))
233 const_state
->immediates
[idx
].val
[swiz
] = reg
->uim_val
;
234 const_state
->immediates_count
= idx
+ 1;
235 const_state
->immediate_idx
++;
238 reg
->flags
= new_flags
;
239 reg
->num
= i
+ (4 * const_state
->offsets
.immediate
);
241 instr
->regs
[n
+ 1] = reg
;
247 unuse(struct ir3_instruction
*instr
)
249 debug_assert(instr
->use_count
> 0);
251 if (--instr
->use_count
== 0) {
252 struct ir3_block
*block
= instr
->block
;
254 instr
->barrier_class
= 0;
255 instr
->barrier_conflict
= 0;
257 /* we don't want to remove anything in keeps (which could
258 * be things like array store's)
260 for (unsigned i
= 0; i
< block
->keeps_count
; i
++) {
261 debug_assert(block
->keeps
[i
] != instr
);
267 * Handles the special case of the 2nd src (n == 1) to "normal" mad
268 * instructions, which cannot reference a constant. See if it is
269 * possible to swap the 1st and 2nd sources.
272 try_swap_mad_two_srcs(struct ir3_instruction
*instr
, unsigned new_flags
)
274 if (!is_mad(instr
->opc
))
277 /* NOTE: pre-swap first two src's before valid_flags(),
278 * which might try to dereference the n'th src:
280 swap(instr
->regs
[0 + 1], instr
->regs
[1 + 1]);
282 /* cat3 doesn't encode immediate, but we can lower immediate
283 * to const if that helps:
285 if (new_flags
& IR3_REG_IMMED
) {
286 new_flags
&= ~IR3_REG_IMMED
;
287 new_flags
|= IR3_REG_CONST
;
291 /* can we propagate mov if we move 2nd src to first? */
292 ir3_valid_flags(instr
, 0, new_flags
) &&
293 /* and does first src fit in second slot? */
294 ir3_valid_flags(instr
, 1, instr
->regs
[1 + 1]->flags
);
297 /* put things back the way they were: */
298 swap(instr
->regs
[0 + 1], instr
->regs
[1 + 1]);
299 } /* otherwise leave things swapped */
305 * Handle cp for a given src register. This additionally handles
306 * the cases of collapsing immedate/const (which replace the src
307 * register with a non-ssa src) or collapsing mov's from relative
308 * src (which needs to also fixup the address src reference by the
312 reg_cp(struct ir3_cp_ctx
*ctx
, struct ir3_instruction
*instr
,
313 struct ir3_register
*reg
, unsigned n
)
315 struct ir3_instruction
*src
= ssa(reg
);
317 if (is_eligible_mov(src
, instr
, true)) {
318 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */
319 struct ir3_register
*src_reg
= src
->regs
[1];
320 unsigned new_flags
= reg
->flags
;
322 combine_flags(&new_flags
, src
);
324 if (ir3_valid_flags(instr
, n
, new_flags
)) {
325 if (new_flags
& IR3_REG_ARRAY
) {
326 debug_assert(!(reg
->flags
& IR3_REG_ARRAY
));
327 reg
->array
= src_reg
->array
;
329 reg
->flags
= new_flags
;
330 reg
->instr
= ssa(src_reg
);
332 instr
->barrier_class
|= src
->barrier_class
;
333 instr
->barrier_conflict
|= src
->barrier_conflict
;
336 reg
->instr
->use_count
++;
340 } else if ((is_same_type_mov(src
) || is_const_mov(src
)) &&
341 /* cannot collapse const/immed/etc into meta instrs: */
343 /* immed/const/etc cases, which require some special handling: */
344 struct ir3_register
*src_reg
= src
->regs
[1];
345 unsigned new_flags
= reg
->flags
;
347 combine_flags(&new_flags
, src
);
349 if (!ir3_valid_flags(instr
, n
, new_flags
)) {
350 /* See if lowering an immediate to const would help. */
351 if (lower_immed(ctx
, instr
, n
, src_reg
, new_flags
))
354 /* special case for "normal" mad instructions, we can
355 * try swapping the first two args if that fits better.
357 * the "plain" MAD's (ie. the ones that don't shift first
358 * src prior to multiply) can swap their first two srcs if
359 * src[0] is !CONST and src[1] is CONST:
361 if ((n
== 1) && try_swap_mad_two_srcs(instr
, new_flags
)) {
368 /* Here we handle the special case of mov from
369 * CONST and/or RELATIV. These need to be handled
370 * specially, because in the case of move from CONST
371 * there is no src ir3_instruction so we need to
372 * replace the ir3_register. And in the case of
373 * RELATIV we need to handle the address register
376 if (src_reg
->flags
& IR3_REG_CONST
) {
377 /* an instruction cannot reference two different
380 if ((src_reg
->flags
& IR3_REG_RELATIV
) &&
381 conflicts(instr
->address
, reg
->instr
->address
))
384 /* This seems to be a hw bug, or something where the timings
385 * just somehow don't work out. This restriction may only
386 * apply if the first src is also CONST.
388 if ((opc_cat(instr
->opc
) == 3) && (n
== 2) &&
389 (src_reg
->flags
& IR3_REG_RELATIV
) &&
390 (src_reg
->array
.offset
== 0))
393 /* When narrowing constant from 32b to 16b, it seems
394 * to work only for float. So we should do this only with
397 if (src
->cat1
.dst_type
== TYPE_F16
) {
398 if (instr
->opc
== OPC_MOV
&& !type_float(instr
->cat1
.src_type
))
400 if (!is_cat2_float(instr
->opc
) && !is_cat3_float(instr
->opc
))
404 src_reg
= ir3_reg_clone(instr
->block
->shader
, src_reg
);
405 src_reg
->flags
= new_flags
;
406 instr
->regs
[n
+1] = src_reg
;
408 if (src_reg
->flags
& IR3_REG_RELATIV
)
409 ir3_instr_set_address(instr
, reg
->instr
->address
);
414 if ((src_reg
->flags
& IR3_REG_RELATIV
) &&
415 !conflicts(instr
->address
, reg
->instr
->address
)) {
416 src_reg
= ir3_reg_clone(instr
->block
->shader
, src_reg
);
417 src_reg
->flags
= new_flags
;
418 instr
->regs
[n
+1] = src_reg
;
419 ir3_instr_set_address(instr
, reg
->instr
->address
);
424 /* NOTE: seems we can only do immed integers, so don't
425 * need to care about float. But we do need to handle
426 * abs/neg *before* checking that the immediate requires
427 * few enough bits to encode:
429 * TODO: do we need to do something to avoid accidentally
430 * catching a float immed?
432 if (src_reg
->flags
& IR3_REG_IMMED
) {
433 int32_t iim_val
= src_reg
->iim_val
;
435 debug_assert((opc_cat(instr
->opc
) == 1) ||
436 (opc_cat(instr
->opc
) == 6) ||
437 ir3_cat2_int(instr
->opc
) ||
438 (is_mad(instr
->opc
) && (n
== 0)));
440 if (new_flags
& IR3_REG_SABS
)
441 iim_val
= abs(iim_val
);
443 if (new_flags
& IR3_REG_SNEG
)
446 if (new_flags
& IR3_REG_BNOT
)
449 /* other than category 1 (mov) we can only encode up to 10 bits: */
450 if (ir3_valid_flags(instr
, n
, new_flags
) &&
451 ((instr
->opc
== OPC_MOV
) ||
452 !((iim_val
& ~0x3ff) && (-iim_val
& ~0x3ff)))) {
453 new_flags
&= ~(IR3_REG_SABS
| IR3_REG_SNEG
| IR3_REG_BNOT
);
454 src_reg
= ir3_reg_clone(instr
->block
->shader
, src_reg
);
455 src_reg
->flags
= new_flags
;
456 src_reg
->iim_val
= iim_val
;
457 instr
->regs
[n
+1] = src_reg
;
460 } else if (lower_immed(ctx
, instr
, n
, src_reg
, new_flags
)) {
461 /* Fell back to loading the immediate as a const */
470 /* Handle special case of eliminating output mov, and similar cases where
471 * there isn't a normal "consuming" instruction. In this case we cannot
472 * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
475 static struct ir3_instruction
*
476 eliminate_output_mov(struct ir3_cp_ctx
*ctx
, struct ir3_instruction
*instr
)
478 if (is_eligible_mov(instr
, NULL
, false)) {
479 struct ir3_register
*reg
= instr
->regs
[1];
480 if (!(reg
->flags
& IR3_REG_ARRAY
)) {
481 struct ir3_instruction
*src_instr
= ssa(reg
);
482 debug_assert(src_instr
);
483 ctx
->progress
= true;
491 * Find instruction src's which are mov's that can be collapsed, replacing
492 * the mov dst with the mov src
495 instr_cp(struct ir3_cp_ctx
*ctx
, struct ir3_instruction
*instr
)
497 if (instr
->regs_count
== 0)
500 if (ir3_instr_check_mark(instr
))
503 /* walk down the graph from each src: */
507 foreach_src_n (reg
, n
, instr
) {
508 struct ir3_instruction
*src
= ssa(reg
);
515 /* TODO non-indirect access we could figure out which register
516 * we actually want and allow cp..
518 if (reg
->flags
& IR3_REG_ARRAY
)
521 /* Don't CP absneg into meta instructions, that won't end well: */
522 if (is_meta(instr
) && (src
->opc
!= OPC_MOV
))
525 progress
|= reg_cp(ctx
, instr
, reg
, n
);
526 ctx
->progress
|= progress
;
530 if (instr
->regs
[0]->flags
& IR3_REG_ARRAY
) {
531 struct ir3_instruction
*src
= ssa(instr
->regs
[0]);
536 if (instr
->address
) {
537 instr_cp(ctx
, instr
->address
);
538 ir3_instr_set_address(instr
, eliminate_output_mov(ctx
, instr
->address
));
541 /* we can end up with extra cmps.s from frontend, which uses a
543 * cmps.s p0.x, cond, 0
545 * as a way to mov into the predicate register. But frequently 'cond'
546 * is itself a cmps.s/cmps.f/cmps.u. So detect this special case and
547 * just re-write the instruction writing predicate register to get rid
548 * of the double cmps.
550 if ((instr
->opc
== OPC_CMPS_S
) &&
551 (instr
->regs
[0]->num
== regid(REG_P0
, 0)) &&
552 ssa(instr
->regs
[1]) &&
553 (instr
->regs
[2]->flags
& IR3_REG_IMMED
) &&
554 (instr
->regs
[2]->iim_val
== 0) &&
555 (instr
->cat2
.condition
== IR3_COND_NE
)) {
556 struct ir3_instruction
*cond
= ssa(instr
->regs
[1]);
561 instr
->opc
= cond
->opc
;
562 instr
->flags
= cond
->flags
;
563 instr
->cat2
= cond
->cat2
;
564 ir3_instr_set_address(instr
, cond
->address
);
565 instr
->regs
[1] = cond
->regs
[1];
566 instr
->regs
[2] = cond
->regs
[2];
567 instr
->barrier_class
|= cond
->barrier_class
;
568 instr
->barrier_conflict
|= cond
->barrier_conflict
;
570 ctx
->progress
= true;
577 /* Handle converting a sam.s2en (taking samp/tex idx params via register)
578 * into a normal sam (encoding immediate samp/tex idx) if they are
579 * immediate. This saves some instructions and regs in the common case
580 * where we know samp/tex at compile time. This needs to be done in the
581 * frontend for bindless tex, though, so don't replicate it here.
583 if (is_tex(instr
) && (instr
->flags
& IR3_INSTR_S2EN
) &&
584 !(instr
->flags
& IR3_INSTR_B
) &&
585 !(ir3_shader_debug
& IR3_DBG_FORCES2EN
)) {
586 /* The first src will be a collect, if both of it's
587 * two sources are mov from imm, then we can
589 struct ir3_instruction
*samp_tex
= ssa(instr
->regs
[1]);
591 debug_assert(samp_tex
->opc
== OPC_META_COLLECT
);
593 struct ir3_instruction
*samp
= ssa(samp_tex
->regs
[1]);
594 struct ir3_instruction
*tex
= ssa(samp_tex
->regs
[2]);
596 if ((samp
->opc
== OPC_MOV
) &&
597 (samp
->regs
[1]->flags
& IR3_REG_IMMED
) &&
598 (tex
->opc
== OPC_MOV
) &&
599 (tex
->regs
[1]->flags
& IR3_REG_IMMED
)) {
600 instr
->flags
&= ~IR3_INSTR_S2EN
;
601 instr
->cat5
.samp
= samp
->regs
[1]->iim_val
;
602 instr
->cat5
.tex
= tex
->regs
[1]->iim_val
;
604 /* shuffle around the regs to remove the first src: */
606 for (unsigned i
= 1; i
< instr
->regs_count
; i
++) {
607 instr
->regs
[i
] = instr
->regs
[i
+ 1];
610 ctx
->progress
= true;
616 ir3_cp(struct ir3
*ir
, struct ir3_shader_variant
*so
)
618 struct ir3_cp_ctx ctx
= {
623 /* This is a bit annoying, and probably wouldn't be necessary if we
624 * tracked a reverse link from producing instruction to consumer.
625 * But we need to know when we've eliminated the last consumer of
626 * a mov, so we need to do a pass to first count consumers of a
629 foreach_block (block
, &ir
->block_list
) {
630 foreach_instr (instr
, &block
->instr_list
) {
632 /* by the way, we don't account for false-dep's, so the CP
633 * pass should always happen before false-dep's are inserted
635 debug_assert(instr
->deps_count
== 0);
637 foreach_ssa_src (src
, instr
) {
645 foreach_output_n (out
, n
, ir
) {
647 ir
->outputs
[n
] = eliminate_output_mov(&ctx
, out
);
650 foreach_block (block
, &ir
->block_list
) {
651 if (block
->condition
) {
652 instr_cp(&ctx
, block
->condition
);
653 block
->condition
= eliminate_output_mov(&ctx
, block
->condition
);
656 for (unsigned i
= 0; i
< block
->keeps_count
; i
++) {
657 instr_cp(&ctx
, block
->keeps
[i
]);
658 block
->keeps
[i
] = eliminate_output_mov(&ctx
, block
->keeps
[i
]);