src/freedreno/ir3/ir3_cp.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include <math.h>
  28 #include "util/half_float.h"
  29 #include "util/u_math.h"
  30
  31 #include "ir3.h"
  32 #include "ir3_compiler.h"
  33 #include "ir3_shader.h"
  34
  35 /*
  36  * Copy Propagate:
  37  */
  38
  39 struct ir3_cp_ctx {
  40         struct ir3 *shader;
  41         struct ir3_shader_variant *so;
  42 };
  43
  44 /* is it a type preserving mov, with ok flags? */
  45 static bool is_eligible_mov(struct ir3_instruction *instr, bool allow_flags)
  46 {
  47         if (is_same_type_mov(instr)) {
  48                 struct ir3_register *dst = instr->regs[0];
  49                 struct ir3_register *src = instr->regs[1];
  50                 struct ir3_instruction *src_instr = ssa(src);
  51
  52                 /* only if mov src is SSA (not const/immed): */
  53                 if (!src_instr)
  54                         return false;
  55
  56                 /* no indirect: */
  57                 if (dst->flags & IR3_REG_RELATIV)
  58                         return false;
  59                 if (src->flags & IR3_REG_RELATIV)
  60                         return false;
  61
  62                 if (src->flags & IR3_REG_ARRAY)
  63                         return false;
  64
  65                 if (!allow_flags)
  66                         if (src->flags & (IR3_REG_FABS | IR3_REG_FNEG |
  67                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
  68                                 return false;
  69
  70                 /* TODO: remove this hack: */
  71                 if (src_instr->opc == OPC_META_FO)
  72                         return false;
  73
  74                 return true;
  75         }
  76         return false;
  77 }
  78
  79 static unsigned cp_flags(unsigned flags)
  80 {
  81         /* only considering these flags (at least for now): */
  82         flags &= (IR3_REG_CONST | IR3_REG_IMMED |
  83                         IR3_REG_FNEG | IR3_REG_FABS |
  84                         IR3_REG_SNEG | IR3_REG_SABS |
  85                         IR3_REG_BNOT | IR3_REG_RELATIV);
  86         return flags;
  87 }
  88
  89 static bool valid_flags(struct ir3_instruction *instr, unsigned n,
  90                 unsigned flags)
  91 {
  92         unsigned valid_flags;
  93
  94         if ((flags & IR3_REG_HIGH) &&
  95                         (opc_cat(instr->opc) > 1) &&
  96                         (instr->block->shader->compiler->gpu_id >= 600))
  97                 return false;
  98
  99         flags = cp_flags(flags);
 100
 101         /* If destination is indirect, then source cannot be.. at least
 102          * I don't think so..
 103          */
 104         if ((instr->regs[0]->flags & IR3_REG_RELATIV) &&
 105                         (flags & IR3_REG_RELATIV))
 106                 return false;
 107
 108         /* TODO it seems to *mostly* work to cp RELATIV, except we get some
 109          * intermittent piglit variable-indexing fails.  Newer blob driver
 110          * doesn't seem to cp these.  Possibly this is hw workaround?  Not
 111          * sure, but until that is understood better, lets just switch off
 112          * cp for indirect src's:
 113          */
 114         if (flags & IR3_REG_RELATIV)
 115                 return false;
 116
 117         switch (opc_cat(instr->opc)) {
 118         case 1:
 119                 valid_flags = IR3_REG_IMMED | IR3_REG_CONST | IR3_REG_RELATIV;
 120                 if (flags & ~valid_flags)
 121                         return false;
 122                 break;
 123         case 2:
 124                 valid_flags = ir3_cat2_absneg(instr->opc) |
 125                                 IR3_REG_CONST | IR3_REG_RELATIV;
 126
 127                 if (ir3_cat2_int(instr->opc))
 128                         valid_flags |= IR3_REG_IMMED;
 129
 130                 if (flags & ~valid_flags)
 131                         return false;
 132
 133                 if (flags & (IR3_REG_CONST | IR3_REG_IMMED)) {
 134                         unsigned m = (n ^ 1) + 1;
 135                         /* cannot deal w/ const in both srcs:
 136                          * (note that some cat2 actually only have a single src)
 137                          */
 138                         if (m < instr->regs_count) {
 139                                 struct ir3_register *reg = instr->regs[m];
 140                                 if ((flags & IR3_REG_CONST) && (reg->flags & IR3_REG_CONST))
 141                                         return false;
 142                                 if ((flags & IR3_REG_IMMED) && (reg->flags & IR3_REG_IMMED))
 143                                         return false;
 144                         }
 145                         /* cannot be const + ABS|NEG: */
 146                         if (flags & (IR3_REG_FABS | IR3_REG_FNEG |
 147                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
 148                                 return false;
 149                 }
 150                 break;
 151         case 3:
 152                 valid_flags = ir3_cat3_absneg(instr->opc) |
 153                                 IR3_REG_CONST | IR3_REG_RELATIV;
 154
 155                 if (flags & ~valid_flags)
 156                         return false;
 157
 158                 if (flags & (IR3_REG_CONST | IR3_REG_RELATIV)) {
 159                         /* cannot deal w/ const/relativ in 2nd src: */
 160                         if (n == 1)
 161                                 return false;
 162                 }
 163
 164                 if (flags & IR3_REG_CONST) {
 165                         /* cannot be const + ABS|NEG: */
 166                         if (flags & (IR3_REG_FABS | IR3_REG_FNEG |
 167                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
 168                                 return false;
 169                 }
 170                 break;
 171         case 4:
 172                 /* seems like blob compiler avoids const as src.. */
 173                 /* TODO double check if this is still the case on a4xx */
 174                 if (flags & (IR3_REG_CONST | IR3_REG_IMMED))
 175                         return false;
 176                 if (flags & (IR3_REG_SABS | IR3_REG_SNEG))
 177                         return false;
 178                 break;
 179         case 5:
 180                 /* no flags allowed */
 181                 if (flags)
 182                         return false;
 183                 break;
 184         case 6:
 185                 valid_flags = IR3_REG_IMMED;
 186                 if (flags & ~valid_flags)
 187                         return false;
 188
 189                 if (flags & IR3_REG_IMMED) {
 190                         /* doesn't seem like we can have immediate src for store
 191                          * instructions:
 192                          *
 193                          * TODO this restriction could also apply to load instructions,
 194                          * but for load instructions this arg is the address (and not
 195                          * really sure any good way to test a hard-coded immed addr src)
 196                          */
 197                         if (is_store(instr) && (n == 1))
 198                                 return false;
 199
 200                         if ((instr->opc == OPC_LDL) && (n != 1))
 201                                 return false;
 202
 203                         if ((instr->opc == OPC_STL) && (n != 2))
 204                                 return false;
 205
 206                         /* disallow CP into anything but the SSBO slot argument for
 207                          * atomics:
 208                          */
 209                         if (is_atomic(instr->opc) && (n != 0))
 210                                 return false;
 211
 212                         if (is_atomic(instr->opc) && !(instr->flags & IR3_INSTR_G))
 213                                 return false;
 214
 215                         /* as with atomics, ldib on a6xx can only have immediate for
 216                          * SSBO slot argument
 217                          */
 218                         if ((instr->opc == OPC_LDIB) && (n != 0))
 219                                 return false;
 220                 }
 221
 222                 break;
 223         }
 224
 225         return true;
 226 }
 227
 228 /* propagate register flags from src to dst.. negates need special
 229  * handling to cancel each other out.
 230  */
 231 static void combine_flags(unsigned *dstflags, struct ir3_instruction *src)
 232 {
 233         unsigned srcflags = src->regs[1]->flags;
 234
 235         /* if what we are combining into already has (abs) flags,
 236          * we can drop (neg) from src:
 237          */
 238         if (*dstflags & IR3_REG_FABS)
 239                 srcflags &= ~IR3_REG_FNEG;
 240         if (*dstflags & IR3_REG_SABS)
 241                 srcflags &= ~IR3_REG_SNEG;
 242
 243         if (srcflags & IR3_REG_FABS)
 244                 *dstflags |= IR3_REG_FABS;
 245         if (srcflags & IR3_REG_SABS)
 246                 *dstflags |= IR3_REG_SABS;
 247         if (srcflags & IR3_REG_FNEG)
 248                 *dstflags ^= IR3_REG_FNEG;
 249         if (srcflags & IR3_REG_SNEG)
 250                 *dstflags ^= IR3_REG_SNEG;
 251         if (srcflags & IR3_REG_BNOT)
 252                 *dstflags ^= IR3_REG_BNOT;
 253
 254         *dstflags &= ~IR3_REG_SSA;
 255         *dstflags |= srcflags & IR3_REG_SSA;
 256         *dstflags |= srcflags & IR3_REG_CONST;
 257         *dstflags |= srcflags & IR3_REG_IMMED;
 258         *dstflags |= srcflags & IR3_REG_RELATIV;
 259         *dstflags |= srcflags & IR3_REG_ARRAY;
 260         *dstflags |= srcflags & IR3_REG_HIGH;
 261
 262         /* if src of the src is boolean we can drop the (abs) since we know
 263          * the source value is already a postitive integer.  This cleans
 264          * up the absnegs that get inserted when converting between nir and
 265          * native boolean (see ir3_b2n/n2b)
 266          */
 267         struct ir3_instruction *srcsrc = ssa(src->regs[1]);
 268         if (srcsrc && is_bool(srcsrc))
 269                 *dstflags &= ~IR3_REG_SABS;
 270 }
 271
 272 static struct ir3_register *
 273 lower_immed(struct ir3_cp_ctx *ctx, struct ir3_register *reg, unsigned new_flags, bool f_opcode)
 274 {
 275         unsigned swiz, idx, i;
 276
 277         reg = ir3_reg_clone(ctx->shader, reg);
 278
 279         /* in some cases, there are restrictions on (abs)/(neg) plus const..
 280          * so just evaluate those and clear the flags:
 281          */
 282         if (new_flags & IR3_REG_SABS) {
 283                 reg->iim_val = abs(reg->iim_val);
 284                 new_flags &= ~IR3_REG_SABS;
 285         }
 286
 287         if (new_flags & IR3_REG_FABS) {
 288                 reg->fim_val = fabs(reg->fim_val);
 289                 new_flags &= ~IR3_REG_FABS;
 290         }
 291
 292         if (new_flags & IR3_REG_SNEG) {
 293                 reg->iim_val = -reg->iim_val;
 294                 new_flags &= ~IR3_REG_SNEG;
 295         }
 296
 297         if (new_flags & IR3_REG_FNEG) {
 298                 reg->fim_val = -reg->fim_val;
 299                 new_flags &= ~IR3_REG_FNEG;
 300         }
 301
 302         /* Reallocate for 4 more elements whenever it's necessary */
 303         struct ir3_const_state *const_state = &ctx->so->shader->const_state;
 304         if (const_state->immediate_idx == const_state->immediates_size * 4) {
 305                 const_state->immediates_size += 4;
 306                 const_state->immediates = realloc (const_state->immediates,
 307                         const_state->immediates_size * sizeof(const_state->immediates[0]));
 308         }
 309
 310         for (i = 0; i < const_state->immediate_idx; i++) {
 311                 swiz = i % 4;
 312                 idx  = i / 4;
 313
 314                 if (const_state->immediates[idx].val[swiz] == reg->uim_val) {
 315                         break;
 316                 }
 317         }
 318
 319         if (i == const_state->immediate_idx) {
 320                 /* need to generate a new immediate: */
 321                 swiz = i % 4;
 322                 idx  = i / 4;
 323
 324                 /* Half constant registers seems to handle only 32-bit values
 325                  * within floating-point opcodes. So convert back to 32-bit values. */
 326                 if (f_opcode && (new_flags & IR3_REG_HALF)) {
 327                         reg->uim_val = fui(_mesa_half_to_float(reg->uim_val));
 328                 }
 329
 330                 const_state->immediates[idx].val[swiz] = reg->uim_val;
 331                 const_state->immediates_count = idx + 1;
 332                 const_state->immediate_idx++;
 333         }
 334
 335         new_flags &= ~IR3_REG_IMMED;
 336         new_flags |= IR3_REG_CONST;
 337         reg->flags = new_flags;
 338         reg->num = i + (4 * const_state->offsets.immediate);
 339
 340         return reg;
 341 }
 342
 343 static void
 344 unuse(struct ir3_instruction *instr)
 345 {
 346         debug_assert(instr->use_count > 0);
 347
 348         if (--instr->use_count == 0) {
 349                 struct ir3_block *block = instr->block;
 350
 351                 instr->barrier_class = 0;
 352                 instr->barrier_conflict = 0;
 353
 354                 /* we don't want to remove anything in keeps (which could
 355                  * be things like array store's)
 356                  */
 357                 for (unsigned i = 0; i < block->keeps_count; i++) {
 358                         debug_assert(block->keeps[i] != instr);
 359                 }
 360         }
 361 }
 362
 363 /**
 364  * Handle cp for a given src register.  This additionally handles
 365  * the cases of collapsing immedate/const (which replace the src
 366  * register with a non-ssa src) or collapsing mov's from relative
 367  * src (which needs to also fixup the address src reference by the
 368  * instruction).
 369  */
 370 static void
 371 reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr,
 372                 struct ir3_register *reg, unsigned n)
 373 {
 374         struct ir3_instruction *src = ssa(reg);
 375
 376         if (is_eligible_mov(src, true)) {
 377                 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */
 378                 struct ir3_register *src_reg = src->regs[1];
 379                 unsigned new_flags = reg->flags;
 380
 381                 combine_flags(&new_flags, src);
 382
 383                 if (valid_flags(instr, n, new_flags)) {
 384                         if (new_flags & IR3_REG_ARRAY) {
 385                                 debug_assert(!(reg->flags & IR3_REG_ARRAY));
 386                                 reg->array = src_reg->array;
 387                         }
 388                         reg->flags = new_flags;
 389                         reg->instr = ssa(src_reg);
 390
 391                         instr->barrier_class |= src->barrier_class;
 392                         instr->barrier_conflict |= src->barrier_conflict;
 393
 394                         unuse(src);
 395                         reg->instr->use_count++;
 396                 }
 397
 398         } else if (is_same_type_mov(src) &&
 399                         /* cannot collapse const/immed/etc into meta instrs: */
 400                         !is_meta(instr)) {
 401                 /* immed/const/etc cases, which require some special handling: */
 402                 struct ir3_register *src_reg = src->regs[1];
 403                 unsigned new_flags = reg->flags;
 404
 405                 combine_flags(&new_flags, src);
 406
 407                 if (!valid_flags(instr, n, new_flags)) {
 408                         /* See if lowering an immediate to const would help. */
 409                         if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) {
 410                                 bool f_opcode = (ir3_cat2_float(instr->opc) ||
 411                                                 ir3_cat3_float(instr->opc)) ? true : false;
 412
 413                                 debug_assert(new_flags & IR3_REG_IMMED);
 414
 415                                 instr->regs[n + 1] = lower_immed(ctx, src_reg, new_flags, f_opcode);
 416                                 return;
 417                         }
 418
 419                         /* special case for "normal" mad instructions, we can
 420                          * try swapping the first two args if that fits better.
 421                          *
 422                          * the "plain" MAD's (ie. the ones that don't shift first
 423                          * src prior to multiply) can swap their first two srcs if
 424                          * src[0] is !CONST and src[1] is CONST:
 425                          */
 426                         if ((n == 1) && is_mad(instr->opc) &&
 427                                         !(instr->regs[0 + 1]->flags & (IR3_REG_CONST | IR3_REG_RELATIV)) &&
 428                                         valid_flags(instr, 0, new_flags & ~IR3_REG_IMMED)) {
 429                                 /* swap src[0] and src[1]: */
 430                                 struct ir3_register *tmp;
 431                                 tmp = instr->regs[0 + 1];
 432                                 instr->regs[0 + 1] = instr->regs[1 + 1];
 433                                 instr->regs[1 + 1] = tmp;
 434
 435                                 n = 0;
 436                         } else {
 437                                 return;
 438                         }
 439                 }
 440
 441                 /* Here we handle the special case of mov from
 442                  * CONST and/or RELATIV.  These need to be handled
 443                  * specially, because in the case of move from CONST
 444                  * there is no src ir3_instruction so we need to
 445                  * replace the ir3_register.  And in the case of
 446                  * RELATIV we need to handle the address register
 447                  * dependency.
 448                  */
 449                 if (src_reg->flags & IR3_REG_CONST) {
 450                         /* an instruction cannot reference two different
 451                          * address registers:
 452                          */
 453                         if ((src_reg->flags & IR3_REG_RELATIV) &&
 454                                         conflicts(instr->address, reg->instr->address))
 455                                 return;
 456
 457                         /* This seems to be a hw bug, or something where the timings
 458                          * just somehow don't work out.  This restriction may only
 459                          * apply if the first src is also CONST.
 460                          */
 461                         if ((opc_cat(instr->opc) == 3) && (n == 2) &&
 462                                         (src_reg->flags & IR3_REG_RELATIV) &&
 463                                         (src_reg->array.offset == 0))
 464                                 return;
 465
 466                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 467                         src_reg->flags = new_flags;
 468                         instr->regs[n+1] = src_reg;
 469
 470                         if (src_reg->flags & IR3_REG_RELATIV)
 471                                 ir3_instr_set_address(instr, reg->instr->address);
 472
 473                         return;
 474                 }
 475
 476                 if ((src_reg->flags & IR3_REG_RELATIV) &&
 477                                 !conflicts(instr->address, reg->instr->address)) {
 478                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 479                         src_reg->flags = new_flags;
 480                         instr->regs[n+1] = src_reg;
 481                         ir3_instr_set_address(instr, reg->instr->address);
 482
 483                         return;
 484                 }
 485
 486                 /* NOTE: seems we can only do immed integers, so don't
 487                  * need to care about float.  But we do need to handle
 488                  * abs/neg *before* checking that the immediate requires
 489                  * few enough bits to encode:
 490                  *
 491                  * TODO: do we need to do something to avoid accidentally
 492                  * catching a float immed?
 493                  */
 494                 if (src_reg->flags & IR3_REG_IMMED) {
 495                         int32_t iim_val = src_reg->iim_val;
 496
 497                         debug_assert((opc_cat(instr->opc) == 1) ||
 498                                         (opc_cat(instr->opc) == 6) ||
 499                                         ir3_cat2_int(instr->opc) ||
 500                                         (is_mad(instr->opc) && (n == 0)));
 501
 502                         if (new_flags & IR3_REG_SABS)
 503                                 iim_val = abs(iim_val);
 504
 505                         if (new_flags & IR3_REG_SNEG)
 506                                 iim_val = -iim_val;
 507
 508                         if (new_flags & IR3_REG_BNOT)
 509                                 iim_val = ~iim_val;
 510
 511                         /* other than category 1 (mov) we can only encode up to 10 bits: */
 512                         if ((instr->opc == OPC_MOV) ||
 513                                         !((iim_val & ~0x3ff) && (-iim_val & ~0x3ff))) {
 514                                 new_flags &= ~(IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT);
 515                                 src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 516                                 src_reg->flags = new_flags;
 517                                 src_reg->iim_val = iim_val;
 518                                 instr->regs[n+1] = src_reg;
 519                         } else if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) {
 520                                 bool f_opcode = (ir3_cat2_float(instr->opc) ||
 521                                                 ir3_cat3_float(instr->opc)) ? true : false;
 522
 523                                 /* See if lowering an immediate to const would help. */
 524                                 instr->regs[n+1] = lower_immed(ctx, src_reg, new_flags, f_opcode);
 525                         }
 526                         return;
 527                 }
 528         }
 529 }
 530
 531 /* Handle special case of eliminating output mov, and similar cases where
 532  * there isn't a normal "consuming" instruction.  In this case we cannot
 533  * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
 534  * be eliminated)
 535  */
 536 static struct ir3_instruction *
 537 eliminate_output_mov(struct ir3_instruction *instr)
 538 {
 539         if (is_eligible_mov(instr, false)) {
 540                 struct ir3_register *reg = instr->regs[1];
 541                 if (!(reg->flags & IR3_REG_ARRAY)) {
 542                         struct ir3_instruction *src_instr = ssa(reg);
 543                         debug_assert(src_instr);
 544                         return src_instr;
 545                 }
 546         }
 547         return instr;
 548 }
 549
 550 /**
 551  * Find instruction src's which are mov's that can be collapsed, replacing
 552  * the mov dst with the mov src
 553  */
 554 static void
 555 instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
 556 {
 557         struct ir3_register *reg;
 558
 559         if (instr->regs_count == 0)
 560                 return;
 561
 562         if (ir3_instr_check_mark(instr))
 563                 return;
 564
 565         /* walk down the graph from each src: */
 566         foreach_src_n(reg, n, instr) {
 567                 struct ir3_instruction *src = ssa(reg);
 568
 569                 if (!src)
 570                         continue;
 571
 572                 instr_cp(ctx, src);
 573
 574                 /* TODO non-indirect access we could figure out which register
 575                  * we actually want and allow cp..
 576                  */
 577                 if (reg->flags & IR3_REG_ARRAY)
 578                         continue;
 579
 580                 /* Don't CP absneg into meta instructions, that won't end well: */
 581                 if (is_meta(instr) && (src->opc != OPC_MOV))
 582                         continue;
 583
 584                 reg_cp(ctx, instr, reg, n);
 585         }
 586
 587         if (instr->regs[0]->flags & IR3_REG_ARRAY) {
 588                 struct ir3_instruction *src = ssa(instr->regs[0]);
 589                 if (src)
 590                         instr_cp(ctx, src);
 591         }
 592
 593         if (instr->address) {
 594                 instr_cp(ctx, instr->address);
 595                 ir3_instr_set_address(instr, eliminate_output_mov(instr->address));
 596         }
 597
 598         /* we can end up with extra cmps.s from frontend, which uses a
 599          *
 600          *    cmps.s p0.x, cond, 0
 601          *
 602          * as a way to mov into the predicate register.  But frequently 'cond'
 603          * is itself a cmps.s/cmps.f/cmps.u.  So detect this special case and
 604          * just re-write the instruction writing predicate register to get rid
 605          * of the double cmps.
 606          */
 607         if ((instr->opc == OPC_CMPS_S) &&
 608                         (instr->regs[0]->num == regid(REG_P0, 0)) &&
 609                         ssa(instr->regs[1]) &&
 610                         (instr->regs[2]->flags & IR3_REG_IMMED) &&
 611                         (instr->regs[2]->iim_val == 0)) {
 612                 struct ir3_instruction *cond = ssa(instr->regs[1]);
 613                 switch (cond->opc) {
 614                 case OPC_CMPS_S:
 615                 case OPC_CMPS_F:
 616                 case OPC_CMPS_U:
 617                         instr->opc   = cond->opc;
 618                         instr->flags = cond->flags;
 619                         instr->cat2  = cond->cat2;
 620                         instr->address = cond->address;
 621                         instr->regs[1] = cond->regs[1];
 622                         instr->regs[2] = cond->regs[2];
 623                         instr->barrier_class |= cond->barrier_class;
 624                         instr->barrier_conflict |= cond->barrier_conflict;
 625                         unuse(cond);
 626                         break;
 627                 default:
 628                         break;
 629                 }
 630         }
 631
 632         /* Handle converting a sam.s2en (taking samp/tex idx params via
 633          * register) into a normal sam (encoding immediate samp/tex idx)
 634          * if they are immediate.  This saves some instructions and regs
 635          * in the common case where we know samp/tex at compile time:
 636          */
 637         if (is_tex(instr) && (instr->flags & IR3_INSTR_S2EN) &&
 638                         !(ir3_shader_debug & IR3_DBG_FORCES2EN)) {
 639                 /* The first src will be a fan-in (collect), if both of it's
 640                  * two sources are mov from imm, then we can
 641                  */
 642                 struct ir3_instruction *samp_tex = ssa(instr->regs[1]);
 643
 644                 debug_assert(samp_tex->opc == OPC_META_FI);
 645
 646                 struct ir3_instruction *samp = ssa(samp_tex->regs[1]);
 647                 struct ir3_instruction *tex  = ssa(samp_tex->regs[2]);
 648
 649                 if ((samp->opc == OPC_MOV) &&
 650                                 (samp->regs[1]->flags & IR3_REG_IMMED) &&
 651                                 (tex->opc == OPC_MOV) &&
 652                                 (tex->regs[1]->flags & IR3_REG_IMMED)) {
 653                         instr->flags &= ~IR3_INSTR_S2EN;
 654                         instr->cat5.samp = samp->regs[1]->iim_val;
 655                         instr->cat5.tex  = tex->regs[1]->iim_val;
 656                         instr->regs[1]->instr = NULL;
 657                 }
 658         }
 659 }
 660
 661 void
 662 ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so)
 663 {
 664         struct ir3_cp_ctx ctx = {
 665                         .shader = ir,
 666                         .so = so,
 667         };
 668
 669         /* This is a bit annoying, and probably wouldn't be necessary if we
 670          * tracked a reverse link from producing instruction to consumer.
 671          * But we need to know when we've eliminated the last consumer of
 672          * a mov, so we need to do a pass to first count consumers of a
 673          * mov.
 674          */
 675         list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
 676                 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
 677                         struct ir3_instruction *src;
 678
 679                         /* by the way, we don't account for false-dep's, so the CP
 680                          * pass should always happen before false-dep's are inserted
 681                          */
 682                         debug_assert(instr->deps_count == 0);
 683
 684                         foreach_ssa_src(src, instr) {
 685                                 src->use_count++;
 686                         }
 687                 }
 688         }
 689
 690         ir3_clear_mark(ir);
 691
 692         for (unsigned i = 0; i < ir->noutputs; i++) {
 693                 if (ir->outputs[i]) {
 694                         instr_cp(&ctx, ir->outputs[i]);
 695                         ir->outputs[i] = eliminate_output_mov(ir->outputs[i]);
 696                 }
 697         }
 698
 699         list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
 700                 if (block->condition) {
 701                         instr_cp(&ctx, block->condition);
 702                         block->condition = eliminate_output_mov(block->condition);
 703                 }
 704
 705                 for (unsigned i = 0; i < block->keeps_count; i++) {
 706                         instr_cp(&ctx, block->keeps[i]);
 707                         block->keeps[i] = eliminate_output_mov(block->keeps[i]);
 708                 }
 709         }
 710 }