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freedreno/ir3/print: print (r) flag
[mesa.git] / src / freedreno / ir3 / ir3_cp.c
1 /*
2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <math.h>
28 #include "util/half_float.h"
29 #include "util/u_math.h"
30
31 #include "ir3.h"
32 #include "ir3_compiler.h"
33 #include "ir3_shader.h"
34
35 #define swap(a, b) \
36 do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
37
38 /*
39 * Copy Propagate:
40 */
41
42 struct ir3_cp_ctx {
43 struct ir3 *shader;
44 struct ir3_shader_variant *so;
45 bool progress;
46 };
47
48 /* is it a type preserving mov, with ok flags?
49 *
50 * @instr: the mov to consider removing
51 * @dst_instr: the instruction consuming the mov (instr)
52 *
53 * TODO maybe drop allow_flags since this is only false when dst is
54 * NULL (ie. outputs)
55 */
56 static bool is_eligible_mov(struct ir3_instruction *instr,
57 struct ir3_instruction *dst_instr, bool allow_flags)
58 {
59 if (is_same_type_mov(instr)) {
60 struct ir3_register *dst = instr->regs[0];
61 struct ir3_register *src = instr->regs[1];
62 struct ir3_instruction *src_instr = ssa(src);
63
64 /* only if mov src is SSA (not const/immed): */
65 if (!src_instr)
66 return false;
67
68 /* no indirect: */
69 if (dst->flags & IR3_REG_RELATIV)
70 return false;
71 if (src->flags & IR3_REG_RELATIV)
72 return false;
73
74 if (src->flags & IR3_REG_ARRAY)
75 return false;
76
77 if (!allow_flags)
78 if (src->flags & (IR3_REG_FABS | IR3_REG_FNEG |
79 IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
80 return false;
81
82 /* If src is coming from fanout/split (ie. one component of a
83 * texture fetch, etc) and we have constraints on swizzle of
84 * destination, then skip it.
85 *
86 * We could possibly do a bit better, and copy-propagation if
87 * we can CP all components that are being fanned out.
88 */
89 if (src_instr->opc == OPC_META_SPLIT) {
90 if (!dst_instr)
91 return false;
92 if (dst_instr->opc == OPC_META_COLLECT)
93 return false;
94 if (dst_instr->cp.left || dst_instr->cp.right)
95 return false;
96 }
97
98 return true;
99 }
100 return false;
101 }
102
103 static unsigned cp_flags(unsigned flags)
104 {
105 /* only considering these flags (at least for now): */
106 flags &= (IR3_REG_CONST | IR3_REG_IMMED |
107 IR3_REG_FNEG | IR3_REG_FABS |
108 IR3_REG_SNEG | IR3_REG_SABS |
109 IR3_REG_BNOT | IR3_REG_RELATIV);
110 return flags;
111 }
112
113 static bool valid_flags(struct ir3_instruction *instr, unsigned n,
114 unsigned flags)
115 {
116 struct ir3_compiler *compiler = instr->block->shader->compiler;
117 unsigned valid_flags;
118
119 if ((flags & IR3_REG_HIGH) &&
120 (opc_cat(instr->opc) > 1) &&
121 (compiler->gpu_id >= 600))
122 return false;
123
124 flags = cp_flags(flags);
125
126 /* If destination is indirect, then source cannot be.. at least
127 * I don't think so..
128 */
129 if ((instr->regs[0]->flags & IR3_REG_RELATIV) &&
130 (flags & IR3_REG_RELATIV))
131 return false;
132
133 if (flags & IR3_REG_RELATIV) {
134 /* TODO need to test on earlier gens.. pretty sure the earlier
135 * problem was just that we didn't check that the src was from
136 * same block (since we can't propagate address register values
137 * across blocks currently)
138 */
139 if (compiler->gpu_id < 600)
140 return false;
141
142 /* NOTE in the special try_swap_mad_two_srcs() case we can be
143 * called on a src that has already had an indirect load folded
144 * in, in which case ssa() returns NULL
145 */
146 if (instr->regs[n+1]->flags & IR3_REG_SSA) {
147 struct ir3_instruction *src = ssa(instr->regs[n+1]);
148 if (src->address->block != instr->block)
149 return false;
150 }
151 }
152
153 switch (opc_cat(instr->opc)) {
154 case 1:
155 valid_flags = IR3_REG_IMMED | IR3_REG_CONST | IR3_REG_RELATIV;
156 if (flags & ~valid_flags)
157 return false;
158 break;
159 case 2:
160 valid_flags = ir3_cat2_absneg(instr->opc) |
161 IR3_REG_CONST | IR3_REG_RELATIV;
162
163 if (ir3_cat2_int(instr->opc))
164 valid_flags |= IR3_REG_IMMED;
165
166 if (flags & ~valid_flags)
167 return false;
168
169 if (flags & (IR3_REG_CONST | IR3_REG_IMMED)) {
170 unsigned m = (n ^ 1) + 1;
171 /* cannot deal w/ const in both srcs:
172 * (note that some cat2 actually only have a single src)
173 */
174 if (m < instr->regs_count) {
175 struct ir3_register *reg = instr->regs[m];
176 if ((flags & IR3_REG_CONST) && (reg->flags & IR3_REG_CONST))
177 return false;
178 if ((flags & IR3_REG_IMMED) && (reg->flags & IR3_REG_IMMED))
179 return false;
180 }
181 }
182 break;
183 case 3:
184 valid_flags = ir3_cat3_absneg(instr->opc) |
185 IR3_REG_CONST | IR3_REG_RELATIV;
186
187 if (flags & ~valid_flags)
188 return false;
189
190 if (flags & (IR3_REG_CONST | IR3_REG_RELATIV)) {
191 /* cannot deal w/ const/relativ in 2nd src: */
192 if (n == 1)
193 return false;
194 }
195
196 break;
197 case 4:
198 /* seems like blob compiler avoids const as src.. */
199 /* TODO double check if this is still the case on a4xx */
200 if (flags & (IR3_REG_CONST | IR3_REG_IMMED))
201 return false;
202 if (flags & (IR3_REG_SABS | IR3_REG_SNEG))
203 return false;
204 break;
205 case 5:
206 /* no flags allowed */
207 if (flags)
208 return false;
209 break;
210 case 6:
211 valid_flags = IR3_REG_IMMED;
212 if (flags & ~valid_flags)
213 return false;
214
215 if (flags & IR3_REG_IMMED) {
216 /* doesn't seem like we can have immediate src for store
217 * instructions:
218 *
219 * TODO this restriction could also apply to load instructions,
220 * but for load instructions this arg is the address (and not
221 * really sure any good way to test a hard-coded immed addr src)
222 */
223 if (is_store(instr) && (n == 1))
224 return false;
225
226 if ((instr->opc == OPC_LDL) && (n == 0))
227 return false;
228
229 if ((instr->opc == OPC_STL) && (n != 2))
230 return false;
231
232 if (instr->opc == OPC_STLW && n == 0)
233 return false;
234
235 if (instr->opc == OPC_LDLW && n == 0)
236 return false;
237
238 /* disallow immediates in anything but the SSBO slot argument for
239 * cat6 instructions:
240 */
241 if (is_atomic(instr->opc) && (n != 0))
242 return false;
243
244 if (is_atomic(instr->opc) && !(instr->flags & IR3_INSTR_G))
245 return false;
246
247 if (instr->opc == OPC_STG && (instr->flags & IR3_INSTR_G) && (n != 2))
248 return false;
249
250 /* as with atomics, these cat6 instrs can only have an immediate
251 * for SSBO/IBO slot argument
252 */
253 switch (instr->opc) {
254 case OPC_LDIB:
255 case OPC_LDC:
256 case OPC_RESINFO:
257 if (n != 0)
258 return false;
259 break;
260 default:
261 break;
262 }
263 }
264
265 break;
266 }
267
268 return true;
269 }
270
271 /* propagate register flags from src to dst.. negates need special
272 * handling to cancel each other out.
273 */
274 static void combine_flags(unsigned *dstflags, struct ir3_instruction *src)
275 {
276 unsigned srcflags = src->regs[1]->flags;
277
278 /* if what we are combining into already has (abs) flags,
279 * we can drop (neg) from src:
280 */
281 if (*dstflags & IR3_REG_FABS)
282 srcflags &= ~IR3_REG_FNEG;
283 if (*dstflags & IR3_REG_SABS)
284 srcflags &= ~IR3_REG_SNEG;
285
286 if (srcflags & IR3_REG_FABS)
287 *dstflags |= IR3_REG_FABS;
288 if (srcflags & IR3_REG_SABS)
289 *dstflags |= IR3_REG_SABS;
290 if (srcflags & IR3_REG_FNEG)
291 *dstflags ^= IR3_REG_FNEG;
292 if (srcflags & IR3_REG_SNEG)
293 *dstflags ^= IR3_REG_SNEG;
294 if (srcflags & IR3_REG_BNOT)
295 *dstflags ^= IR3_REG_BNOT;
296
297 *dstflags &= ~IR3_REG_SSA;
298 *dstflags |= srcflags & IR3_REG_SSA;
299 *dstflags |= srcflags & IR3_REG_CONST;
300 *dstflags |= srcflags & IR3_REG_IMMED;
301 *dstflags |= srcflags & IR3_REG_RELATIV;
302 *dstflags |= srcflags & IR3_REG_ARRAY;
303 *dstflags |= srcflags & IR3_REG_HIGH;
304
305 /* if src of the src is boolean we can drop the (abs) since we know
306 * the source value is already a postitive integer. This cleans
307 * up the absnegs that get inserted when converting between nir and
308 * native boolean (see ir3_b2n/n2b)
309 */
310 struct ir3_instruction *srcsrc = ssa(src->regs[1]);
311 if (srcsrc && is_bool(srcsrc))
312 *dstflags &= ~IR3_REG_SABS;
313 }
314
315 /* Tries lowering an immediate register argument to a const buffer access by
316 * adding to the list of immediates to be pushed to the const buffer when
317 * switching to this shader.
318 */
319 static bool
320 lower_immed(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr, unsigned n,
321 struct ir3_register *reg, unsigned new_flags)
322 {
323 if (!(new_flags & IR3_REG_IMMED))
324 return false;
325
326 new_flags &= ~IR3_REG_IMMED;
327 new_flags |= IR3_REG_CONST;
328
329 if (!valid_flags(instr, n, new_flags))
330 return false;
331
332 unsigned swiz, idx, i;
333
334 reg = ir3_reg_clone(ctx->shader, reg);
335
336 /* Half constant registers seems to handle only 32-bit values
337 * within floating-point opcodes. So convert back to 32-bit values.
338 */
339 bool f_opcode = (is_cat2_float(instr->opc) ||
340 is_cat3_float(instr->opc)) ? true : false;
341 if (f_opcode && (new_flags & IR3_REG_HALF))
342 reg->uim_val = fui(_mesa_half_to_float(reg->uim_val));
343
344 /* in some cases, there are restrictions on (abs)/(neg) plus const..
345 * so just evaluate those and clear the flags:
346 */
347 if (new_flags & IR3_REG_SABS) {
348 reg->iim_val = abs(reg->iim_val);
349 new_flags &= ~IR3_REG_SABS;
350 }
351
352 if (new_flags & IR3_REG_FABS) {
353 reg->fim_val = fabs(reg->fim_val);
354 new_flags &= ~IR3_REG_FABS;
355 }
356
357 if (new_flags & IR3_REG_SNEG) {
358 reg->iim_val = -reg->iim_val;
359 new_flags &= ~IR3_REG_SNEG;
360 }
361
362 if (new_flags & IR3_REG_FNEG) {
363 reg->fim_val = -reg->fim_val;
364 new_flags &= ~IR3_REG_FNEG;
365 }
366
367 /* Reallocate for 4 more elements whenever it's necessary */
368 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
369 if (const_state->immediate_idx == const_state->immediates_size * 4) {
370 const_state->immediates_size += 4;
371 const_state->immediates = realloc (const_state->immediates,
372 const_state->immediates_size * sizeof(const_state->immediates[0]));
373
374 for (int i = const_state->immediate_idx; i < const_state->immediates_size * 4; i++)
375 const_state->immediates[i / 4].val[i % 4] = 0xd0d0d0d0;
376 }
377
378 for (i = 0; i < const_state->immediate_idx; i++) {
379 swiz = i % 4;
380 idx = i / 4;
381
382 if (const_state->immediates[idx].val[swiz] == reg->uim_val) {
383 break;
384 }
385 }
386
387 if (i == const_state->immediate_idx) {
388 struct ir3_compiler *compiler = instr->block->shader->compiler;
389 /* Add on a new immediate to be pushed, if we have space left in the
390 * constbuf.
391 */
392 if (const_state->offsets.immediate + const_state->immediate_idx / 4 >=
393 compiler->max_const)
394 return false;
395
396 swiz = i % 4;
397 idx = i / 4;
398
399 const_state->immediates[idx].val[swiz] = reg->uim_val;
400 const_state->immediates_count = idx + 1;
401 const_state->immediate_idx++;
402 }
403
404 reg->flags = new_flags;
405 reg->num = i + (4 * const_state->offsets.immediate);
406
407 instr->regs[n + 1] = reg;
408
409 return true;
410 }
411
412 static void
413 unuse(struct ir3_instruction *instr)
414 {
415 debug_assert(instr->use_count > 0);
416
417 if (--instr->use_count == 0) {
418 struct ir3_block *block = instr->block;
419
420 instr->barrier_class = 0;
421 instr->barrier_conflict = 0;
422
423 /* we don't want to remove anything in keeps (which could
424 * be things like array store's)
425 */
426 for (unsigned i = 0; i < block->keeps_count; i++) {
427 debug_assert(block->keeps[i] != instr);
428 }
429 }
430 }
431
432 /**
433 * Handles the special case of the 2nd src (n == 1) to "normal" mad
434 * instructions, which cannot reference a constant. See if it is
435 * possible to swap the 1st and 2nd sources.
436 */
437 static bool
438 try_swap_mad_two_srcs(struct ir3_instruction *instr, unsigned new_flags)
439 {
440 if (!is_mad(instr->opc))
441 return false;
442
443 /* NOTE: pre-swap first two src's before valid_flags(),
444 * which might try to dereference the n'th src:
445 */
446 swap(instr->regs[0 + 1], instr->regs[1 + 1]);
447
448 /* cat3 doesn't encode immediate, but we can lower immediate
449 * to const if that helps:
450 */
451 if (new_flags & IR3_REG_IMMED) {
452 new_flags &= ~IR3_REG_IMMED;
453 new_flags |= IR3_REG_CONST;
454 }
455
456 bool valid_swap =
457 /* can we propagate mov if we move 2nd src to first? */
458 valid_flags(instr, 0, new_flags) &&
459 /* and does first src fit in second slot? */
460 valid_flags(instr, 1, instr->regs[1 + 1]->flags);
461
462 if (!valid_swap) {
463 /* put things back the way they were: */
464 swap(instr->regs[0 + 1], instr->regs[1 + 1]);
465 } /* otherwise leave things swapped */
466
467 return valid_swap;
468 }
469
470 /**
471 * Handle cp for a given src register. This additionally handles
472 * the cases of collapsing immedate/const (which replace the src
473 * register with a non-ssa src) or collapsing mov's from relative
474 * src (which needs to also fixup the address src reference by the
475 * instruction).
476 */
477 static bool
478 reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr,
479 struct ir3_register *reg, unsigned n)
480 {
481 struct ir3_instruction *src = ssa(reg);
482
483 if (is_eligible_mov(src, instr, true)) {
484 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */
485 struct ir3_register *src_reg = src->regs[1];
486 unsigned new_flags = reg->flags;
487
488 combine_flags(&new_flags, src);
489
490 if (valid_flags(instr, n, new_flags)) {
491 if (new_flags & IR3_REG_ARRAY) {
492 debug_assert(!(reg->flags & IR3_REG_ARRAY));
493 reg->array = src_reg->array;
494 }
495 reg->flags = new_flags;
496 reg->instr = ssa(src_reg);
497
498 instr->barrier_class |= src->barrier_class;
499 instr->barrier_conflict |= src->barrier_conflict;
500
501 unuse(src);
502 reg->instr->use_count++;
503
504 return true;
505 }
506 } else if ((is_same_type_mov(src) || is_const_mov(src)) &&
507 /* cannot collapse const/immed/etc into meta instrs: */
508 !is_meta(instr)) {
509 /* immed/const/etc cases, which require some special handling: */
510 struct ir3_register *src_reg = src->regs[1];
511 unsigned new_flags = reg->flags;
512
513 combine_flags(&new_flags, src);
514
515 if (!valid_flags(instr, n, new_flags)) {
516 /* See if lowering an immediate to const would help. */
517 if (lower_immed(ctx, instr, n, src_reg, new_flags))
518 return true;
519
520 /* special case for "normal" mad instructions, we can
521 * try swapping the first two args if that fits better.
522 *
523 * the "plain" MAD's (ie. the ones that don't shift first
524 * src prior to multiply) can swap their first two srcs if
525 * src[0] is !CONST and src[1] is CONST:
526 */
527 if ((n == 1) && try_swap_mad_two_srcs(instr, new_flags)) {
528 return true;
529 } else {
530 return false;
531 }
532 }
533
534 /* Here we handle the special case of mov from
535 * CONST and/or RELATIV. These need to be handled
536 * specially, because in the case of move from CONST
537 * there is no src ir3_instruction so we need to
538 * replace the ir3_register. And in the case of
539 * RELATIV we need to handle the address register
540 * dependency.
541 */
542 if (src_reg->flags & IR3_REG_CONST) {
543 /* an instruction cannot reference two different
544 * address registers:
545 */
546 if ((src_reg->flags & IR3_REG_RELATIV) &&
547 conflicts(instr->address, reg->instr->address))
548 return false;
549
550 /* This seems to be a hw bug, or something where the timings
551 * just somehow don't work out. This restriction may only
552 * apply if the first src is also CONST.
553 */
554 if ((opc_cat(instr->opc) == 3) && (n == 2) &&
555 (src_reg->flags & IR3_REG_RELATIV) &&
556 (src_reg->array.offset == 0))
557 return false;
558
559 /* When narrowing constant from 32b to 16b, it seems
560 * to work only for float. So we should do this only with
561 * float opcodes.
562 */
563 if (src->cat1.dst_type == TYPE_F16) {
564 if (instr->opc == OPC_MOV && !type_float(instr->cat1.src_type))
565 return false;
566 if (!is_cat2_float(instr->opc) && !is_cat3_float(instr->opc))
567 return false;
568 }
569
570 src_reg = ir3_reg_clone(instr->block->shader, src_reg);
571 src_reg->flags = new_flags;
572 instr->regs[n+1] = src_reg;
573
574 if (src_reg->flags & IR3_REG_RELATIV)
575 ir3_instr_set_address(instr, reg->instr->address);
576
577 return true;
578 }
579
580 if ((src_reg->flags & IR3_REG_RELATIV) &&
581 !conflicts(instr->address, reg->instr->address)) {
582 src_reg = ir3_reg_clone(instr->block->shader, src_reg);
583 src_reg->flags = new_flags;
584 instr->regs[n+1] = src_reg;
585 ir3_instr_set_address(instr, reg->instr->address);
586
587 return true;
588 }
589
590 /* NOTE: seems we can only do immed integers, so don't
591 * need to care about float. But we do need to handle
592 * abs/neg *before* checking that the immediate requires
593 * few enough bits to encode:
594 *
595 * TODO: do we need to do something to avoid accidentally
596 * catching a float immed?
597 */
598 if (src_reg->flags & IR3_REG_IMMED) {
599 int32_t iim_val = src_reg->iim_val;
600
601 debug_assert((opc_cat(instr->opc) == 1) ||
602 (opc_cat(instr->opc) == 6) ||
603 ir3_cat2_int(instr->opc) ||
604 (is_mad(instr->opc) && (n == 0)));
605
606 if (new_flags & IR3_REG_SABS)
607 iim_val = abs(iim_val);
608
609 if (new_flags & IR3_REG_SNEG)
610 iim_val = -iim_val;
611
612 if (new_flags & IR3_REG_BNOT)
613 iim_val = ~iim_val;
614
615 /* other than category 1 (mov) we can only encode up to 10 bits: */
616 if (valid_flags(instr, n, new_flags) &&
617 ((instr->opc == OPC_MOV) ||
618 !((iim_val & ~0x3ff) && (-iim_val & ~0x3ff)))) {
619 new_flags &= ~(IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT);
620 src_reg = ir3_reg_clone(instr->block->shader, src_reg);
621 src_reg->flags = new_flags;
622 src_reg->iim_val = iim_val;
623 instr->regs[n+1] = src_reg;
624
625 return true;
626 } else if (lower_immed(ctx, instr, n, src_reg, new_flags)) {
627 /* Fell back to loading the immediate as a const */
628 return true;
629 }
630 }
631 }
632
633 return false;
634 }
635
636 /* Handle special case of eliminating output mov, and similar cases where
637 * there isn't a normal "consuming" instruction. In this case we cannot
638 * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
639 * be eliminated)
640 */
641 static struct ir3_instruction *
642 eliminate_output_mov(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
643 {
644 if (is_eligible_mov(instr, NULL, false)) {
645 struct ir3_register *reg = instr->regs[1];
646 if (!(reg->flags & IR3_REG_ARRAY)) {
647 struct ir3_instruction *src_instr = ssa(reg);
648 debug_assert(src_instr);
649 ctx->progress = true;
650 return src_instr;
651 }
652 }
653 return instr;
654 }
655
656 /**
657 * Find instruction src's which are mov's that can be collapsed, replacing
658 * the mov dst with the mov src
659 */
660 static void
661 instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
662 {
663 if (instr->regs_count == 0)
664 return;
665
666 if (ir3_instr_check_mark(instr))
667 return;
668
669 /* walk down the graph from each src: */
670 bool progress;
671 do {
672 progress = false;
673 foreach_src_n (reg, n, instr) {
674 struct ir3_instruction *src = ssa(reg);
675
676 if (!src)
677 continue;
678
679 instr_cp(ctx, src);
680
681 /* TODO non-indirect access we could figure out which register
682 * we actually want and allow cp..
683 */
684 if (reg->flags & IR3_REG_ARRAY)
685 continue;
686
687 /* Don't CP absneg into meta instructions, that won't end well: */
688 if (is_meta(instr) && (src->opc != OPC_MOV))
689 continue;
690
691 progress |= reg_cp(ctx, instr, reg, n);
692 ctx->progress |= progress;
693 }
694 } while (progress);
695
696 if (instr->regs[0]->flags & IR3_REG_ARRAY) {
697 struct ir3_instruction *src = ssa(instr->regs[0]);
698 if (src)
699 instr_cp(ctx, src);
700 }
701
702 if (instr->address) {
703 instr_cp(ctx, instr->address);
704 ir3_instr_set_address(instr, eliminate_output_mov(ctx, instr->address));
705 }
706
707 /* we can end up with extra cmps.s from frontend, which uses a
708 *
709 * cmps.s p0.x, cond, 0
710 *
711 * as a way to mov into the predicate register. But frequently 'cond'
712 * is itself a cmps.s/cmps.f/cmps.u. So detect this special case and
713 * just re-write the instruction writing predicate register to get rid
714 * of the double cmps.
715 */
716 if ((instr->opc == OPC_CMPS_S) &&
717 (instr->regs[0]->num == regid(REG_P0, 0)) &&
718 ssa(instr->regs[1]) &&
719 (instr->regs[2]->flags & IR3_REG_IMMED) &&
720 (instr->regs[2]->iim_val == 0) &&
721 (instr->cat2.condition == IR3_COND_NE)) {
722 struct ir3_instruction *cond = ssa(instr->regs[1]);
723 switch (cond->opc) {
724 case OPC_CMPS_S:
725 case OPC_CMPS_F:
726 case OPC_CMPS_U:
727 instr->opc = cond->opc;
728 instr->flags = cond->flags;
729 instr->cat2 = cond->cat2;
730 ir3_instr_set_address(instr, cond->address);
731 instr->regs[1] = cond->regs[1];
732 instr->regs[2] = cond->regs[2];
733 instr->barrier_class |= cond->barrier_class;
734 instr->barrier_conflict |= cond->barrier_conflict;
735 unuse(cond);
736 ctx->progress = true;
737 break;
738 default:
739 break;
740 }
741 }
742
743 /* Handle converting a sam.s2en (taking samp/tex idx params via register)
744 * into a normal sam (encoding immediate samp/tex idx) if they are
745 * immediate. This saves some instructions and regs in the common case
746 * where we know samp/tex at compile time. This needs to be done in the
747 * frontend for bindless tex, though, so don't replicate it here.
748 */
749 if (is_tex(instr) && (instr->flags & IR3_INSTR_S2EN) &&
750 !(instr->flags & IR3_INSTR_B) &&
751 !(ir3_shader_debug & IR3_DBG_FORCES2EN)) {
752 /* The first src will be a collect, if both of it's
753 * two sources are mov from imm, then we can
754 */
755 struct ir3_instruction *samp_tex = ssa(instr->regs[1]);
756
757 debug_assert(samp_tex->opc == OPC_META_COLLECT);
758
759 struct ir3_instruction *samp = ssa(samp_tex->regs[1]);
760 struct ir3_instruction *tex = ssa(samp_tex->regs[2]);
761
762 if ((samp->opc == OPC_MOV) &&
763 (samp->regs[1]->flags & IR3_REG_IMMED) &&
764 (tex->opc == OPC_MOV) &&
765 (tex->regs[1]->flags & IR3_REG_IMMED)) {
766 instr->flags &= ~IR3_INSTR_S2EN;
767 instr->cat5.samp = samp->regs[1]->iim_val;
768 instr->cat5.tex = tex->regs[1]->iim_val;
769
770 /* shuffle around the regs to remove the first src: */
771 instr->regs_count--;
772 for (unsigned i = 1; i < instr->regs_count; i++) {
773 instr->regs[i] = instr->regs[i + 1];
774 }
775
776 ctx->progress = true;
777 }
778 }
779 }
780
781 bool
782 ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so)
783 {
784 struct ir3_cp_ctx ctx = {
785 .shader = ir,
786 .so = so,
787 };
788
789 /* This is a bit annoying, and probably wouldn't be necessary if we
790 * tracked a reverse link from producing instruction to consumer.
791 * But we need to know when we've eliminated the last consumer of
792 * a mov, so we need to do a pass to first count consumers of a
793 * mov.
794 */
795 foreach_block (block, &ir->block_list) {
796 foreach_instr (instr, &block->instr_list) {
797
798 /* by the way, we don't account for false-dep's, so the CP
799 * pass should always happen before false-dep's are inserted
800 */
801 debug_assert(instr->deps_count == 0);
802
803 foreach_ssa_src (src, instr) {
804 src->use_count++;
805 }
806 }
807 }
808
809 ir3_clear_mark(ir);
810
811 foreach_output_n (out, n, ir) {
812 instr_cp(&ctx, out);
813 ir->outputs[n] = eliminate_output_mov(&ctx, out);
814 }
815
816 foreach_block (block, &ir->block_list) {
817 if (block->condition) {
818 instr_cp(&ctx, block->condition);
819 block->condition = eliminate_output_mov(&ctx, block->condition);
820 }
821
822 for (unsigned i = 0; i < block->keeps_count; i++) {
823 instr_cp(&ctx, block->keeps[i]);
824 block->keeps[i] = eliminate_output_mov(&ctx, block->keeps[i]);
825 }
826 }
827
828 return ctx.progress;
829 }