src/freedreno/ir3/ir3_cp.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include <math.h>
  28 #include "util/half_float.h"
  29 #include "util/u_math.h"
  30
  31 #include "ir3.h"
  32 #include "ir3_compiler.h"
  33 #include "ir3_shader.h"
  34
  35 #define swap(a, b) \
  36         do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
  37
  38 /*
  39  * Copy Propagate:
  40  */
  41
  42 struct ir3_cp_ctx {
  43         struct ir3 *shader;
  44         struct ir3_shader_variant *so;
  45 };
  46
  47 /* is it a type preserving mov, with ok flags?
  48  *
  49  * @instr: the mov to consider removing
  50  * @dst_instr: the instruction consuming the mov (instr)
  51  *
  52  * TODO maybe drop allow_flags since this is only false when dst is
  53  * NULL (ie. outputs)
  54  */
  55 static bool is_eligible_mov(struct ir3_instruction *instr,
  56                 struct ir3_instruction *dst_instr, bool allow_flags)
  57 {
  58         if (is_same_type_mov(instr)) {
  59                 struct ir3_register *dst = instr->regs[0];
  60                 struct ir3_register *src = instr->regs[1];
  61                 struct ir3_instruction *src_instr = ssa(src);
  62
  63                 /* only if mov src is SSA (not const/immed): */
  64                 if (!src_instr)
  65                         return false;
  66
  67                 /* no indirect: */
  68                 if (dst->flags & IR3_REG_RELATIV)
  69                         return false;
  70                 if (src->flags & IR3_REG_RELATIV)
  71                         return false;
  72
  73                 if (src->flags & IR3_REG_ARRAY)
  74                         return false;
  75
  76                 if (!allow_flags)
  77                         if (src->flags & (IR3_REG_FABS | IR3_REG_FNEG |
  78                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
  79                                 return false;
  80
  81                 /* If src is coming from fanout/split (ie. one component of a
  82                  * texture fetch, etc) and we have constraints on swizzle of
  83                  * destination, then skip it.
  84                  *
  85                  * We could possibly do a bit better, and copy-propagation if
  86                  * we can CP all components that are being fanned out.
  87                  */
  88                 if (src_instr->opc == OPC_META_SPLIT) {
  89                         if (!dst_instr)
  90                                 return false;
  91                         if (dst_instr->opc == OPC_META_COLLECT)
  92                                 return false;
  93                         if (dst_instr->cp.left || dst_instr->cp.right)
  94                                 return false;
  95                 }
  96
  97                 return true;
  98         }
  99         return false;
 100 }
 101
 102 static unsigned cp_flags(unsigned flags)
 103 {
 104         /* only considering these flags (at least for now): */
 105         flags &= (IR3_REG_CONST | IR3_REG_IMMED |
 106                         IR3_REG_FNEG | IR3_REG_FABS |
 107                         IR3_REG_SNEG | IR3_REG_SABS |
 108                         IR3_REG_BNOT | IR3_REG_RELATIV);
 109         return flags;
 110 }
 111
 112 static bool valid_flags(struct ir3_instruction *instr, unsigned n,
 113                 unsigned flags)
 114 {
 115         struct ir3_compiler *compiler = instr->block->shader->compiler;
 116         unsigned valid_flags;
 117
 118         if ((flags & IR3_REG_HIGH) &&
 119                         (opc_cat(instr->opc) > 1) &&
 120                         (compiler->gpu_id >= 600))
 121                 return false;
 122
 123         flags = cp_flags(flags);
 124
 125         /* If destination is indirect, then source cannot be.. at least
 126          * I don't think so..
 127          */
 128         if ((instr->regs[0]->flags & IR3_REG_RELATIV) &&
 129                         (flags & IR3_REG_RELATIV))
 130                 return false;
 131
 132         if (flags & IR3_REG_RELATIV) {
 133                 /* TODO need to test on earlier gens.. pretty sure the earlier
 134                  * problem was just that we didn't check that the src was from
 135                  * same block (since we can't propagate address register values
 136                  * across blocks currently)
 137                  */
 138                 if (compiler->gpu_id < 600)
 139                         return false;
 140
 141                 /* NOTE in the special try_swap_mad_two_srcs() case we can be
 142                  * called on a src that has already had an indirect load folded
 143                  * in, in which case ssa() returns NULL
 144                  */
 145                 struct ir3_instruction *src = ssa(instr->regs[n+1]);
 146                 if (src && src->address->block != instr->block)
 147                         return false;
 148         }
 149
 150         switch (opc_cat(instr->opc)) {
 151         case 1:
 152                 valid_flags = IR3_REG_IMMED | IR3_REG_CONST | IR3_REG_RELATIV;
 153                 if (flags & ~valid_flags)
 154                         return false;
 155                 break;
 156         case 2:
 157                 valid_flags = ir3_cat2_absneg(instr->opc) |
 158                                 IR3_REG_CONST | IR3_REG_RELATIV;
 159
 160                 if (ir3_cat2_int(instr->opc))
 161                         valid_flags |= IR3_REG_IMMED;
 162
 163                 if (flags & ~valid_flags)
 164                         return false;
 165
 166                 if (flags & (IR3_REG_CONST | IR3_REG_IMMED)) {
 167                         unsigned m = (n ^ 1) + 1;
 168                         /* cannot deal w/ const in both srcs:
 169                          * (note that some cat2 actually only have a single src)
 170                          */
 171                         if (m < instr->regs_count) {
 172                                 struct ir3_register *reg = instr->regs[m];
 173                                 if ((flags & IR3_REG_CONST) && (reg->flags & IR3_REG_CONST))
 174                                         return false;
 175                                 if ((flags & IR3_REG_IMMED) && (reg->flags & IR3_REG_IMMED))
 176                                         return false;
 177                         }
 178                 }
 179                 break;
 180         case 3:
 181                 valid_flags = ir3_cat3_absneg(instr->opc) |
 182                                 IR3_REG_CONST | IR3_REG_RELATIV;
 183
 184                 if (flags & ~valid_flags)
 185                         return false;
 186
 187                 if (flags & (IR3_REG_CONST | IR3_REG_RELATIV)) {
 188                         /* cannot deal w/ const/relativ in 2nd src: */
 189                         if (n == 1)
 190                                 return false;
 191                 }
 192
 193                 break;
 194         case 4:
 195                 /* seems like blob compiler avoids const as src.. */
 196                 /* TODO double check if this is still the case on a4xx */
 197                 if (flags & (IR3_REG_CONST | IR3_REG_IMMED))
 198                         return false;
 199                 if (flags & (IR3_REG_SABS | IR3_REG_SNEG))
 200                         return false;
 201                 break;
 202         case 5:
 203                 /* no flags allowed */
 204                 if (flags)
 205                         return false;
 206                 break;
 207         case 6:
 208                 valid_flags = IR3_REG_IMMED;
 209                 if (flags & ~valid_flags)
 210                         return false;
 211
 212                 if (flags & IR3_REG_IMMED) {
 213                         /* doesn't seem like we can have immediate src for store
 214                          * instructions:
 215                          *
 216                          * TODO this restriction could also apply to load instructions,
 217                          * but for load instructions this arg is the address (and not
 218                          * really sure any good way to test a hard-coded immed addr src)
 219                          */
 220                         if (is_store(instr) && (n == 1))
 221                                 return false;
 222
 223                         if ((instr->opc == OPC_LDL) && (n == 0))
 224                                 return false;
 225
 226                         if ((instr->opc == OPC_STL) && (n != 2))
 227                                 return false;
 228
 229                         if (instr->opc == OPC_STLW && n == 0)
 230                                 return false;
 231
 232                         if (instr->opc == OPC_LDLW && n == 0)
 233                                 return false;
 234
 235                         /* disallow CP into anything but the SSBO slot argument for
 236                          * atomics:
 237                          */
 238                         if (is_atomic(instr->opc) && (n != 0))
 239                                 return false;
 240
 241                         if (is_atomic(instr->opc) && !(instr->flags & IR3_INSTR_G))
 242                                 return false;
 243
 244                         if (instr->opc == OPC_STG && (instr->flags & IR3_INSTR_G) && (n != 2))
 245                                 return false;
 246
 247                         /* as with atomics, ldib and ldc on a6xx can only have immediate
 248                          * for SSBO slot argument
 249                          */
 250                         if ((instr->opc == OPC_LDIB || instr->opc == OPC_LDC) && (n != 0))
 251                                 return false;
 252                 }
 253
 254                 break;
 255         }
 256
 257         return true;
 258 }
 259
 260 /* propagate register flags from src to dst.. negates need special
 261  * handling to cancel each other out.
 262  */
 263 static void combine_flags(unsigned *dstflags, struct ir3_instruction *src)
 264 {
 265         unsigned srcflags = src->regs[1]->flags;
 266
 267         /* if what we are combining into already has (abs) flags,
 268          * we can drop (neg) from src:
 269          */
 270         if (*dstflags & IR3_REG_FABS)
 271                 srcflags &= ~IR3_REG_FNEG;
 272         if (*dstflags & IR3_REG_SABS)
 273                 srcflags &= ~IR3_REG_SNEG;
 274
 275         if (srcflags & IR3_REG_FABS)
 276                 *dstflags |= IR3_REG_FABS;
 277         if (srcflags & IR3_REG_SABS)
 278                 *dstflags |= IR3_REG_SABS;
 279         if (srcflags & IR3_REG_FNEG)
 280                 *dstflags ^= IR3_REG_FNEG;
 281         if (srcflags & IR3_REG_SNEG)
 282                 *dstflags ^= IR3_REG_SNEG;
 283         if (srcflags & IR3_REG_BNOT)
 284                 *dstflags ^= IR3_REG_BNOT;
 285
 286         *dstflags &= ~IR3_REG_SSA;
 287         *dstflags |= srcflags & IR3_REG_SSA;
 288         *dstflags |= srcflags & IR3_REG_CONST;
 289         *dstflags |= srcflags & IR3_REG_IMMED;
 290         *dstflags |= srcflags & IR3_REG_RELATIV;
 291         *dstflags |= srcflags & IR3_REG_ARRAY;
 292         *dstflags |= srcflags & IR3_REG_HIGH;
 293
 294         /* if src of the src is boolean we can drop the (abs) since we know
 295          * the source value is already a postitive integer.  This cleans
 296          * up the absnegs that get inserted when converting between nir and
 297          * native boolean (see ir3_b2n/n2b)
 298          */
 299         struct ir3_instruction *srcsrc = ssa(src->regs[1]);
 300         if (srcsrc && is_bool(srcsrc))
 301                 *dstflags &= ~IR3_REG_SABS;
 302 }
 303
 304 static struct ir3_register *
 305 lower_immed(struct ir3_cp_ctx *ctx, struct ir3_register *reg, unsigned new_flags, bool f_opcode)
 306 {
 307         unsigned swiz, idx, i;
 308
 309         reg = ir3_reg_clone(ctx->shader, reg);
 310
 311         /* Half constant registers seems to handle only 32-bit values
 312          * within floating-point opcodes. So convert back to 32-bit values.
 313          */
 314         if (f_opcode && (new_flags & IR3_REG_HALF))
 315                 reg->uim_val = fui(_mesa_half_to_float(reg->uim_val));
 316
 317         /* in some cases, there are restrictions on (abs)/(neg) plus const..
 318          * so just evaluate those and clear the flags:
 319          */
 320         if (new_flags & IR3_REG_SABS) {
 321                 reg->iim_val = abs(reg->iim_val);
 322                 new_flags &= ~IR3_REG_SABS;
 323         }
 324
 325         if (new_flags & IR3_REG_FABS) {
 326                 reg->fim_val = fabs(reg->fim_val);
 327                 new_flags &= ~IR3_REG_FABS;
 328         }
 329
 330         if (new_flags & IR3_REG_SNEG) {
 331                 reg->iim_val = -reg->iim_val;
 332                 new_flags &= ~IR3_REG_SNEG;
 333         }
 334
 335         if (new_flags & IR3_REG_FNEG) {
 336                 reg->fim_val = -reg->fim_val;
 337                 new_flags &= ~IR3_REG_FNEG;
 338         }
 339
 340         /* Reallocate for 4 more elements whenever it's necessary */
 341         struct ir3_const_state *const_state = &ctx->so->shader->const_state;
 342         if (const_state->immediate_idx == const_state->immediates_size * 4) {
 343                 const_state->immediates_size += 4;
 344                 const_state->immediates = realloc (const_state->immediates,
 345                         const_state->immediates_size * sizeof(const_state->immediates[0]));
 346
 347                 for (int i = const_state->immediate_idx; i < const_state->immediates_size * 4; i++)
 348                         const_state->immediates[i / 4].val[i % 4] = 0xd0d0d0d0;
 349         }
 350
 351         for (i = 0; i < const_state->immediate_idx; i++) {
 352                 swiz = i % 4;
 353                 idx  = i / 4;
 354
 355                 if (const_state->immediates[idx].val[swiz] == reg->uim_val) {
 356                         break;
 357                 }
 358         }
 359
 360         if (i == const_state->immediate_idx) {
 361                 /* need to generate a new immediate: */
 362                 swiz = i % 4;
 363                 idx  = i / 4;
 364
 365                 const_state->immediates[idx].val[swiz] = reg->uim_val;
 366                 const_state->immediates_count = idx + 1;
 367                 const_state->immediate_idx++;
 368         }
 369
 370         new_flags &= ~IR3_REG_IMMED;
 371         new_flags |= IR3_REG_CONST;
 372         reg->flags = new_flags;
 373         reg->num = i + (4 * const_state->offsets.immediate);
 374
 375         return reg;
 376 }
 377
 378 static void
 379 unuse(struct ir3_instruction *instr)
 380 {
 381         debug_assert(instr->use_count > 0);
 382
 383         if (--instr->use_count == 0) {
 384                 struct ir3_block *block = instr->block;
 385
 386                 instr->barrier_class = 0;
 387                 instr->barrier_conflict = 0;
 388
 389                 /* we don't want to remove anything in keeps (which could
 390                  * be things like array store's)
 391                  */
 392                 for (unsigned i = 0; i < block->keeps_count; i++) {
 393                         debug_assert(block->keeps[i] != instr);
 394                 }
 395         }
 396 }
 397
 398 /**
 399  * Handles the special case of the 2nd src (n == 1) to "normal" mad
 400  * instructions, which cannot reference a constant.  See if it is
 401  * possible to swap the 1st and 2nd sources.
 402  */
 403 static bool
 404 try_swap_mad_two_srcs(struct ir3_instruction *instr, unsigned new_flags)
 405 {
 406         if (!is_mad(instr->opc))
 407                 return false;
 408
 409         /* NOTE: pre-swap first two src's before valid_flags(),
 410          * which might try to dereference the n'th src:
 411          */
 412         swap(instr->regs[0 + 1], instr->regs[1 + 1]);
 413
 414         /* cat3 doesn't encode immediate, but we can lower immediate
 415          * to const if that helps:
 416          */
 417         if (new_flags & IR3_REG_IMMED) {
 418                 new_flags &= ~IR3_REG_IMMED;
 419                 new_flags |=  IR3_REG_CONST;
 420         }
 421
 422         bool valid_swap =
 423                 /* can we propagate mov if we move 2nd src to first? */
 424                 valid_flags(instr, 0, new_flags) &&
 425                 /* and does first src fit in second slot? */
 426                 valid_flags(instr, 1, instr->regs[1 + 1]->flags);
 427
 428         if (!valid_swap) {
 429                 /* put things back the way they were: */
 430                 swap(instr->regs[0 + 1], instr->regs[1 + 1]);
 431         }   /* otherwise leave things swapped */
 432
 433         return valid_swap;
 434 }
 435
 436 /**
 437  * Handle cp for a given src register.  This additionally handles
 438  * the cases of collapsing immedate/const (which replace the src
 439  * register with a non-ssa src) or collapsing mov's from relative
 440  * src (which needs to also fixup the address src reference by the
 441  * instruction).
 442  */
 443 static bool
 444 reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr,
 445                 struct ir3_register *reg, unsigned n)
 446 {
 447         struct ir3_instruction *src = ssa(reg);
 448
 449         if (is_eligible_mov(src, instr, true)) {
 450                 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */
 451                 struct ir3_register *src_reg = src->regs[1];
 452                 unsigned new_flags = reg->flags;
 453
 454                 combine_flags(&new_flags, src);
 455
 456                 if (valid_flags(instr, n, new_flags)) {
 457                         if (new_flags & IR3_REG_ARRAY) {
 458                                 debug_assert(!(reg->flags & IR3_REG_ARRAY));
 459                                 reg->array = src_reg->array;
 460                         }
 461                         reg->flags = new_flags;
 462                         reg->instr = ssa(src_reg);
 463
 464                         instr->barrier_class |= src->barrier_class;
 465                         instr->barrier_conflict |= src->barrier_conflict;
 466
 467                         unuse(src);
 468                         reg->instr->use_count++;
 469
 470                         return true;
 471                 }
 472         } else if ((is_same_type_mov(src) || is_const_mov(src)) &&
 473                         /* cannot collapse const/immed/etc into meta instrs: */
 474                         !is_meta(instr)) {
 475                 /* immed/const/etc cases, which require some special handling: */
 476                 struct ir3_register *src_reg = src->regs[1];
 477                 unsigned new_flags = reg->flags;
 478
 479                 combine_flags(&new_flags, src);
 480
 481                 if (!valid_flags(instr, n, new_flags)) {
 482                         /* See if lowering an immediate to const would help. */
 483                         if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) {
 484                                 bool f_opcode = (is_cat2_float(instr->opc) ||
 485                                                 is_cat3_float(instr->opc)) ? true : false;
 486
 487                                 debug_assert(new_flags & IR3_REG_IMMED);
 488
 489                                 instr->regs[n + 1] = lower_immed(ctx, src_reg, new_flags, f_opcode);
 490                                 return true;
 491                         }
 492
 493                         /* special case for "normal" mad instructions, we can
 494                          * try swapping the first two args if that fits better.
 495                          *
 496                          * the "plain" MAD's (ie. the ones that don't shift first
 497                          * src prior to multiply) can swap their first two srcs if
 498                          * src[0] is !CONST and src[1] is CONST:
 499                          */
 500                         if ((n == 1) && try_swap_mad_two_srcs(instr, new_flags)) {
 501                                 return true;
 502                         } else {
 503                                 return false;
 504                         }
 505                 }
 506
 507                 /* Here we handle the special case of mov from
 508                  * CONST and/or RELATIV.  These need to be handled
 509                  * specially, because in the case of move from CONST
 510                  * there is no src ir3_instruction so we need to
 511                  * replace the ir3_register.  And in the case of
 512                  * RELATIV we need to handle the address register
 513                  * dependency.
 514                  */
 515                 if (src_reg->flags & IR3_REG_CONST) {
 516                         /* an instruction cannot reference two different
 517                          * address registers:
 518                          */
 519                         if ((src_reg->flags & IR3_REG_RELATIV) &&
 520                                         conflicts(instr->address, reg->instr->address))
 521                                 return false;
 522
 523                         /* This seems to be a hw bug, or something where the timings
 524                          * just somehow don't work out.  This restriction may only
 525                          * apply if the first src is also CONST.
 526                          */
 527                         if ((opc_cat(instr->opc) == 3) && (n == 2) &&
 528                                         (src_reg->flags & IR3_REG_RELATIV) &&
 529                                         (src_reg->array.offset == 0))
 530                                 return false;
 531
 532                         /* When narrowing constant from 32b to 16b, it seems
 533                          * to work only for float. So we should do this only with
 534                          * float opcodes.
 535                          */
 536                         if (src->cat1.dst_type == TYPE_F16) {
 537                                 if (instr->opc == OPC_MOV && !type_float(instr->cat1.src_type))
 538                                         return false;
 539                                 if (!is_cat2_float(instr->opc) && !is_cat3_float(instr->opc))
 540                                         return false;
 541                         }
 542
 543                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 544                         src_reg->flags = new_flags;
 545                         instr->regs[n+1] = src_reg;
 546
 547                         if (src_reg->flags & IR3_REG_RELATIV)
 548                                 ir3_instr_set_address(instr, reg->instr->address);
 549
 550                         return true;
 551                 }
 552
 553                 if ((src_reg->flags & IR3_REG_RELATIV) &&
 554                                 !conflicts(instr->address, reg->instr->address)) {
 555                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 556                         src_reg->flags = new_flags;
 557                         instr->regs[n+1] = src_reg;
 558                         ir3_instr_set_address(instr, reg->instr->address);
 559
 560                         return true;
 561                 }
 562
 563                 /* NOTE: seems we can only do immed integers, so don't
 564                  * need to care about float.  But we do need to handle
 565                  * abs/neg *before* checking that the immediate requires
 566                  * few enough bits to encode:
 567                  *
 568                  * TODO: do we need to do something to avoid accidentally
 569                  * catching a float immed?
 570                  */
 571                 if (src_reg->flags & IR3_REG_IMMED) {
 572                         int32_t iim_val = src_reg->iim_val;
 573
 574                         debug_assert((opc_cat(instr->opc) == 1) ||
 575                                         (opc_cat(instr->opc) == 6) ||
 576                                         ir3_cat2_int(instr->opc) ||
 577                                         (is_mad(instr->opc) && (n == 0)));
 578
 579                         if (new_flags & IR3_REG_SABS)
 580                                 iim_val = abs(iim_val);
 581
 582                         if (new_flags & IR3_REG_SNEG)
 583                                 iim_val = -iim_val;
 584
 585                         if (new_flags & IR3_REG_BNOT)
 586                                 iim_val = ~iim_val;
 587
 588                         /* other than category 1 (mov) we can only encode up to 10 bits: */
 589                         if (valid_flags(instr, n, new_flags) &&
 590                                         ((instr->opc == OPC_MOV) ||
 591                                          !((iim_val & ~0x3ff) && (-iim_val & ~0x3ff)))) {
 592                                 new_flags &= ~(IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT);
 593                                 src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 594                                 src_reg->flags = new_flags;
 595                                 src_reg->iim_val = iim_val;
 596                                 instr->regs[n+1] = src_reg;
 597
 598                                 return true;
 599                         } else if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) {
 600                                 bool f_opcode = (is_cat2_float(instr->opc) ||
 601                                                 is_cat3_float(instr->opc)) ? true : false;
 602
 603                                 /* See if lowering an immediate to const would help. */
 604                                 instr->regs[n+1] = lower_immed(ctx, src_reg, new_flags, f_opcode);
 605
 606                                 return true;
 607                         }
 608                 }
 609         }
 610
 611         return false;
 612 }
 613
 614 /* Handle special case of eliminating output mov, and similar cases where
 615  * there isn't a normal "consuming" instruction.  In this case we cannot
 616  * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
 617  * be eliminated)
 618  */
 619 static struct ir3_instruction *
 620 eliminate_output_mov(struct ir3_instruction *instr)
 621 {
 622         if (is_eligible_mov(instr, NULL, false)) {
 623                 struct ir3_register *reg = instr->regs[1];
 624                 if (!(reg->flags & IR3_REG_ARRAY)) {
 625                         struct ir3_instruction *src_instr = ssa(reg);
 626                         debug_assert(src_instr);
 627                         return src_instr;
 628                 }
 629         }
 630         return instr;
 631 }
 632
 633 /**
 634  * Find instruction src's which are mov's that can be collapsed, replacing
 635  * the mov dst with the mov src
 636  */
 637 static void
 638 instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
 639 {
 640         struct ir3_register *reg;
 641
 642         if (instr->regs_count == 0)
 643                 return;
 644
 645         if (ir3_instr_check_mark(instr))
 646                 return;
 647
 648         /* walk down the graph from each src: */
 649         bool progress;
 650         do {
 651                 progress = false;
 652                 foreach_src_n (reg, n, instr) {
 653                         struct ir3_instruction *src = ssa(reg);
 654
 655                         if (!src)
 656                                 continue;
 657
 658                         instr_cp(ctx, src);
 659
 660                         /* TODO non-indirect access we could figure out which register
 661                          * we actually want and allow cp..
 662                          */
 663                         if (reg->flags & IR3_REG_ARRAY)
 664                                 continue;
 665
 666                         /* Don't CP absneg into meta instructions, that won't end well: */
 667                         if (is_meta(instr) && (src->opc != OPC_MOV))
 668                                 continue;
 669
 670                         progress |= reg_cp(ctx, instr, reg, n);
 671                 }
 672         } while (progress);
 673
 674         if (instr->regs[0]->flags & IR3_REG_ARRAY) {
 675                 struct ir3_instruction *src = ssa(instr->regs[0]);
 676                 if (src)
 677                         instr_cp(ctx, src);
 678         }
 679
 680         if (instr->address) {
 681                 instr_cp(ctx, instr->address);
 682                 ir3_instr_set_address(instr, eliminate_output_mov(instr->address));
 683         }
 684
 685         /* we can end up with extra cmps.s from frontend, which uses a
 686          *
 687          *    cmps.s p0.x, cond, 0
 688          *
 689          * as a way to mov into the predicate register.  But frequently 'cond'
 690          * is itself a cmps.s/cmps.f/cmps.u.  So detect this special case and
 691          * just re-write the instruction writing predicate register to get rid
 692          * of the double cmps.
 693          */
 694         if ((instr->opc == OPC_CMPS_S) &&
 695                         (instr->regs[0]->num == regid(REG_P0, 0)) &&
 696                         ssa(instr->regs[1]) &&
 697                         (instr->regs[2]->flags & IR3_REG_IMMED) &&
 698                         (instr->regs[2]->iim_val == 0)) {
 699                 struct ir3_instruction *cond = ssa(instr->regs[1]);
 700                 switch (cond->opc) {
 701                 case OPC_CMPS_S:
 702                 case OPC_CMPS_F:
 703                 case OPC_CMPS_U:
 704                         instr->opc   = cond->opc;
 705                         instr->flags = cond->flags;
 706                         instr->cat2  = cond->cat2;
 707                         ir3_instr_set_address(instr, cond->address);
 708                         instr->regs[1] = cond->regs[1];
 709                         instr->regs[2] = cond->regs[2];
 710                         instr->barrier_class |= cond->barrier_class;
 711                         instr->barrier_conflict |= cond->barrier_conflict;
 712                         unuse(cond);
 713                         break;
 714                 default:
 715                         break;
 716                 }
 717         }
 718
 719         /* Handle converting a sam.s2en (taking samp/tex idx params via register)
 720          * into a normal sam (encoding immediate samp/tex idx) if they are
 721          * immediate. This saves some instructions and regs in the common case
 722          * where we know samp/tex at compile time. This needs to be done in the
 723          * frontend for bindless tex, though, so don't replicate it here.
 724          */
 725         if (is_tex(instr) && (instr->flags & IR3_INSTR_S2EN) &&
 726                         !(instr->flags & IR3_INSTR_B) &&
 727                         !(ir3_shader_debug & IR3_DBG_FORCES2EN)) {
 728                 /* The first src will be a collect, if both of it's
 729                  * two sources are mov from imm, then we can
 730                  */
 731                 struct ir3_instruction *samp_tex = ssa(instr->regs[1]);
 732
 733                 debug_assert(samp_tex->opc == OPC_META_COLLECT);
 734
 735                 struct ir3_instruction *samp = ssa(samp_tex->regs[1]);
 736                 struct ir3_instruction *tex  = ssa(samp_tex->regs[2]);
 737
 738                 if ((samp->opc == OPC_MOV) &&
 739                                 (samp->regs[1]->flags & IR3_REG_IMMED) &&
 740                                 (tex->opc == OPC_MOV) &&
 741                                 (tex->regs[1]->flags & IR3_REG_IMMED)) {
 742                         instr->flags &= ~IR3_INSTR_S2EN;
 743                         instr->cat5.samp = samp->regs[1]->iim_val;
 744                         instr->cat5.tex  = tex->regs[1]->iim_val;
 745
 746                         /* shuffle around the regs to remove the first src: */
 747                         instr->regs_count--;
 748                         for (unsigned i = 1; i < instr->regs_count; i++) {
 749                                 instr->regs[i] = instr->regs[i + 1];
 750                         }
 751                 }
 752         }
 753 }
 754
 755 void
 756 ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so)
 757 {
 758         struct ir3_cp_ctx ctx = {
 759                         .shader = ir,
 760                         .so = so,
 761         };
 762
 763         /* This is a bit annoying, and probably wouldn't be necessary if we
 764          * tracked a reverse link from producing instruction to consumer.
 765          * But we need to know when we've eliminated the last consumer of
 766          * a mov, so we need to do a pass to first count consumers of a
 767          * mov.
 768          */
 769         foreach_block (block, &ir->block_list) {
 770                 foreach_instr (instr, &block->instr_list) {
 771                         struct ir3_instruction *src;
 772
 773                         /* by the way, we don't account for false-dep's, so the CP
 774                          * pass should always happen before false-dep's are inserted
 775                          */
 776                         debug_assert(instr->deps_count == 0);
 777
 778                         foreach_ssa_src (src, instr) {
 779                                 src->use_count++;
 780                         }
 781                 }
 782         }
 783
 784         ir3_clear_mark(ir);
 785
 786         struct ir3_instruction *out;
 787         foreach_output_n (out, n, ir) {
 788                 instr_cp(&ctx, out);
 789                 ir->outputs[n] = eliminate_output_mov(out);
 790         }
 791
 792         foreach_block (block, &ir->block_list) {
 793                 if (block->condition) {
 794                         instr_cp(&ctx, block->condition);
 795                         block->condition = eliminate_output_mov(block->condition);
 796                 }
 797
 798                 for (unsigned i = 0; i < block->keeps_count; i++) {
 799                         instr_cp(&ctx, block->keeps[i]);
 800                         block->keeps[i] = eliminate_output_mov(block->keeps[i]);
 801                 }
 802         }
 803 }