src/freedreno/ir3/ir3_cp.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include <math.h>
  28 #include "util/half_float.h"
  29 #include "util/u_math.h"
  30
  31 #include "ir3.h"
  32 #include "ir3_compiler.h"
  33 #include "ir3_shader.h"
  34
  35 #define swap(a, b) \
  36         do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
  37
  38 /*
  39  * Copy Propagate:
  40  */
  41
  42 struct ir3_cp_ctx {
  43         struct ir3 *shader;
  44         struct ir3_shader_variant *so;
  45         bool progress;
  46 };
  47
  48 /* is it a type preserving mov, with ok flags?
  49  *
  50  * @instr: the mov to consider removing
  51  * @dst_instr: the instruction consuming the mov (instr)
  52  *
  53  * TODO maybe drop allow_flags since this is only false when dst is
  54  * NULL (ie. outputs)
  55  */
  56 static bool is_eligible_mov(struct ir3_instruction *instr,
  57                 struct ir3_instruction *dst_instr, bool allow_flags)
  58 {
  59         if (is_same_type_mov(instr)) {
  60                 struct ir3_register *dst = instr->regs[0];
  61                 struct ir3_register *src = instr->regs[1];
  62                 struct ir3_instruction *src_instr = ssa(src);
  63
  64                 /* only if mov src is SSA (not const/immed): */
  65                 if (!src_instr)
  66                         return false;
  67
  68                 /* no indirect: */
  69                 if (dst->flags & IR3_REG_RELATIV)
  70                         return false;
  71                 if (src->flags & IR3_REG_RELATIV)
  72                         return false;
  73
  74                 if (src->flags & IR3_REG_ARRAY)
  75                         return false;
  76
  77                 if (!allow_flags)
  78                         if (src->flags & (IR3_REG_FABS | IR3_REG_FNEG |
  79                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
  80                                 return false;
  81
  82                 /* If src is coming from fanout/split (ie. one component of a
  83                  * texture fetch, etc) and we have constraints on swizzle of
  84                  * destination, then skip it.
  85                  *
  86                  * We could possibly do a bit better, and copy-propagation if
  87                  * we can CP all components that are being fanned out.
  88                  */
  89                 if (src_instr->opc == OPC_META_SPLIT) {
  90                         if (!dst_instr)
  91                                 return false;
  92                         if (dst_instr->opc == OPC_META_COLLECT)
  93                                 return false;
  94                         if (dst_instr->cp.left || dst_instr->cp.right)
  95                                 return false;
  96                 }
  97
  98                 return true;
  99         }
 100         return false;
 101 }
 102
 103 static unsigned cp_flags(unsigned flags)
 104 {
 105         /* only considering these flags (at least for now): */
 106         flags &= (IR3_REG_CONST | IR3_REG_IMMED |
 107                         IR3_REG_FNEG | IR3_REG_FABS |
 108                         IR3_REG_SNEG | IR3_REG_SABS |
 109                         IR3_REG_BNOT | IR3_REG_RELATIV);
 110         return flags;
 111 }
 112
 113 static bool valid_flags(struct ir3_instruction *instr, unsigned n,
 114                 unsigned flags)
 115 {
 116         struct ir3_compiler *compiler = instr->block->shader->compiler;
 117         unsigned valid_flags;
 118
 119         if ((flags & IR3_REG_HIGH) &&
 120                         (opc_cat(instr->opc) > 1) &&
 121                         (compiler->gpu_id >= 600))
 122                 return false;
 123
 124         flags = cp_flags(flags);
 125
 126         /* If destination is indirect, then source cannot be.. at least
 127          * I don't think so..
 128          */
 129         if ((instr->regs[0]->flags & IR3_REG_RELATIV) &&
 130                         (flags & IR3_REG_RELATIV))
 131                 return false;
 132
 133         if (flags & IR3_REG_RELATIV) {
 134                 /* TODO need to test on earlier gens.. pretty sure the earlier
 135                  * problem was just that we didn't check that the src was from
 136                  * same block (since we can't propagate address register values
 137                  * across blocks currently)
 138                  */
 139                 if (compiler->gpu_id < 600)
 140                         return false;
 141
 142                 /* NOTE in the special try_swap_mad_two_srcs() case we can be
 143                  * called on a src that has already had an indirect load folded
 144                  * in, in which case ssa() returns NULL
 145                  */
 146                 struct ir3_instruction *src = ssa(instr->regs[n+1]);
 147                 if (src && src->address->block != instr->block)
 148                         return false;
 149         }
 150
 151         switch (opc_cat(instr->opc)) {
 152         case 1:
 153                 valid_flags = IR3_REG_IMMED | IR3_REG_CONST | IR3_REG_RELATIV;
 154                 if (flags & ~valid_flags)
 155                         return false;
 156                 break;
 157         case 2:
 158                 valid_flags = ir3_cat2_absneg(instr->opc) |
 159                                 IR3_REG_CONST | IR3_REG_RELATIV;
 160
 161                 if (ir3_cat2_int(instr->opc))
 162                         valid_flags |= IR3_REG_IMMED;
 163
 164                 if (flags & ~valid_flags)
 165                         return false;
 166
 167                 if (flags & (IR3_REG_CONST | IR3_REG_IMMED)) {
 168                         unsigned m = (n ^ 1) + 1;
 169                         /* cannot deal w/ const in both srcs:
 170                          * (note that some cat2 actually only have a single src)
 171                          */
 172                         if (m < instr->regs_count) {
 173                                 struct ir3_register *reg = instr->regs[m];
 174                                 if ((flags & IR3_REG_CONST) && (reg->flags & IR3_REG_CONST))
 175                                         return false;
 176                                 if ((flags & IR3_REG_IMMED) && (reg->flags & IR3_REG_IMMED))
 177                                         return false;
 178                         }
 179                 }
 180                 break;
 181         case 3:
 182                 valid_flags = ir3_cat3_absneg(instr->opc) |
 183                                 IR3_REG_CONST | IR3_REG_RELATIV;
 184
 185                 if (flags & ~valid_flags)
 186                         return false;
 187
 188                 if (flags & (IR3_REG_CONST | IR3_REG_RELATIV)) {
 189                         /* cannot deal w/ const/relativ in 2nd src: */
 190                         if (n == 1)
 191                                 return false;
 192                 }
 193
 194                 break;
 195         case 4:
 196                 /* seems like blob compiler avoids const as src.. */
 197                 /* TODO double check if this is still the case on a4xx */
 198                 if (flags & (IR3_REG_CONST | IR3_REG_IMMED))
 199                         return false;
 200                 if (flags & (IR3_REG_SABS | IR3_REG_SNEG))
 201                         return false;
 202                 break;
 203         case 5:
 204                 /* no flags allowed */
 205                 if (flags)
 206                         return false;
 207                 break;
 208         case 6:
 209                 valid_flags = IR3_REG_IMMED;
 210                 if (flags & ~valid_flags)
 211                         return false;
 212
 213                 if (flags & IR3_REG_IMMED) {
 214                         /* doesn't seem like we can have immediate src for store
 215                          * instructions:
 216                          *
 217                          * TODO this restriction could also apply to load instructions,
 218                          * but for load instructions this arg is the address (and not
 219                          * really sure any good way to test a hard-coded immed addr src)
 220                          */
 221                         if (is_store(instr) && (n == 1))
 222                                 return false;
 223
 224                         if ((instr->opc == OPC_LDL) && (n == 0))
 225                                 return false;
 226
 227                         if ((instr->opc == OPC_STL) && (n != 2))
 228                                 return false;
 229
 230                         if (instr->opc == OPC_STLW && n == 0)
 231                                 return false;
 232
 233                         if (instr->opc == OPC_LDLW && n == 0)
 234                                 return false;
 235
 236                         /* disallow immediates in anything but the SSBO slot argument for
 237                          * cat6 instructions:
 238                          */
 239                         if (is_atomic(instr->opc) && (n != 0))
 240                                 return false;
 241
 242                         if (is_atomic(instr->opc) && !(instr->flags & IR3_INSTR_G))
 243                                 return false;
 244
 245                         if (instr->opc == OPC_STG && (instr->flags & IR3_INSTR_G) && (n != 2))
 246                                 return false;
 247
 248                         /* as with atomics, these cat6 instrs can only have an immediate
 249                          * for SSBO/IBO slot argument
 250                          */
 251                         switch (instr->opc) {
 252                         case OPC_LDIB:
 253                         case OPC_LDC:
 254                         case OPC_RESINFO:
 255                                 if (n != 0)
 256                                         return false;
 257                                 break;
 258                         default:
 259                                 break;
 260                         }
 261                 }
 262
 263                 break;
 264         }
 265
 266         return true;
 267 }
 268
 269 /* propagate register flags from src to dst.. negates need special
 270  * handling to cancel each other out.
 271  */
 272 static void combine_flags(unsigned *dstflags, struct ir3_instruction *src)
 273 {
 274         unsigned srcflags = src->regs[1]->flags;
 275
 276         /* if what we are combining into already has (abs) flags,
 277          * we can drop (neg) from src:
 278          */
 279         if (*dstflags & IR3_REG_FABS)
 280                 srcflags &= ~IR3_REG_FNEG;
 281         if (*dstflags & IR3_REG_SABS)
 282                 srcflags &= ~IR3_REG_SNEG;
 283
 284         if (srcflags & IR3_REG_FABS)
 285                 *dstflags |= IR3_REG_FABS;
 286         if (srcflags & IR3_REG_SABS)
 287                 *dstflags |= IR3_REG_SABS;
 288         if (srcflags & IR3_REG_FNEG)
 289                 *dstflags ^= IR3_REG_FNEG;
 290         if (srcflags & IR3_REG_SNEG)
 291                 *dstflags ^= IR3_REG_SNEG;
 292         if (srcflags & IR3_REG_BNOT)
 293                 *dstflags ^= IR3_REG_BNOT;
 294
 295         *dstflags &= ~IR3_REG_SSA;
 296         *dstflags |= srcflags & IR3_REG_SSA;
 297         *dstflags |= srcflags & IR3_REG_CONST;
 298         *dstflags |= srcflags & IR3_REG_IMMED;
 299         *dstflags |= srcflags & IR3_REG_RELATIV;
 300         *dstflags |= srcflags & IR3_REG_ARRAY;
 301         *dstflags |= srcflags & IR3_REG_HIGH;
 302
 303         /* if src of the src is boolean we can drop the (abs) since we know
 304          * the source value is already a postitive integer.  This cleans
 305          * up the absnegs that get inserted when converting between nir and
 306          * native boolean (see ir3_b2n/n2b)
 307          */
 308         struct ir3_instruction *srcsrc = ssa(src->regs[1]);
 309         if (srcsrc && is_bool(srcsrc))
 310                 *dstflags &= ~IR3_REG_SABS;
 311 }
 312
 313 static struct ir3_register *
 314 lower_immed(struct ir3_cp_ctx *ctx, struct ir3_register *reg, unsigned new_flags, bool f_opcode)
 315 {
 316         unsigned swiz, idx, i;
 317
 318         reg = ir3_reg_clone(ctx->shader, reg);
 319
 320         /* Half constant registers seems to handle only 32-bit values
 321          * within floating-point opcodes. So convert back to 32-bit values.
 322          */
 323         if (f_opcode && (new_flags & IR3_REG_HALF))
 324                 reg->uim_val = fui(_mesa_half_to_float(reg->uim_val));
 325
 326         /* in some cases, there are restrictions on (abs)/(neg) plus const..
 327          * so just evaluate those and clear the flags:
 328          */
 329         if (new_flags & IR3_REG_SABS) {
 330                 reg->iim_val = abs(reg->iim_val);
 331                 new_flags &= ~IR3_REG_SABS;
 332         }
 333
 334         if (new_flags & IR3_REG_FABS) {
 335                 reg->fim_val = fabs(reg->fim_val);
 336                 new_flags &= ~IR3_REG_FABS;
 337         }
 338
 339         if (new_flags & IR3_REG_SNEG) {
 340                 reg->iim_val = -reg->iim_val;
 341                 new_flags &= ~IR3_REG_SNEG;
 342         }
 343
 344         if (new_flags & IR3_REG_FNEG) {
 345                 reg->fim_val = -reg->fim_val;
 346                 new_flags &= ~IR3_REG_FNEG;
 347         }
 348
 349         /* Reallocate for 4 more elements whenever it's necessary */
 350         struct ir3_const_state *const_state = &ctx->so->shader->const_state;
 351         if (const_state->immediate_idx == const_state->immediates_size * 4) {
 352                 const_state->immediates_size += 4;
 353                 const_state->immediates = realloc (const_state->immediates,
 354                         const_state->immediates_size * sizeof(const_state->immediates[0]));
 355
 356                 for (int i = const_state->immediate_idx; i < const_state->immediates_size * 4; i++)
 357                         const_state->immediates[i / 4].val[i % 4] = 0xd0d0d0d0;
 358         }
 359
 360         for (i = 0; i < const_state->immediate_idx; i++) {
 361                 swiz = i % 4;
 362                 idx  = i / 4;
 363
 364                 if (const_state->immediates[idx].val[swiz] == reg->uim_val) {
 365                         break;
 366                 }
 367         }
 368
 369         if (i == const_state->immediate_idx) {
 370                 /* need to generate a new immediate: */
 371                 swiz = i % 4;
 372                 idx  = i / 4;
 373
 374                 const_state->immediates[idx].val[swiz] = reg->uim_val;
 375                 const_state->immediates_count = idx + 1;
 376                 const_state->immediate_idx++;
 377         }
 378
 379         new_flags &= ~IR3_REG_IMMED;
 380         new_flags |= IR3_REG_CONST;
 381         reg->flags = new_flags;
 382         reg->num = i + (4 * const_state->offsets.immediate);
 383
 384         return reg;
 385 }
 386
 387 static void
 388 unuse(struct ir3_instruction *instr)
 389 {
 390         debug_assert(instr->use_count > 0);
 391
 392         if (--instr->use_count == 0) {
 393                 struct ir3_block *block = instr->block;
 394
 395                 instr->barrier_class = 0;
 396                 instr->barrier_conflict = 0;
 397
 398                 /* we don't want to remove anything in keeps (which could
 399                  * be things like array store's)
 400                  */
 401                 for (unsigned i = 0; i < block->keeps_count; i++) {
 402                         debug_assert(block->keeps[i] != instr);
 403                 }
 404         }
 405 }
 406
 407 /**
 408  * Handles the special case of the 2nd src (n == 1) to "normal" mad
 409  * instructions, which cannot reference a constant.  See if it is
 410  * possible to swap the 1st and 2nd sources.
 411  */
 412 static bool
 413 try_swap_mad_two_srcs(struct ir3_instruction *instr, unsigned new_flags)
 414 {
 415         if (!is_mad(instr->opc))
 416                 return false;
 417
 418         /* NOTE: pre-swap first two src's before valid_flags(),
 419          * which might try to dereference the n'th src:
 420          */
 421         swap(instr->regs[0 + 1], instr->regs[1 + 1]);
 422
 423         /* cat3 doesn't encode immediate, but we can lower immediate
 424          * to const if that helps:
 425          */
 426         if (new_flags & IR3_REG_IMMED) {
 427                 new_flags &= ~IR3_REG_IMMED;
 428                 new_flags |=  IR3_REG_CONST;
 429         }
 430
 431         bool valid_swap =
 432                 /* can we propagate mov if we move 2nd src to first? */
 433                 valid_flags(instr, 0, new_flags) &&
 434                 /* and does first src fit in second slot? */
 435                 valid_flags(instr, 1, instr->regs[1 + 1]->flags);
 436
 437         if (!valid_swap) {
 438                 /* put things back the way they were: */
 439                 swap(instr->regs[0 + 1], instr->regs[1 + 1]);
 440         }   /* otherwise leave things swapped */
 441
 442         return valid_swap;
 443 }
 444
 445 /**
 446  * Handle cp for a given src register.  This additionally handles
 447  * the cases of collapsing immedate/const (which replace the src
 448  * register with a non-ssa src) or collapsing mov's from relative
 449  * src (which needs to also fixup the address src reference by the
 450  * instruction).
 451  */
 452 static bool
 453 reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr,
 454                 struct ir3_register *reg, unsigned n)
 455 {
 456         struct ir3_instruction *src = ssa(reg);
 457
 458         if (is_eligible_mov(src, instr, true)) {
 459                 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */
 460                 struct ir3_register *src_reg = src->regs[1];
 461                 unsigned new_flags = reg->flags;
 462
 463                 combine_flags(&new_flags, src);
 464
 465                 if (valid_flags(instr, n, new_flags)) {
 466                         if (new_flags & IR3_REG_ARRAY) {
 467                                 debug_assert(!(reg->flags & IR3_REG_ARRAY));
 468                                 reg->array = src_reg->array;
 469                         }
 470                         reg->flags = new_flags;
 471                         reg->instr = ssa(src_reg);
 472
 473                         instr->barrier_class |= src->barrier_class;
 474                         instr->barrier_conflict |= src->barrier_conflict;
 475
 476                         unuse(src);
 477                         reg->instr->use_count++;
 478
 479                         return true;
 480                 }
 481         } else if ((is_same_type_mov(src) || is_const_mov(src)) &&
 482                         /* cannot collapse const/immed/etc into meta instrs: */
 483                         !is_meta(instr)) {
 484                 /* immed/const/etc cases, which require some special handling: */
 485                 struct ir3_register *src_reg = src->regs[1];
 486                 unsigned new_flags = reg->flags;
 487
 488                 combine_flags(&new_flags, src);
 489
 490                 if (!valid_flags(instr, n, new_flags)) {
 491                         /* See if lowering an immediate to const would help. */
 492                         if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) {
 493                                 bool f_opcode = (is_cat2_float(instr->opc) ||
 494                                                 is_cat3_float(instr->opc)) ? true : false;
 495
 496                                 debug_assert(new_flags & IR3_REG_IMMED);
 497
 498                                 instr->regs[n + 1] = lower_immed(ctx, src_reg, new_flags, f_opcode);
 499                                 return true;
 500                         }
 501
 502                         /* special case for "normal" mad instructions, we can
 503                          * try swapping the first two args if that fits better.
 504                          *
 505                          * the "plain" MAD's (ie. the ones that don't shift first
 506                          * src prior to multiply) can swap their first two srcs if
 507                          * src[0] is !CONST and src[1] is CONST:
 508                          */
 509                         if ((n == 1) && try_swap_mad_two_srcs(instr, new_flags)) {
 510                                 return true;
 511                         } else {
 512                                 return false;
 513                         }
 514                 }
 515
 516                 /* Here we handle the special case of mov from
 517                  * CONST and/or RELATIV.  These need to be handled
 518                  * specially, because in the case of move from CONST
 519                  * there is no src ir3_instruction so we need to
 520                  * replace the ir3_register.  And in the case of
 521                  * RELATIV we need to handle the address register
 522                  * dependency.
 523                  */
 524                 if (src_reg->flags & IR3_REG_CONST) {
 525                         /* an instruction cannot reference two different
 526                          * address registers:
 527                          */
 528                         if ((src_reg->flags & IR3_REG_RELATIV) &&
 529                                         conflicts(instr->address, reg->instr->address))
 530                                 return false;
 531
 532                         /* This seems to be a hw bug, or something where the timings
 533                          * just somehow don't work out.  This restriction may only
 534                          * apply if the first src is also CONST.
 535                          */
 536                         if ((opc_cat(instr->opc) == 3) && (n == 2) &&
 537                                         (src_reg->flags & IR3_REG_RELATIV) &&
 538                                         (src_reg->array.offset == 0))
 539                                 return false;
 540
 541                         /* When narrowing constant from 32b to 16b, it seems
 542                          * to work only for float. So we should do this only with
 543                          * float opcodes.
 544                          */
 545                         if (src->cat1.dst_type == TYPE_F16) {
 546                                 if (instr->opc == OPC_MOV && !type_float(instr->cat1.src_type))
 547                                         return false;
 548                                 if (!is_cat2_float(instr->opc) && !is_cat3_float(instr->opc))
 549                                         return false;
 550                         }
 551
 552                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 553                         src_reg->flags = new_flags;
 554                         instr->regs[n+1] = src_reg;
 555
 556                         if (src_reg->flags & IR3_REG_RELATIV)
 557                                 ir3_instr_set_address(instr, reg->instr->address);
 558
 559                         return true;
 560                 }
 561
 562                 if ((src_reg->flags & IR3_REG_RELATIV) &&
 563                                 !conflicts(instr->address, reg->instr->address)) {
 564                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 565                         src_reg->flags = new_flags;
 566                         instr->regs[n+1] = src_reg;
 567                         ir3_instr_set_address(instr, reg->instr->address);
 568
 569                         return true;
 570                 }
 571
 572                 /* NOTE: seems we can only do immed integers, so don't
 573                  * need to care about float.  But we do need to handle
 574                  * abs/neg *before* checking that the immediate requires
 575                  * few enough bits to encode:
 576                  *
 577                  * TODO: do we need to do something to avoid accidentally
 578                  * catching a float immed?
 579                  */
 580                 if (src_reg->flags & IR3_REG_IMMED) {
 581                         int32_t iim_val = src_reg->iim_val;
 582
 583                         debug_assert((opc_cat(instr->opc) == 1) ||
 584                                         (opc_cat(instr->opc) == 6) ||
 585                                         ir3_cat2_int(instr->opc) ||
 586                                         (is_mad(instr->opc) && (n == 0)));
 587
 588                         if (new_flags & IR3_REG_SABS)
 589                                 iim_val = abs(iim_val);
 590
 591                         if (new_flags & IR3_REG_SNEG)
 592                                 iim_val = -iim_val;
 593
 594                         if (new_flags & IR3_REG_BNOT)
 595                                 iim_val = ~iim_val;
 596
 597                         /* other than category 1 (mov) we can only encode up to 10 bits: */
 598                         if (valid_flags(instr, n, new_flags) &&
 599                                         ((instr->opc == OPC_MOV) ||
 600                                          !((iim_val & ~0x3ff) && (-iim_val & ~0x3ff)))) {
 601                                 new_flags &= ~(IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT);
 602                                 src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 603                                 src_reg->flags = new_flags;
 604                                 src_reg->iim_val = iim_val;
 605                                 instr->regs[n+1] = src_reg;
 606
 607                                 return true;
 608                         } else if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) {
 609                                 bool f_opcode = (is_cat2_float(instr->opc) ||
 610                                                 is_cat3_float(instr->opc)) ? true : false;
 611
 612                                 /* See if lowering an immediate to const would help. */
 613                                 instr->regs[n+1] = lower_immed(ctx, src_reg, new_flags, f_opcode);
 614
 615                                 return true;
 616                         }
 617                 }
 618         }
 619
 620         return false;
 621 }
 622
 623 /* Handle special case of eliminating output mov, and similar cases where
 624  * there isn't a normal "consuming" instruction.  In this case we cannot
 625  * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
 626  * be eliminated)
 627  */
 628 static struct ir3_instruction *
 629 eliminate_output_mov(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
 630 {
 631         if (is_eligible_mov(instr, NULL, false)) {
 632                 struct ir3_register *reg = instr->regs[1];
 633                 if (!(reg->flags & IR3_REG_ARRAY)) {
 634                         struct ir3_instruction *src_instr = ssa(reg);
 635                         debug_assert(src_instr);
 636                         ctx->progress = true;
 637                         return src_instr;
 638                 }
 639         }
 640         return instr;
 641 }
 642
 643 /**
 644  * Find instruction src's which are mov's that can be collapsed, replacing
 645  * the mov dst with the mov src
 646  */
 647 static void
 648 instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
 649 {
 650         if (instr->regs_count == 0)
 651                 return;
 652
 653         if (ir3_instr_check_mark(instr))
 654                 return;
 655
 656         /* walk down the graph from each src: */
 657         bool progress;
 658         do {
 659                 progress = false;
 660                 foreach_src_n (reg, n, instr) {
 661                         struct ir3_instruction *src = ssa(reg);
 662
 663                         if (!src)
 664                                 continue;
 665
 666                         instr_cp(ctx, src);
 667
 668                         /* TODO non-indirect access we could figure out which register
 669                          * we actually want and allow cp..
 670                          */
 671                         if (reg->flags & IR3_REG_ARRAY)
 672                                 continue;
 673
 674                         /* Don't CP absneg into meta instructions, that won't end well: */
 675                         if (is_meta(instr) && (src->opc != OPC_MOV))
 676                                 continue;
 677
 678                         progress |= reg_cp(ctx, instr, reg, n);
 679                         ctx->progress |= progress;
 680                 }
 681         } while (progress);
 682
 683         if (instr->regs[0]->flags & IR3_REG_ARRAY) {
 684                 struct ir3_instruction *src = ssa(instr->regs[0]);
 685                 if (src)
 686                         instr_cp(ctx, src);
 687         }
 688
 689         if (instr->address) {
 690                 instr_cp(ctx, instr->address);
 691                 ir3_instr_set_address(instr, eliminate_output_mov(ctx, instr->address));
 692         }
 693
 694         /* we can end up with extra cmps.s from frontend, which uses a
 695          *
 696          *    cmps.s p0.x, cond, 0
 697          *
 698          * as a way to mov into the predicate register.  But frequently 'cond'
 699          * is itself a cmps.s/cmps.f/cmps.u.  So detect this special case and
 700          * just re-write the instruction writing predicate register to get rid
 701          * of the double cmps.
 702          */
 703         if ((instr->opc == OPC_CMPS_S) &&
 704                         (instr->regs[0]->num == regid(REG_P0, 0)) &&
 705                         ssa(instr->regs[1]) &&
 706                         (instr->regs[2]->flags & IR3_REG_IMMED) &&
 707                         (instr->regs[2]->iim_val == 0) &&
 708                         (instr->cat2.condition == IR3_COND_NE)) {
 709                 struct ir3_instruction *cond = ssa(instr->regs[1]);
 710                 switch (cond->opc) {
 711                 case OPC_CMPS_S:
 712                 case OPC_CMPS_F:
 713                 case OPC_CMPS_U:
 714                         instr->opc   = cond->opc;
 715                         instr->flags = cond->flags;
 716                         instr->cat2  = cond->cat2;
 717                         ir3_instr_set_address(instr, cond->address);
 718                         instr->regs[1] = cond->regs[1];
 719                         instr->regs[2] = cond->regs[2];
 720                         instr->barrier_class |= cond->barrier_class;
 721                         instr->barrier_conflict |= cond->barrier_conflict;
 722                         unuse(cond);
 723                         ctx->progress = true;
 724                         break;
 725                 default:
 726                         break;
 727                 }
 728         }
 729
 730         /* Handle converting a sam.s2en (taking samp/tex idx params via register)
 731          * into a normal sam (encoding immediate samp/tex idx) if they are
 732          * immediate. This saves some instructions and regs in the common case
 733          * where we know samp/tex at compile time. This needs to be done in the
 734          * frontend for bindless tex, though, so don't replicate it here.
 735          */
 736         if (is_tex(instr) && (instr->flags & IR3_INSTR_S2EN) &&
 737                         !(instr->flags & IR3_INSTR_B) &&
 738                         !(ir3_shader_debug & IR3_DBG_FORCES2EN)) {
 739                 /* The first src will be a collect, if both of it's
 740                  * two sources are mov from imm, then we can
 741                  */
 742                 struct ir3_instruction *samp_tex = ssa(instr->regs[1]);
 743
 744                 debug_assert(samp_tex->opc == OPC_META_COLLECT);
 745
 746                 struct ir3_instruction *samp = ssa(samp_tex->regs[1]);
 747                 struct ir3_instruction *tex  = ssa(samp_tex->regs[2]);
 748
 749                 if ((samp->opc == OPC_MOV) &&
 750                                 (samp->regs[1]->flags & IR3_REG_IMMED) &&
 751                                 (tex->opc == OPC_MOV) &&
 752                                 (tex->regs[1]->flags & IR3_REG_IMMED)) {
 753                         instr->flags &= ~IR3_INSTR_S2EN;
 754                         instr->cat5.samp = samp->regs[1]->iim_val;
 755                         instr->cat5.tex  = tex->regs[1]->iim_val;
 756
 757                         /* shuffle around the regs to remove the first src: */
 758                         instr->regs_count--;
 759                         for (unsigned i = 1; i < instr->regs_count; i++) {
 760                                 instr->regs[i] = instr->regs[i + 1];
 761                         }
 762
 763                         ctx->progress = true;
 764                 }
 765         }
 766 }
 767
 768 bool
 769 ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so)
 770 {
 771         struct ir3_cp_ctx ctx = {
 772                         .shader = ir,
 773                         .so = so,
 774         };
 775
 776         /* This is a bit annoying, and probably wouldn't be necessary if we
 777          * tracked a reverse link from producing instruction to consumer.
 778          * But we need to know when we've eliminated the last consumer of
 779          * a mov, so we need to do a pass to first count consumers of a
 780          * mov.
 781          */
 782         foreach_block (block, &ir->block_list) {
 783                 foreach_instr (instr, &block->instr_list) {
 784
 785                         /* by the way, we don't account for false-dep's, so the CP
 786                          * pass should always happen before false-dep's are inserted
 787                          */
 788                         debug_assert(instr->deps_count == 0);
 789
 790                         foreach_ssa_src (src, instr) {
 791                                 src->use_count++;
 792                         }
 793                 }
 794         }
 795
 796         ir3_clear_mark(ir);
 797
 798         foreach_output_n (out, n, ir) {
 799                 instr_cp(&ctx, out);
 800                 ir->outputs[n] = eliminate_output_mov(&ctx, out);
 801         }
 802
 803         foreach_block (block, &ir->block_list) {
 804                 if (block->condition) {
 805                         instr_cp(&ctx, block->condition);
 806                         block->condition = eliminate_output_mov(&ctx, block->condition);
 807                 }
 808
 809                 for (unsigned i = 0; i < block->keeps_count; i++) {
 810                         instr_cp(&ctx, block->keeps[i]);
 811                         block->keeps[i] = eliminate_output_mov(&ctx, block->keeps[i]);
 812                 }
 813         }
 814
 815         return ctx.progress;
 816 }