src/freedreno/ir3/ir3_cp.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include <math.h>
  28 #include "util/half_float.h"
  29 #include "util/u_math.h"
  30
  31 #include "ir3.h"
  32 #include "ir3_compiler.h"
  33 #include "ir3_shader.h"
  34
  35 #define swap(a, b) \
  36         do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
  37
  38 /*
  39  * Copy Propagate:
  40  */
  41
  42 struct ir3_cp_ctx {
  43         struct ir3 *shader;
  44         struct ir3_shader_variant *so;
  45         bool progress;
  46 };
  47
  48 /* is it a type preserving mov, with ok flags?
  49  *
  50  * @instr: the mov to consider removing
  51  * @dst_instr: the instruction consuming the mov (instr)
  52  *
  53  * TODO maybe drop allow_flags since this is only false when dst is
  54  * NULL (ie. outputs)
  55  */
  56 static bool is_eligible_mov(struct ir3_instruction *instr,
  57                 struct ir3_instruction *dst_instr, bool allow_flags)
  58 {
  59         if (is_same_type_mov(instr)) {
  60                 struct ir3_register *dst = instr->regs[0];
  61                 struct ir3_register *src = instr->regs[1];
  62                 struct ir3_instruction *src_instr = ssa(src);
  63
  64                 /* only if mov src is SSA (not const/immed): */
  65                 if (!src_instr)
  66                         return false;
  67
  68                 /* no indirect: */
  69                 if (dst->flags & IR3_REG_RELATIV)
  70                         return false;
  71                 if (src->flags & IR3_REG_RELATIV)
  72                         return false;
  73
  74                 if (src->flags & IR3_REG_ARRAY)
  75                         return false;
  76
  77                 if (!allow_flags)
  78                         if (src->flags & (IR3_REG_FABS | IR3_REG_FNEG |
  79                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
  80                                 return false;
  81
  82                 /* If src is coming from fanout/split (ie. one component of a
  83                  * texture fetch, etc) and we have constraints on swizzle of
  84                  * destination, then skip it.
  85                  *
  86                  * We could possibly do a bit better, and copy-propagation if
  87                  * we can CP all components that are being fanned out.
  88                  */
  89                 if (src_instr->opc == OPC_META_SPLIT) {
  90                         if (!dst_instr)
  91                                 return false;
  92                         if (dst_instr->opc == OPC_META_COLLECT)
  93                                 return false;
  94                         if (dst_instr->cp.left || dst_instr->cp.right)
  95                                 return false;
  96                 }
  97
  98                 return true;
  99         }
 100         return false;
 101 }
 102
 103 static unsigned cp_flags(unsigned flags)
 104 {
 105         /* only considering these flags (at least for now): */
 106         flags &= (IR3_REG_CONST | IR3_REG_IMMED |
 107                         IR3_REG_FNEG | IR3_REG_FABS |
 108                         IR3_REG_SNEG | IR3_REG_SABS |
 109                         IR3_REG_BNOT | IR3_REG_RELATIV);
 110         return flags;
 111 }
 112
 113 static bool valid_flags(struct ir3_instruction *instr, unsigned n,
 114                 unsigned flags)
 115 {
 116         struct ir3_compiler *compiler = instr->block->shader->compiler;
 117         unsigned valid_flags;
 118
 119         if ((flags & IR3_REG_HIGH) &&
 120                         (opc_cat(instr->opc) > 1) &&
 121                         (compiler->gpu_id >= 600))
 122                 return false;
 123
 124         flags = cp_flags(flags);
 125
 126         /* If destination is indirect, then source cannot be.. at least
 127          * I don't think so..
 128          */
 129         if ((instr->regs[0]->flags & IR3_REG_RELATIV) &&
 130                         (flags & IR3_REG_RELATIV))
 131                 return false;
 132
 133         if (flags & IR3_REG_RELATIV) {
 134                 /* TODO need to test on earlier gens.. pretty sure the earlier
 135                  * problem was just that we didn't check that the src was from
 136                  * same block (since we can't propagate address register values
 137                  * across blocks currently)
 138                  */
 139                 if (compiler->gpu_id < 600)
 140                         return false;
 141
 142                 /* NOTE in the special try_swap_mad_two_srcs() case we can be
 143                  * called on a src that has already had an indirect load folded
 144                  * in, in which case ssa() returns NULL
 145                  */
 146                 struct ir3_instruction *src = ssa(instr->regs[n+1]);
 147                 if (src && src->address->block != instr->block)
 148                         return false;
 149         }
 150
 151         switch (opc_cat(instr->opc)) {
 152         case 1:
 153                 valid_flags = IR3_REG_IMMED | IR3_REG_CONST | IR3_REG_RELATIV;
 154                 if (flags & ~valid_flags)
 155                         return false;
 156                 break;
 157         case 2:
 158                 valid_flags = ir3_cat2_absneg(instr->opc) |
 159                                 IR3_REG_CONST | IR3_REG_RELATIV;
 160
 161                 if (ir3_cat2_int(instr->opc))
 162                         valid_flags |= IR3_REG_IMMED;
 163
 164                 if (flags & ~valid_flags)
 165                         return false;
 166
 167                 if (flags & (IR3_REG_CONST | IR3_REG_IMMED)) {
 168                         unsigned m = (n ^ 1) + 1;
 169                         /* cannot deal w/ const in both srcs:
 170                          * (note that some cat2 actually only have a single src)
 171                          */
 172                         if (m < instr->regs_count) {
 173                                 struct ir3_register *reg = instr->regs[m];
 174                                 if ((flags & IR3_REG_CONST) && (reg->flags & IR3_REG_CONST))
 175                                         return false;
 176                                 if ((flags & IR3_REG_IMMED) && (reg->flags & IR3_REG_IMMED))
 177                                         return false;
 178                         }
 179                 }
 180                 break;
 181         case 3:
 182                 valid_flags = ir3_cat3_absneg(instr->opc) |
 183                                 IR3_REG_CONST | IR3_REG_RELATIV;
 184
 185                 if (flags & ~valid_flags)
 186                         return false;
 187
 188                 if (flags & (IR3_REG_CONST | IR3_REG_RELATIV)) {
 189                         /* cannot deal w/ const/relativ in 2nd src: */
 190                         if (n == 1)
 191                                 return false;
 192                 }
 193
 194                 break;
 195         case 4:
 196                 /* seems like blob compiler avoids const as src.. */
 197                 /* TODO double check if this is still the case on a4xx */
 198                 if (flags & (IR3_REG_CONST | IR3_REG_IMMED))
 199                         return false;
 200                 if (flags & (IR3_REG_SABS | IR3_REG_SNEG))
 201                         return false;
 202                 break;
 203         case 5:
 204                 /* no flags allowed */
 205                 if (flags)
 206                         return false;
 207                 break;
 208         case 6:
 209                 valid_flags = IR3_REG_IMMED;
 210                 if (flags & ~valid_flags)
 211                         return false;
 212
 213                 if (flags & IR3_REG_IMMED) {
 214                         /* doesn't seem like we can have immediate src for store
 215                          * instructions:
 216                          *
 217                          * TODO this restriction could also apply to load instructions,
 218                          * but for load instructions this arg is the address (and not
 219                          * really sure any good way to test a hard-coded immed addr src)
 220                          */
 221                         if (is_store(instr) && (n == 1))
 222                                 return false;
 223
 224                         if ((instr->opc == OPC_LDL) && (n == 0))
 225                                 return false;
 226
 227                         if ((instr->opc == OPC_STL) && (n != 2))
 228                                 return false;
 229
 230                         if (instr->opc == OPC_STLW && n == 0)
 231                                 return false;
 232
 233                         if (instr->opc == OPC_LDLW && n == 0)
 234                                 return false;
 235
 236                         /* disallow CP into anything but the SSBO slot argument for
 237                          * atomics:
 238                          */
 239                         if (is_atomic(instr->opc) && (n != 0))
 240                                 return false;
 241
 242                         if (is_atomic(instr->opc) && !(instr->flags & IR3_INSTR_G))
 243                                 return false;
 244
 245                         if (instr->opc == OPC_STG && (instr->flags & IR3_INSTR_G) && (n != 2))
 246                                 return false;
 247
 248                         /* as with atomics, ldib and ldc on a6xx can only have immediate
 249                          * for SSBO slot argument
 250                          */
 251                         if ((instr->opc == OPC_LDIB || instr->opc == OPC_LDC) && (n != 0))
 252                                 return false;
 253                 }
 254
 255                 break;
 256         }
 257
 258         return true;
 259 }
 260
 261 /* propagate register flags from src to dst.. negates need special
 262  * handling to cancel each other out.
 263  */
 264 static void combine_flags(unsigned *dstflags, struct ir3_instruction *src)
 265 {
 266         unsigned srcflags = src->regs[1]->flags;
 267
 268         /* if what we are combining into already has (abs) flags,
 269          * we can drop (neg) from src:
 270          */
 271         if (*dstflags & IR3_REG_FABS)
 272                 srcflags &= ~IR3_REG_FNEG;
 273         if (*dstflags & IR3_REG_SABS)
 274                 srcflags &= ~IR3_REG_SNEG;
 275
 276         if (srcflags & IR3_REG_FABS)
 277                 *dstflags |= IR3_REG_FABS;
 278         if (srcflags & IR3_REG_SABS)
 279                 *dstflags |= IR3_REG_SABS;
 280         if (srcflags & IR3_REG_FNEG)
 281                 *dstflags ^= IR3_REG_FNEG;
 282         if (srcflags & IR3_REG_SNEG)
 283                 *dstflags ^= IR3_REG_SNEG;
 284         if (srcflags & IR3_REG_BNOT)
 285                 *dstflags ^= IR3_REG_BNOT;
 286
 287         *dstflags &= ~IR3_REG_SSA;
 288         *dstflags |= srcflags & IR3_REG_SSA;
 289         *dstflags |= srcflags & IR3_REG_CONST;
 290         *dstflags |= srcflags & IR3_REG_IMMED;
 291         *dstflags |= srcflags & IR3_REG_RELATIV;
 292         *dstflags |= srcflags & IR3_REG_ARRAY;
 293         *dstflags |= srcflags & IR3_REG_HIGH;
 294
 295         /* if src of the src is boolean we can drop the (abs) since we know
 296          * the source value is already a postitive integer.  This cleans
 297          * up the absnegs that get inserted when converting between nir and
 298          * native boolean (see ir3_b2n/n2b)
 299          */
 300         struct ir3_instruction *srcsrc = ssa(src->regs[1]);
 301         if (srcsrc && is_bool(srcsrc))
 302                 *dstflags &= ~IR3_REG_SABS;
 303 }
 304
 305 static struct ir3_register *
 306 lower_immed(struct ir3_cp_ctx *ctx, struct ir3_register *reg, unsigned new_flags, bool f_opcode)
 307 {
 308         unsigned swiz, idx, i;
 309
 310         reg = ir3_reg_clone(ctx->shader, reg);
 311
 312         /* Half constant registers seems to handle only 32-bit values
 313          * within floating-point opcodes. So convert back to 32-bit values.
 314          */
 315         if (f_opcode && (new_flags & IR3_REG_HALF))
 316                 reg->uim_val = fui(_mesa_half_to_float(reg->uim_val));
 317
 318         /* in some cases, there are restrictions on (abs)/(neg) plus const..
 319          * so just evaluate those and clear the flags:
 320          */
 321         if (new_flags & IR3_REG_SABS) {
 322                 reg->iim_val = abs(reg->iim_val);
 323                 new_flags &= ~IR3_REG_SABS;
 324         }
 325
 326         if (new_flags & IR3_REG_FABS) {
 327                 reg->fim_val = fabs(reg->fim_val);
 328                 new_flags &= ~IR3_REG_FABS;
 329         }
 330
 331         if (new_flags & IR3_REG_SNEG) {
 332                 reg->iim_val = -reg->iim_val;
 333                 new_flags &= ~IR3_REG_SNEG;
 334         }
 335
 336         if (new_flags & IR3_REG_FNEG) {
 337                 reg->fim_val = -reg->fim_val;
 338                 new_flags &= ~IR3_REG_FNEG;
 339         }
 340
 341         /* Reallocate for 4 more elements whenever it's necessary */
 342         struct ir3_const_state *const_state = &ctx->so->shader->const_state;
 343         if (const_state->immediate_idx == const_state->immediates_size * 4) {
 344                 const_state->immediates_size += 4;
 345                 const_state->immediates = realloc (const_state->immediates,
 346                         const_state->immediates_size * sizeof(const_state->immediates[0]));
 347
 348                 for (int i = const_state->immediate_idx; i < const_state->immediates_size * 4; i++)
 349                         const_state->immediates[i / 4].val[i % 4] = 0xd0d0d0d0;
 350         }
 351
 352         for (i = 0; i < const_state->immediate_idx; i++) {
 353                 swiz = i % 4;
 354                 idx  = i / 4;
 355
 356                 if (const_state->immediates[idx].val[swiz] == reg->uim_val) {
 357                         break;
 358                 }
 359         }
 360
 361         if (i == const_state->immediate_idx) {
 362                 /* need to generate a new immediate: */
 363                 swiz = i % 4;
 364                 idx  = i / 4;
 365
 366                 const_state->immediates[idx].val[swiz] = reg->uim_val;
 367                 const_state->immediates_count = idx + 1;
 368                 const_state->immediate_idx++;
 369         }
 370
 371         new_flags &= ~IR3_REG_IMMED;
 372         new_flags |= IR3_REG_CONST;
 373         reg->flags = new_flags;
 374         reg->num = i + (4 * const_state->offsets.immediate);
 375
 376         return reg;
 377 }
 378
 379 static void
 380 unuse(struct ir3_instruction *instr)
 381 {
 382         debug_assert(instr->use_count > 0);
 383
 384         if (--instr->use_count == 0) {
 385                 struct ir3_block *block = instr->block;
 386
 387                 instr->barrier_class = 0;
 388                 instr->barrier_conflict = 0;
 389
 390                 /* we don't want to remove anything in keeps (which could
 391                  * be things like array store's)
 392                  */
 393                 for (unsigned i = 0; i < block->keeps_count; i++) {
 394                         debug_assert(block->keeps[i] != instr);
 395                 }
 396         }
 397 }
 398
 399 /**
 400  * Handles the special case of the 2nd src (n == 1) to "normal" mad
 401  * instructions, which cannot reference a constant.  See if it is
 402  * possible to swap the 1st and 2nd sources.
 403  */
 404 static bool
 405 try_swap_mad_two_srcs(struct ir3_instruction *instr, unsigned new_flags)
 406 {
 407         if (!is_mad(instr->opc))
 408                 return false;
 409
 410         /* NOTE: pre-swap first two src's before valid_flags(),
 411          * which might try to dereference the n'th src:
 412          */
 413         swap(instr->regs[0 + 1], instr->regs[1 + 1]);
 414
 415         /* cat3 doesn't encode immediate, but we can lower immediate
 416          * to const if that helps:
 417          */
 418         if (new_flags & IR3_REG_IMMED) {
 419                 new_flags &= ~IR3_REG_IMMED;
 420                 new_flags |=  IR3_REG_CONST;
 421         }
 422
 423         bool valid_swap =
 424                 /* can we propagate mov if we move 2nd src to first? */
 425                 valid_flags(instr, 0, new_flags) &&
 426                 /* and does first src fit in second slot? */
 427                 valid_flags(instr, 1, instr->regs[1 + 1]->flags);
 428
 429         if (!valid_swap) {
 430                 /* put things back the way they were: */
 431                 swap(instr->regs[0 + 1], instr->regs[1 + 1]);
 432         }   /* otherwise leave things swapped */
 433
 434         return valid_swap;
 435 }
 436
 437 /**
 438  * Handle cp for a given src register.  This additionally handles
 439  * the cases of collapsing immedate/const (which replace the src
 440  * register with a non-ssa src) or collapsing mov's from relative
 441  * src (which needs to also fixup the address src reference by the
 442  * instruction).
 443  */
 444 static bool
 445 reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr,
 446                 struct ir3_register *reg, unsigned n)
 447 {
 448         struct ir3_instruction *src = ssa(reg);
 449
 450         if (is_eligible_mov(src, instr, true)) {
 451                 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */
 452                 struct ir3_register *src_reg = src->regs[1];
 453                 unsigned new_flags = reg->flags;
 454
 455                 combine_flags(&new_flags, src);
 456
 457                 if (valid_flags(instr, n, new_flags)) {
 458                         if (new_flags & IR3_REG_ARRAY) {
 459                                 debug_assert(!(reg->flags & IR3_REG_ARRAY));
 460                                 reg->array = src_reg->array;
 461                         }
 462                         reg->flags = new_flags;
 463                         reg->instr = ssa(src_reg);
 464
 465                         instr->barrier_class |= src->barrier_class;
 466                         instr->barrier_conflict |= src->barrier_conflict;
 467
 468                         unuse(src);
 469                         reg->instr->use_count++;
 470
 471                         return true;
 472                 }
 473         } else if ((is_same_type_mov(src) || is_const_mov(src)) &&
 474                         /* cannot collapse const/immed/etc into meta instrs: */
 475                         !is_meta(instr)) {
 476                 /* immed/const/etc cases, which require some special handling: */
 477                 struct ir3_register *src_reg = src->regs[1];
 478                 unsigned new_flags = reg->flags;
 479
 480                 combine_flags(&new_flags, src);
 481
 482                 if (!valid_flags(instr, n, new_flags)) {
 483                         /* See if lowering an immediate to const would help. */
 484                         if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) {
 485                                 bool f_opcode = (is_cat2_float(instr->opc) ||
 486                                                 is_cat3_float(instr->opc)) ? true : false;
 487
 488                                 debug_assert(new_flags & IR3_REG_IMMED);
 489
 490                                 instr->regs[n + 1] = lower_immed(ctx, src_reg, new_flags, f_opcode);
 491                                 return true;
 492                         }
 493
 494                         /* special case for "normal" mad instructions, we can
 495                          * try swapping the first two args if that fits better.
 496                          *
 497                          * the "plain" MAD's (ie. the ones that don't shift first
 498                          * src prior to multiply) can swap their first two srcs if
 499                          * src[0] is !CONST and src[1] is CONST:
 500                          */
 501                         if ((n == 1) && try_swap_mad_two_srcs(instr, new_flags)) {
 502                                 return true;
 503                         } else {
 504                                 return false;
 505                         }
 506                 }
 507
 508                 /* Here we handle the special case of mov from
 509                  * CONST and/or RELATIV.  These need to be handled
 510                  * specially, because in the case of move from CONST
 511                  * there is no src ir3_instruction so we need to
 512                  * replace the ir3_register.  And in the case of
 513                  * RELATIV we need to handle the address register
 514                  * dependency.
 515                  */
 516                 if (src_reg->flags & IR3_REG_CONST) {
 517                         /* an instruction cannot reference two different
 518                          * address registers:
 519                          */
 520                         if ((src_reg->flags & IR3_REG_RELATIV) &&
 521                                         conflicts(instr->address, reg->instr->address))
 522                                 return false;
 523
 524                         /* This seems to be a hw bug, or something where the timings
 525                          * just somehow don't work out.  This restriction may only
 526                          * apply if the first src is also CONST.
 527                          */
 528                         if ((opc_cat(instr->opc) == 3) && (n == 2) &&
 529                                         (src_reg->flags & IR3_REG_RELATIV) &&
 530                                         (src_reg->array.offset == 0))
 531                                 return false;
 532
 533                         /* When narrowing constant from 32b to 16b, it seems
 534                          * to work only for float. So we should do this only with
 535                          * float opcodes.
 536                          */
 537                         if (src->cat1.dst_type == TYPE_F16) {
 538                                 if (instr->opc == OPC_MOV && !type_float(instr->cat1.src_type))
 539                                         return false;
 540                                 if (!is_cat2_float(instr->opc) && !is_cat3_float(instr->opc))
 541                                         return false;
 542                         }
 543
 544                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 545                         src_reg->flags = new_flags;
 546                         instr->regs[n+1] = src_reg;
 547
 548                         if (src_reg->flags & IR3_REG_RELATIV)
 549                                 ir3_instr_set_address(instr, reg->instr->address);
 550
 551                         return true;
 552                 }
 553
 554                 if ((src_reg->flags & IR3_REG_RELATIV) &&
 555                                 !conflicts(instr->address, reg->instr->address)) {
 556                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 557                         src_reg->flags = new_flags;
 558                         instr->regs[n+1] = src_reg;
 559                         ir3_instr_set_address(instr, reg->instr->address);
 560
 561                         return true;
 562                 }
 563
 564                 /* NOTE: seems we can only do immed integers, so don't
 565                  * need to care about float.  But we do need to handle
 566                  * abs/neg *before* checking that the immediate requires
 567                  * few enough bits to encode:
 568                  *
 569                  * TODO: do we need to do something to avoid accidentally
 570                  * catching a float immed?
 571                  */
 572                 if (src_reg->flags & IR3_REG_IMMED) {
 573                         int32_t iim_val = src_reg->iim_val;
 574
 575                         debug_assert((opc_cat(instr->opc) == 1) ||
 576                                         (opc_cat(instr->opc) == 6) ||
 577                                         ir3_cat2_int(instr->opc) ||
 578                                         (is_mad(instr->opc) && (n == 0)));
 579
 580                         if (new_flags & IR3_REG_SABS)
 581                                 iim_val = abs(iim_val);
 582
 583                         if (new_flags & IR3_REG_SNEG)
 584                                 iim_val = -iim_val;
 585
 586                         if (new_flags & IR3_REG_BNOT)
 587                                 iim_val = ~iim_val;
 588
 589                         /* other than category 1 (mov) we can only encode up to 10 bits: */
 590                         if (valid_flags(instr, n, new_flags) &&
 591                                         ((instr->opc == OPC_MOV) ||
 592                                          !((iim_val & ~0x3ff) && (-iim_val & ~0x3ff)))) {
 593                                 new_flags &= ~(IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT);
 594                                 src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 595                                 src_reg->flags = new_flags;
 596                                 src_reg->iim_val = iim_val;
 597                                 instr->regs[n+1] = src_reg;
 598
 599                                 return true;
 600                         } else if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) {
 601                                 bool f_opcode = (is_cat2_float(instr->opc) ||
 602                                                 is_cat3_float(instr->opc)) ? true : false;
 603
 604                                 /* See if lowering an immediate to const would help. */
 605                                 instr->regs[n+1] = lower_immed(ctx, src_reg, new_flags, f_opcode);
 606
 607                                 return true;
 608                         }
 609                 }
 610         }
 611
 612         return false;
 613 }
 614
 615 /* Handle special case of eliminating output mov, and similar cases where
 616  * there isn't a normal "consuming" instruction.  In this case we cannot
 617  * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
 618  * be eliminated)
 619  */
 620 static struct ir3_instruction *
 621 eliminate_output_mov(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
 622 {
 623         if (is_eligible_mov(instr, NULL, false)) {
 624                 struct ir3_register *reg = instr->regs[1];
 625                 if (!(reg->flags & IR3_REG_ARRAY)) {
 626                         struct ir3_instruction *src_instr = ssa(reg);
 627                         debug_assert(src_instr);
 628                         ctx->progress = true;
 629                         return src_instr;
 630                 }
 631         }
 632         return instr;
 633 }
 634
 635 /**
 636  * Find instruction src's which are mov's that can be collapsed, replacing
 637  * the mov dst with the mov src
 638  */
 639 static void
 640 instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
 641 {
 642         if (instr->regs_count == 0)
 643                 return;
 644
 645         if (ir3_instr_check_mark(instr))
 646                 return;
 647
 648         /* walk down the graph from each src: */
 649         bool progress;
 650         do {
 651                 progress = false;
 652                 foreach_src_n (reg, n, instr) {
 653                         struct ir3_instruction *src = ssa(reg);
 654
 655                         if (!src)
 656                                 continue;
 657
 658                         instr_cp(ctx, src);
 659
 660                         /* TODO non-indirect access we could figure out which register
 661                          * we actually want and allow cp..
 662                          */
 663                         if (reg->flags & IR3_REG_ARRAY)
 664                                 continue;
 665
 666                         /* Don't CP absneg into meta instructions, that won't end well: */
 667                         if (is_meta(instr) && (src->opc != OPC_MOV))
 668                                 continue;
 669
 670                         progress |= reg_cp(ctx, instr, reg, n);
 671                         ctx->progress |= progress;
 672                 }
 673         } while (progress);
 674
 675         if (instr->regs[0]->flags & IR3_REG_ARRAY) {
 676                 struct ir3_instruction *src = ssa(instr->regs[0]);
 677                 if (src)
 678                         instr_cp(ctx, src);
 679         }
 680
 681         if (instr->address) {
 682                 instr_cp(ctx, instr->address);
 683                 ir3_instr_set_address(instr, eliminate_output_mov(ctx, instr->address));
 684         }
 685
 686         /* we can end up with extra cmps.s from frontend, which uses a
 687          *
 688          *    cmps.s p0.x, cond, 0
 689          *
 690          * as a way to mov into the predicate register.  But frequently 'cond'
 691          * is itself a cmps.s/cmps.f/cmps.u.  So detect this special case and
 692          * just re-write the instruction writing predicate register to get rid
 693          * of the double cmps.
 694          */
 695         if ((instr->opc == OPC_CMPS_S) &&
 696                         (instr->regs[0]->num == regid(REG_P0, 0)) &&
 697                         ssa(instr->regs[1]) &&
 698                         (instr->regs[2]->flags & IR3_REG_IMMED) &&
 699                         (instr->regs[2]->iim_val == 0)) {
 700                 struct ir3_instruction *cond = ssa(instr->regs[1]);
 701                 switch (cond->opc) {
 702                 case OPC_CMPS_S:
 703                 case OPC_CMPS_F:
 704                 case OPC_CMPS_U:
 705                         instr->opc   = cond->opc;
 706                         instr->flags = cond->flags;
 707                         instr->cat2  = cond->cat2;
 708                         ir3_instr_set_address(instr, cond->address);
 709                         instr->regs[1] = cond->regs[1];
 710                         instr->regs[2] = cond->regs[2];
 711                         instr->barrier_class |= cond->barrier_class;
 712                         instr->barrier_conflict |= cond->barrier_conflict;
 713                         unuse(cond);
 714                         ctx->progress = true;
 715                         break;
 716                 default:
 717                         break;
 718                 }
 719         }
 720
 721         /* Handle converting a sam.s2en (taking samp/tex idx params via register)
 722          * into a normal sam (encoding immediate samp/tex idx) if they are
 723          * immediate. This saves some instructions and regs in the common case
 724          * where we know samp/tex at compile time. This needs to be done in the
 725          * frontend for bindless tex, though, so don't replicate it here.
 726          */
 727         if (is_tex(instr) && (instr->flags & IR3_INSTR_S2EN) &&
 728                         !(instr->flags & IR3_INSTR_B) &&
 729                         !(ir3_shader_debug & IR3_DBG_FORCES2EN)) {
 730                 /* The first src will be a collect, if both of it's
 731                  * two sources are mov from imm, then we can
 732                  */
 733                 struct ir3_instruction *samp_tex = ssa(instr->regs[1]);
 734
 735                 debug_assert(samp_tex->opc == OPC_META_COLLECT);
 736
 737                 struct ir3_instruction *samp = ssa(samp_tex->regs[1]);
 738                 struct ir3_instruction *tex  = ssa(samp_tex->regs[2]);
 739
 740                 if ((samp->opc == OPC_MOV) &&
 741                                 (samp->regs[1]->flags & IR3_REG_IMMED) &&
 742                                 (tex->opc == OPC_MOV) &&
 743                                 (tex->regs[1]->flags & IR3_REG_IMMED)) {
 744                         instr->flags &= ~IR3_INSTR_S2EN;
 745                         instr->cat5.samp = samp->regs[1]->iim_val;
 746                         instr->cat5.tex  = tex->regs[1]->iim_val;
 747
 748                         /* shuffle around the regs to remove the first src: */
 749                         instr->regs_count--;
 750                         for (unsigned i = 1; i < instr->regs_count; i++) {
 751                                 instr->regs[i] = instr->regs[i + 1];
 752                         }
 753
 754                         ctx->progress = true;
 755                 }
 756         }
 757 }
 758
 759 bool
 760 ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so)
 761 {
 762         struct ir3_cp_ctx ctx = {
 763                         .shader = ir,
 764                         .so = so,
 765         };
 766
 767         /* This is a bit annoying, and probably wouldn't be necessary if we
 768          * tracked a reverse link from producing instruction to consumer.
 769          * But we need to know when we've eliminated the last consumer of
 770          * a mov, so we need to do a pass to first count consumers of a
 771          * mov.
 772          */
 773         foreach_block (block, &ir->block_list) {
 774                 foreach_instr (instr, &block->instr_list) {
 775                         struct ir3_instruction *src;
 776
 777                         /* by the way, we don't account for false-dep's, so the CP
 778                          * pass should always happen before false-dep's are inserted
 779                          */
 780                         debug_assert(instr->deps_count == 0);
 781
 782                         foreach_ssa_src (src, instr) {
 783                                 src->use_count++;
 784                         }
 785                 }
 786         }
 787
 788         ir3_clear_mark(ir);
 789
 790         struct ir3_instruction *out;
 791         foreach_output_n (out, n, ir) {
 792                 instr_cp(&ctx, out);
 793                 ir->outputs[n] = eliminate_output_mov(&ctx, out);
 794         }
 795
 796         foreach_block (block, &ir->block_list) {
 797                 if (block->condition) {
 798                         instr_cp(&ctx, block->condition);
 799                         block->condition = eliminate_output_mov(&ctx, block->condition);
 800                 }
 801
 802                 for (unsigned i = 0; i < block->keeps_count; i++) {
 803                         instr_cp(&ctx, block->keeps[i]);
 804                         block->keeps[i] = eliminate_output_mov(&ctx, block->keeps[i]);
 805                 }
 806         }
 807
 808         return ctx.progress;
 809 }