src/freedreno/ir3/ir3_cp.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include <math.h>
  28
  29 #include "ir3.h"
  30 #include "ir3_compiler.h"
  31 #include "ir3_shader.h"
  32
  33 /*
  34  * Copy Propagate:
  35  */
  36
  37 struct ir3_cp_ctx {
  38         struct ir3 *shader;
  39         struct ir3_shader_variant *so;
  40 };
  41
  42 /* is it a type preserving mov, with ok flags? */
  43 static bool is_eligible_mov(struct ir3_instruction *instr, bool allow_flags)
  44 {
  45         if (is_same_type_mov(instr)) {
  46                 struct ir3_register *dst = instr->regs[0];
  47                 struct ir3_register *src = instr->regs[1];
  48                 struct ir3_instruction *src_instr = ssa(src);
  49
  50                 /* only if mov src is SSA (not const/immed): */
  51                 if (!src_instr)
  52                         return false;
  53
  54                 /* no indirect: */
  55                 if (dst->flags & IR3_REG_RELATIV)
  56                         return false;
  57                 if (src->flags & IR3_REG_RELATIV)
  58                         return false;
  59
  60                 if (src->flags & IR3_REG_ARRAY)
  61                         return false;
  62
  63                 if (!allow_flags)
  64                         if (src->flags & (IR3_REG_FABS | IR3_REG_FNEG |
  65                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
  66                                 return false;
  67
  68                 /* TODO: remove this hack: */
  69                 if (src_instr->opc == OPC_META_FO)
  70                         return false;
  71
  72                 return true;
  73         }
  74         return false;
  75 }
  76
  77 static unsigned cp_flags(unsigned flags)
  78 {
  79         /* only considering these flags (at least for now): */
  80         flags &= (IR3_REG_CONST | IR3_REG_IMMED |
  81                         IR3_REG_FNEG | IR3_REG_FABS |
  82                         IR3_REG_SNEG | IR3_REG_SABS |
  83                         IR3_REG_BNOT | IR3_REG_RELATIV);
  84         return flags;
  85 }
  86
  87 static bool valid_flags(struct ir3_instruction *instr, unsigned n,
  88                 unsigned flags)
  89 {
  90         unsigned valid_flags;
  91
  92         if ((flags & IR3_REG_HIGH) &&
  93                         (opc_cat(instr->opc) > 1) &&
  94                         (instr->block->shader->compiler->gpu_id >= 600))
  95                 return false;
  96
  97         flags = cp_flags(flags);
  98
  99         /* If destination is indirect, then source cannot be.. at least
 100          * I don't think so..
 101          */
 102         if ((instr->regs[0]->flags & IR3_REG_RELATIV) &&
 103                         (flags & IR3_REG_RELATIV))
 104                 return false;
 105
 106         /* TODO it seems to *mostly* work to cp RELATIV, except we get some
 107          * intermittent piglit variable-indexing fails.  Newer blob driver
 108          * doesn't seem to cp these.  Possibly this is hw workaround?  Not
 109          * sure, but until that is understood better, lets just switch off
 110          * cp for indirect src's:
 111          */
 112         if (flags & IR3_REG_RELATIV)
 113                 return false;
 114
 115         switch (opc_cat(instr->opc)) {
 116         case 1:
 117                 valid_flags = IR3_REG_IMMED | IR3_REG_CONST | IR3_REG_RELATIV;
 118                 if (flags & ~valid_flags)
 119                         return false;
 120                 break;
 121         case 2:
 122                 valid_flags = ir3_cat2_absneg(instr->opc) |
 123                                 IR3_REG_CONST | IR3_REG_RELATIV;
 124
 125                 if (ir3_cat2_int(instr->opc))
 126                         valid_flags |= IR3_REG_IMMED;
 127
 128                 if (flags & ~valid_flags)
 129                         return false;
 130
 131                 if (flags & (IR3_REG_CONST | IR3_REG_IMMED)) {
 132                         unsigned m = (n ^ 1) + 1;
 133                         /* cannot deal w/ const in both srcs:
 134                          * (note that some cat2 actually only have a single src)
 135                          */
 136                         if (m < instr->regs_count) {
 137                                 struct ir3_register *reg = instr->regs[m];
 138                                 if ((flags & IR3_REG_CONST) && (reg->flags & IR3_REG_CONST))
 139                                         return false;
 140                                 if ((flags & IR3_REG_IMMED) && (reg->flags & IR3_REG_IMMED))
 141                                         return false;
 142                         }
 143                         /* cannot be const + ABS|NEG: */
 144                         if (flags & (IR3_REG_FABS | IR3_REG_FNEG |
 145                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
 146                                 return false;
 147                 }
 148                 break;
 149         case 3:
 150                 valid_flags = ir3_cat3_absneg(instr->opc) |
 151                                 IR3_REG_CONST | IR3_REG_RELATIV;
 152
 153                 if (flags & ~valid_flags)
 154                         return false;
 155
 156                 if (flags & (IR3_REG_CONST | IR3_REG_RELATIV)) {
 157                         /* cannot deal w/ const/relativ in 2nd src: */
 158                         if (n == 1)
 159                                 return false;
 160                 }
 161
 162                 if (flags & IR3_REG_CONST) {
 163                         /* cannot be const + ABS|NEG: */
 164                         if (flags & (IR3_REG_FABS | IR3_REG_FNEG |
 165                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
 166                                 return false;
 167                 }
 168                 break;
 169         case 4:
 170                 /* seems like blob compiler avoids const as src.. */
 171                 /* TODO double check if this is still the case on a4xx */
 172                 if (flags & (IR3_REG_CONST | IR3_REG_IMMED))
 173                         return false;
 174                 if (flags & (IR3_REG_SABS | IR3_REG_SNEG))
 175                         return false;
 176                 break;
 177         case 5:
 178                 /* no flags allowed */
 179                 if (flags)
 180                         return false;
 181                 break;
 182         case 6:
 183                 valid_flags = IR3_REG_IMMED;
 184                 if (flags & ~valid_flags)
 185                         return false;
 186
 187                 if (flags & IR3_REG_IMMED) {
 188                         /* doesn't seem like we can have immediate src for store
 189                          * instructions:
 190                          *
 191                          * TODO this restriction could also apply to load instructions,
 192                          * but for load instructions this arg is the address (and not
 193                          * really sure any good way to test a hard-coded immed addr src)
 194                          */
 195                         if (is_store(instr) && (n == 1))
 196                                 return false;
 197
 198                         if ((instr->opc == OPC_LDL) && (n != 1))
 199                                 return false;
 200
 201                         if ((instr->opc == OPC_STL) && (n != 2))
 202                                 return false;
 203
 204                         /* disallow CP into anything but the SSBO slot argument for
 205                          * atomics:
 206                          */
 207                         if (is_atomic(instr->opc) && (n != 0))
 208                                 return false;
 209
 210                         if (is_atomic(instr->opc) && !(instr->flags & IR3_INSTR_G))
 211                                 return false;
 212
 213                         /* as with atomics, ldib on a6xx can only have immediate for
 214                          * SSBO slot argument
 215                          */
 216                         if ((instr->opc == OPC_LDIB) && (n != 0))
 217                                 return false;
 218                 }
 219
 220                 break;
 221         }
 222
 223         return true;
 224 }
 225
 226 /* propagate register flags from src to dst.. negates need special
 227  * handling to cancel each other out.
 228  */
 229 static void combine_flags(unsigned *dstflags, struct ir3_instruction *src)
 230 {
 231         unsigned srcflags = src->regs[1]->flags;
 232
 233         /* if what we are combining into already has (abs) flags,
 234          * we can drop (neg) from src:
 235          */
 236         if (*dstflags & IR3_REG_FABS)
 237                 srcflags &= ~IR3_REG_FNEG;
 238         if (*dstflags & IR3_REG_SABS)
 239                 srcflags &= ~IR3_REG_SNEG;
 240
 241         if (srcflags & IR3_REG_FABS)
 242                 *dstflags |= IR3_REG_FABS;
 243         if (srcflags & IR3_REG_SABS)
 244                 *dstflags |= IR3_REG_SABS;
 245         if (srcflags & IR3_REG_FNEG)
 246                 *dstflags ^= IR3_REG_FNEG;
 247         if (srcflags & IR3_REG_SNEG)
 248                 *dstflags ^= IR3_REG_SNEG;
 249         if (srcflags & IR3_REG_BNOT)
 250                 *dstflags ^= IR3_REG_BNOT;
 251
 252         *dstflags &= ~IR3_REG_SSA;
 253         *dstflags |= srcflags & IR3_REG_SSA;
 254         *dstflags |= srcflags & IR3_REG_CONST;
 255         *dstflags |= srcflags & IR3_REG_IMMED;
 256         *dstflags |= srcflags & IR3_REG_RELATIV;
 257         *dstflags |= srcflags & IR3_REG_ARRAY;
 258         *dstflags |= srcflags & IR3_REG_HIGH;
 259
 260         /* if src of the src is boolean we can drop the (abs) since we know
 261          * the source value is already a postitive integer.  This cleans
 262          * up the absnegs that get inserted when converting between nir and
 263          * native boolean (see ir3_b2n/n2b)
 264          */
 265         struct ir3_instruction *srcsrc = ssa(src->regs[1]);
 266         if (srcsrc && is_bool(srcsrc))
 267                 *dstflags &= ~IR3_REG_SABS;
 268 }
 269
 270 static struct ir3_register *
 271 lower_immed(struct ir3_cp_ctx *ctx, struct ir3_register *reg, unsigned new_flags)
 272 {
 273         unsigned swiz, idx, i;
 274
 275         reg = ir3_reg_clone(ctx->shader, reg);
 276
 277         /* in some cases, there are restrictions on (abs)/(neg) plus const..
 278          * so just evaluate those and clear the flags:
 279          */
 280         if (new_flags & IR3_REG_SABS) {
 281                 reg->iim_val = abs(reg->iim_val);
 282                 new_flags &= ~IR3_REG_SABS;
 283         }
 284
 285         if (new_flags & IR3_REG_FABS) {
 286                 reg->fim_val = fabs(reg->fim_val);
 287                 new_flags &= ~IR3_REG_FABS;
 288         }
 289
 290         if (new_flags & IR3_REG_SNEG) {
 291                 reg->iim_val = -reg->iim_val;
 292                 new_flags &= ~IR3_REG_SNEG;
 293         }
 294
 295         if (new_flags & IR3_REG_FNEG) {
 296                 reg->fim_val = -reg->fim_val;
 297                 new_flags &= ~IR3_REG_FNEG;
 298         }
 299
 300         /* Reallocate for 4 more elements whenever it's necessary */
 301         struct ir3_const_state *const_state = &ctx->so->const_state;
 302         if (const_state->immediate_idx == const_state->immediates_size * 4) {
 303                 const_state->immediates_size += 4;
 304                 const_state->immediates = realloc (const_state->immediates,
 305                         const_state->immediates_size * sizeof(const_state->immediates[0]));
 306         }
 307
 308         for (i = 0; i < const_state->immediate_idx; i++) {
 309                 swiz = i % 4;
 310                 idx  = i / 4;
 311
 312                 if (const_state->immediates[idx].val[swiz] == reg->uim_val) {
 313                         break;
 314                 }
 315         }
 316
 317         if (i == const_state->immediate_idx) {
 318                 /* need to generate a new immediate: */
 319                 swiz = i % 4;
 320                 idx  = i / 4;
 321                 const_state->immediates[idx].val[swiz] = reg->uim_val;
 322                 const_state->immediates_count = idx + 1;
 323                 const_state->immediate_idx++;
 324         }
 325
 326         new_flags &= ~IR3_REG_IMMED;
 327         new_flags |= IR3_REG_CONST;
 328         reg->flags = new_flags;
 329         reg->num = i + (4 * const_state->offsets.immediate);
 330
 331         return reg;
 332 }
 333
 334 static void
 335 unuse(struct ir3_instruction *instr)
 336 {
 337         debug_assert(instr->use_count > 0);
 338
 339         if (--instr->use_count == 0) {
 340                 struct ir3_block *block = instr->block;
 341
 342                 instr->barrier_class = 0;
 343                 instr->barrier_conflict = 0;
 344
 345                 /* we don't want to remove anything in keeps (which could
 346                  * be things like array store's)
 347                  */
 348                 for (unsigned i = 0; i < block->keeps_count; i++) {
 349                         debug_assert(block->keeps[i] != instr);
 350                 }
 351         }
 352 }
 353
 354 /**
 355  * Handle cp for a given src register.  This additionally handles
 356  * the cases of collapsing immedate/const (which replace the src
 357  * register with a non-ssa src) or collapsing mov's from relative
 358  * src (which needs to also fixup the address src reference by the
 359  * instruction).
 360  */
 361 static void
 362 reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr,
 363                 struct ir3_register *reg, unsigned n)
 364 {
 365         struct ir3_instruction *src = ssa(reg);
 366
 367         if (is_eligible_mov(src, true)) {
 368                 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */
 369                 struct ir3_register *src_reg = src->regs[1];
 370                 unsigned new_flags = reg->flags;
 371
 372                 combine_flags(&new_flags, src);
 373
 374                 if (valid_flags(instr, n, new_flags)) {
 375                         if (new_flags & IR3_REG_ARRAY) {
 376                                 debug_assert(!(reg->flags & IR3_REG_ARRAY));
 377                                 reg->array = src_reg->array;
 378                         }
 379                         reg->flags = new_flags;
 380                         reg->instr = ssa(src_reg);
 381
 382                         instr->barrier_class |= src->barrier_class;
 383                         instr->barrier_conflict |= src->barrier_conflict;
 384
 385                         unuse(src);
 386                         reg->instr->use_count++;
 387                 }
 388
 389         } else if (is_same_type_mov(src) &&
 390                         /* cannot collapse const/immed/etc into meta instrs: */
 391                         !is_meta(instr)) {
 392                 /* immed/const/etc cases, which require some special handling: */
 393                 struct ir3_register *src_reg = src->regs[1];
 394                 unsigned new_flags = reg->flags;
 395
 396                 combine_flags(&new_flags, src);
 397
 398                 if (!valid_flags(instr, n, new_flags)) {
 399                         /* See if lowering an immediate to const would help. */
 400                         if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) {
 401                                 debug_assert(new_flags & IR3_REG_IMMED);
 402                                 instr->regs[n + 1] = lower_immed(ctx, src_reg, new_flags);
 403                                 return;
 404                         }
 405
 406                         /* special case for "normal" mad instructions, we can
 407                          * try swapping the first two args if that fits better.
 408                          *
 409                          * the "plain" MAD's (ie. the ones that don't shift first
 410                          * src prior to multiply) can swap their first two srcs if
 411                          * src[0] is !CONST and src[1] is CONST:
 412                          */
 413                         if ((n == 1) && is_mad(instr->opc) &&
 414                                         !(instr->regs[0 + 1]->flags & (IR3_REG_CONST | IR3_REG_RELATIV)) &&
 415                                         valid_flags(instr, 0, new_flags & ~IR3_REG_IMMED)) {
 416                                 /* swap src[0] and src[1]: */
 417                                 struct ir3_register *tmp;
 418                                 tmp = instr->regs[0 + 1];
 419                                 instr->regs[0 + 1] = instr->regs[1 + 1];
 420                                 instr->regs[1 + 1] = tmp;
 421
 422                                 n = 0;
 423                         } else {
 424                                 return;
 425                         }
 426                 }
 427
 428                 /* Here we handle the special case of mov from
 429                  * CONST and/or RELATIV.  These need to be handled
 430                  * specially, because in the case of move from CONST
 431                  * there is no src ir3_instruction so we need to
 432                  * replace the ir3_register.  And in the case of
 433                  * RELATIV we need to handle the address register
 434                  * dependency.
 435                  */
 436                 if (src_reg->flags & IR3_REG_CONST) {
 437                         /* an instruction cannot reference two different
 438                          * address registers:
 439                          */
 440                         if ((src_reg->flags & IR3_REG_RELATIV) &&
 441                                         conflicts(instr->address, reg->instr->address))
 442                                 return;
 443
 444                         /* This seems to be a hw bug, or something where the timings
 445                          * just somehow don't work out.  This restriction may only
 446                          * apply if the first src is also CONST.
 447                          */
 448                         if ((opc_cat(instr->opc) == 3) && (n == 2) &&
 449                                         (src_reg->flags & IR3_REG_RELATIV) &&
 450                                         (src_reg->array.offset == 0))
 451                                 return;
 452
 453                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 454                         src_reg->flags = new_flags;
 455                         instr->regs[n+1] = src_reg;
 456
 457                         if (src_reg->flags & IR3_REG_RELATIV)
 458                                 ir3_instr_set_address(instr, reg->instr->address);
 459
 460                         return;
 461                 }
 462
 463                 if ((src_reg->flags & IR3_REG_RELATIV) &&
 464                                 !conflicts(instr->address, reg->instr->address)) {
 465                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 466                         src_reg->flags = new_flags;
 467                         instr->regs[n+1] = src_reg;
 468                         ir3_instr_set_address(instr, reg->instr->address);
 469
 470                         return;
 471                 }
 472
 473                 /* NOTE: seems we can only do immed integers, so don't
 474                  * need to care about float.  But we do need to handle
 475                  * abs/neg *before* checking that the immediate requires
 476                  * few enough bits to encode:
 477                  *
 478                  * TODO: do we need to do something to avoid accidentally
 479                  * catching a float immed?
 480                  */
 481                 if (src_reg->flags & IR3_REG_IMMED) {
 482                         int32_t iim_val = src_reg->iim_val;
 483
 484                         debug_assert((opc_cat(instr->opc) == 1) ||
 485                                         (opc_cat(instr->opc) == 6) ||
 486                                         ir3_cat2_int(instr->opc) ||
 487                                         (is_mad(instr->opc) && (n == 0)));
 488
 489                         if (new_flags & IR3_REG_SABS)
 490                                 iim_val = abs(iim_val);
 491
 492                         if (new_flags & IR3_REG_SNEG)
 493                                 iim_val = -iim_val;
 494
 495                         if (new_flags & IR3_REG_BNOT)
 496                                 iim_val = ~iim_val;
 497
 498                         /* other than category 1 (mov) we can only encode up to 10 bits: */
 499                         if ((instr->opc == OPC_MOV) ||
 500                                         !((iim_val & ~0x3ff) && (-iim_val & ~0x3ff))) {
 501                                 new_flags &= ~(IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT);
 502                                 src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 503                                 src_reg->flags = new_flags;
 504                                 src_reg->iim_val = iim_val;
 505                                 instr->regs[n+1] = src_reg;
 506                         } else if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) {
 507                                 /* See if lowering an immediate to const would help. */
 508                                 instr->regs[n+1] = lower_immed(ctx, src_reg, new_flags);
 509                         }
 510
 511                         return;
 512                 }
 513         }
 514 }
 515
 516 /* Handle special case of eliminating output mov, and similar cases where
 517  * there isn't a normal "consuming" instruction.  In this case we cannot
 518  * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
 519  * be eliminated)
 520  */
 521 static struct ir3_instruction *
 522 eliminate_output_mov(struct ir3_instruction *instr)
 523 {
 524         if (is_eligible_mov(instr, false)) {
 525                 struct ir3_register *reg = instr->regs[1];
 526                 if (!(reg->flags & IR3_REG_ARRAY)) {
 527                         struct ir3_instruction *src_instr = ssa(reg);
 528                         debug_assert(src_instr);
 529                         return src_instr;
 530                 }
 531         }
 532         return instr;
 533 }
 534
 535 /**
 536  * Find instruction src's which are mov's that can be collapsed, replacing
 537  * the mov dst with the mov src
 538  */
 539 static void
 540 instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
 541 {
 542         struct ir3_register *reg;
 543
 544         if (instr->regs_count == 0)
 545                 return;
 546
 547         if (ir3_instr_check_mark(instr))
 548                 return;
 549
 550         /* walk down the graph from each src: */
 551         foreach_src_n(reg, n, instr) {
 552                 struct ir3_instruction *src = ssa(reg);
 553
 554                 if (!src)
 555                         continue;
 556
 557                 instr_cp(ctx, src);
 558
 559                 /* TODO non-indirect access we could figure out which register
 560                  * we actually want and allow cp..
 561                  */
 562                 if (reg->flags & IR3_REG_ARRAY)
 563                         continue;
 564
 565                 /* Don't CP absneg into meta instructions, that won't end well: */
 566                 if (is_meta(instr) && (src->opc != OPC_MOV))
 567                         continue;
 568
 569                 reg_cp(ctx, instr, reg, n);
 570         }
 571
 572         if (instr->regs[0]->flags & IR3_REG_ARRAY) {
 573                 struct ir3_instruction *src = ssa(instr->regs[0]);
 574                 if (src)
 575                         instr_cp(ctx, src);
 576         }
 577
 578         if (instr->address) {
 579                 instr_cp(ctx, instr->address);
 580                 ir3_instr_set_address(instr, eliminate_output_mov(instr->address));
 581         }
 582
 583         /* we can end up with extra cmps.s from frontend, which uses a
 584          *
 585          *    cmps.s p0.x, cond, 0
 586          *
 587          * as a way to mov into the predicate register.  But frequently 'cond'
 588          * is itself a cmps.s/cmps.f/cmps.u.  So detect this special case and
 589          * just re-write the instruction writing predicate register to get rid
 590          * of the double cmps.
 591          */
 592         if ((instr->opc == OPC_CMPS_S) &&
 593                         (instr->regs[0]->num == regid(REG_P0, 0)) &&
 594                         ssa(instr->regs[1]) &&
 595                         (instr->regs[2]->flags & IR3_REG_IMMED) &&
 596                         (instr->regs[2]->iim_val == 0)) {
 597                 struct ir3_instruction *cond = ssa(instr->regs[1]);
 598                 switch (cond->opc) {
 599                 case OPC_CMPS_S:
 600                 case OPC_CMPS_F:
 601                 case OPC_CMPS_U:
 602                         instr->opc   = cond->opc;
 603                         instr->flags = cond->flags;
 604                         instr->cat2  = cond->cat2;
 605                         instr->address = cond->address;
 606                         instr->regs[1] = cond->regs[1];
 607                         instr->regs[2] = cond->regs[2];
 608                         instr->barrier_class |= cond->barrier_class;
 609                         instr->barrier_conflict |= cond->barrier_conflict;
 610                         unuse(cond);
 611                         break;
 612                 default:
 613                         break;
 614                 }
 615         }
 616
 617         /* Handle converting a sam.s2en (taking samp/tex idx params via
 618          * register) into a normal sam (encoding immediate samp/tex idx)
 619          * if they are immediate.  This saves some instructions and regs
 620          * in the common case where we know samp/tex at compile time:
 621          */
 622         if (is_tex(instr) && (instr->flags & IR3_INSTR_S2EN) &&
 623                         !(ir3_shader_debug & IR3_DBG_FORCES2EN)) {
 624                 /* The first src will be a fan-in (collect), if both of it's
 625                  * two sources are mov from imm, then we can
 626                  */
 627                 struct ir3_instruction *samp_tex = ssa(instr->regs[1]);
 628
 629                 debug_assert(samp_tex->opc == OPC_META_FI);
 630
 631                 struct ir3_instruction *samp = ssa(samp_tex->regs[1]);
 632                 struct ir3_instruction *tex  = ssa(samp_tex->regs[2]);
 633
 634                 if ((samp->opc == OPC_MOV) &&
 635                                 (samp->regs[1]->flags & IR3_REG_IMMED) &&
 636                                 (tex->opc == OPC_MOV) &&
 637                                 (tex->regs[1]->flags & IR3_REG_IMMED)) {
 638                         instr->flags &= ~IR3_INSTR_S2EN;
 639                         instr->cat5.samp = samp->regs[1]->iim_val;
 640                         instr->cat5.tex  = tex->regs[1]->iim_val;
 641                         instr->regs[1]->instr = NULL;
 642                 }
 643         }
 644 }
 645
 646 void
 647 ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so)
 648 {
 649         struct ir3_cp_ctx ctx = {
 650                         .shader = ir,
 651                         .so = so,
 652         };
 653
 654         /* This is a bit annoying, and probably wouldn't be necessary if we
 655          * tracked a reverse link from producing instruction to consumer.
 656          * But we need to know when we've eliminated the last consumer of
 657          * a mov, so we need to do a pass to first count consumers of a
 658          * mov.
 659          */
 660         list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
 661                 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
 662                         struct ir3_instruction *src;
 663
 664                         /* by the way, we don't account for false-dep's, so the CP
 665                          * pass should always happen before false-dep's are inserted
 666                          */
 667                         debug_assert(instr->deps_count == 0);
 668
 669                         foreach_ssa_src(src, instr) {
 670                                 src->use_count++;
 671                         }
 672                 }
 673         }
 674
 675         ir3_clear_mark(ir);
 676
 677         for (unsigned i = 0; i < ir->noutputs; i++) {
 678                 if (ir->outputs[i]) {
 679                         instr_cp(&ctx, ir->outputs[i]);
 680                         ir->outputs[i] = eliminate_output_mov(ir->outputs[i]);
 681                 }
 682         }
 683
 684         list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
 685                 if (block->condition) {
 686                         instr_cp(&ctx, block->condition);
 687                         block->condition = eliminate_output_mov(block->condition);
 688                 }
 689
 690                 for (unsigned i = 0; i < block->keeps_count; i++) {
 691                         instr_cp(&ctx, block->keeps[i]);
 692                         block->keeps[i] = eliminate_output_mov(block->keeps[i]);
 693                 }
 694         }
 695 }