src/freedreno/ir3/ir3_cp.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include <math.h>
  28
  29 #include "ir3.h"
  30 #include "ir3_shader.h"
  31
  32 /*
  33  * Copy Propagate:
  34  */
  35
  36 struct ir3_cp_ctx {
  37         struct ir3 *shader;
  38         struct ir3_shader_variant *so;
  39         unsigned immediate_idx;
  40 };
  41
  42 /* is it a type preserving mov, with ok flags? */
  43 static bool is_eligible_mov(struct ir3_instruction *instr, bool allow_flags)
  44 {
  45         if (is_same_type_mov(instr)) {
  46                 struct ir3_register *dst = instr->regs[0];
  47                 struct ir3_register *src = instr->regs[1];
  48                 struct ir3_instruction *src_instr = ssa(src);
  49
  50                 /* only if mov src is SSA (not const/immed): */
  51                 if (!src_instr)
  52                         return false;
  53
  54                 /* no indirect: */
  55                 if (dst->flags & IR3_REG_RELATIV)
  56                         return false;
  57                 if (src->flags & IR3_REG_RELATIV)
  58                         return false;
  59
  60                 if (src->flags & IR3_REG_ARRAY)
  61                         return false;
  62
  63                 if (!allow_flags)
  64                         if (src->flags & (IR3_REG_FABS | IR3_REG_FNEG |
  65                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
  66                                 return false;
  67
  68                 /* TODO: remove this hack: */
  69                 if (src_instr->opc == OPC_META_FO)
  70                         return false;
  71
  72                 return true;
  73         }
  74         return false;
  75 }
  76
  77 static unsigned cp_flags(unsigned flags)
  78 {
  79         /* only considering these flags (at least for now): */
  80         flags &= (IR3_REG_CONST | IR3_REG_IMMED |
  81                         IR3_REG_FNEG | IR3_REG_FABS |
  82                         IR3_REG_SNEG | IR3_REG_SABS |
  83                         IR3_REG_BNOT | IR3_REG_RELATIV);
  84         return flags;
  85 }
  86
  87 static bool valid_flags(struct ir3_instruction *instr, unsigned n,
  88                 unsigned flags)
  89 {
  90         unsigned valid_flags;
  91         flags = cp_flags(flags);
  92
  93         /* If destination is indirect, then source cannot be.. at least
  94          * I don't think so..
  95          */
  96         if ((instr->regs[0]->flags & IR3_REG_RELATIV) &&
  97                         (flags & IR3_REG_RELATIV))
  98                 return false;
  99
 100         /* TODO it seems to *mostly* work to cp RELATIV, except we get some
 101          * intermittent piglit variable-indexing fails.  Newer blob driver
 102          * doesn't seem to cp these.  Possibly this is hw workaround?  Not
 103          * sure, but until that is understood better, lets just switch off
 104          * cp for indirect src's:
 105          */
 106         if (flags & IR3_REG_RELATIV)
 107                 return false;
 108
 109         switch (opc_cat(instr->opc)) {
 110         case 1:
 111                 valid_flags = IR3_REG_IMMED | IR3_REG_CONST | IR3_REG_RELATIV;
 112                 if (flags & ~valid_flags)
 113                         return false;
 114                 break;
 115         case 2:
 116                 valid_flags = ir3_cat2_absneg(instr->opc) |
 117                                 IR3_REG_CONST | IR3_REG_RELATIV;
 118
 119                 if (ir3_cat2_int(instr->opc))
 120                         valid_flags |= IR3_REG_IMMED;
 121
 122                 if (flags & ~valid_flags)
 123                         return false;
 124
 125                 if (flags & (IR3_REG_CONST | IR3_REG_IMMED)) {
 126                         unsigned m = (n ^ 1) + 1;
 127                         /* cannot deal w/ const in both srcs:
 128                          * (note that some cat2 actually only have a single src)
 129                          */
 130                         if (m < instr->regs_count) {
 131                                 struct ir3_register *reg = instr->regs[m];
 132                                 if ((flags & IR3_REG_CONST) && (reg->flags & IR3_REG_CONST))
 133                                         return false;
 134                                 if ((flags & IR3_REG_IMMED) && (reg->flags & IR3_REG_IMMED))
 135                                         return false;
 136                         }
 137                         /* cannot be const + ABS|NEG: */
 138                         if (flags & (IR3_REG_FABS | IR3_REG_FNEG |
 139                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
 140                                 return false;
 141                 }
 142                 break;
 143         case 3:
 144                 valid_flags = ir3_cat3_absneg(instr->opc) |
 145                                 IR3_REG_CONST | IR3_REG_RELATIV;
 146
 147                 if (flags & ~valid_flags)
 148                         return false;
 149
 150                 if (flags & (IR3_REG_CONST | IR3_REG_RELATIV)) {
 151                         /* cannot deal w/ const/relativ in 2nd src: */
 152                         if (n == 1)
 153                                 return false;
 154                 }
 155
 156                 if (flags & IR3_REG_CONST) {
 157                         /* cannot be const + ABS|NEG: */
 158                         if (flags & (IR3_REG_FABS | IR3_REG_FNEG |
 159                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
 160                                 return false;
 161                 }
 162                 break;
 163         case 4:
 164                 /* seems like blob compiler avoids const as src.. */
 165                 /* TODO double check if this is still the case on a4xx */
 166                 if (flags & (IR3_REG_CONST | IR3_REG_IMMED))
 167                         return false;
 168                 if (flags & (IR3_REG_SABS | IR3_REG_SNEG))
 169                         return false;
 170                 break;
 171         case 5:
 172                 /* no flags allowed */
 173                 if (flags)
 174                         return false;
 175                 break;
 176         case 6:
 177                 valid_flags = IR3_REG_IMMED;
 178                 if (flags & ~valid_flags)
 179                         return false;
 180
 181                 if (flags & IR3_REG_IMMED) {
 182                         /* doesn't seem like we can have immediate src for store
 183                          * instructions:
 184                          *
 185                          * TODO this restriction could also apply to load instructions,
 186                          * but for load instructions this arg is the address (and not
 187                          * really sure any good way to test a hard-coded immed addr src)
 188                          */
 189                         if (is_store(instr) && (n == 1))
 190                                 return false;
 191
 192                         if ((instr->opc == OPC_LDL) && (n != 1))
 193                                 return false;
 194
 195                         if ((instr->opc == OPC_STL) && (n != 2))
 196                                 return false;
 197
 198                         /* disallow CP into anything but the SSBO slot argument for
 199                          * atomics:
 200                          */
 201                         if (is_atomic(instr->opc) && (n != 0))
 202                                 return false;
 203
 204                         if (is_atomic(instr->opc) && !(instr->flags & IR3_INSTR_G))
 205                                 return false;
 206                 }
 207
 208                 break;
 209         }
 210
 211         return true;
 212 }
 213
 214 /* propagate register flags from src to dst.. negates need special
 215  * handling to cancel each other out.
 216  */
 217 static void combine_flags(unsigned *dstflags, struct ir3_instruction *src)
 218 {
 219         unsigned srcflags = src->regs[1]->flags;
 220
 221         /* if what we are combining into already has (abs) flags,
 222          * we can drop (neg) from src:
 223          */
 224         if (*dstflags & IR3_REG_FABS)
 225                 srcflags &= ~IR3_REG_FNEG;
 226         if (*dstflags & IR3_REG_SABS)
 227                 srcflags &= ~IR3_REG_SNEG;
 228
 229         if (srcflags & IR3_REG_FABS)
 230                 *dstflags |= IR3_REG_FABS;
 231         if (srcflags & IR3_REG_SABS)
 232                 *dstflags |= IR3_REG_SABS;
 233         if (srcflags & IR3_REG_FNEG)
 234                 *dstflags ^= IR3_REG_FNEG;
 235         if (srcflags & IR3_REG_SNEG)
 236                 *dstflags ^= IR3_REG_SNEG;
 237         if (srcflags & IR3_REG_BNOT)
 238                 *dstflags ^= IR3_REG_BNOT;
 239
 240         *dstflags &= ~IR3_REG_SSA;
 241         *dstflags |= srcflags & IR3_REG_SSA;
 242         *dstflags |= srcflags & IR3_REG_CONST;
 243         *dstflags |= srcflags & IR3_REG_IMMED;
 244         *dstflags |= srcflags & IR3_REG_RELATIV;
 245         *dstflags |= srcflags & IR3_REG_ARRAY;
 246
 247         /* if src of the src is boolean we can drop the (abs) since we know
 248          * the source value is already a postitive integer.  This cleans
 249          * up the absnegs that get inserted when converting between nir and
 250          * native boolean (see ir3_b2n/n2b)
 251          */
 252         struct ir3_instruction *srcsrc = ssa(src->regs[1]);
 253         if (srcsrc && is_bool(srcsrc))
 254                 *dstflags &= ~IR3_REG_SABS;
 255 }
 256
 257 static struct ir3_register *
 258 lower_immed(struct ir3_cp_ctx *ctx, struct ir3_register *reg, unsigned new_flags)
 259 {
 260         unsigned swiz, idx, i;
 261
 262         reg = ir3_reg_clone(ctx->shader, reg);
 263
 264         /* in some cases, there are restrictions on (abs)/(neg) plus const..
 265          * so just evaluate those and clear the flags:
 266          */
 267         if (new_flags & IR3_REG_SABS) {
 268                 reg->iim_val = abs(reg->iim_val);
 269                 new_flags &= ~IR3_REG_SABS;
 270         }
 271
 272         if (new_flags & IR3_REG_FABS) {
 273                 reg->fim_val = fabs(reg->fim_val);
 274                 new_flags &= ~IR3_REG_FABS;
 275         }
 276
 277         if (new_flags & IR3_REG_SNEG) {
 278                 reg->iim_val = -reg->iim_val;
 279                 new_flags &= ~IR3_REG_SNEG;
 280         }
 281
 282         if (new_flags & IR3_REG_FNEG) {
 283                 reg->fim_val = -reg->fim_val;
 284                 new_flags &= ~IR3_REG_FNEG;
 285         }
 286
 287         /* Reallocate for 4 more elements whenever it's necessary */
 288         if (ctx->immediate_idx == ctx->so->immediates_size * 4) {
 289                 ctx->so->immediates_size += 4;
 290                 ctx->so->immediates = realloc (ctx->so->immediates,
 291                         ctx->so->immediates_size * sizeof (ctx->so->immediates[0]));
 292         }
 293
 294         for (i = 0; i < ctx->immediate_idx; i++) {
 295                 swiz = i % 4;
 296                 idx  = i / 4;
 297
 298                 if (ctx->so->immediates[idx].val[swiz] == reg->uim_val) {
 299                         break;
 300                 }
 301         }
 302
 303         if (i == ctx->immediate_idx) {
 304                 /* need to generate a new immediate: */
 305                 swiz = i % 4;
 306                 idx  = i / 4;
 307                 ctx->so->immediates[idx].val[swiz] = reg->uim_val;
 308                 ctx->so->immediates_count = idx + 1;
 309                 ctx->immediate_idx++;
 310         }
 311
 312         new_flags &= ~IR3_REG_IMMED;
 313         new_flags |= IR3_REG_CONST;
 314         reg->flags = new_flags;
 315         reg->num = i + (4 * ctx->so->constbase.immediate);
 316
 317         return reg;
 318 }
 319
 320 static void
 321 unuse(struct ir3_instruction *instr)
 322 {
 323         debug_assert(instr->use_count > 0);
 324
 325         if (--instr->use_count == 0) {
 326                 struct ir3_block *block = instr->block;
 327
 328                 instr->barrier_class = 0;
 329                 instr->barrier_conflict = 0;
 330
 331                 /* we don't want to remove anything in keeps (which could
 332                  * be things like array store's)
 333                  */
 334                 for (unsigned i = 0; i < block->keeps_count; i++) {
 335                         debug_assert(block->keeps[i] != instr);
 336                 }
 337         }
 338 }
 339
 340 /**
 341  * Handle cp for a given src register.  This additionally handles
 342  * the cases of collapsing immedate/const (which replace the src
 343  * register with a non-ssa src) or collapsing mov's from relative
 344  * src (which needs to also fixup the address src reference by the
 345  * instruction).
 346  */
 347 static void
 348 reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr,
 349                 struct ir3_register *reg, unsigned n)
 350 {
 351         struct ir3_instruction *src = ssa(reg);
 352
 353         if (is_eligible_mov(src, true)) {
 354                 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */
 355                 struct ir3_register *src_reg = src->regs[1];
 356                 unsigned new_flags = reg->flags;
 357
 358                 combine_flags(&new_flags, src);
 359
 360                 if (valid_flags(instr, n, new_flags)) {
 361                         if (new_flags & IR3_REG_ARRAY) {
 362                                 debug_assert(!(reg->flags & IR3_REG_ARRAY));
 363                                 reg->array = src_reg->array;
 364                         }
 365                         reg->flags = new_flags;
 366                         reg->instr = ssa(src_reg);
 367
 368                         instr->barrier_class |= src->barrier_class;
 369                         instr->barrier_conflict |= src->barrier_conflict;
 370
 371                         unuse(src);
 372                         reg->instr->use_count++;
 373                 }
 374
 375         } else if (is_same_type_mov(src) &&
 376                         /* cannot collapse const/immed/etc into meta instrs: */
 377                         !is_meta(instr)) {
 378                 /* immed/const/etc cases, which require some special handling: */
 379                 struct ir3_register *src_reg = src->regs[1];
 380                 unsigned new_flags = reg->flags;
 381
 382                 combine_flags(&new_flags, src);
 383
 384                 if (!valid_flags(instr, n, new_flags)) {
 385                         /* See if lowering an immediate to const would help. */
 386                         if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) {
 387                                 debug_assert(new_flags & IR3_REG_IMMED);
 388                                 instr->regs[n + 1] = lower_immed(ctx, src_reg, new_flags);
 389                                 return;
 390                         }
 391
 392                         /* special case for "normal" mad instructions, we can
 393                          * try swapping the first two args if that fits better.
 394                          *
 395                          * the "plain" MAD's (ie. the ones that don't shift first
 396                          * src prior to multiply) can swap their first two srcs if
 397                          * src[0] is !CONST and src[1] is CONST:
 398                          */
 399                         if ((n == 1) && is_mad(instr->opc) &&
 400                                         !(instr->regs[0 + 1]->flags & (IR3_REG_CONST | IR3_REG_RELATIV)) &&
 401                                         valid_flags(instr, 0, new_flags & ~IR3_REG_IMMED)) {
 402                                 /* swap src[0] and src[1]: */
 403                                 struct ir3_register *tmp;
 404                                 tmp = instr->regs[0 + 1];
 405                                 instr->regs[0 + 1] = instr->regs[1 + 1];
 406                                 instr->regs[1 + 1] = tmp;
 407
 408                                 n = 0;
 409                         } else {
 410                                 return;
 411                         }
 412                 }
 413
 414                 /* Here we handle the special case of mov from
 415                  * CONST and/or RELATIV.  These need to be handled
 416                  * specially, because in the case of move from CONST
 417                  * there is no src ir3_instruction so we need to
 418                  * replace the ir3_register.  And in the case of
 419                  * RELATIV we need to handle the address register
 420                  * dependency.
 421                  */
 422                 if (src_reg->flags & IR3_REG_CONST) {
 423                         /* an instruction cannot reference two different
 424                          * address registers:
 425                          */
 426                         if ((src_reg->flags & IR3_REG_RELATIV) &&
 427                                         conflicts(instr->address, reg->instr->address))
 428                                 return;
 429
 430                         /* This seems to be a hw bug, or something where the timings
 431                          * just somehow don't work out.  This restriction may only
 432                          * apply if the first src is also CONST.
 433                          */
 434                         if ((opc_cat(instr->opc) == 3) && (n == 2) &&
 435                                         (src_reg->flags & IR3_REG_RELATIV) &&
 436                                         (src_reg->array.offset == 0))
 437                                 return;
 438
 439                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 440                         src_reg->flags = new_flags;
 441                         instr->regs[n+1] = src_reg;
 442
 443                         if (src_reg->flags & IR3_REG_RELATIV)
 444                                 ir3_instr_set_address(instr, reg->instr->address);
 445
 446                         return;
 447                 }
 448
 449                 if ((src_reg->flags & IR3_REG_RELATIV) &&
 450                                 !conflicts(instr->address, reg->instr->address)) {
 451                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 452                         src_reg->flags = new_flags;
 453                         instr->regs[n+1] = src_reg;
 454                         ir3_instr_set_address(instr, reg->instr->address);
 455
 456                         return;
 457                 }
 458
 459                 /* NOTE: seems we can only do immed integers, so don't
 460                  * need to care about float.  But we do need to handle
 461                  * abs/neg *before* checking that the immediate requires
 462                  * few enough bits to encode:
 463                  *
 464                  * TODO: do we need to do something to avoid accidentally
 465                  * catching a float immed?
 466                  */
 467                 if (src_reg->flags & IR3_REG_IMMED) {
 468                         int32_t iim_val = src_reg->iim_val;
 469
 470                         debug_assert((opc_cat(instr->opc) == 1) ||
 471                                         (opc_cat(instr->opc) == 6) ||
 472                                         ir3_cat2_int(instr->opc) ||
 473                                         (is_mad(instr->opc) && (n == 0)));
 474
 475                         if (new_flags & IR3_REG_SABS)
 476                                 iim_val = abs(iim_val);
 477
 478                         if (new_flags & IR3_REG_SNEG)
 479                                 iim_val = -iim_val;
 480
 481                         if (new_flags & IR3_REG_BNOT)
 482                                 iim_val = ~iim_val;
 483
 484                         /* other than category 1 (mov) we can only encode up to 10 bits: */
 485                         if ((instr->opc == OPC_MOV) ||
 486                                         !((iim_val & ~0x3ff) && (-iim_val & ~0x3ff))) {
 487                                 new_flags &= ~(IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT);
 488                                 src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 489                                 src_reg->flags = new_flags;
 490                                 src_reg->iim_val = iim_val;
 491                                 instr->regs[n+1] = src_reg;
 492                         } else if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) {
 493                                 /* See if lowering an immediate to const would help. */
 494                                 instr->regs[n+1] = lower_immed(ctx, src_reg, new_flags);
 495                         }
 496
 497                         return;
 498                 }
 499         }
 500 }
 501
 502 /* Handle special case of eliminating output mov, and similar cases where
 503  * there isn't a normal "consuming" instruction.  In this case we cannot
 504  * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
 505  * be eliminated)
 506  */
 507 static struct ir3_instruction *
 508 eliminate_output_mov(struct ir3_instruction *instr)
 509 {
 510         if (is_eligible_mov(instr, false)) {
 511                 struct ir3_register *reg = instr->regs[1];
 512                 if (!(reg->flags & IR3_REG_ARRAY)) {
 513                         struct ir3_instruction *src_instr = ssa(reg);
 514                         debug_assert(src_instr);
 515                         return src_instr;
 516                 }
 517         }
 518         return instr;
 519 }
 520
 521 /**
 522  * Find instruction src's which are mov's that can be collapsed, replacing
 523  * the mov dst with the mov src
 524  */
 525 static void
 526 instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
 527 {
 528         struct ir3_register *reg;
 529
 530         if (instr->regs_count == 0)
 531                 return;
 532
 533         if (ir3_instr_check_mark(instr))
 534                 return;
 535
 536         /* walk down the graph from each src: */
 537         foreach_src_n(reg, n, instr) {
 538                 struct ir3_instruction *src = ssa(reg);
 539
 540                 if (!src)
 541                         continue;
 542
 543                 instr_cp(ctx, src);
 544
 545                 /* TODO non-indirect access we could figure out which register
 546                  * we actually want and allow cp..
 547                  */
 548                 if (reg->flags & IR3_REG_ARRAY)
 549                         continue;
 550
 551                 /* Don't CP absneg into meta instructions, that won't end well: */
 552                 if (is_meta(instr) && (src->opc != OPC_MOV))
 553                         continue;
 554
 555                 reg_cp(ctx, instr, reg, n);
 556         }
 557
 558         if (instr->regs[0]->flags & IR3_REG_ARRAY) {
 559                 struct ir3_instruction *src = ssa(instr->regs[0]);
 560                 if (src)
 561                         instr_cp(ctx, src);
 562         }
 563
 564         if (instr->address) {
 565                 instr_cp(ctx, instr->address);
 566                 ir3_instr_set_address(instr, eliminate_output_mov(instr->address));
 567         }
 568
 569         /* we can end up with extra cmps.s from frontend, which uses a
 570          *
 571          *    cmps.s p0.x, cond, 0
 572          *
 573          * as a way to mov into the predicate register.  But frequently 'cond'
 574          * is itself a cmps.s/cmps.f/cmps.u.  So detect this special case and
 575          * just re-write the instruction writing predicate register to get rid
 576          * of the double cmps.
 577          */
 578         if ((instr->opc == OPC_CMPS_S) &&
 579                         (instr->regs[0]->num == regid(REG_P0, 0)) &&
 580                         ssa(instr->regs[1]) &&
 581                         (instr->regs[2]->flags & IR3_REG_IMMED) &&
 582                         (instr->regs[2]->iim_val == 0)) {
 583                 struct ir3_instruction *cond = ssa(instr->regs[1]);
 584                 switch (cond->opc) {
 585                 case OPC_CMPS_S:
 586                 case OPC_CMPS_F:
 587                 case OPC_CMPS_U:
 588                         instr->opc   = cond->opc;
 589                         instr->flags = cond->flags;
 590                         instr->cat2  = cond->cat2;
 591                         instr->address = cond->address;
 592                         instr->regs[1] = cond->regs[1];
 593                         instr->regs[2] = cond->regs[2];
 594                         instr->barrier_class |= cond->barrier_class;
 595                         instr->barrier_conflict |= cond->barrier_conflict;
 596                         unuse(cond);
 597                         break;
 598                 default:
 599                         break;
 600                 }
 601         }
 602 }
 603
 604 void
 605 ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so)
 606 {
 607         struct ir3_cp_ctx ctx = {
 608                         .shader = ir,
 609                         .so = so,
 610         };
 611
 612         /* This is a bit annoying, and probably wouldn't be necessary if we
 613          * tracked a reverse link from producing instruction to consumer.
 614          * But we need to know when we've eliminated the last consumer of
 615          * a mov, so we need to do a pass to first count consumers of a
 616          * mov.
 617          */
 618         list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
 619                 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
 620                         struct ir3_instruction *src;
 621
 622                         /* by the way, we don't account for false-dep's, so the CP
 623                          * pass should always happen before false-dep's are inserted
 624                          */
 625                         debug_assert(instr->deps_count == 0);
 626
 627                         foreach_ssa_src(src, instr) {
 628                                 src->use_count++;
 629                         }
 630                 }
 631         }
 632
 633         ir3_clear_mark(ir);
 634
 635         for (unsigned i = 0; i < ir->noutputs; i++) {
 636                 if (ir->outputs[i]) {
 637                         instr_cp(&ctx, ir->outputs[i]);
 638                         ir->outputs[i] = eliminate_output_mov(ir->outputs[i]);
 639                 }
 640         }
 641
 642         list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
 643                 if (block->condition) {
 644                         instr_cp(&ctx, block->condition);
 645                         block->condition = eliminate_output_mov(block->condition);
 646                 }
 647
 648                 for (unsigned i = 0; i < block->keeps_count; i++) {
 649                         instr_cp(&ctx, block->keeps[i]);
 650                         block->keeps[i] = eliminate_output_mov(block->keeps[i]);
 651                 }
 652         }
 653 }