2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
28 #include "util/half_float.h"
29 #include "util/u_math.h"
32 #include "ir3_compiler.h"
33 #include "ir3_shader.h"
36 do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
44 struct ir3_shader_variant
*so
;
48 /* is it a type preserving mov, with ok flags?
50 * @instr: the mov to consider removing
51 * @dst_instr: the instruction consuming the mov (instr)
53 * TODO maybe drop allow_flags since this is only false when dst is
56 static bool is_eligible_mov(struct ir3_instruction
*instr
,
57 struct ir3_instruction
*dst_instr
, bool allow_flags
)
59 if (is_same_type_mov(instr
)) {
60 struct ir3_register
*dst
= instr
->regs
[0];
61 struct ir3_register
*src
= instr
->regs
[1];
62 struct ir3_instruction
*src_instr
= ssa(src
);
64 /* only if mov src is SSA (not const/immed): */
69 if (dst
->flags
& IR3_REG_RELATIV
)
71 if (src
->flags
& IR3_REG_RELATIV
)
74 if (src
->flags
& IR3_REG_ARRAY
)
78 if (src
->flags
& (IR3_REG_FABS
| IR3_REG_FNEG
|
79 IR3_REG_SABS
| IR3_REG_SNEG
| IR3_REG_BNOT
))
82 /* If src is coming from fanout/split (ie. one component of a
83 * texture fetch, etc) and we have constraints on swizzle of
84 * destination, then skip it.
86 * We could possibly do a bit better, and copy-propagation if
87 * we can CP all components that are being fanned out.
89 if (src_instr
->opc
== OPC_META_SPLIT
) {
92 if (dst_instr
->opc
== OPC_META_COLLECT
)
94 if (dst_instr
->cp
.left
|| dst_instr
->cp
.right
)
103 static unsigned cp_flags(unsigned flags
)
105 /* only considering these flags (at least for now): */
106 flags
&= (IR3_REG_CONST
| IR3_REG_IMMED
|
107 IR3_REG_FNEG
| IR3_REG_FABS
|
108 IR3_REG_SNEG
| IR3_REG_SABS
|
109 IR3_REG_BNOT
| IR3_REG_RELATIV
);
113 static bool valid_flags(struct ir3_instruction
*instr
, unsigned n
,
116 struct ir3_compiler
*compiler
= instr
->block
->shader
->compiler
;
117 unsigned valid_flags
;
119 if ((flags
& IR3_REG_HIGH
) &&
120 (opc_cat(instr
->opc
) > 1) &&
121 (compiler
->gpu_id
>= 600))
124 flags
= cp_flags(flags
);
126 /* If destination is indirect, then source cannot be.. at least
129 if ((instr
->regs
[0]->flags
& IR3_REG_RELATIV
) &&
130 (flags
& IR3_REG_RELATIV
))
133 if (flags
& IR3_REG_RELATIV
) {
134 /* TODO need to test on earlier gens.. pretty sure the earlier
135 * problem was just that we didn't check that the src was from
136 * same block (since we can't propagate address register values
137 * across blocks currently)
139 if (compiler
->gpu_id
< 600)
142 /* NOTE in the special try_swap_mad_two_srcs() case we can be
143 * called on a src that has already had an indirect load folded
144 * in, in which case ssa() returns NULL
146 struct ir3_instruction
*src
= ssa(instr
->regs
[n
+1]);
147 if (src
&& src
->address
->block
!= instr
->block
)
151 switch (opc_cat(instr
->opc
)) {
153 valid_flags
= IR3_REG_IMMED
| IR3_REG_CONST
| IR3_REG_RELATIV
;
154 if (flags
& ~valid_flags
)
158 valid_flags
= ir3_cat2_absneg(instr
->opc
) |
159 IR3_REG_CONST
| IR3_REG_RELATIV
;
161 if (ir3_cat2_int(instr
->opc
))
162 valid_flags
|= IR3_REG_IMMED
;
164 if (flags
& ~valid_flags
)
167 if (flags
& (IR3_REG_CONST
| IR3_REG_IMMED
)) {
168 unsigned m
= (n
^ 1) + 1;
169 /* cannot deal w/ const in both srcs:
170 * (note that some cat2 actually only have a single src)
172 if (m
< instr
->regs_count
) {
173 struct ir3_register
*reg
= instr
->regs
[m
];
174 if ((flags
& IR3_REG_CONST
) && (reg
->flags
& IR3_REG_CONST
))
176 if ((flags
& IR3_REG_IMMED
) && (reg
->flags
& IR3_REG_IMMED
))
182 valid_flags
= ir3_cat3_absneg(instr
->opc
) |
183 IR3_REG_CONST
| IR3_REG_RELATIV
;
185 if (flags
& ~valid_flags
)
188 if (flags
& (IR3_REG_CONST
| IR3_REG_RELATIV
)) {
189 /* cannot deal w/ const/relativ in 2nd src: */
196 /* seems like blob compiler avoids const as src.. */
197 /* TODO double check if this is still the case on a4xx */
198 if (flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
200 if (flags
& (IR3_REG_SABS
| IR3_REG_SNEG
))
204 /* no flags allowed */
209 valid_flags
= IR3_REG_IMMED
;
210 if (flags
& ~valid_flags
)
213 if (flags
& IR3_REG_IMMED
) {
214 /* doesn't seem like we can have immediate src for store
217 * TODO this restriction could also apply to load instructions,
218 * but for load instructions this arg is the address (and not
219 * really sure any good way to test a hard-coded immed addr src)
221 if (is_store(instr
) && (n
== 1))
224 if ((instr
->opc
== OPC_LDL
) && (n
== 0))
227 if ((instr
->opc
== OPC_STL
) && (n
!= 2))
230 if (instr
->opc
== OPC_STLW
&& n
== 0)
233 if (instr
->opc
== OPC_LDLW
&& n
== 0)
236 /* disallow immediates in anything but the SSBO slot argument for
239 if (is_atomic(instr
->opc
) && (n
!= 0))
242 if (is_atomic(instr
->opc
) && !(instr
->flags
& IR3_INSTR_G
))
245 if (instr
->opc
== OPC_STG
&& (instr
->flags
& IR3_INSTR_G
) && (n
!= 2))
248 /* as with atomics, these cat6 instrs can only have an immediate
249 * for SSBO/IBO slot argument
251 switch (instr
->opc
) {
269 /* propagate register flags from src to dst.. negates need special
270 * handling to cancel each other out.
272 static void combine_flags(unsigned *dstflags
, struct ir3_instruction
*src
)
274 unsigned srcflags
= src
->regs
[1]->flags
;
276 /* if what we are combining into already has (abs) flags,
277 * we can drop (neg) from src:
279 if (*dstflags
& IR3_REG_FABS
)
280 srcflags
&= ~IR3_REG_FNEG
;
281 if (*dstflags
& IR3_REG_SABS
)
282 srcflags
&= ~IR3_REG_SNEG
;
284 if (srcflags
& IR3_REG_FABS
)
285 *dstflags
|= IR3_REG_FABS
;
286 if (srcflags
& IR3_REG_SABS
)
287 *dstflags
|= IR3_REG_SABS
;
288 if (srcflags
& IR3_REG_FNEG
)
289 *dstflags
^= IR3_REG_FNEG
;
290 if (srcflags
& IR3_REG_SNEG
)
291 *dstflags
^= IR3_REG_SNEG
;
292 if (srcflags
& IR3_REG_BNOT
)
293 *dstflags
^= IR3_REG_BNOT
;
295 *dstflags
&= ~IR3_REG_SSA
;
296 *dstflags
|= srcflags
& IR3_REG_SSA
;
297 *dstflags
|= srcflags
& IR3_REG_CONST
;
298 *dstflags
|= srcflags
& IR3_REG_IMMED
;
299 *dstflags
|= srcflags
& IR3_REG_RELATIV
;
300 *dstflags
|= srcflags
& IR3_REG_ARRAY
;
301 *dstflags
|= srcflags
& IR3_REG_HIGH
;
303 /* if src of the src is boolean we can drop the (abs) since we know
304 * the source value is already a postitive integer. This cleans
305 * up the absnegs that get inserted when converting between nir and
306 * native boolean (see ir3_b2n/n2b)
308 struct ir3_instruction
*srcsrc
= ssa(src
->regs
[1]);
309 if (srcsrc
&& is_bool(srcsrc
))
310 *dstflags
&= ~IR3_REG_SABS
;
313 /* Tries lowering an immediate register argument to a const buffer access by
314 * adding to the list of immediates to be pushed to the const buffer when
315 * switching to this shader.
318 lower_immed(struct ir3_cp_ctx
*ctx
, struct ir3_instruction
*instr
, unsigned n
,
319 struct ir3_register
*reg
, unsigned new_flags
)
321 if (!(new_flags
& IR3_REG_IMMED
))
324 new_flags
&= ~IR3_REG_IMMED
;
325 new_flags
|= IR3_REG_CONST
;
327 if (!valid_flags(instr
, n
, new_flags
))
330 unsigned swiz
, idx
, i
;
332 reg
= ir3_reg_clone(ctx
->shader
, reg
);
334 /* Half constant registers seems to handle only 32-bit values
335 * within floating-point opcodes. So convert back to 32-bit values.
337 bool f_opcode
= (is_cat2_float(instr
->opc
) ||
338 is_cat3_float(instr
->opc
)) ? true : false;
339 if (f_opcode
&& (new_flags
& IR3_REG_HALF
))
340 reg
->uim_val
= fui(_mesa_half_to_float(reg
->uim_val
));
342 /* in some cases, there are restrictions on (abs)/(neg) plus const..
343 * so just evaluate those and clear the flags:
345 if (new_flags
& IR3_REG_SABS
) {
346 reg
->iim_val
= abs(reg
->iim_val
);
347 new_flags
&= ~IR3_REG_SABS
;
350 if (new_flags
& IR3_REG_FABS
) {
351 reg
->fim_val
= fabs(reg
->fim_val
);
352 new_flags
&= ~IR3_REG_FABS
;
355 if (new_flags
& IR3_REG_SNEG
) {
356 reg
->iim_val
= -reg
->iim_val
;
357 new_flags
&= ~IR3_REG_SNEG
;
360 if (new_flags
& IR3_REG_FNEG
) {
361 reg
->fim_val
= -reg
->fim_val
;
362 new_flags
&= ~IR3_REG_FNEG
;
365 /* Reallocate for 4 more elements whenever it's necessary */
366 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
367 if (const_state
->immediate_idx
== const_state
->immediates_size
* 4) {
368 const_state
->immediates_size
+= 4;
369 const_state
->immediates
= realloc (const_state
->immediates
,
370 const_state
->immediates_size
* sizeof(const_state
->immediates
[0]));
372 for (int i
= const_state
->immediate_idx
; i
< const_state
->immediates_size
* 4; i
++)
373 const_state
->immediates
[i
/ 4].val
[i
% 4] = 0xd0d0d0d0;
376 for (i
= 0; i
< const_state
->immediate_idx
; i
++) {
380 if (const_state
->immediates
[idx
].val
[swiz
] == reg
->uim_val
) {
385 if (i
== const_state
->immediate_idx
) {
386 /* need to generate a new immediate: */
390 const_state
->immediates
[idx
].val
[swiz
] = reg
->uim_val
;
391 const_state
->immediates_count
= idx
+ 1;
392 const_state
->immediate_idx
++;
395 reg
->flags
= new_flags
;
396 reg
->num
= i
+ (4 * const_state
->offsets
.immediate
);
398 instr
->regs
[n
+ 1] = reg
;
404 unuse(struct ir3_instruction
*instr
)
406 debug_assert(instr
->use_count
> 0);
408 if (--instr
->use_count
== 0) {
409 struct ir3_block
*block
= instr
->block
;
411 instr
->barrier_class
= 0;
412 instr
->barrier_conflict
= 0;
414 /* we don't want to remove anything in keeps (which could
415 * be things like array store's)
417 for (unsigned i
= 0; i
< block
->keeps_count
; i
++) {
418 debug_assert(block
->keeps
[i
] != instr
);
424 * Handles the special case of the 2nd src (n == 1) to "normal" mad
425 * instructions, which cannot reference a constant. See if it is
426 * possible to swap the 1st and 2nd sources.
429 try_swap_mad_two_srcs(struct ir3_instruction
*instr
, unsigned new_flags
)
431 if (!is_mad(instr
->opc
))
434 /* NOTE: pre-swap first two src's before valid_flags(),
435 * which might try to dereference the n'th src:
437 swap(instr
->regs
[0 + 1], instr
->regs
[1 + 1]);
439 /* cat3 doesn't encode immediate, but we can lower immediate
440 * to const if that helps:
442 if (new_flags
& IR3_REG_IMMED
) {
443 new_flags
&= ~IR3_REG_IMMED
;
444 new_flags
|= IR3_REG_CONST
;
448 /* can we propagate mov if we move 2nd src to first? */
449 valid_flags(instr
, 0, new_flags
) &&
450 /* and does first src fit in second slot? */
451 valid_flags(instr
, 1, instr
->regs
[1 + 1]->flags
);
454 /* put things back the way they were: */
455 swap(instr
->regs
[0 + 1], instr
->regs
[1 + 1]);
456 } /* otherwise leave things swapped */
462 * Handle cp for a given src register. This additionally handles
463 * the cases of collapsing immedate/const (which replace the src
464 * register with a non-ssa src) or collapsing mov's from relative
465 * src (which needs to also fixup the address src reference by the
469 reg_cp(struct ir3_cp_ctx
*ctx
, struct ir3_instruction
*instr
,
470 struct ir3_register
*reg
, unsigned n
)
472 struct ir3_instruction
*src
= ssa(reg
);
474 if (is_eligible_mov(src
, instr
, true)) {
475 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */
476 struct ir3_register
*src_reg
= src
->regs
[1];
477 unsigned new_flags
= reg
->flags
;
479 combine_flags(&new_flags
, src
);
481 if (valid_flags(instr
, n
, new_flags
)) {
482 if (new_flags
& IR3_REG_ARRAY
) {
483 debug_assert(!(reg
->flags
& IR3_REG_ARRAY
));
484 reg
->array
= src_reg
->array
;
486 reg
->flags
= new_flags
;
487 reg
->instr
= ssa(src_reg
);
489 instr
->barrier_class
|= src
->barrier_class
;
490 instr
->barrier_conflict
|= src
->barrier_conflict
;
493 reg
->instr
->use_count
++;
497 } else if ((is_same_type_mov(src
) || is_const_mov(src
)) &&
498 /* cannot collapse const/immed/etc into meta instrs: */
500 /* immed/const/etc cases, which require some special handling: */
501 struct ir3_register
*src_reg
= src
->regs
[1];
502 unsigned new_flags
= reg
->flags
;
504 combine_flags(&new_flags
, src
);
506 if (!valid_flags(instr
, n
, new_flags
)) {
507 /* See if lowering an immediate to const would help. */
508 if (lower_immed(ctx
, instr
, n
, src_reg
, new_flags
))
511 /* special case for "normal" mad instructions, we can
512 * try swapping the first two args if that fits better.
514 * the "plain" MAD's (ie. the ones that don't shift first
515 * src prior to multiply) can swap their first two srcs if
516 * src[0] is !CONST and src[1] is CONST:
518 if ((n
== 1) && try_swap_mad_two_srcs(instr
, new_flags
)) {
525 /* Here we handle the special case of mov from
526 * CONST and/or RELATIV. These need to be handled
527 * specially, because in the case of move from CONST
528 * there is no src ir3_instruction so we need to
529 * replace the ir3_register. And in the case of
530 * RELATIV we need to handle the address register
533 if (src_reg
->flags
& IR3_REG_CONST
) {
534 /* an instruction cannot reference two different
537 if ((src_reg
->flags
& IR3_REG_RELATIV
) &&
538 conflicts(instr
->address
, reg
->instr
->address
))
541 /* This seems to be a hw bug, or something where the timings
542 * just somehow don't work out. This restriction may only
543 * apply if the first src is also CONST.
545 if ((opc_cat(instr
->opc
) == 3) && (n
== 2) &&
546 (src_reg
->flags
& IR3_REG_RELATIV
) &&
547 (src_reg
->array
.offset
== 0))
550 /* When narrowing constant from 32b to 16b, it seems
551 * to work only for float. So we should do this only with
554 if (src
->cat1
.dst_type
== TYPE_F16
) {
555 if (instr
->opc
== OPC_MOV
&& !type_float(instr
->cat1
.src_type
))
557 if (!is_cat2_float(instr
->opc
) && !is_cat3_float(instr
->opc
))
561 src_reg
= ir3_reg_clone(instr
->block
->shader
, src_reg
);
562 src_reg
->flags
= new_flags
;
563 instr
->regs
[n
+1] = src_reg
;
565 if (src_reg
->flags
& IR3_REG_RELATIV
)
566 ir3_instr_set_address(instr
, reg
->instr
->address
);
571 if ((src_reg
->flags
& IR3_REG_RELATIV
) &&
572 !conflicts(instr
->address
, reg
->instr
->address
)) {
573 src_reg
= ir3_reg_clone(instr
->block
->shader
, src_reg
);
574 src_reg
->flags
= new_flags
;
575 instr
->regs
[n
+1] = src_reg
;
576 ir3_instr_set_address(instr
, reg
->instr
->address
);
581 /* NOTE: seems we can only do immed integers, so don't
582 * need to care about float. But we do need to handle
583 * abs/neg *before* checking that the immediate requires
584 * few enough bits to encode:
586 * TODO: do we need to do something to avoid accidentally
587 * catching a float immed?
589 if (src_reg
->flags
& IR3_REG_IMMED
) {
590 int32_t iim_val
= src_reg
->iim_val
;
592 debug_assert((opc_cat(instr
->opc
) == 1) ||
593 (opc_cat(instr
->opc
) == 6) ||
594 ir3_cat2_int(instr
->opc
) ||
595 (is_mad(instr
->opc
) && (n
== 0)));
597 if (new_flags
& IR3_REG_SABS
)
598 iim_val
= abs(iim_val
);
600 if (new_flags
& IR3_REG_SNEG
)
603 if (new_flags
& IR3_REG_BNOT
)
606 /* other than category 1 (mov) we can only encode up to 10 bits: */
607 if (valid_flags(instr
, n
, new_flags
) &&
608 ((instr
->opc
== OPC_MOV
) ||
609 !((iim_val
& ~0x3ff) && (-iim_val
& ~0x3ff)))) {
610 new_flags
&= ~(IR3_REG_SABS
| IR3_REG_SNEG
| IR3_REG_BNOT
);
611 src_reg
= ir3_reg_clone(instr
->block
->shader
, src_reg
);
612 src_reg
->flags
= new_flags
;
613 src_reg
->iim_val
= iim_val
;
614 instr
->regs
[n
+1] = src_reg
;
617 } else if (lower_immed(ctx
, instr
, n
, src_reg
, new_flags
)) {
618 /* Fell back to loading the immediate as a const */
627 /* Handle special case of eliminating output mov, and similar cases where
628 * there isn't a normal "consuming" instruction. In this case we cannot
629 * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
632 static struct ir3_instruction
*
633 eliminate_output_mov(struct ir3_cp_ctx
*ctx
, struct ir3_instruction
*instr
)
635 if (is_eligible_mov(instr
, NULL
, false)) {
636 struct ir3_register
*reg
= instr
->regs
[1];
637 if (!(reg
->flags
& IR3_REG_ARRAY
)) {
638 struct ir3_instruction
*src_instr
= ssa(reg
);
639 debug_assert(src_instr
);
640 ctx
->progress
= true;
648 * Find instruction src's which are mov's that can be collapsed, replacing
649 * the mov dst with the mov src
652 instr_cp(struct ir3_cp_ctx
*ctx
, struct ir3_instruction
*instr
)
654 if (instr
->regs_count
== 0)
657 if (ir3_instr_check_mark(instr
))
660 /* walk down the graph from each src: */
664 foreach_src_n (reg
, n
, instr
) {
665 struct ir3_instruction
*src
= ssa(reg
);
672 /* TODO non-indirect access we could figure out which register
673 * we actually want and allow cp..
675 if (reg
->flags
& IR3_REG_ARRAY
)
678 /* Don't CP absneg into meta instructions, that won't end well: */
679 if (is_meta(instr
) && (src
->opc
!= OPC_MOV
))
682 progress
|= reg_cp(ctx
, instr
, reg
, n
);
683 ctx
->progress
|= progress
;
687 if (instr
->regs
[0]->flags
& IR3_REG_ARRAY
) {
688 struct ir3_instruction
*src
= ssa(instr
->regs
[0]);
693 if (instr
->address
) {
694 instr_cp(ctx
, instr
->address
);
695 ir3_instr_set_address(instr
, eliminate_output_mov(ctx
, instr
->address
));
698 /* we can end up with extra cmps.s from frontend, which uses a
700 * cmps.s p0.x, cond, 0
702 * as a way to mov into the predicate register. But frequently 'cond'
703 * is itself a cmps.s/cmps.f/cmps.u. So detect this special case and
704 * just re-write the instruction writing predicate register to get rid
705 * of the double cmps.
707 if ((instr
->opc
== OPC_CMPS_S
) &&
708 (instr
->regs
[0]->num
== regid(REG_P0
, 0)) &&
709 ssa(instr
->regs
[1]) &&
710 (instr
->regs
[2]->flags
& IR3_REG_IMMED
) &&
711 (instr
->regs
[2]->iim_val
== 0) &&
712 (instr
->cat2
.condition
== IR3_COND_NE
)) {
713 struct ir3_instruction
*cond
= ssa(instr
->regs
[1]);
718 instr
->opc
= cond
->opc
;
719 instr
->flags
= cond
->flags
;
720 instr
->cat2
= cond
->cat2
;
721 ir3_instr_set_address(instr
, cond
->address
);
722 instr
->regs
[1] = cond
->regs
[1];
723 instr
->regs
[2] = cond
->regs
[2];
724 instr
->barrier_class
|= cond
->barrier_class
;
725 instr
->barrier_conflict
|= cond
->barrier_conflict
;
727 ctx
->progress
= true;
734 /* Handle converting a sam.s2en (taking samp/tex idx params via register)
735 * into a normal sam (encoding immediate samp/tex idx) if they are
736 * immediate. This saves some instructions and regs in the common case
737 * where we know samp/tex at compile time. This needs to be done in the
738 * frontend for bindless tex, though, so don't replicate it here.
740 if (is_tex(instr
) && (instr
->flags
& IR3_INSTR_S2EN
) &&
741 !(instr
->flags
& IR3_INSTR_B
) &&
742 !(ir3_shader_debug
& IR3_DBG_FORCES2EN
)) {
743 /* The first src will be a collect, if both of it's
744 * two sources are mov from imm, then we can
746 struct ir3_instruction
*samp_tex
= ssa(instr
->regs
[1]);
748 debug_assert(samp_tex
->opc
== OPC_META_COLLECT
);
750 struct ir3_instruction
*samp
= ssa(samp_tex
->regs
[1]);
751 struct ir3_instruction
*tex
= ssa(samp_tex
->regs
[2]);
753 if ((samp
->opc
== OPC_MOV
) &&
754 (samp
->regs
[1]->flags
& IR3_REG_IMMED
) &&
755 (tex
->opc
== OPC_MOV
) &&
756 (tex
->regs
[1]->flags
& IR3_REG_IMMED
)) {
757 instr
->flags
&= ~IR3_INSTR_S2EN
;
758 instr
->cat5
.samp
= samp
->regs
[1]->iim_val
;
759 instr
->cat5
.tex
= tex
->regs
[1]->iim_val
;
761 /* shuffle around the regs to remove the first src: */
763 for (unsigned i
= 1; i
< instr
->regs_count
; i
++) {
764 instr
->regs
[i
] = instr
->regs
[i
+ 1];
767 ctx
->progress
= true;
773 ir3_cp(struct ir3
*ir
, struct ir3_shader_variant
*so
)
775 struct ir3_cp_ctx ctx
= {
780 /* This is a bit annoying, and probably wouldn't be necessary if we
781 * tracked a reverse link from producing instruction to consumer.
782 * But we need to know when we've eliminated the last consumer of
783 * a mov, so we need to do a pass to first count consumers of a
786 foreach_block (block
, &ir
->block_list
) {
787 foreach_instr (instr
, &block
->instr_list
) {
789 /* by the way, we don't account for false-dep's, so the CP
790 * pass should always happen before false-dep's are inserted
792 debug_assert(instr
->deps_count
== 0);
794 foreach_ssa_src (src
, instr
) {
802 foreach_output_n (out
, n
, ir
) {
804 ir
->outputs
[n
] = eliminate_output_mov(&ctx
, out
);
807 foreach_block (block
, &ir
->block_list
) {
808 if (block
->condition
) {
809 instr_cp(&ctx
, block
->condition
);
810 block
->condition
= eliminate_output_mov(&ctx
, block
->condition
);
813 for (unsigned i
= 0; i
< block
->keeps_count
; i
++) {
814 instr_cp(&ctx
, block
->keeps
[i
]);
815 block
->keeps
[i
] = eliminate_output_mov(&ctx
, block
->keeps
[i
]);