2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
28 #include "util/half_float.h"
29 #include "util/u_math.h"
32 #include "ir3_compiler.h"
33 #include "ir3_shader.h"
36 do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
44 struct ir3_shader_variant
*so
;
47 /* is it a type preserving mov, with ok flags?
49 * @instr: the mov to consider removing
50 * @dst_instr: the instruction consuming the mov (instr)
52 * TODO maybe drop allow_flags since this is only false when dst is
55 static bool is_eligible_mov(struct ir3_instruction
*instr
,
56 struct ir3_instruction
*dst_instr
, bool allow_flags
)
58 if (is_same_type_mov(instr
)) {
59 struct ir3_register
*dst
= instr
->regs
[0];
60 struct ir3_register
*src
= instr
->regs
[1];
61 struct ir3_instruction
*src_instr
= ssa(src
);
63 /* only if mov src is SSA (not const/immed): */
68 if (dst
->flags
& IR3_REG_RELATIV
)
70 if (src
->flags
& IR3_REG_RELATIV
)
73 if (src
->flags
& IR3_REG_ARRAY
)
77 if (src
->flags
& (IR3_REG_FABS
| IR3_REG_FNEG
|
78 IR3_REG_SABS
| IR3_REG_SNEG
| IR3_REG_BNOT
))
81 /* If src is coming from fanout/split (ie. one component of a
82 * texture fetch, etc) and we have constraints on swizzle of
83 * destination, then skip it.
85 * We could possibly do a bit better, and copy-propagation if
86 * we can CP all components that are being fanned out.
88 if (src_instr
->opc
== OPC_META_FO
) {
91 if (dst_instr
->opc
== OPC_META_FI
)
93 if (dst_instr
->cp
.left
|| dst_instr
->cp
.right
)
102 static unsigned cp_flags(unsigned flags
)
104 /* only considering these flags (at least for now): */
105 flags
&= (IR3_REG_CONST
| IR3_REG_IMMED
|
106 IR3_REG_FNEG
| IR3_REG_FABS
|
107 IR3_REG_SNEG
| IR3_REG_SABS
|
108 IR3_REG_BNOT
| IR3_REG_RELATIV
);
112 static bool valid_flags(struct ir3_instruction
*instr
, unsigned n
,
115 struct ir3_compiler
*compiler
= instr
->block
->shader
->compiler
;
116 unsigned valid_flags
;
118 if ((flags
& IR3_REG_HIGH
) &&
119 (opc_cat(instr
->opc
) > 1) &&
120 (compiler
->gpu_id
>= 600))
123 flags
= cp_flags(flags
);
125 /* If destination is indirect, then source cannot be.. at least
128 if ((instr
->regs
[0]->flags
& IR3_REG_RELATIV
) &&
129 (flags
& IR3_REG_RELATIV
))
132 if (flags
& IR3_REG_RELATIV
) {
133 /* TODO need to test on earlier gens.. pretty sure the earlier
134 * problem was just that we didn't check that the src was from
135 * same block (since we can't propagate address register values
136 * across blocks currently)
138 if (compiler
->gpu_id
< 600)
141 /* NOTE in the special try_swap_mad_two_srcs() case we can be
142 * called on a src that has already had an indirect load folded
143 * in, in which case ssa() returns NULL
145 struct ir3_instruction
*src
= ssa(instr
->regs
[n
+1]);
146 if (src
&& src
->address
->block
!= instr
->block
)
150 switch (opc_cat(instr
->opc
)) {
152 valid_flags
= IR3_REG_IMMED
| IR3_REG_CONST
| IR3_REG_RELATIV
;
153 if (flags
& ~valid_flags
)
157 valid_flags
= ir3_cat2_absneg(instr
->opc
) |
158 IR3_REG_CONST
| IR3_REG_RELATIV
;
160 if (ir3_cat2_int(instr
->opc
))
161 valid_flags
|= IR3_REG_IMMED
;
163 if (flags
& ~valid_flags
)
166 if (flags
& (IR3_REG_CONST
| IR3_REG_IMMED
)) {
167 unsigned m
= (n
^ 1) + 1;
168 /* cannot deal w/ const in both srcs:
169 * (note that some cat2 actually only have a single src)
171 if (m
< instr
->regs_count
) {
172 struct ir3_register
*reg
= instr
->regs
[m
];
173 if ((flags
& IR3_REG_CONST
) && (reg
->flags
& IR3_REG_CONST
))
175 if ((flags
& IR3_REG_IMMED
) && (reg
->flags
& IR3_REG_IMMED
))
181 valid_flags
= ir3_cat3_absneg(instr
->opc
) |
182 IR3_REG_CONST
| IR3_REG_RELATIV
;
184 if (flags
& ~valid_flags
)
187 if (flags
& (IR3_REG_CONST
| IR3_REG_RELATIV
)) {
188 /* cannot deal w/ const/relativ in 2nd src: */
195 /* seems like blob compiler avoids const as src.. */
196 /* TODO double check if this is still the case on a4xx */
197 if (flags
& (IR3_REG_CONST
| IR3_REG_IMMED
))
199 if (flags
& (IR3_REG_SABS
| IR3_REG_SNEG
))
203 /* no flags allowed */
208 valid_flags
= IR3_REG_IMMED
;
209 if (flags
& ~valid_flags
)
212 if (flags
& IR3_REG_IMMED
) {
213 /* doesn't seem like we can have immediate src for store
216 * TODO this restriction could also apply to load instructions,
217 * but for load instructions this arg is the address (and not
218 * really sure any good way to test a hard-coded immed addr src)
220 if (is_store(instr
) && (n
== 1))
223 if ((instr
->opc
== OPC_LDL
) && (n
== 0))
226 if ((instr
->opc
== OPC_STL
) && (n
!= 2))
229 if (instr
->opc
== OPC_STLW
&& n
== 0)
232 /* disallow CP into anything but the SSBO slot argument for
235 if (is_atomic(instr
->opc
) && (n
!= 0))
238 if (is_atomic(instr
->opc
) && !(instr
->flags
& IR3_INSTR_G
))
241 /* as with atomics, ldib on a6xx can only have immediate for
244 if ((instr
->opc
== OPC_LDIB
) && (n
!= 0))
254 /* propagate register flags from src to dst.. negates need special
255 * handling to cancel each other out.
257 static void combine_flags(unsigned *dstflags
, struct ir3_instruction
*src
)
259 unsigned srcflags
= src
->regs
[1]->flags
;
261 /* if what we are combining into already has (abs) flags,
262 * we can drop (neg) from src:
264 if (*dstflags
& IR3_REG_FABS
)
265 srcflags
&= ~IR3_REG_FNEG
;
266 if (*dstflags
& IR3_REG_SABS
)
267 srcflags
&= ~IR3_REG_SNEG
;
269 if (srcflags
& IR3_REG_FABS
)
270 *dstflags
|= IR3_REG_FABS
;
271 if (srcflags
& IR3_REG_SABS
)
272 *dstflags
|= IR3_REG_SABS
;
273 if (srcflags
& IR3_REG_FNEG
)
274 *dstflags
^= IR3_REG_FNEG
;
275 if (srcflags
& IR3_REG_SNEG
)
276 *dstflags
^= IR3_REG_SNEG
;
277 if (srcflags
& IR3_REG_BNOT
)
278 *dstflags
^= IR3_REG_BNOT
;
280 *dstflags
&= ~IR3_REG_SSA
;
281 *dstflags
|= srcflags
& IR3_REG_SSA
;
282 *dstflags
|= srcflags
& IR3_REG_CONST
;
283 *dstflags
|= srcflags
& IR3_REG_IMMED
;
284 *dstflags
|= srcflags
& IR3_REG_RELATIV
;
285 *dstflags
|= srcflags
& IR3_REG_ARRAY
;
286 *dstflags
|= srcflags
& IR3_REG_HIGH
;
288 /* if src of the src is boolean we can drop the (abs) since we know
289 * the source value is already a postitive integer. This cleans
290 * up the absnegs that get inserted when converting between nir and
291 * native boolean (see ir3_b2n/n2b)
293 struct ir3_instruction
*srcsrc
= ssa(src
->regs
[1]);
294 if (srcsrc
&& is_bool(srcsrc
))
295 *dstflags
&= ~IR3_REG_SABS
;
298 static struct ir3_register
*
299 lower_immed(struct ir3_cp_ctx
*ctx
, struct ir3_register
*reg
, unsigned new_flags
, bool f_opcode
)
301 unsigned swiz
, idx
, i
;
303 reg
= ir3_reg_clone(ctx
->shader
, reg
);
305 /* in some cases, there are restrictions on (abs)/(neg) plus const..
306 * so just evaluate those and clear the flags:
308 if (new_flags
& IR3_REG_SABS
) {
309 reg
->iim_val
= abs(reg
->iim_val
);
310 new_flags
&= ~IR3_REG_SABS
;
313 if (new_flags
& IR3_REG_FABS
) {
314 reg
->fim_val
= fabs(reg
->fim_val
);
315 new_flags
&= ~IR3_REG_FABS
;
318 if (new_flags
& IR3_REG_SNEG
) {
319 reg
->iim_val
= -reg
->iim_val
;
320 new_flags
&= ~IR3_REG_SNEG
;
323 if (new_flags
& IR3_REG_FNEG
) {
324 reg
->fim_val
= -reg
->fim_val
;
325 new_flags
&= ~IR3_REG_FNEG
;
328 /* Reallocate for 4 more elements whenever it's necessary */
329 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
330 if (const_state
->immediate_idx
== const_state
->immediates_size
* 4) {
331 const_state
->immediates_size
+= 4;
332 const_state
->immediates
= realloc (const_state
->immediates
,
333 const_state
->immediates_size
* sizeof(const_state
->immediates
[0]));
336 for (i
= 0; i
< const_state
->immediate_idx
; i
++) {
340 if (const_state
->immediates
[idx
].val
[swiz
] == reg
->uim_val
) {
345 if (i
== const_state
->immediate_idx
) {
346 /* need to generate a new immediate: */
350 /* Half constant registers seems to handle only 32-bit values
351 * within floating-point opcodes. So convert back to 32-bit values. */
352 if (f_opcode
&& (new_flags
& IR3_REG_HALF
)) {
353 reg
->uim_val
= fui(_mesa_half_to_float(reg
->uim_val
));
356 const_state
->immediates
[idx
].val
[swiz
] = reg
->uim_val
;
357 const_state
->immediates_count
= idx
+ 1;
358 const_state
->immediate_idx
++;
361 new_flags
&= ~IR3_REG_IMMED
;
362 new_flags
|= IR3_REG_CONST
;
363 reg
->flags
= new_flags
;
364 reg
->num
= i
+ (4 * const_state
->offsets
.immediate
);
370 unuse(struct ir3_instruction
*instr
)
372 debug_assert(instr
->use_count
> 0);
374 if (--instr
->use_count
== 0) {
375 struct ir3_block
*block
= instr
->block
;
377 instr
->barrier_class
= 0;
378 instr
->barrier_conflict
= 0;
380 /* we don't want to remove anything in keeps (which could
381 * be things like array store's)
383 for (unsigned i
= 0; i
< block
->keeps_count
; i
++) {
384 debug_assert(block
->keeps
[i
] != instr
);
390 * Handles the special case of the 2nd src (n == 1) to "normal" mad
391 * instructions, which cannot reference a constant. See if it is
392 * possible to swap the 1st and 2nd sources.
395 try_swap_mad_two_srcs(struct ir3_instruction
*instr
, unsigned new_flags
)
397 if (!is_mad(instr
->opc
))
400 /* NOTE: pre-swap first two src's before valid_flags(),
401 * which might try to dereference the n'th src:
403 swap(instr
->regs
[0 + 1], instr
->regs
[1 + 1]);
405 /* cat3 doesn't encode immediate, but we can lower immediate
406 * to const if that helps:
408 if (new_flags
& IR3_REG_IMMED
) {
409 new_flags
&= ~IR3_REG_IMMED
;
410 new_flags
|= IR3_REG_CONST
;
414 /* can we propagate mov if we move 2nd src to first? */
415 valid_flags(instr
, 0, new_flags
) &&
416 /* and does first src fit in second slot? */
417 valid_flags(instr
, 1, instr
->regs
[1 + 1]->flags
);
420 /* put things back the way they were: */
421 swap(instr
->regs
[0 + 1], instr
->regs
[1 + 1]);
422 } /* otherwise leave things swapped */
428 * Handle cp for a given src register. This additionally handles
429 * the cases of collapsing immedate/const (which replace the src
430 * register with a non-ssa src) or collapsing mov's from relative
431 * src (which needs to also fixup the address src reference by the
435 reg_cp(struct ir3_cp_ctx
*ctx
, struct ir3_instruction
*instr
,
436 struct ir3_register
*reg
, unsigned n
)
438 struct ir3_instruction
*src
= ssa(reg
);
440 if (is_eligible_mov(src
, instr
, true)) {
441 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */
442 struct ir3_register
*src_reg
= src
->regs
[1];
443 unsigned new_flags
= reg
->flags
;
445 combine_flags(&new_flags
, src
);
447 if (valid_flags(instr
, n
, new_flags
)) {
448 if (new_flags
& IR3_REG_ARRAY
) {
449 debug_assert(!(reg
->flags
& IR3_REG_ARRAY
));
450 reg
->array
= src_reg
->array
;
452 reg
->flags
= new_flags
;
453 reg
->instr
= ssa(src_reg
);
455 instr
->barrier_class
|= src
->barrier_class
;
456 instr
->barrier_conflict
|= src
->barrier_conflict
;
459 reg
->instr
->use_count
++;
463 } else if (is_same_type_mov(src
) &&
464 /* cannot collapse const/immed/etc into meta instrs: */
466 /* immed/const/etc cases, which require some special handling: */
467 struct ir3_register
*src_reg
= src
->regs
[1];
468 unsigned new_flags
= reg
->flags
;
470 combine_flags(&new_flags
, src
);
472 if (!valid_flags(instr
, n
, new_flags
)) {
473 /* See if lowering an immediate to const would help. */
474 if (valid_flags(instr
, n
, (new_flags
& ~IR3_REG_IMMED
) | IR3_REG_CONST
)) {
475 bool f_opcode
= (ir3_cat2_float(instr
->opc
) ||
476 ir3_cat3_float(instr
->opc
)) ? true : false;
478 debug_assert(new_flags
& IR3_REG_IMMED
);
480 instr
->regs
[n
+ 1] = lower_immed(ctx
, src_reg
, new_flags
, f_opcode
);
484 /* special case for "normal" mad instructions, we can
485 * try swapping the first two args if that fits better.
487 * the "plain" MAD's (ie. the ones that don't shift first
488 * src prior to multiply) can swap their first two srcs if
489 * src[0] is !CONST and src[1] is CONST:
491 if ((n
== 1) && try_swap_mad_two_srcs(instr
, new_flags
)) {
498 /* Here we handle the special case of mov from
499 * CONST and/or RELATIV. These need to be handled
500 * specially, because in the case of move from CONST
501 * there is no src ir3_instruction so we need to
502 * replace the ir3_register. And in the case of
503 * RELATIV we need to handle the address register
506 if (src_reg
->flags
& IR3_REG_CONST
) {
507 /* an instruction cannot reference two different
510 if ((src_reg
->flags
& IR3_REG_RELATIV
) &&
511 conflicts(instr
->address
, reg
->instr
->address
))
514 /* This seems to be a hw bug, or something where the timings
515 * just somehow don't work out. This restriction may only
516 * apply if the first src is also CONST.
518 if ((opc_cat(instr
->opc
) == 3) && (n
== 2) &&
519 (src_reg
->flags
& IR3_REG_RELATIV
) &&
520 (src_reg
->array
.offset
== 0))
523 src_reg
= ir3_reg_clone(instr
->block
->shader
, src_reg
);
524 src_reg
->flags
= new_flags
;
525 instr
->regs
[n
+1] = src_reg
;
527 if (src_reg
->flags
& IR3_REG_RELATIV
)
528 ir3_instr_set_address(instr
, reg
->instr
->address
);
533 if ((src_reg
->flags
& IR3_REG_RELATIV
) &&
534 !conflicts(instr
->address
, reg
->instr
->address
)) {
535 src_reg
= ir3_reg_clone(instr
->block
->shader
, src_reg
);
536 src_reg
->flags
= new_flags
;
537 instr
->regs
[n
+1] = src_reg
;
538 ir3_instr_set_address(instr
, reg
->instr
->address
);
543 /* NOTE: seems we can only do immed integers, so don't
544 * need to care about float. But we do need to handle
545 * abs/neg *before* checking that the immediate requires
546 * few enough bits to encode:
548 * TODO: do we need to do something to avoid accidentally
549 * catching a float immed?
551 if (src_reg
->flags
& IR3_REG_IMMED
) {
552 int32_t iim_val
= src_reg
->iim_val
;
554 debug_assert((opc_cat(instr
->opc
) == 1) ||
555 (opc_cat(instr
->opc
) == 6) ||
556 ir3_cat2_int(instr
->opc
) ||
557 (is_mad(instr
->opc
) && (n
== 0)));
559 if (new_flags
& IR3_REG_SABS
)
560 iim_val
= abs(iim_val
);
562 if (new_flags
& IR3_REG_SNEG
)
565 if (new_flags
& IR3_REG_BNOT
)
568 /* other than category 1 (mov) we can only encode up to 10 bits: */
569 if (valid_flags(instr
, n
, new_flags
) &&
570 ((instr
->opc
== OPC_MOV
) ||
571 !((iim_val
& ~0x3ff) && (-iim_val
& ~0x3ff)))) {
572 new_flags
&= ~(IR3_REG_SABS
| IR3_REG_SNEG
| IR3_REG_BNOT
);
573 src_reg
= ir3_reg_clone(instr
->block
->shader
, src_reg
);
574 src_reg
->flags
= new_flags
;
575 src_reg
->iim_val
= iim_val
;
576 instr
->regs
[n
+1] = src_reg
;
579 } else if (valid_flags(instr
, n
, (new_flags
& ~IR3_REG_IMMED
) | IR3_REG_CONST
)) {
580 bool f_opcode
= (ir3_cat2_float(instr
->opc
) ||
581 ir3_cat3_float(instr
->opc
)) ? true : false;
583 /* See if lowering an immediate to const would help. */
584 instr
->regs
[n
+1] = lower_immed(ctx
, src_reg
, new_flags
, f_opcode
);
594 /* Handle special case of eliminating output mov, and similar cases where
595 * there isn't a normal "consuming" instruction. In this case we cannot
596 * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
599 static struct ir3_instruction
*
600 eliminate_output_mov(struct ir3_instruction
*instr
)
602 if (is_eligible_mov(instr
, NULL
, false)) {
603 struct ir3_register
*reg
= instr
->regs
[1];
604 if (!(reg
->flags
& IR3_REG_ARRAY
)) {
605 struct ir3_instruction
*src_instr
= ssa(reg
);
606 debug_assert(src_instr
);
614 * Find instruction src's which are mov's that can be collapsed, replacing
615 * the mov dst with the mov src
618 instr_cp(struct ir3_cp_ctx
*ctx
, struct ir3_instruction
*instr
)
620 struct ir3_register
*reg
;
622 if (instr
->regs_count
== 0)
625 if (ir3_instr_check_mark(instr
))
628 /* walk down the graph from each src: */
632 foreach_src_n(reg
, n
, instr
) {
633 struct ir3_instruction
*src
= ssa(reg
);
640 /* TODO non-indirect access we could figure out which register
641 * we actually want and allow cp..
643 if (reg
->flags
& IR3_REG_ARRAY
)
646 /* Don't CP absneg into meta instructions, that won't end well: */
647 if (is_meta(instr
) && (src
->opc
!= OPC_MOV
))
650 progress
|= reg_cp(ctx
, instr
, reg
, n
);
654 if (instr
->regs
[0]->flags
& IR3_REG_ARRAY
) {
655 struct ir3_instruction
*src
= ssa(instr
->regs
[0]);
660 if (instr
->address
) {
661 instr_cp(ctx
, instr
->address
);
662 ir3_instr_set_address(instr
, eliminate_output_mov(instr
->address
));
665 /* we can end up with extra cmps.s from frontend, which uses a
667 * cmps.s p0.x, cond, 0
669 * as a way to mov into the predicate register. But frequently 'cond'
670 * is itself a cmps.s/cmps.f/cmps.u. So detect this special case and
671 * just re-write the instruction writing predicate register to get rid
672 * of the double cmps.
674 if ((instr
->opc
== OPC_CMPS_S
) &&
675 (instr
->regs
[0]->num
== regid(REG_P0
, 0)) &&
676 ssa(instr
->regs
[1]) &&
677 (instr
->regs
[2]->flags
& IR3_REG_IMMED
) &&
678 (instr
->regs
[2]->iim_val
== 0)) {
679 struct ir3_instruction
*cond
= ssa(instr
->regs
[1]);
684 instr
->opc
= cond
->opc
;
685 instr
->flags
= cond
->flags
;
686 instr
->cat2
= cond
->cat2
;
687 ir3_instr_set_address(instr
, cond
->address
);
688 instr
->regs
[1] = cond
->regs
[1];
689 instr
->regs
[2] = cond
->regs
[2];
690 instr
->barrier_class
|= cond
->barrier_class
;
691 instr
->barrier_conflict
|= cond
->barrier_conflict
;
699 /* Handle converting a sam.s2en (taking samp/tex idx params via
700 * register) into a normal sam (encoding immediate samp/tex idx)
701 * if they are immediate. This saves some instructions and regs
702 * in the common case where we know samp/tex at compile time:
704 if (is_tex(instr
) && (instr
->flags
& IR3_INSTR_S2EN
) &&
705 !(ir3_shader_debug
& IR3_DBG_FORCES2EN
)) {
706 /* The first src will be a fan-in (collect), if both of it's
707 * two sources are mov from imm, then we can
709 struct ir3_instruction
*samp_tex
= ssa(instr
->regs
[1]);
711 debug_assert(samp_tex
->opc
== OPC_META_FI
);
713 struct ir3_instruction
*samp
= ssa(samp_tex
->regs
[1]);
714 struct ir3_instruction
*tex
= ssa(samp_tex
->regs
[2]);
716 if ((samp
->opc
== OPC_MOV
) &&
717 (samp
->regs
[1]->flags
& IR3_REG_IMMED
) &&
718 (tex
->opc
== OPC_MOV
) &&
719 (tex
->regs
[1]->flags
& IR3_REG_IMMED
)) {
720 instr
->flags
&= ~IR3_INSTR_S2EN
;
721 instr
->cat5
.samp
= samp
->regs
[1]->iim_val
;
722 instr
->cat5
.tex
= tex
->regs
[1]->iim_val
;
723 instr
->regs
[1]->instr
= NULL
;
729 ir3_cp(struct ir3
*ir
, struct ir3_shader_variant
*so
)
731 struct ir3_cp_ctx ctx
= {
736 /* This is a bit annoying, and probably wouldn't be necessary if we
737 * tracked a reverse link from producing instruction to consumer.
738 * But we need to know when we've eliminated the last consumer of
739 * a mov, so we need to do a pass to first count consumers of a
742 list_for_each_entry (struct ir3_block
, block
, &ir
->block_list
, node
) {
743 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
744 struct ir3_instruction
*src
;
746 /* by the way, we don't account for false-dep's, so the CP
747 * pass should always happen before false-dep's are inserted
749 debug_assert(instr
->deps_count
== 0);
751 foreach_ssa_src(src
, instr
) {
759 for (unsigned i
= 0; i
< ir
->noutputs
; i
++) {
760 if (ir
->outputs
[i
]) {
761 instr_cp(&ctx
, ir
->outputs
[i
]);
762 ir
->outputs
[i
] = eliminate_output_mov(ir
->outputs
[i
]);
766 list_for_each_entry (struct ir3_block
, block
, &ir
->block_list
, node
) {
767 if (block
->condition
) {
768 instr_cp(&ctx
, block
->condition
);
769 block
->condition
= eliminate_output_mov(block
->condition
);
772 for (unsigned i
= 0; i
< block
->keeps_count
; i
++) {
773 instr_cp(&ctx
, block
->keeps
[i
]);
774 block
->keeps
[i
] = eliminate_output_mov(block
->keeps
[i
]);