src/freedreno/ir3/ir3_cp.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include <math.h>
  28 #include "util/half_float.h"
  29 #include "util/u_math.h"
  30
  31 #include "ir3.h"
  32 #include "ir3_compiler.h"
  33 #include "ir3_shader.h"
  34
  35 #define swap(a, b) \
  36         do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
  37
  38 /*
  39  * Copy Propagate:
  40  */
  41
  42 struct ir3_cp_ctx {
  43         struct ir3 *shader;
  44         struct ir3_shader_variant *so;
  45 };
  46
  47 /* is it a type preserving mov, with ok flags?
  48  *
  49  * @instr: the mov to consider removing
  50  * @dst_instr: the instruction consuming the mov (instr)
  51  *
  52  * TODO maybe drop allow_flags since this is only false when dst is
  53  * NULL (ie. outputs)
  54  */
  55 static bool is_eligible_mov(struct ir3_instruction *instr,
  56                 struct ir3_instruction *dst_instr, bool allow_flags)
  57 {
  58         if (is_same_type_mov(instr)) {
  59                 struct ir3_register *dst = instr->regs[0];
  60                 struct ir3_register *src = instr->regs[1];
  61                 struct ir3_instruction *src_instr = ssa(src);
  62
  63                 /* only if mov src is SSA (not const/immed): */
  64                 if (!src_instr)
  65                         return false;
  66
  67                 /* no indirect: */
  68                 if (dst->flags & IR3_REG_RELATIV)
  69                         return false;
  70                 if (src->flags & IR3_REG_RELATIV)
  71                         return false;
  72
  73                 if (src->flags & IR3_REG_ARRAY)
  74                         return false;
  75
  76                 if (!allow_flags)
  77                         if (src->flags & (IR3_REG_FABS | IR3_REG_FNEG |
  78                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
  79                                 return false;
  80
  81                 /* If src is coming from fanout/split (ie. one component of a
  82                  * texture fetch, etc) and we have constraints on swizzle of
  83                  * destination, then skip it.
  84                  *
  85                  * We could possibly do a bit better, and copy-propagation if
  86                  * we can CP all components that are being fanned out.
  87                  */
  88                 if (src_instr->opc == OPC_META_FO) {
  89                         if (!dst_instr)
  90                                 return false;
  91                         if (dst_instr->opc == OPC_META_FI)
  92                                 return false;
  93                         if (dst_instr->cp.left || dst_instr->cp.right)
  94                                 return false;
  95                 }
  96
  97                 return true;
  98         }
  99         return false;
 100 }
 101
 102 static unsigned cp_flags(unsigned flags)
 103 {
 104         /* only considering these flags (at least for now): */
 105         flags &= (IR3_REG_CONST | IR3_REG_IMMED |
 106                         IR3_REG_FNEG | IR3_REG_FABS |
 107                         IR3_REG_SNEG | IR3_REG_SABS |
 108                         IR3_REG_BNOT | IR3_REG_RELATIV);
 109         return flags;
 110 }
 111
 112 static bool valid_flags(struct ir3_instruction *instr, unsigned n,
 113                 unsigned flags)
 114 {
 115         struct ir3_compiler *compiler = instr->block->shader->compiler;
 116         unsigned valid_flags;
 117
 118         if ((flags & IR3_REG_HIGH) &&
 119                         (opc_cat(instr->opc) > 1) &&
 120                         (compiler->gpu_id >= 600))
 121                 return false;
 122
 123         flags = cp_flags(flags);
 124
 125         /* If destination is indirect, then source cannot be.. at least
 126          * I don't think so..
 127          */
 128         if ((instr->regs[0]->flags & IR3_REG_RELATIV) &&
 129                         (flags & IR3_REG_RELATIV))
 130                 return false;
 131
 132         if (flags & IR3_REG_RELATIV) {
 133                 /* TODO need to test on earlier gens.. pretty sure the earlier
 134                  * problem was just that we didn't check that the src was from
 135                  * same block (since we can't propagate address register values
 136                  * across blocks currently)
 137                  */
 138                 if (compiler->gpu_id < 600)
 139                         return false;
 140
 141                 /* NOTE in the special try_swap_mad_two_srcs() case we can be
 142                  * called on a src that has already had an indirect load folded
 143                  * in, in which case ssa() returns NULL
 144                  */
 145                 struct ir3_instruction *src = ssa(instr->regs[n+1]);
 146                 if (src && src->address->block != instr->block)
 147                         return false;
 148         }
 149
 150         switch (opc_cat(instr->opc)) {
 151         case 1:
 152                 valid_flags = IR3_REG_IMMED | IR3_REG_CONST | IR3_REG_RELATIV;
 153                 if (flags & ~valid_flags)
 154                         return false;
 155                 break;
 156         case 2:
 157                 valid_flags = ir3_cat2_absneg(instr->opc) |
 158                                 IR3_REG_CONST | IR3_REG_RELATIV;
 159
 160                 if (ir3_cat2_int(instr->opc))
 161                         valid_flags |= IR3_REG_IMMED;
 162
 163                 if (flags & ~valid_flags)
 164                         return false;
 165
 166                 if (flags & (IR3_REG_CONST | IR3_REG_IMMED)) {
 167                         unsigned m = (n ^ 1) + 1;
 168                         /* cannot deal w/ const in both srcs:
 169                          * (note that some cat2 actually only have a single src)
 170                          */
 171                         if (m < instr->regs_count) {
 172                                 struct ir3_register *reg = instr->regs[m];
 173                                 if ((flags & IR3_REG_CONST) && (reg->flags & IR3_REG_CONST))
 174                                         return false;
 175                                 if ((flags & IR3_REG_IMMED) && (reg->flags & IR3_REG_IMMED))
 176                                         return false;
 177                         }
 178                         /* cannot be const + ABS|NEG: */
 179                         if (flags & (IR3_REG_FABS | IR3_REG_FNEG |
 180                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
 181                                 return false;
 182                 }
 183                 break;
 184         case 3:
 185                 valid_flags = ir3_cat3_absneg(instr->opc) |
 186                                 IR3_REG_CONST | IR3_REG_RELATIV;
 187
 188                 if (flags & ~valid_flags)
 189                         return false;
 190
 191                 if (flags & (IR3_REG_CONST | IR3_REG_RELATIV)) {
 192                         /* cannot deal w/ const/relativ in 2nd src: */
 193                         if (n == 1)
 194                                 return false;
 195                 }
 196
 197                 if (flags & IR3_REG_CONST) {
 198                         /* cannot be const + ABS|NEG: */
 199                         if (flags & (IR3_REG_FABS | IR3_REG_FNEG |
 200                                         IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
 201                                 return false;
 202                 }
 203                 break;
 204         case 4:
 205                 /* seems like blob compiler avoids const as src.. */
 206                 /* TODO double check if this is still the case on a4xx */
 207                 if (flags & (IR3_REG_CONST | IR3_REG_IMMED))
 208                         return false;
 209                 if (flags & (IR3_REG_SABS | IR3_REG_SNEG))
 210                         return false;
 211                 break;
 212         case 5:
 213                 /* no flags allowed */
 214                 if (flags)
 215                         return false;
 216                 break;
 217         case 6:
 218                 valid_flags = IR3_REG_IMMED;
 219                 if (flags & ~valid_flags)
 220                         return false;
 221
 222                 if (flags & IR3_REG_IMMED) {
 223                         /* doesn't seem like we can have immediate src for store
 224                          * instructions:
 225                          *
 226                          * TODO this restriction could also apply to load instructions,
 227                          * but for load instructions this arg is the address (and not
 228                          * really sure any good way to test a hard-coded immed addr src)
 229                          */
 230                         if (is_store(instr) && (n == 1))
 231                                 return false;
 232
 233                         if ((instr->opc == OPC_LDL) && (n == 0))
 234                                 return false;
 235
 236                         if ((instr->opc == OPC_STL) && (n != 2))
 237                                 return false;
 238
 239                         if (instr->opc == OPC_STLW && n == 0)
 240                                 return false;
 241
 242                         /* disallow CP into anything but the SSBO slot argument for
 243                          * atomics:
 244                          */
 245                         if (is_atomic(instr->opc) && (n != 0))
 246                                 return false;
 247
 248                         if (is_atomic(instr->opc) && !(instr->flags & IR3_INSTR_G))
 249                                 return false;
 250
 251                         /* as with atomics, ldib on a6xx can only have immediate for
 252                          * SSBO slot argument
 253                          */
 254                         if ((instr->opc == OPC_LDIB) && (n != 0))
 255                                 return false;
 256                 }
 257
 258                 break;
 259         }
 260
 261         return true;
 262 }
 263
 264 /* propagate register flags from src to dst.. negates need special
 265  * handling to cancel each other out.
 266  */
 267 static void combine_flags(unsigned *dstflags, struct ir3_instruction *src)
 268 {
 269         unsigned srcflags = src->regs[1]->flags;
 270
 271         /* if what we are combining into already has (abs) flags,
 272          * we can drop (neg) from src:
 273          */
 274         if (*dstflags & IR3_REG_FABS)
 275                 srcflags &= ~IR3_REG_FNEG;
 276         if (*dstflags & IR3_REG_SABS)
 277                 srcflags &= ~IR3_REG_SNEG;
 278
 279         if (srcflags & IR3_REG_FABS)
 280                 *dstflags |= IR3_REG_FABS;
 281         if (srcflags & IR3_REG_SABS)
 282                 *dstflags |= IR3_REG_SABS;
 283         if (srcflags & IR3_REG_FNEG)
 284                 *dstflags ^= IR3_REG_FNEG;
 285         if (srcflags & IR3_REG_SNEG)
 286                 *dstflags ^= IR3_REG_SNEG;
 287         if (srcflags & IR3_REG_BNOT)
 288                 *dstflags ^= IR3_REG_BNOT;
 289
 290         *dstflags &= ~IR3_REG_SSA;
 291         *dstflags |= srcflags & IR3_REG_SSA;
 292         *dstflags |= srcflags & IR3_REG_CONST;
 293         *dstflags |= srcflags & IR3_REG_IMMED;
 294         *dstflags |= srcflags & IR3_REG_RELATIV;
 295         *dstflags |= srcflags & IR3_REG_ARRAY;
 296         *dstflags |= srcflags & IR3_REG_HIGH;
 297
 298         /* if src of the src is boolean we can drop the (abs) since we know
 299          * the source value is already a postitive integer.  This cleans
 300          * up the absnegs that get inserted when converting between nir and
 301          * native boolean (see ir3_b2n/n2b)
 302          */
 303         struct ir3_instruction *srcsrc = ssa(src->regs[1]);
 304         if (srcsrc && is_bool(srcsrc))
 305                 *dstflags &= ~IR3_REG_SABS;
 306 }
 307
 308 static struct ir3_register *
 309 lower_immed(struct ir3_cp_ctx *ctx, struct ir3_register *reg, unsigned new_flags, bool f_opcode)
 310 {
 311         unsigned swiz, idx, i;
 312
 313         reg = ir3_reg_clone(ctx->shader, reg);
 314
 315         /* in some cases, there are restrictions on (abs)/(neg) plus const..
 316          * so just evaluate those and clear the flags:
 317          */
 318         if (new_flags & IR3_REG_SABS) {
 319                 reg->iim_val = abs(reg->iim_val);
 320                 new_flags &= ~IR3_REG_SABS;
 321         }
 322
 323         if (new_flags & IR3_REG_FABS) {
 324                 reg->fim_val = fabs(reg->fim_val);
 325                 new_flags &= ~IR3_REG_FABS;
 326         }
 327
 328         if (new_flags & IR3_REG_SNEG) {
 329                 reg->iim_val = -reg->iim_val;
 330                 new_flags &= ~IR3_REG_SNEG;
 331         }
 332
 333         if (new_flags & IR3_REG_FNEG) {
 334                 reg->fim_val = -reg->fim_val;
 335                 new_flags &= ~IR3_REG_FNEG;
 336         }
 337
 338         /* Reallocate for 4 more elements whenever it's necessary */
 339         struct ir3_const_state *const_state = &ctx->so->shader->const_state;
 340         if (const_state->immediate_idx == const_state->immediates_size * 4) {
 341                 const_state->immediates_size += 4;
 342                 const_state->immediates = realloc (const_state->immediates,
 343                         const_state->immediates_size * sizeof(const_state->immediates[0]));
 344         }
 345
 346         for (i = 0; i < const_state->immediate_idx; i++) {
 347                 swiz = i % 4;
 348                 idx  = i / 4;
 349
 350                 if (const_state->immediates[idx].val[swiz] == reg->uim_val) {
 351                         break;
 352                 }
 353         }
 354
 355         if (i == const_state->immediate_idx) {
 356                 /* need to generate a new immediate: */
 357                 swiz = i % 4;
 358                 idx  = i / 4;
 359
 360                 /* Half constant registers seems to handle only 32-bit values
 361                  * within floating-point opcodes. So convert back to 32-bit values. */
 362                 if (f_opcode && (new_flags & IR3_REG_HALF)) {
 363                         reg->uim_val = fui(_mesa_half_to_float(reg->uim_val));
 364                 }
 365
 366                 const_state->immediates[idx].val[swiz] = reg->uim_val;
 367                 const_state->immediates_count = idx + 1;
 368                 const_state->immediate_idx++;
 369         }
 370
 371         new_flags &= ~IR3_REG_IMMED;
 372         new_flags |= IR3_REG_CONST;
 373         reg->flags = new_flags;
 374         reg->num = i + (4 * const_state->offsets.immediate);
 375
 376         return reg;
 377 }
 378
 379 static void
 380 unuse(struct ir3_instruction *instr)
 381 {
 382         debug_assert(instr->use_count > 0);
 383
 384         if (--instr->use_count == 0) {
 385                 struct ir3_block *block = instr->block;
 386
 387                 instr->barrier_class = 0;
 388                 instr->barrier_conflict = 0;
 389
 390                 /* we don't want to remove anything in keeps (which could
 391                  * be things like array store's)
 392                  */
 393                 for (unsigned i = 0; i < block->keeps_count; i++) {
 394                         debug_assert(block->keeps[i] != instr);
 395                 }
 396         }
 397 }
 398
 399 /**
 400  * Handles the special case of the 2nd src (n == 1) to "normal" mad
 401  * instructions, which cannot reference a constant.  See if it is
 402  * possible to swap the 1st and 2nd sources.
 403  */
 404 static bool
 405 try_swap_mad_two_srcs(struct ir3_instruction *instr, unsigned new_flags)
 406 {
 407         if (!is_mad(instr->opc))
 408                 return false;
 409
 410         /* NOTE: pre-swap first two src's before valid_flags(),
 411          * which might try to dereference the n'th src:
 412          */
 413         swap(instr->regs[0 + 1], instr->regs[1 + 1]);
 414
 415         /* cat3 doesn't encode immediate, but we can lower immediate
 416          * to const if that helps:
 417          */
 418         if (new_flags & IR3_REG_IMMED) {
 419                 new_flags &= ~IR3_REG_IMMED;
 420                 new_flags |=  IR3_REG_CONST;
 421         }
 422
 423         bool valid_swap =
 424                 /* can we propagate mov if we move 2nd src to first? */
 425                 valid_flags(instr, 0, new_flags) &&
 426                 /* and does first src fit in second slot? */
 427                 valid_flags(instr, 1, instr->regs[1 + 1]->flags);
 428
 429         if (!valid_swap) {
 430                 /* put things back the way they were: */
 431                 swap(instr->regs[0 + 1], instr->regs[1 + 1]);
 432         }   /* otherwise leave things swapped */
 433
 434         return valid_swap;
 435 }
 436
 437 /**
 438  * Handle cp for a given src register.  This additionally handles
 439  * the cases of collapsing immedate/const (which replace the src
 440  * register with a non-ssa src) or collapsing mov's from relative
 441  * src (which needs to also fixup the address src reference by the
 442  * instruction).
 443  */
 444 static void
 445 reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr,
 446                 struct ir3_register *reg, unsigned n)
 447 {
 448         struct ir3_instruction *src = ssa(reg);
 449
 450         if (is_eligible_mov(src, instr, true)) {
 451                 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */
 452                 struct ir3_register *src_reg = src->regs[1];
 453                 unsigned new_flags = reg->flags;
 454
 455                 combine_flags(&new_flags, src);
 456
 457                 if (valid_flags(instr, n, new_flags)) {
 458                         if (new_flags & IR3_REG_ARRAY) {
 459                                 debug_assert(!(reg->flags & IR3_REG_ARRAY));
 460                                 reg->array = src_reg->array;
 461                         }
 462                         reg->flags = new_flags;
 463                         reg->instr = ssa(src_reg);
 464
 465                         instr->barrier_class |= src->barrier_class;
 466                         instr->barrier_conflict |= src->barrier_conflict;
 467
 468                         unuse(src);
 469                         reg->instr->use_count++;
 470                 }
 471
 472         } else if (is_same_type_mov(src) &&
 473                         /* cannot collapse const/immed/etc into meta instrs: */
 474                         !is_meta(instr)) {
 475                 /* immed/const/etc cases, which require some special handling: */
 476                 struct ir3_register *src_reg = src->regs[1];
 477                 unsigned new_flags = reg->flags;
 478
 479                 combine_flags(&new_flags, src);
 480
 481                 if (!valid_flags(instr, n, new_flags)) {
 482                         /* See if lowering an immediate to const would help. */
 483                         if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) {
 484                                 bool f_opcode = (ir3_cat2_float(instr->opc) ||
 485                                                 ir3_cat3_float(instr->opc)) ? true : false;
 486
 487                                 debug_assert(new_flags & IR3_REG_IMMED);
 488
 489                                 instr->regs[n + 1] = lower_immed(ctx, src_reg, new_flags, f_opcode);
 490                                 return;
 491                         }
 492
 493                         /* special case for "normal" mad instructions, we can
 494                          * try swapping the first two args if that fits better.
 495                          *
 496                          * the "plain" MAD's (ie. the ones that don't shift first
 497                          * src prior to multiply) can swap their first two srcs if
 498                          * src[0] is !CONST and src[1] is CONST:
 499                          */
 500                         if ((n == 1) && try_swap_mad_two_srcs(instr, new_flags)) {
 501                                 /* we swapped, so now we are dealing with 1st src: */
 502                                 n = 0;
 503                         } else {
 504                                 return;
 505                         }
 506                 }
 507
 508                 /* Here we handle the special case of mov from
 509                  * CONST and/or RELATIV.  These need to be handled
 510                  * specially, because in the case of move from CONST
 511                  * there is no src ir3_instruction so we need to
 512                  * replace the ir3_register.  And in the case of
 513                  * RELATIV we need to handle the address register
 514                  * dependency.
 515                  */
 516                 if (src_reg->flags & IR3_REG_CONST) {
 517                         /* an instruction cannot reference two different
 518                          * address registers:
 519                          */
 520                         if ((src_reg->flags & IR3_REG_RELATIV) &&
 521                                         conflicts(instr->address, reg->instr->address))
 522                                 return;
 523
 524                         /* This seems to be a hw bug, or something where the timings
 525                          * just somehow don't work out.  This restriction may only
 526                          * apply if the first src is also CONST.
 527                          */
 528                         if ((opc_cat(instr->opc) == 3) && (n == 2) &&
 529                                         (src_reg->flags & IR3_REG_RELATIV) &&
 530                                         (src_reg->array.offset == 0))
 531                                 return;
 532
 533                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 534                         src_reg->flags = new_flags;
 535                         instr->regs[n+1] = src_reg;
 536
 537                         if (src_reg->flags & IR3_REG_RELATIV)
 538                                 ir3_instr_set_address(instr, reg->instr->address);
 539
 540                         return;
 541                 }
 542
 543                 if ((src_reg->flags & IR3_REG_RELATIV) &&
 544                                 !conflicts(instr->address, reg->instr->address)) {
 545                         src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 546                         src_reg->flags = new_flags;
 547                         instr->regs[n+1] = src_reg;
 548                         ir3_instr_set_address(instr, reg->instr->address);
 549
 550                         return;
 551                 }
 552
 553                 /* NOTE: seems we can only do immed integers, so don't
 554                  * need to care about float.  But we do need to handle
 555                  * abs/neg *before* checking that the immediate requires
 556                  * few enough bits to encode:
 557                  *
 558                  * TODO: do we need to do something to avoid accidentally
 559                  * catching a float immed?
 560                  */
 561                 if (src_reg->flags & IR3_REG_IMMED) {
 562                         int32_t iim_val = src_reg->iim_val;
 563
 564                         debug_assert((opc_cat(instr->opc) == 1) ||
 565                                         (opc_cat(instr->opc) == 6) ||
 566                                         ir3_cat2_int(instr->opc) ||
 567                                         (is_mad(instr->opc) && (n == 0)));
 568
 569                         if (new_flags & IR3_REG_SABS)
 570                                 iim_val = abs(iim_val);
 571
 572                         if (new_flags & IR3_REG_SNEG)
 573                                 iim_val = -iim_val;
 574
 575                         if (new_flags & IR3_REG_BNOT)
 576                                 iim_val = ~iim_val;
 577
 578                         /* other than category 1 (mov) we can only encode up to 10 bits: */
 579                         if (valid_flags(instr, n, new_flags) &&
 580                                         ((instr->opc == OPC_MOV) ||
 581                                          !((iim_val & ~0x3ff) && (-iim_val & ~0x3ff)))) {
 582                                 new_flags &= ~(IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT);
 583                                 src_reg = ir3_reg_clone(instr->block->shader, src_reg);
 584                                 src_reg->flags = new_flags;
 585                                 src_reg->iim_val = iim_val;
 586                                 instr->regs[n+1] = src_reg;
 587                         } else if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) {
 588                                 bool f_opcode = (ir3_cat2_float(instr->opc) ||
 589                                                 ir3_cat3_float(instr->opc)) ? true : false;
 590
 591                                 /* See if lowering an immediate to const would help. */
 592                                 instr->regs[n+1] = lower_immed(ctx, src_reg, new_flags, f_opcode);
 593                         }
 594                         return;
 595                 }
 596         }
 597 }
 598
 599 /* Handle special case of eliminating output mov, and similar cases where
 600  * there isn't a normal "consuming" instruction.  In this case we cannot
 601  * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
 602  * be eliminated)
 603  */
 604 static struct ir3_instruction *
 605 eliminate_output_mov(struct ir3_instruction *instr)
 606 {
 607         if (is_eligible_mov(instr, NULL, false)) {
 608                 struct ir3_register *reg = instr->regs[1];
 609                 if (!(reg->flags & IR3_REG_ARRAY)) {
 610                         struct ir3_instruction *src_instr = ssa(reg);
 611                         debug_assert(src_instr);
 612                         return src_instr;
 613                 }
 614         }
 615         return instr;
 616 }
 617
 618 /**
 619  * Find instruction src's which are mov's that can be collapsed, replacing
 620  * the mov dst with the mov src
 621  */
 622 static void
 623 instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
 624 {
 625         struct ir3_register *reg;
 626
 627         if (instr->regs_count == 0)
 628                 return;
 629
 630         if (ir3_instr_check_mark(instr))
 631                 return;
 632
 633         /* walk down the graph from each src: */
 634         foreach_src_n(reg, n, instr) {
 635                 struct ir3_instruction *src = ssa(reg);
 636
 637                 if (!src)
 638                         continue;
 639
 640                 instr_cp(ctx, src);
 641
 642                 /* TODO non-indirect access we could figure out which register
 643                  * we actually want and allow cp..
 644                  */
 645                 if (reg->flags & IR3_REG_ARRAY)
 646                         continue;
 647
 648                 /* Don't CP absneg into meta instructions, that won't end well: */
 649                 if (is_meta(instr) && (src->opc != OPC_MOV))
 650                         continue;
 651
 652                 reg_cp(ctx, instr, reg, n);
 653         }
 654
 655         if (instr->regs[0]->flags & IR3_REG_ARRAY) {
 656                 struct ir3_instruction *src = ssa(instr->regs[0]);
 657                 if (src)
 658                         instr_cp(ctx, src);
 659         }
 660
 661         if (instr->address) {
 662                 instr_cp(ctx, instr->address);
 663                 ir3_instr_set_address(instr, eliminate_output_mov(instr->address));
 664         }
 665
 666         /* we can end up with extra cmps.s from frontend, which uses a
 667          *
 668          *    cmps.s p0.x, cond, 0
 669          *
 670          * as a way to mov into the predicate register.  But frequently 'cond'
 671          * is itself a cmps.s/cmps.f/cmps.u.  So detect this special case and
 672          * just re-write the instruction writing predicate register to get rid
 673          * of the double cmps.
 674          */
 675         if ((instr->opc == OPC_CMPS_S) &&
 676                         (instr->regs[0]->num == regid(REG_P0, 0)) &&
 677                         ssa(instr->regs[1]) &&
 678                         (instr->regs[2]->flags & IR3_REG_IMMED) &&
 679                         (instr->regs[2]->iim_val == 0)) {
 680                 struct ir3_instruction *cond = ssa(instr->regs[1]);
 681                 switch (cond->opc) {
 682                 case OPC_CMPS_S:
 683                 case OPC_CMPS_F:
 684                 case OPC_CMPS_U:
 685                         instr->opc   = cond->opc;
 686                         instr->flags = cond->flags;
 687                         instr->cat2  = cond->cat2;
 688                         ir3_instr_set_address(instr, cond->address);
 689                         instr->regs[1] = cond->regs[1];
 690                         instr->regs[2] = cond->regs[2];
 691                         instr->barrier_class |= cond->barrier_class;
 692                         instr->barrier_conflict |= cond->barrier_conflict;
 693                         unuse(cond);
 694                         break;
 695                 default:
 696                         break;
 697                 }
 698         }
 699
 700         /* Handle converting a sam.s2en (taking samp/tex idx params via
 701          * register) into a normal sam (encoding immediate samp/tex idx)
 702          * if they are immediate.  This saves some instructions and regs
 703          * in the common case where we know samp/tex at compile time:
 704          */
 705         if (is_tex(instr) && (instr->flags & IR3_INSTR_S2EN) &&
 706                         !(ir3_shader_debug & IR3_DBG_FORCES2EN)) {
 707                 /* The first src will be a fan-in (collect), if both of it's
 708                  * two sources are mov from imm, then we can
 709                  */
 710                 struct ir3_instruction *samp_tex = ssa(instr->regs[1]);
 711
 712                 debug_assert(samp_tex->opc == OPC_META_FI);
 713
 714                 struct ir3_instruction *samp = ssa(samp_tex->regs[1]);
 715                 struct ir3_instruction *tex  = ssa(samp_tex->regs[2]);
 716
 717                 if ((samp->opc == OPC_MOV) &&
 718                                 (samp->regs[1]->flags & IR3_REG_IMMED) &&
 719                                 (tex->opc == OPC_MOV) &&
 720                                 (tex->regs[1]->flags & IR3_REG_IMMED)) {
 721                         instr->flags &= ~IR3_INSTR_S2EN;
 722                         instr->cat5.samp = samp->regs[1]->iim_val;
 723                         instr->cat5.tex  = tex->regs[1]->iim_val;
 724                         instr->regs[1]->instr = NULL;
 725                 }
 726         }
 727 }
 728
 729 void
 730 ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so)
 731 {
 732         struct ir3_cp_ctx ctx = {
 733                         .shader = ir,
 734                         .so = so,
 735         };
 736
 737         /* This is a bit annoying, and probably wouldn't be necessary if we
 738          * tracked a reverse link from producing instruction to consumer.
 739          * But we need to know when we've eliminated the last consumer of
 740          * a mov, so we need to do a pass to first count consumers of a
 741          * mov.
 742          */
 743         list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
 744                 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
 745                         struct ir3_instruction *src;
 746
 747                         /* by the way, we don't account for false-dep's, so the CP
 748                          * pass should always happen before false-dep's are inserted
 749                          */
 750                         debug_assert(instr->deps_count == 0);
 751
 752                         foreach_ssa_src(src, instr) {
 753                                 src->use_count++;
 754                         }
 755                 }
 756         }
 757
 758         ir3_clear_mark(ir);
 759
 760         for (unsigned i = 0; i < ir->noutputs; i++) {
 761                 if (ir->outputs[i]) {
 762                         instr_cp(&ctx, ir->outputs[i]);
 763                         ir->outputs[i] = eliminate_output_mov(ir->outputs[i]);
 764                 }
 765         }
 766
 767         list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
 768                 if (block->condition) {
 769                         instr_cp(&ctx, block->condition);
 770                         block->condition = eliminate_output_mov(block->condition);
 771                 }
 772
 773                 for (unsigned i = 0; i < block->keeps_count; i++) {
 774                         instr_cp(&ctx, block->keeps[i]);
 775                         block->keeps[i] = eliminate_output_mov(block->keeps[i]);
 776                 }
 777         }
 778 }