src/freedreno/ir3/ir3_legalize.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "util/ralloc.h"
  28 #include "util/u_math.h"
  29
  30 #include "ir3.h"
  31 #include "ir3_compiler.h"
  32
  33 /*
  34  * Legalize:
  35  *
  36  * We currently require that scheduling ensures that we have enough nop's
  37  * in all the right places.  The legalize step mostly handles fixing up
  38  * instruction flags ((ss)/(sy)/(ei)), and collapses sequences of nop's
  39  * into fewer nop's w/ rpt flag.
  40  */
  41
  42 struct ir3_legalize_ctx {
  43         struct ir3_compiler *compiler;
  44         gl_shader_stage type;
  45         bool has_ssbo;
  46         bool need_pixlod;
  47         int max_bary;
  48 };
  49
  50 struct ir3_legalize_state {
  51         regmask_t needs_ss;
  52         regmask_t needs_ss_war;       /* write after read */
  53         regmask_t needs_sy;
  54 };
  55
  56 struct ir3_legalize_block_data {
  57         bool valid;
  58         struct ir3_legalize_state state;
  59 };
  60
  61 /* We want to evaluate each block from the position of any other
  62  * predecessor block, in order that the flags set are the union of
  63  * all possible program paths.
  64  *
  65  * To do this, we need to know the output state (needs_ss/ss_war/sy)
  66  * of all predecessor blocks.  The tricky thing is loops, which mean
  67  * that we can't simply recursively process each predecessor block
  68  * before legalizing the current block.
  69  *
  70  * How we handle that is by looping over all the blocks until the
  71  * results converge.  If the output state of a given block changes
  72  * in a given pass, this means that all successor blocks are not
  73  * yet fully legalized.
  74  */
  75
  76 static bool
  77 legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
  78 {
  79         struct ir3_legalize_block_data *bd = block->data;
  80
  81         if (bd->valid)
  82                 return false;
  83
  84         struct ir3_instruction *last_input = NULL;
  85         struct ir3_instruction *last_rel = NULL;
  86         struct ir3_instruction *last_n = NULL;
  87         struct list_head instr_list;
  88         struct ir3_legalize_state prev_state = bd->state;
  89         struct ir3_legalize_state *state = &bd->state;
  90         bool last_input_needs_ss = false;
  91         bool has_tex_prefetch = false;
  92
  93         /* our input state is the OR of all predecessor blocks' state: */
  94         set_foreach(block->predecessors, entry) {
  95                 struct ir3_block *predecessor = (struct ir3_block *)entry->key;
  96                 struct ir3_legalize_block_data *pbd = predecessor->data;
  97                 struct ir3_legalize_state *pstate = &pbd->state;
  98
  99                 /* Our input (ss)/(sy) state is based on OR'ing the output
 100                  * state of all our predecessor blocks
 101                  */
 102                 regmask_or(&state->needs_ss,
 103                                 &state->needs_ss, &pstate->needs_ss);
 104                 regmask_or(&state->needs_ss_war,
 105                                 &state->needs_ss_war, &pstate->needs_ss_war);
 106                 regmask_or(&state->needs_sy,
 107                                 &state->needs_sy, &pstate->needs_sy);
 108         }
 109
 110         /* remove all the instructions from the list, we'll be adding
 111          * them back in as we go
 112          */
 113         list_replace(&block->instr_list, &instr_list);
 114         list_inithead(&block->instr_list);
 115
 116         list_for_each_entry_safe (struct ir3_instruction, n, &instr_list, node) {
 117                 struct ir3_register *reg;
 118                 unsigned i;
 119
 120                 n->flags &= ~(IR3_INSTR_SS | IR3_INSTR_SY);
 121
 122                 /* _meta::tex_prefetch instructions removed later in
 123                  * collect_tex_prefetches()
 124                  */
 125                 if (is_meta(n) && (n->opc != OPC_META_TEX_PREFETCH))
 126                         continue;
 127
 128                 if (is_input(n)) {
 129                         struct ir3_register *inloc = n->regs[1];
 130                         assert(inloc->flags & IR3_REG_IMMED);
 131                         ctx->max_bary = MAX2(ctx->max_bary, inloc->iim_val);
 132                 }
 133
 134                 if (last_n && is_barrier(last_n)) {
 135                         n->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
 136                         last_input_needs_ss = false;
 137                 }
 138
 139                 if (last_n && opc_cat(last_n->opc) == 0 && opc_op(last_n->opc) == 13)
 140                         n->flags |= IR3_INSTR_SS;
 141
 142                 /* NOTE: consider dst register too.. it could happen that
 143                  * texture sample instruction (for example) writes some
 144                  * components which are unused.  A subsequent instruction
 145                  * that writes the same register can race w/ the sam instr
 146                  * resulting in undefined results:
 147                  */
 148                 for (i = 0; i < n->regs_count; i++) {
 149                         reg = n->regs[i];
 150
 151                         if (reg_gpr(reg)) {
 152
 153                                 /* TODO: we probably only need (ss) for alu
 154                                  * instr consuming sfu result.. need to make
 155                                  * some tests for both this and (sy)..
 156                                  */
 157                                 if (regmask_get(&state->needs_ss, reg)) {
 158                                         n->flags |= IR3_INSTR_SS;
 159                                         last_input_needs_ss = false;
 160                                         regmask_init(&state->needs_ss_war);
 161                                         regmask_init(&state->needs_ss);
 162                                 }
 163
 164                                 if (regmask_get(&state->needs_sy, reg)) {
 165                                         n->flags |= IR3_INSTR_SY;
 166                                         regmask_init(&state->needs_sy);
 167                                 }
 168                         }
 169
 170                         /* TODO: is it valid to have address reg loaded from a
 171                          * relative src (ie. mova a0, c<a0.x+4>)?  If so, the
 172                          * last_rel check below should be moved ahead of this:
 173                          */
 174                         if (reg->flags & IR3_REG_RELATIV)
 175                                 last_rel = n;
 176                 }
 177
 178                 if (n->regs_count > 0) {
 179                         reg = n->regs[0];
 180                         if (regmask_get(&state->needs_ss_war, reg)) {
 181                                 n->flags |= IR3_INSTR_SS;
 182                                 last_input_needs_ss = false;
 183                                 regmask_init(&state->needs_ss_war);
 184                                 regmask_init(&state->needs_ss);
 185                         }
 186
 187                         if (last_rel && (reg->num == regid(REG_A0, 0))) {
 188                                 last_rel->flags |= IR3_INSTR_UL;
 189                                 last_rel = NULL;
 190                         }
 191                 }
 192
 193                 /* cat5+ does not have an (ss) bit, if needed we need to
 194                  * insert a nop to carry the sync flag.  Would be kinda
 195                  * clever if we were aware of this during scheduling, but
 196                  * this should be a pretty rare case:
 197                  */
 198                 if ((n->flags & IR3_INSTR_SS) && (opc_cat(n->opc) >= 5)) {
 199                         struct ir3_instruction *nop;
 200                         nop = ir3_NOP(block);
 201                         nop->flags |= IR3_INSTR_SS;
 202                         n->flags &= ~IR3_INSTR_SS;
 203                 }
 204
 205                 /* need to be able to set (ss) on first instruction: */
 206                 if (list_is_empty(&block->instr_list) && (opc_cat(n->opc) >= 5))
 207                         ir3_NOP(block);
 208
 209                 if (is_nop(n) && !list_is_empty(&block->instr_list)) {
 210                         struct ir3_instruction *last = list_last_entry(&block->instr_list,
 211                                         struct ir3_instruction, node);
 212                         if (is_nop(last) && (last->repeat < 5)) {
 213                                 last->repeat++;
 214                                 last->flags |= n->flags;
 215                                 continue;
 216                         }
 217
 218                         /* NOTE: I think the nopN encoding works for a5xx and
 219                          * probably a4xx, but not a3xx.  So far only tested on
 220                          * a6xx.
 221                          */
 222                         if ((ctx->compiler->gpu_id >= 600) && !n->flags && (last->nop < 3) &&
 223                                         ((opc_cat(last->opc) == 2) || (opc_cat(last->opc) == 3))) {
 224                                 last->nop++;
 225                                 continue;
 226                         }
 227                 }
 228
 229                 if (ctx->compiler->samgq_workaround &&
 230                         ctx->type == MESA_SHADER_VERTEX && n->opc == OPC_SAMGQ) {
 231                         struct ir3_instruction *samgp;
 232
 233                         for (i = 0; i < 4; i++) {
 234                                 samgp = ir3_instr_clone(n);
 235                                 samgp->opc = OPC_SAMGP0 + i;
 236                                 if (i > 1)
 237                                         samgp->flags |= IR3_INSTR_SY;
 238                         }
 239                         list_delinit(&n->node);
 240                 } else {
 241                         list_addtail(&n->node, &block->instr_list);
 242                 }
 243
 244                 if (is_sfu(n))
 245                         regmask_set(&state->needs_ss, n->regs[0]);
 246
 247                 if (is_tex(n) || (n->opc == OPC_META_TEX_PREFETCH)) {
 248                         regmask_set(&state->needs_sy, n->regs[0]);
 249                         ctx->need_pixlod = true;
 250                         if (n->opc == OPC_META_TEX_PREFETCH)
 251                                 has_tex_prefetch = true;
 252                 } else if (n->opc == OPC_RESINFO) {
 253                         regmask_set(&state->needs_ss, n->regs[0]);
 254                         ir3_NOP(block)->flags |= IR3_INSTR_SS;
 255                         last_input_needs_ss = false;
 256                 } else if (is_load(n)) {
 257                         /* seems like ldlv needs (ss) bit instead??  which is odd but
 258                          * makes a bunch of flat-varying tests start working on a4xx.
 259                          */
 260                         if ((n->opc == OPC_LDLV) || (n->opc == OPC_LDL) || (n->opc == OPC_LDLW))
 261                                 regmask_set(&state->needs_ss, n->regs[0]);
 262                         else
 263                                 regmask_set(&state->needs_sy, n->regs[0]);
 264                 } else if (is_atomic(n->opc)) {
 265                         if (n->flags & IR3_INSTR_G) {
 266                                 if (ctx->compiler->gpu_id >= 600) {
 267                                         /* New encoding, returns  result via second src: */
 268                                         regmask_set(&state->needs_sy, n->regs[3]);
 269                                 } else {
 270                                         regmask_set(&state->needs_sy, n->regs[0]);
 271                                 }
 272                         } else {
 273                                 regmask_set(&state->needs_ss, n->regs[0]);
 274                         }
 275                 }
 276
 277                 if (is_ssbo(n->opc) || (is_atomic(n->opc) && (n->flags & IR3_INSTR_G)))
 278                         ctx->has_ssbo = true;
 279
 280                 /* both tex/sfu appear to not always immediately consume
 281                  * their src register(s):
 282                  */
 283                 if (is_tex(n) || is_sfu(n) || is_mem(n)) {
 284                         foreach_src(reg, n) {
 285                                 if (reg_gpr(reg))
 286                                         regmask_set(&state->needs_ss_war, reg);
 287                         }
 288                 }
 289
 290                 if (is_input(n)) {
 291                         last_input = n;
 292                         last_input_needs_ss |= (n->opc == OPC_LDLV);
 293                 }
 294
 295                 last_n = n;
 296         }
 297
 298         if (last_input) {
 299                 assert(block == list_first_entry(&block->shader->block_list,
 300                                 struct ir3_block, node));
 301                 /* special hack.. if using ldlv to bypass interpolation,
 302                  * we need to insert a dummy bary.f on which we can set
 303                  * the (ei) flag:
 304                  */
 305                 if (is_mem(last_input) && (last_input->opc == OPC_LDLV)) {
 306                         struct ir3_instruction *baryf;
 307
 308                         /* (ss)bary.f (ei)r63.x, 0, r0.x */
 309                         baryf = ir3_instr_create(block, OPC_BARY_F);
 310                         ir3_reg_create(baryf, regid(63, 0), 0);
 311                         ir3_reg_create(baryf, 0, IR3_REG_IMMED)->iim_val = 0;
 312                         ir3_reg_create(baryf, regid(0, 0), 0);
 313
 314                         /* insert the dummy bary.f after last_input: */
 315                         list_delinit(&baryf->node);
 316                         list_add(&baryf->node, &last_input->node);
 317
 318                         last_input = baryf;
 319
 320                         /* by definition, we need (ss) since we are inserting
 321                          * the dummy bary.f immediately after the ldlv:
 322                          */
 323                         last_input_needs_ss = true;
 324                 }
 325                 last_input->regs[0]->flags |= IR3_REG_EI;
 326                 if (last_input_needs_ss)
 327                         last_input->flags |= IR3_INSTR_SS;
 328         } else if (has_tex_prefetch) {
 329                 /* texture prefetch, but *no* inputs.. we need to insert a
 330                  * dummy bary.f at the top of the shader to unblock varying
 331                  * storage:
 332                  */
 333                 struct ir3_instruction *baryf;
 334
 335                 /* (ss)bary.f (ei)r63.x, 0, r0.x */
 336                 baryf = ir3_instr_create(block, OPC_BARY_F);
 337                 ir3_reg_create(baryf, regid(63, 0), 0)->flags |= IR3_REG_EI;
 338                 ir3_reg_create(baryf, 0, IR3_REG_IMMED)->iim_val = 0;
 339                 ir3_reg_create(baryf, regid(0, 0), 0);
 340
 341                 /* insert the dummy bary.f at head: */
 342                 list_delinit(&baryf->node);
 343                 list_add(&baryf->node, &block->instr_list);
 344         }
 345
 346         if (last_rel)
 347                 last_rel->flags |= IR3_INSTR_UL;
 348
 349         bd->valid = true;
 350
 351         if (memcmp(&prev_state, state, sizeof(*state))) {
 352                 /* our output state changed, this invalidates all of our
 353                  * successors:
 354                  */
 355                 for (unsigned i = 0; i < ARRAY_SIZE(block->successors); i++) {
 356                         if (!block->successors[i])
 357                                 break;
 358                         struct ir3_legalize_block_data *pbd = block->successors[i]->data;
 359                         pbd->valid = false;
 360                 }
 361         }
 362
 363         return true;
 364 }
 365
 366 /* NOTE: branch instructions are always the last instruction(s)
 367  * in the block.  We take advantage of this as we resolve the
 368  * branches, since "if (foo) break;" constructs turn into
 369  * something like:
 370  *
 371  *   block3 {
 372  *      ...
 373  *      0029:021: mov.s32s32 r62.x, r1.y
 374  *      0082:022: br !p0.x, target=block5
 375  *      0083:023: br p0.x, target=block4
 376  *      // succs: if _[0029:021: mov.s32s32] block4; else block5;
 377  *   }
 378  *   block4 {
 379  *      0084:024: jump, target=block6
 380  *      // succs: block6;
 381  *   }
 382  *   block5 {
 383  *      0085:025: jump, target=block7
 384  *      // succs: block7;
 385  *   }
 386  *
 387  * ie. only instruction in block4/block5 is a jump, so when
 388  * resolving branches we can easily detect this by checking
 389  * that the first instruction in the target block is itself
 390  * a jump, and setup the br directly to the jump's target
 391  * (and strip back out the now unreached jump)
 392  *
 393  * TODO sometimes we end up with things like:
 394  *
 395  *    br !p0.x, #2
 396  *    br p0.x, #12
 397  *    add.u r0.y, r0.y, 1
 398  *
 399  * If we swapped the order of the branches, we could drop one.
 400  */
 401 static struct ir3_block *
 402 resolve_dest_block(struct ir3_block *block)
 403 {
 404         /* special case for last block: */
 405         if (!block->successors[0])
 406                 return block;
 407
 408         /* NOTE that we may or may not have inserted the jump
 409          * in the target block yet, so conditions to resolve
 410          * the dest to the dest block's successor are:
 411          *
 412          *   (1) successor[1] == NULL &&
 413          *   (2) (block-is-empty || only-instr-is-jump)
 414          */
 415         if (block->successors[1] == NULL) {
 416                 if (list_is_empty(&block->instr_list)) {
 417                         return block->successors[0];
 418                 } else if (list_length(&block->instr_list) == 1) {
 419                         struct ir3_instruction *instr = list_first_entry(
 420                                         &block->instr_list, struct ir3_instruction, node);
 421                         if (instr->opc == OPC_JUMP)
 422                                 return block->successors[0];
 423                 }
 424         }
 425         return block;
 426 }
 427
 428 static void
 429 remove_unused_block(struct ir3_block *old_target)
 430 {
 431         list_delinit(&old_target->node);
 432
 433         /* cleanup dangling predecessors: */
 434         for (unsigned i = 0; i < ARRAY_SIZE(old_target->successors); i++) {
 435                 if (old_target->successors[i]) {
 436                         struct ir3_block *succ = old_target->successors[i];
 437                         _mesa_set_remove_key(succ->predecessors, old_target);
 438                 }
 439         }
 440 }
 441
 442 static void
 443 retarget_jump(struct ir3_instruction *instr, struct ir3_block *new_target)
 444 {
 445         struct ir3_block *old_target = instr->cat0.target;
 446         struct ir3_block *cur_block = instr->block;
 447
 448         /* update current blocks successors to reflect the retargetting: */
 449         if (cur_block->successors[0] == old_target) {
 450                 cur_block->successors[0] = new_target;
 451         } else {
 452                 debug_assert(cur_block->successors[1] == old_target);
 453                 cur_block->successors[1] = new_target;
 454         }
 455
 456         /* update new target's predecessors: */
 457         _mesa_set_add(new_target->predecessors, cur_block);
 458
 459         /* and remove old_target's predecessor: */
 460         debug_assert(_mesa_set_search(old_target->predecessors, cur_block));
 461         _mesa_set_remove_key(old_target->predecessors, cur_block);
 462
 463         if (old_target->predecessors->entries == 0)
 464                 remove_unused_block(old_target);
 465
 466         instr->cat0.target = new_target;
 467 }
 468
 469 static bool
 470 resolve_jump(struct ir3_instruction *instr)
 471 {
 472         struct ir3_block *tblock =
 473                 resolve_dest_block(instr->cat0.target);
 474         struct ir3_instruction *target;
 475
 476         if (tblock != instr->cat0.target) {
 477                 retarget_jump(instr, tblock);
 478                 return true;
 479         }
 480
 481         target = list_first_entry(&tblock->instr_list,
 482                                 struct ir3_instruction, node);
 483
 484         /* TODO maybe a less fragile way to do this.  But we are expecting
 485          * a pattern from sched_block() that looks like:
 486          *
 487          *   br !p0.x, #else-block
 488          *   br p0.x, #if-block
 489          *
 490          * if the first branch target is +2, or if 2nd branch target is +1
 491          * then we can just drop the jump.
 492          */
 493         unsigned next_block;
 494         if (instr->cat0.inv == true)
 495                 next_block = 2;
 496         else
 497                 next_block = 1;
 498
 499         if (target->ip == (instr->ip + next_block)) {
 500                 list_delinit(&instr->node);
 501                 return true;
 502         } else {
 503                 instr->cat0.immed =
 504                         (int)target->ip - (int)instr->ip;
 505         }
 506         return false;
 507 }
 508
 509 /* resolve jumps, removing jumps/branches to immediately following
 510  * instruction which we end up with from earlier stages.  Since
 511  * removing an instruction can invalidate earlier instruction's
 512  * branch offsets, we need to do this iteratively until no more
 513  * branches are removed.
 514  */
 515 static bool
 516 resolve_jumps(struct ir3 *ir)
 517 {
 518         list_for_each_entry (struct ir3_block, block, &ir->block_list, node)
 519                 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node)
 520                         if (is_flow(instr) && instr->cat0.target)
 521                                 if (resolve_jump(instr))
 522                                         return true;
 523
 524         return false;
 525 }
 526
 527 static void mark_jp(struct ir3_block *block)
 528 {
 529         struct ir3_instruction *target = list_first_entry(&block->instr_list,
 530                         struct ir3_instruction, node);
 531         target->flags |= IR3_INSTR_JP;
 532 }
 533
 534 /* Mark points where control flow converges or diverges.
 535  *
 536  * Divergence points could actually be re-convergence points where
 537  * "parked" threads are recoverged with threads that took the opposite
 538  * path last time around.  Possibly it is easier to think of (jp) as
 539  * "the execution mask might have changed".
 540  */
 541 static void
 542 mark_xvergence_points(struct ir3 *ir)
 543 {
 544         list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
 545                 if (block->predecessors->entries > 1) {
 546                         /* if a block has more than one possible predecessor, then
 547                          * the first instruction is a convergence point.
 548                          */
 549                         mark_jp(block);
 550                 } else if (block->predecessors->entries == 1) {
 551                         /* If a block has one predecessor, which has multiple possible
 552                          * successors, it is a divergence point.
 553                          */
 554                         set_foreach(block->predecessors, entry) {
 555                                 struct ir3_block *predecessor = (struct ir3_block *)entry->key;
 556                                 if (predecessor->successors[1]) {
 557                                         mark_jp(block);
 558                                 }
 559                         }
 560                 }
 561         }
 562 }
 563
 564 void
 565 ir3_legalize(struct ir3 *ir, bool *has_ssbo, bool *need_pixlod, int *max_bary)
 566 {
 567         struct ir3_legalize_ctx *ctx = rzalloc(ir, struct ir3_legalize_ctx);
 568         bool progress;
 569
 570         ctx->max_bary = -1;
 571         ctx->compiler = ir->compiler;
 572         ctx->type = ir->type;
 573
 574         /* allocate per-block data: */
 575         list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
 576                 block->data = rzalloc(ctx, struct ir3_legalize_block_data);
 577         }
 578
 579         /* process each block: */
 580         do {
 581                 progress = false;
 582                 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
 583                         progress |= legalize_block(ctx, block);
 584                 }
 585         } while (progress);
 586
 587         *has_ssbo = ctx->has_ssbo;
 588         *need_pixlod = ctx->need_pixlod;
 589         *max_bary = ctx->max_bary;
 590
 591         do {
 592                 ir3_count_instructions(ir);
 593         } while(resolve_jumps(ir));
 594
 595         mark_xvergence_points(ir);
 596
 597         ralloc_free(ctx);
 598 }