src/freedreno/ir3/ir3_legalize.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "util/ralloc.h"
  28 #include "util/u_math.h"
  29
  30 #include "ir3.h"
  31 #include "ir3_compiler.h"
  32
  33 /*
  34  * Legalize:
  35  *
  36  * We currently require that scheduling ensures that we have enough nop's
  37  * in all the right places.  The legalize step mostly handles fixing up
  38  * instruction flags ((ss)/(sy)/(ei)), and collapses sequences of nop's
  39  * into fewer nop's w/ rpt flag.
  40  */
  41
  42 struct ir3_legalize_ctx {
  43         struct ir3_compiler *compiler;
  44         gl_shader_stage type;
  45         bool has_ssbo;
  46         bool need_pixlod;
  47         int max_bary;
  48 };
  49
  50 struct ir3_legalize_state {
  51         regmask_t needs_ss;
  52         regmask_t needs_ss_war;       /* write after read */
  53         regmask_t needs_sy;
  54 };
  55
  56 struct ir3_legalize_block_data {
  57         bool valid;
  58         struct ir3_legalize_state state;
  59 };
  60
  61 /* We want to evaluate each block from the position of any other
  62  * predecessor block, in order that the flags set are the union of
  63  * all possible program paths.
  64  *
  65  * To do this, we need to know the output state (needs_ss/ss_war/sy)
  66  * of all predecessor blocks.  The tricky thing is loops, which mean
  67  * that we can't simply recursively process each predecessor block
  68  * before legalizing the current block.
  69  *
  70  * How we handle that is by looping over all the blocks until the
  71  * results converge.  If the output state of a given block changes
  72  * in a given pass, this means that all successor blocks are not
  73  * yet fully legalized.
  74  */
  75
  76 static bool
  77 legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
  78 {
  79         struct ir3_legalize_block_data *bd = block->data;
  80
  81         if (bd->valid)
  82                 return false;
  83
  84         struct ir3_instruction *last_input = NULL;
  85         struct ir3_instruction *last_rel = NULL;
  86         struct ir3_instruction *last_n = NULL;
  87         struct list_head instr_list;
  88         struct ir3_legalize_state prev_state = bd->state;
  89         struct ir3_legalize_state *state = &bd->state;
  90         bool last_input_needs_ss = false;
  91
  92         /* our input state is the OR of all predecessor blocks' state: */
  93         for (unsigned i = 0; i < block->predecessors_count; i++) {
  94                 struct ir3_legalize_block_data *pbd = block->predecessors[i]->data;
  95                 struct ir3_legalize_state *pstate = &pbd->state;
  96
  97                 /* Our input (ss)/(sy) state is based on OR'ing the output
  98                  * state of all our predecessor blocks
  99                  */
 100                 regmask_or(&state->needs_ss,
 101                                 &state->needs_ss, &pstate->needs_ss);
 102                 regmask_or(&state->needs_ss_war,
 103                                 &state->needs_ss_war, &pstate->needs_ss_war);
 104                 regmask_or(&state->needs_sy,
 105                                 &state->needs_sy, &pstate->needs_sy);
 106         }
 107
 108         /* remove all the instructions from the list, we'll be adding
 109          * them back in as we go
 110          */
 111         list_replace(&block->instr_list, &instr_list);
 112         list_inithead(&block->instr_list);
 113
 114         list_for_each_entry_safe (struct ir3_instruction, n, &instr_list, node) {
 115                 struct ir3_register *reg;
 116                 unsigned i;
 117
 118                 n->flags &= ~(IR3_INSTR_SS | IR3_INSTR_SY);
 119
 120                 if (is_meta(n))
 121                         continue;
 122
 123                 if (is_input(n)) {
 124                         struct ir3_register *inloc = n->regs[1];
 125                         assert(inloc->flags & IR3_REG_IMMED);
 126                         ctx->max_bary = MAX2(ctx->max_bary, inloc->iim_val);
 127                 }
 128
 129                 if (last_n && is_barrier(last_n)) {
 130                         n->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
 131                         last_input_needs_ss = false;
 132                 }
 133
 134                 /* NOTE: consider dst register too.. it could happen that
 135                  * texture sample instruction (for example) writes some
 136                  * components which are unused.  A subsequent instruction
 137                  * that writes the same register can race w/ the sam instr
 138                  * resulting in undefined results:
 139                  */
 140                 for (i = 0; i < n->regs_count; i++) {
 141                         reg = n->regs[i];
 142
 143                         if (reg_gpr(reg)) {
 144
 145                                 /* TODO: we probably only need (ss) for alu
 146                                  * instr consuming sfu result.. need to make
 147                                  * some tests for both this and (sy)..
 148                                  */
 149                                 if (regmask_get(&state->needs_ss, reg)) {
 150                                         n->flags |= IR3_INSTR_SS;
 151                                         last_input_needs_ss = false;
 152                                         regmask_init(&state->needs_ss_war);
 153                                         regmask_init(&state->needs_ss);
 154                                 }
 155
 156                                 if (regmask_get(&state->needs_sy, reg)) {
 157                                         n->flags |= IR3_INSTR_SY;
 158                                         regmask_init(&state->needs_sy);
 159                                 }
 160                         }
 161
 162                         /* TODO: is it valid to have address reg loaded from a
 163                          * relative src (ie. mova a0, c<a0.x+4>)?  If so, the
 164                          * last_rel check below should be moved ahead of this:
 165                          */
 166                         if (reg->flags & IR3_REG_RELATIV)
 167                                 last_rel = n;
 168                 }
 169
 170                 if (n->regs_count > 0) {
 171                         reg = n->regs[0];
 172                         if (regmask_get(&state->needs_ss_war, reg)) {
 173                                 n->flags |= IR3_INSTR_SS;
 174                                 last_input_needs_ss = false;
 175                                 regmask_init(&state->needs_ss_war);
 176                                 regmask_init(&state->needs_ss);
 177                         }
 178
 179                         if (last_rel && (reg->num == regid(REG_A0, 0))) {
 180                                 last_rel->flags |= IR3_INSTR_UL;
 181                                 last_rel = NULL;
 182                         }
 183                 }
 184
 185                 /* cat5+ does not have an (ss) bit, if needed we need to
 186                  * insert a nop to carry the sync flag.  Would be kinda
 187                  * clever if we were aware of this during scheduling, but
 188                  * this should be a pretty rare case:
 189                  */
 190                 if ((n->flags & IR3_INSTR_SS) && (opc_cat(n->opc) >= 5)) {
 191                         struct ir3_instruction *nop;
 192                         nop = ir3_NOP(block);
 193                         nop->flags |= IR3_INSTR_SS;
 194                         n->flags &= ~IR3_INSTR_SS;
 195                 }
 196
 197                 /* need to be able to set (ss) on first instruction: */
 198                 if (list_empty(&block->instr_list) && (opc_cat(n->opc) >= 5))
 199                         ir3_NOP(block);
 200
 201                 if (is_nop(n) && !list_empty(&block->instr_list)) {
 202                         struct ir3_instruction *last = list_last_entry(&block->instr_list,
 203                                         struct ir3_instruction, node);
 204                         if (is_nop(last) && (last->repeat < 5)) {
 205                                 last->repeat++;
 206                                 last->flags |= n->flags;
 207                                 continue;
 208                         }
 209
 210                         /* NOTE: I think the nopN encoding works for a5xx and
 211                          * probably a4xx, but not a3xx.  So far only tested on
 212                          * a6xx.
 213                          */
 214                         if ((ctx->compiler->gpu_id >= 600) && !n->flags && (last->nop < 3) &&
 215                                         ((opc_cat(last->opc) == 2) || (opc_cat(last->opc) == 3))) {
 216                                 last->nop++;
 217                                 continue;
 218                         }
 219                 }
 220
 221                 if (ctx->compiler->samgq_workaround &&
 222                         ctx->type == MESA_SHADER_VERTEX && n->opc == OPC_SAMGQ) {
 223                         struct ir3_instruction *samgp;
 224
 225                         for (i = 0; i < 4; i++) {
 226                                 samgp = ir3_instr_clone(n);
 227                                 samgp->opc = OPC_SAMGP0 + i;
 228                                 if (i > 1)
 229                                         samgp->flags |= IR3_INSTR_SY;
 230                         }
 231                         list_delinit(&n->node);
 232                 } else {
 233                         list_addtail(&n->node, &block->instr_list);
 234                 }
 235
 236                 if (is_sfu(n))
 237                         regmask_set(&state->needs_ss, n->regs[0]);
 238
 239                 if (is_tex(n)) {
 240                         regmask_set(&state->needs_sy, n->regs[0]);
 241                         ctx->need_pixlod = true;
 242                 } else if (n->opc == OPC_RESINFO) {
 243                         regmask_set(&state->needs_ss, n->regs[0]);
 244                         ir3_NOP(block)->flags |= IR3_INSTR_SS;
 245                         last_input_needs_ss = false;
 246                 } else if (is_load(n)) {
 247                         /* seems like ldlv needs (ss) bit instead??  which is odd but
 248                          * makes a bunch of flat-varying tests start working on a4xx.
 249                          */
 250                         if ((n->opc == OPC_LDLV) || (n->opc == OPC_LDL))
 251                                 regmask_set(&state->needs_ss, n->regs[0]);
 252                         else
 253                                 regmask_set(&state->needs_sy, n->regs[0]);
 254                 } else if (is_atomic(n->opc)) {
 255                         if (n->flags & IR3_INSTR_G) {
 256                                 if (ctx->compiler->gpu_id >= 600) {
 257                                         /* New encoding, returns  result via second src: */
 258                                         regmask_set(&state->needs_sy, n->regs[3]);
 259                                 } else {
 260                                         regmask_set(&state->needs_sy, n->regs[0]);
 261                                 }
 262                         } else {
 263                                 regmask_set(&state->needs_ss, n->regs[0]);
 264                         }
 265                 }
 266
 267                 if (is_ssbo(n->opc) || (is_atomic(n->opc) && (n->flags & IR3_INSTR_G)))
 268                         ctx->has_ssbo = true;
 269
 270                 /* both tex/sfu appear to not always immediately consume
 271                  * their src register(s):
 272                  */
 273                 if (is_tex(n) || is_sfu(n) || is_mem(n)) {
 274                         foreach_src(reg, n) {
 275                                 if (reg_gpr(reg))
 276                                         regmask_set(&state->needs_ss_war, reg);
 277                         }
 278                 }
 279
 280                 if (is_input(n)) {
 281                         last_input = n;
 282                         last_input_needs_ss |= (n->opc == OPC_LDLV);
 283                 }
 284
 285                 last_n = n;
 286         }
 287
 288         if (last_input) {
 289                 assert(block == list_first_entry(&block->shader->block_list,
 290                                 struct ir3_block, node));
 291                 /* special hack.. if using ldlv to bypass interpolation,
 292                  * we need to insert a dummy bary.f on which we can set
 293                  * the (ei) flag:
 294                  */
 295                 if (is_mem(last_input) && (last_input->opc == OPC_LDLV)) {
 296                         struct ir3_instruction *baryf;
 297
 298                         /* (ss)bary.f (ei)r63.x, 0, r0.x */
 299                         baryf = ir3_instr_create(block, OPC_BARY_F);
 300                         ir3_reg_create(baryf, regid(63, 0), 0);
 301                         ir3_reg_create(baryf, 0, IR3_REG_IMMED)->iim_val = 0;
 302                         ir3_reg_create(baryf, regid(0, 0), 0);
 303
 304                         /* insert the dummy bary.f after last_input: */
 305                         list_delinit(&baryf->node);
 306                         list_add(&baryf->node, &last_input->node);
 307
 308                         last_input = baryf;
 309                 }
 310                 last_input->regs[0]->flags |= IR3_REG_EI;
 311                 if (last_input_needs_ss)
 312                         last_input->flags |= IR3_INSTR_SS;
 313         }
 314
 315         if (last_rel)
 316                 last_rel->flags |= IR3_INSTR_UL;
 317
 318         bd->valid = true;
 319
 320         if (memcmp(&prev_state, state, sizeof(*state))) {
 321                 /* our output state changed, this invalidates all of our
 322                  * successors:
 323                  */
 324                 for (unsigned i = 0; i < ARRAY_SIZE(block->successors); i++) {
 325                         if (!block->successors[i])
 326                                 break;
 327                         struct ir3_legalize_block_data *pbd = block->successors[i]->data;
 328                         pbd->valid = false;
 329                 }
 330         }
 331
 332         return true;
 333 }
 334
 335 /* NOTE: branch instructions are always the last instruction(s)
 336  * in the block.  We take advantage of this as we resolve the
 337  * branches, since "if (foo) break;" constructs turn into
 338  * something like:
 339  *
 340  *   block3 {
 341  *      ...
 342  *      0029:021: mov.s32s32 r62.x, r1.y
 343  *      0082:022: br !p0.x, target=block5
 344  *      0083:023: br p0.x, target=block4
 345  *      // succs: if _[0029:021: mov.s32s32] block4; else block5;
 346  *   }
 347  *   block4 {
 348  *      0084:024: jump, target=block6
 349  *      // succs: block6;
 350  *   }
 351  *   block5 {
 352  *      0085:025: jump, target=block7
 353  *      // succs: block7;
 354  *   }
 355  *
 356  * ie. only instruction in block4/block5 is a jump, so when
 357  * resolving branches we can easily detect this by checking
 358  * that the first instruction in the target block is itself
 359  * a jump, and setup the br directly to the jump's target
 360  * (and strip back out the now unreached jump)
 361  *
 362  * TODO sometimes we end up with things like:
 363  *
 364  *    br !p0.x, #2
 365  *    br p0.x, #12
 366  *    add.u r0.y, r0.y, 1
 367  *
 368  * If we swapped the order of the branches, we could drop one.
 369  */
 370 static struct ir3_block *
 371 resolve_dest_block(struct ir3_block *block)
 372 {
 373         /* special case for last block: */
 374         if (!block->successors[0])
 375                 return block;
 376
 377         /* NOTE that we may or may not have inserted the jump
 378          * in the target block yet, so conditions to resolve
 379          * the dest to the dest block's successor are:
 380          *
 381          *   (1) successor[1] == NULL &&
 382          *   (2) (block-is-empty || only-instr-is-jump)
 383          */
 384         if (block->successors[1] == NULL) {
 385                 if (list_empty(&block->instr_list)) {
 386                         return block->successors[0];
 387                 } else if (list_length(&block->instr_list) == 1) {
 388                         struct ir3_instruction *instr = list_first_entry(
 389                                         &block->instr_list, struct ir3_instruction, node);
 390                         if (instr->opc == OPC_JUMP)
 391                                 return block->successors[0];
 392                 }
 393         }
 394         return block;
 395 }
 396
 397 static bool
 398 resolve_jump(struct ir3_instruction *instr)
 399 {
 400         struct ir3_block *tblock =
 401                 resolve_dest_block(instr->cat0.target);
 402         struct ir3_instruction *target;
 403
 404         if (tblock != instr->cat0.target) {
 405                 list_delinit(&instr->cat0.target->node);
 406                 instr->cat0.target = tblock;
 407                 return true;
 408         }
 409
 410         target = list_first_entry(&tblock->instr_list,
 411                                 struct ir3_instruction, node);
 412
 413         /* TODO maybe a less fragile way to do this.  But we are expecting
 414          * a pattern from sched_block() that looks like:
 415          *
 416          *   br !p0.x, #else-block
 417          *   br p0.x, #if-block
 418          *
 419          * if the first branch target is +2, or if 2nd branch target is +1
 420          * then we can just drop the jump.
 421          */
 422         unsigned next_block;
 423         if (instr->cat0.inv == true)
 424                 next_block = 2;
 425         else
 426                 next_block = 1;
 427
 428         if ((!target) || (target->ip == (instr->ip + next_block))) {
 429                 list_delinit(&instr->node);
 430                 return true;
 431         } else {
 432                 instr->cat0.immed =
 433                         (int)target->ip - (int)instr->ip;
 434         }
 435         return false;
 436 }
 437
 438 /* resolve jumps, removing jumps/branches to immediately following
 439  * instruction which we end up with from earlier stages.  Since
 440  * removing an instruction can invalidate earlier instruction's
 441  * branch offsets, we need to do this iteratively until no more
 442  * branches are removed.
 443  */
 444 static bool
 445 resolve_jumps(struct ir3 *ir)
 446 {
 447         list_for_each_entry (struct ir3_block, block, &ir->block_list, node)
 448                 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node)
 449                         if (is_flow(instr) && instr->cat0.target)
 450                                 if (resolve_jump(instr))
 451                                         return true;
 452
 453         return false;
 454 }
 455
 456 /* we want to mark points where divergent flow control re-converges
 457  * with (jp) flags.  For now, since we don't do any optimization for
 458  * things that start out as a 'do {} while()', re-convergence points
 459  * will always be a branch or jump target.  Note that this is overly
 460  * conservative, since unconditional jump targets are not convergence
 461  * points, we are just assuming that the other path to reach the jump
 462  * target was divergent.  If we were clever enough to optimize the
 463  * jump at end of a loop back to a conditional branch into a single
 464  * conditional branch, ie. like:
 465  *
 466  *    add.f r1.w, r0.x, (neg)(r)c2.x   <= loop start
 467  *    mul.f r1.z, r1.z, r0.x
 468  *    mul.f r1.y, r1.y, r0.x
 469  *    mul.f r0.z, r1.x, r0.x
 470  *    mul.f r0.w, r0.y, r0.x
 471  *    cmps.f.ge r0.x, (r)c2.y, (r)r1.w
 472  *    add.s r0.x, (r)r0.x, (r)-1
 473  *    sel.f32 r0.x, (r)c3.y, (r)r0.x, c3.x
 474  *    cmps.f.eq p0.x, r0.x, c3.y
 475  *    mov.f32f32 r0.x, r1.w
 476  *    mov.f32f32 r0.y, r0.w
 477  *    mov.f32f32 r1.x, r0.z
 478  *    (rpt2)nop
 479  *    br !p0.x, #-13
 480  *    (jp)mul.f r0.x, c263.y, r1.y
 481  *
 482  * Then we'd have to be more clever, as the convergence point is no
 483  * longer a branch or jump target.
 484  */
 485 static void
 486 mark_convergence_points(struct ir3 *ir)
 487 {
 488         list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
 489                 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
 490                         if (is_flow(instr) && instr->cat0.target) {
 491                                 struct ir3_instruction *target =
 492                                         list_first_entry(&instr->cat0.target->instr_list,
 493                                                         struct ir3_instruction, node);
 494                                 target->flags |= IR3_INSTR_JP;
 495                         }
 496                 }
 497         }
 498 }
 499
 500 void
 501 ir3_legalize(struct ir3 *ir, bool *has_ssbo, bool *need_pixlod, int *max_bary)
 502 {
 503         struct ir3_legalize_ctx *ctx = rzalloc(ir, struct ir3_legalize_ctx);
 504         bool progress;
 505
 506         ctx->max_bary = -1;
 507         ctx->compiler = ir->compiler;
 508         ctx->type = ir->type;
 509
 510         /* allocate per-block data: */
 511         list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
 512                 block->data = rzalloc(ctx, struct ir3_legalize_block_data);
 513         }
 514
 515         /* process each block: */
 516         do {
 517                 progress = false;
 518                 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
 519                         progress |= legalize_block(ctx, block);
 520                 }
 521         } while (progress);
 522
 523         *has_ssbo = ctx->has_ssbo;
 524         *need_pixlod = ctx->need_pixlod;
 525         *max_bary = ctx->max_bary;
 526
 527         do {
 528                 ir3_count_instructions(ir);
 529         } while(resolve_jumps(ir));
 530
 531         mark_convergence_points(ir);
 532
 533         ralloc_free(ctx);
 534 }