2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "util/ralloc.h"
28 #include "util/u_math.h"
31 #include "ir3_compiler.h"
36 * We currently require that scheduling ensures that we have enough nop's
37 * in all the right places. The legalize step mostly handles fixing up
38 * instruction flags ((ss)/(sy)/(ei)), and collapses sequences of nop's
39 * into fewer nop's w/ rpt flag.
42 struct ir3_legalize_ctx
{
43 struct ir3_compiler
*compiler
;
50 struct ir3_legalize_state
{
52 regmask_t needs_ss_war
; /* write after read */
56 struct ir3_legalize_block_data
{
58 struct ir3_legalize_state state
;
61 /* We want to evaluate each block from the position of any other
62 * predecessor block, in order that the flags set are the union of
63 * all possible program paths.
65 * To do this, we need to know the output state (needs_ss/ss_war/sy)
66 * of all predecessor blocks. The tricky thing is loops, which mean
67 * that we can't simply recursively process each predecessor block
68 * before legalizing the current block.
70 * How we handle that is by looping over all the blocks until the
71 * results converge. If the output state of a given block changes
72 * in a given pass, this means that all successor blocks are not
73 * yet fully legalized.
77 legalize_block(struct ir3_legalize_ctx
*ctx
, struct ir3_block
*block
)
79 struct ir3_legalize_block_data
*bd
= block
->data
;
84 struct ir3_instruction
*last_input
= NULL
;
85 struct ir3_instruction
*last_rel
= NULL
;
86 struct ir3_instruction
*last_n
= NULL
;
87 struct list_head instr_list
;
88 struct ir3_legalize_state prev_state
= bd
->state
;
89 struct ir3_legalize_state
*state
= &bd
->state
;
90 bool last_input_needs_ss
= false;
92 /* our input state is the OR of all predecessor blocks' state: */
93 for (unsigned i
= 0; i
< block
->predecessors_count
; i
++) {
94 struct ir3_legalize_block_data
*pbd
= block
->predecessors
[i
]->data
;
95 struct ir3_legalize_state
*pstate
= &pbd
->state
;
97 /* Our input (ss)/(sy) state is based on OR'ing the output
98 * state of all our predecessor blocks
100 regmask_or(&state
->needs_ss
,
101 &state
->needs_ss
, &pstate
->needs_ss
);
102 regmask_or(&state
->needs_ss_war
,
103 &state
->needs_ss_war
, &pstate
->needs_ss_war
);
104 regmask_or(&state
->needs_sy
,
105 &state
->needs_sy
, &pstate
->needs_sy
);
108 /* remove all the instructions from the list, we'll be adding
109 * them back in as we go
111 list_replace(&block
->instr_list
, &instr_list
);
112 list_inithead(&block
->instr_list
);
114 list_for_each_entry_safe (struct ir3_instruction
, n
, &instr_list
, node
) {
115 struct ir3_register
*reg
;
118 n
->flags
&= ~(IR3_INSTR_SS
| IR3_INSTR_SY
);
124 struct ir3_register
*inloc
= n
->regs
[1];
125 assert(inloc
->flags
& IR3_REG_IMMED
);
126 ctx
->max_bary
= MAX2(ctx
->max_bary
, inloc
->iim_val
);
129 if (last_n
&& is_barrier(last_n
)) {
130 n
->flags
|= IR3_INSTR_SS
| IR3_INSTR_SY
;
131 last_input_needs_ss
= false;
134 /* NOTE: consider dst register too.. it could happen that
135 * texture sample instruction (for example) writes some
136 * components which are unused. A subsequent instruction
137 * that writes the same register can race w/ the sam instr
138 * resulting in undefined results:
140 for (i
= 0; i
< n
->regs_count
; i
++) {
145 /* TODO: we probably only need (ss) for alu
146 * instr consuming sfu result.. need to make
147 * some tests for both this and (sy)..
149 if (regmask_get(&state
->needs_ss
, reg
)) {
150 n
->flags
|= IR3_INSTR_SS
;
151 last_input_needs_ss
= false;
152 regmask_init(&state
->needs_ss_war
);
153 regmask_init(&state
->needs_ss
);
156 if (regmask_get(&state
->needs_sy
, reg
)) {
157 n
->flags
|= IR3_INSTR_SY
;
158 regmask_init(&state
->needs_sy
);
162 /* TODO: is it valid to have address reg loaded from a
163 * relative src (ie. mova a0, c<a0.x+4>)? If so, the
164 * last_rel check below should be moved ahead of this:
166 if (reg
->flags
& IR3_REG_RELATIV
)
170 if (n
->regs_count
> 0) {
172 if (regmask_get(&state
->needs_ss_war
, reg
)) {
173 n
->flags
|= IR3_INSTR_SS
;
174 last_input_needs_ss
= false;
175 regmask_init(&state
->needs_ss_war
);
176 regmask_init(&state
->needs_ss
);
179 if (last_rel
&& (reg
->num
== regid(REG_A0
, 0))) {
180 last_rel
->flags
|= IR3_INSTR_UL
;
185 /* cat5+ does not have an (ss) bit, if needed we need to
186 * insert a nop to carry the sync flag. Would be kinda
187 * clever if we were aware of this during scheduling, but
188 * this should be a pretty rare case:
190 if ((n
->flags
& IR3_INSTR_SS
) && (opc_cat(n
->opc
) >= 5)) {
191 struct ir3_instruction
*nop
;
192 nop
= ir3_NOP(block
);
193 nop
->flags
|= IR3_INSTR_SS
;
194 n
->flags
&= ~IR3_INSTR_SS
;
197 /* need to be able to set (ss) on first instruction: */
198 if (list_empty(&block
->instr_list
) && (opc_cat(n
->opc
) >= 5))
201 if (is_nop(n
) && !list_empty(&block
->instr_list
)) {
202 struct ir3_instruction
*last
= list_last_entry(&block
->instr_list
,
203 struct ir3_instruction
, node
);
204 if (is_nop(last
) && (last
->repeat
< 5)) {
206 last
->flags
|= n
->flags
;
210 /* NOTE: I think the nopN encoding works for a5xx and
211 * probably a4xx, but not a3xx. So far only tested on
214 if ((ctx
->compiler
->gpu_id
>= 600) && !n
->flags
&& (last
->nop
< 3) &&
215 ((opc_cat(last
->opc
) == 2) || (opc_cat(last
->opc
) == 3))) {
221 if (ctx
->compiler
->samgq_workaround
&&
222 ctx
->type
== MESA_SHADER_VERTEX
&& n
->opc
== OPC_SAMGQ
) {
223 struct ir3_instruction
*samgp
;
225 for (i
= 0; i
< 4; i
++) {
226 samgp
= ir3_instr_clone(n
);
227 samgp
->opc
= OPC_SAMGP0
+ i
;
229 samgp
->flags
|= IR3_INSTR_SY
;
231 list_delinit(&n
->node
);
233 list_addtail(&n
->node
, &block
->instr_list
);
237 regmask_set(&state
->needs_ss
, n
->regs
[0]);
240 regmask_set(&state
->needs_sy
, n
->regs
[0]);
241 ctx
->need_pixlod
= true;
242 } else if (n
->opc
== OPC_RESINFO
) {
243 regmask_set(&state
->needs_ss
, n
->regs
[0]);
244 ir3_NOP(block
)->flags
|= IR3_INSTR_SS
;
245 last_input_needs_ss
= false;
246 } else if (is_load(n
)) {
247 /* seems like ldlv needs (ss) bit instead?? which is odd but
248 * makes a bunch of flat-varying tests start working on a4xx.
250 if ((n
->opc
== OPC_LDLV
) || (n
->opc
== OPC_LDL
))
251 regmask_set(&state
->needs_ss
, n
->regs
[0]);
253 regmask_set(&state
->needs_sy
, n
->regs
[0]);
254 } else if (is_atomic(n
->opc
)) {
255 if (n
->flags
& IR3_INSTR_G
) {
256 if (ctx
->compiler
->gpu_id
>= 600) {
257 /* New encoding, returns result via second src: */
258 regmask_set(&state
->needs_sy
, n
->regs
[3]);
260 regmask_set(&state
->needs_sy
, n
->regs
[0]);
263 regmask_set(&state
->needs_ss
, n
->regs
[0]);
267 if (is_ssbo(n
->opc
) || (is_atomic(n
->opc
) && (n
->flags
& IR3_INSTR_G
)))
268 ctx
->has_ssbo
= true;
270 /* both tex/sfu appear to not always immediately consume
271 * their src register(s):
273 if (is_tex(n
) || is_sfu(n
) || is_mem(n
)) {
274 foreach_src(reg
, n
) {
276 regmask_set(&state
->needs_ss_war
, reg
);
282 last_input_needs_ss
|= (n
->opc
== OPC_LDLV
);
289 assert(block
== list_first_entry(&block
->shader
->block_list
,
290 struct ir3_block
, node
));
291 /* special hack.. if using ldlv to bypass interpolation,
292 * we need to insert a dummy bary.f on which we can set
295 if (is_mem(last_input
) && (last_input
->opc
== OPC_LDLV
)) {
296 struct ir3_instruction
*baryf
;
298 /* (ss)bary.f (ei)r63.x, 0, r0.x */
299 baryf
= ir3_instr_create(block
, OPC_BARY_F
);
300 ir3_reg_create(baryf
, regid(63, 0), 0);
301 ir3_reg_create(baryf
, 0, IR3_REG_IMMED
)->iim_val
= 0;
302 ir3_reg_create(baryf
, regid(0, 0), 0);
304 /* insert the dummy bary.f after last_input: */
305 list_delinit(&baryf
->node
);
306 list_add(&baryf
->node
, &last_input
->node
);
310 /* by definition, we need (ss) since we are inserting
311 * the dummy bary.f immediately after the ldlv:
313 last_input_needs_ss
= true;
315 last_input
->regs
[0]->flags
|= IR3_REG_EI
;
316 if (last_input_needs_ss
)
317 last_input
->flags
|= IR3_INSTR_SS
;
321 last_rel
->flags
|= IR3_INSTR_UL
;
325 if (memcmp(&prev_state
, state
, sizeof(*state
))) {
326 /* our output state changed, this invalidates all of our
329 for (unsigned i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
330 if (!block
->successors
[i
])
332 struct ir3_legalize_block_data
*pbd
= block
->successors
[i
]->data
;
340 /* NOTE: branch instructions are always the last instruction(s)
341 * in the block. We take advantage of this as we resolve the
342 * branches, since "if (foo) break;" constructs turn into
347 * 0029:021: mov.s32s32 r62.x, r1.y
348 * 0082:022: br !p0.x, target=block5
349 * 0083:023: br p0.x, target=block4
350 * // succs: if _[0029:021: mov.s32s32] block4; else block5;
353 * 0084:024: jump, target=block6
357 * 0085:025: jump, target=block7
361 * ie. only instruction in block4/block5 is a jump, so when
362 * resolving branches we can easily detect this by checking
363 * that the first instruction in the target block is itself
364 * a jump, and setup the br directly to the jump's target
365 * (and strip back out the now unreached jump)
367 * TODO sometimes we end up with things like:
371 * add.u r0.y, r0.y, 1
373 * If we swapped the order of the branches, we could drop one.
375 static struct ir3_block
*
376 resolve_dest_block(struct ir3_block
*block
)
378 /* special case for last block: */
379 if (!block
->successors
[0])
382 /* NOTE that we may or may not have inserted the jump
383 * in the target block yet, so conditions to resolve
384 * the dest to the dest block's successor are:
386 * (1) successor[1] == NULL &&
387 * (2) (block-is-empty || only-instr-is-jump)
389 if (block
->successors
[1] == NULL
) {
390 if (list_empty(&block
->instr_list
)) {
391 return block
->successors
[0];
392 } else if (list_length(&block
->instr_list
) == 1) {
393 struct ir3_instruction
*instr
= list_first_entry(
394 &block
->instr_list
, struct ir3_instruction
, node
);
395 if (instr
->opc
== OPC_JUMP
)
396 return block
->successors
[0];
403 resolve_jump(struct ir3_instruction
*instr
)
405 struct ir3_block
*tblock
=
406 resolve_dest_block(instr
->cat0
.target
);
407 struct ir3_instruction
*target
;
409 if (tblock
!= instr
->cat0
.target
) {
410 list_delinit(&instr
->cat0
.target
->node
);
411 instr
->cat0
.target
= tblock
;
415 target
= list_first_entry(&tblock
->instr_list
,
416 struct ir3_instruction
, node
);
418 /* TODO maybe a less fragile way to do this. But we are expecting
419 * a pattern from sched_block() that looks like:
421 * br !p0.x, #else-block
424 * if the first branch target is +2, or if 2nd branch target is +1
425 * then we can just drop the jump.
428 if (instr
->cat0
.inv
== true)
433 if ((!target
) || (target
->ip
== (instr
->ip
+ next_block
))) {
434 list_delinit(&instr
->node
);
438 (int)target
->ip
- (int)instr
->ip
;
443 /* resolve jumps, removing jumps/branches to immediately following
444 * instruction which we end up with from earlier stages. Since
445 * removing an instruction can invalidate earlier instruction's
446 * branch offsets, we need to do this iteratively until no more
447 * branches are removed.
450 resolve_jumps(struct ir3
*ir
)
452 list_for_each_entry (struct ir3_block
, block
, &ir
->block_list
, node
)
453 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
)
454 if (is_flow(instr
) && instr
->cat0
.target
)
455 if (resolve_jump(instr
))
461 /* we want to mark points where divergent flow control re-converges
462 * with (jp) flags. For now, since we don't do any optimization for
463 * things that start out as a 'do {} while()', re-convergence points
464 * will always be a branch or jump target. Note that this is overly
465 * conservative, since unconditional jump targets are not convergence
466 * points, we are just assuming that the other path to reach the jump
467 * target was divergent. If we were clever enough to optimize the
468 * jump at end of a loop back to a conditional branch into a single
469 * conditional branch, ie. like:
471 * add.f r1.w, r0.x, (neg)(r)c2.x <= loop start
472 * mul.f r1.z, r1.z, r0.x
473 * mul.f r1.y, r1.y, r0.x
474 * mul.f r0.z, r1.x, r0.x
475 * mul.f r0.w, r0.y, r0.x
476 * cmps.f.ge r0.x, (r)c2.y, (r)r1.w
477 * add.s r0.x, (r)r0.x, (r)-1
478 * sel.f32 r0.x, (r)c3.y, (r)r0.x, c3.x
479 * cmps.f.eq p0.x, r0.x, c3.y
480 * mov.f32f32 r0.x, r1.w
481 * mov.f32f32 r0.y, r0.w
482 * mov.f32f32 r1.x, r0.z
485 * (jp)mul.f r0.x, c263.y, r1.y
487 * Then we'd have to be more clever, as the convergence point is no
488 * longer a branch or jump target.
491 mark_convergence_points(struct ir3
*ir
)
493 list_for_each_entry (struct ir3_block
, block
, &ir
->block_list
, node
) {
494 list_for_each_entry (struct ir3_instruction
, instr
, &block
->instr_list
, node
) {
495 if (is_flow(instr
) && instr
->cat0
.target
) {
496 struct ir3_instruction
*target
=
497 list_first_entry(&instr
->cat0
.target
->instr_list
,
498 struct ir3_instruction
, node
);
499 target
->flags
|= IR3_INSTR_JP
;
506 ir3_legalize(struct ir3
*ir
, bool *has_ssbo
, bool *need_pixlod
, int *max_bary
)
508 struct ir3_legalize_ctx
*ctx
= rzalloc(ir
, struct ir3_legalize_ctx
);
512 ctx
->compiler
= ir
->compiler
;
513 ctx
->type
= ir
->type
;
515 /* allocate per-block data: */
516 list_for_each_entry (struct ir3_block
, block
, &ir
->block_list
, node
) {
517 block
->data
= rzalloc(ctx
, struct ir3_legalize_block_data
);
520 /* process each block: */
523 list_for_each_entry (struct ir3_block
, block
, &ir
->block_list
, node
) {
524 progress
|= legalize_block(ctx
, block
);
528 *has_ssbo
= ctx
->has_ssbo
;
529 *need_pixlod
= ctx
->need_pixlod
;
530 *max_bary
= ctx
->max_bary
;
533 ir3_count_instructions(ir
);
534 } while(resolve_jumps(ir
));
536 mark_convergence_points(ir
);