2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "util/ralloc.h"
28 #include "util/u_math.h"
31 #include "ir3_compiler.h"
36 * We currently require that scheduling ensures that we have enough nop's
37 * in all the right places. The legalize step mostly handles fixing up
38 * instruction flags ((ss)/(sy)/(ei)), and collapses sequences of nop's
39 * into fewer nop's w/ rpt flag.
42 struct ir3_legalize_ctx
{
43 struct ir3_compiler
*compiler
;
44 struct ir3_shader_variant
*so
;
49 struct ir3_legalize_state
{
51 regmask_t needs_ss_war
; /* write after read */
55 struct ir3_legalize_block_data
{
57 struct ir3_legalize_state state
;
60 /* We want to evaluate each block from the position of any other
61 * predecessor block, in order that the flags set are the union of
62 * all possible program paths.
64 * To do this, we need to know the output state (needs_ss/ss_war/sy)
65 * of all predecessor blocks. The tricky thing is loops, which mean
66 * that we can't simply recursively process each predecessor block
67 * before legalizing the current block.
69 * How we handle that is by looping over all the blocks until the
70 * results converge. If the output state of a given block changes
71 * in a given pass, this means that all successor blocks are not
72 * yet fully legalized.
76 legalize_block(struct ir3_legalize_ctx
*ctx
, struct ir3_block
*block
)
78 struct ir3_legalize_block_data
*bd
= block
->data
;
83 struct ir3_instruction
*last_input
= NULL
;
84 struct ir3_instruction
*last_rel
= NULL
;
85 struct ir3_instruction
*last_n
= NULL
;
86 struct list_head instr_list
;
87 struct ir3_legalize_state prev_state
= bd
->state
;
88 struct ir3_legalize_state
*state
= &bd
->state
;
89 bool last_input_needs_ss
= false;
90 bool has_tex_prefetch
= false;
92 /* our input state is the OR of all predecessor blocks' state: */
93 set_foreach(block
->predecessors
, entry
) {
94 struct ir3_block
*predecessor
= (struct ir3_block
*)entry
->key
;
95 struct ir3_legalize_block_data
*pbd
= predecessor
->data
;
96 struct ir3_legalize_state
*pstate
= &pbd
->state
;
98 /* Our input (ss)/(sy) state is based on OR'ing the output
99 * state of all our predecessor blocks
101 regmask_or(&state
->needs_ss
,
102 &state
->needs_ss
, &pstate
->needs_ss
);
103 regmask_or(&state
->needs_ss_war
,
104 &state
->needs_ss_war
, &pstate
->needs_ss_war
);
105 regmask_or(&state
->needs_sy
,
106 &state
->needs_sy
, &pstate
->needs_sy
);
109 /* remove all the instructions from the list, we'll be adding
110 * them back in as we go
112 list_replace(&block
->instr_list
, &instr_list
);
113 list_inithead(&block
->instr_list
);
115 foreach_instr_safe (n
, &instr_list
) {
116 struct ir3_register
*reg
;
119 n
->flags
&= ~(IR3_INSTR_SS
| IR3_INSTR_SY
);
121 /* _meta::tex_prefetch instructions removed later in
122 * collect_tex_prefetches()
124 if (is_meta(n
) && (n
->opc
!= OPC_META_TEX_PREFETCH
))
128 struct ir3_register
*inloc
= n
->regs
[1];
129 assert(inloc
->flags
& IR3_REG_IMMED
);
130 ctx
->max_bary
= MAX2(ctx
->max_bary
, inloc
->iim_val
);
133 if (last_n
&& is_barrier(last_n
)) {
134 n
->flags
|= IR3_INSTR_SS
| IR3_INSTR_SY
;
135 last_input_needs_ss
= false;
136 regmask_init(&state
->needs_ss_war
);
137 regmask_init(&state
->needs_ss
);
138 regmask_init(&state
->needs_sy
);
141 if (last_n
&& (last_n
->opc
== OPC_IF
)) {
142 n
->flags
|= IR3_INSTR_SS
;
143 regmask_init(&state
->needs_ss_war
);
144 regmask_init(&state
->needs_ss
);
147 /* NOTE: consider dst register too.. it could happen that
148 * texture sample instruction (for example) writes some
149 * components which are unused. A subsequent instruction
150 * that writes the same register can race w/ the sam instr
151 * resulting in undefined results:
153 for (i
= 0; i
< n
->regs_count
; i
++) {
158 /* TODO: we probably only need (ss) for alu
159 * instr consuming sfu result.. need to make
160 * some tests for both this and (sy)..
162 if (regmask_get(&state
->needs_ss
, reg
)) {
163 n
->flags
|= IR3_INSTR_SS
;
164 last_input_needs_ss
= false;
165 regmask_init(&state
->needs_ss_war
);
166 regmask_init(&state
->needs_ss
);
169 if (regmask_get(&state
->needs_sy
, reg
)) {
170 n
->flags
|= IR3_INSTR_SY
;
171 regmask_init(&state
->needs_sy
);
175 /* TODO: is it valid to have address reg loaded from a
176 * relative src (ie. mova a0, c<a0.x+4>)? If so, the
177 * last_rel check below should be moved ahead of this:
179 if (reg
->flags
& IR3_REG_RELATIV
)
183 if (n
->regs_count
> 0) {
185 if (regmask_get(&state
->needs_ss_war
, reg
)) {
186 n
->flags
|= IR3_INSTR_SS
;
187 last_input_needs_ss
= false;
188 regmask_init(&state
->needs_ss_war
);
189 regmask_init(&state
->needs_ss
);
192 if (last_rel
&& (reg
->num
== regid(REG_A0
, 0))) {
193 last_rel
->flags
|= IR3_INSTR_UL
;
198 /* cat5+ does not have an (ss) bit, if needed we need to
199 * insert a nop to carry the sync flag. Would be kinda
200 * clever if we were aware of this during scheduling, but
201 * this should be a pretty rare case:
203 if ((n
->flags
& IR3_INSTR_SS
) && (opc_cat(n
->opc
) >= 5)) {
204 struct ir3_instruction
*nop
;
205 nop
= ir3_NOP(block
);
206 nop
->flags
|= IR3_INSTR_SS
;
207 n
->flags
&= ~IR3_INSTR_SS
;
210 /* need to be able to set (ss) on first instruction: */
211 if (list_is_empty(&block
->instr_list
) && (opc_cat(n
->opc
) >= 5))
214 if (ctx
->compiler
->samgq_workaround
&&
215 ctx
->type
== MESA_SHADER_VERTEX
&& n
->opc
== OPC_SAMGQ
) {
216 struct ir3_instruction
*samgp
;
218 list_delinit(&n
->node
);
220 for (i
= 0; i
< 4; i
++) {
221 samgp
= ir3_instr_clone(n
);
222 samgp
->opc
= OPC_SAMGP0
+ i
;
224 samgp
->flags
|= IR3_INSTR_SY
;
227 list_addtail(&n
->node
, &block
->instr_list
);
230 if (n
->opc
== OPC_DSXPP_1
|| n
->opc
== OPC_DSYPP_1
) {
231 struct ir3_instruction
*op_p
= ir3_instr_clone(n
);
232 op_p
->flags
= IR3_INSTR_P
;
234 ctx
->so
->need_fine_derivatives
= true;
238 regmask_set(&state
->needs_ss
, n
->regs
[0]);
240 if (is_tex_or_prefetch(n
)) {
241 regmask_set(&state
->needs_sy
, n
->regs
[0]);
242 if (n
->opc
== OPC_META_TEX_PREFETCH
)
243 has_tex_prefetch
= true;
244 } else if (n
->opc
== OPC_RESINFO
) {
245 regmask_set(&state
->needs_ss
, n
->regs
[0]);
246 ir3_NOP(block
)->flags
|= IR3_INSTR_SS
;
247 last_input_needs_ss
= false;
248 } else if (is_load(n
)) {
249 /* seems like ldlv needs (ss) bit instead?? which is odd but
250 * makes a bunch of flat-varying tests start working on a4xx.
252 if ((n
->opc
== OPC_LDLV
) || (n
->opc
== OPC_LDL
) || (n
->opc
== OPC_LDLW
))
253 regmask_set(&state
->needs_ss
, n
->regs
[0]);
255 regmask_set(&state
->needs_sy
, n
->regs
[0]);
256 } else if (is_atomic(n
->opc
)) {
257 if (n
->flags
& IR3_INSTR_G
) {
258 if (ctx
->compiler
->gpu_id
>= 600) {
259 /* New encoding, returns result via second src: */
260 regmask_set(&state
->needs_sy
, n
->regs
[3]);
262 regmask_set(&state
->needs_sy
, n
->regs
[0]);
265 regmask_set(&state
->needs_ss
, n
->regs
[0]);
269 if (is_ssbo(n
->opc
) || (is_atomic(n
->opc
) && (n
->flags
& IR3_INSTR_G
)))
270 ctx
->so
->has_ssbo
= true;
272 /* both tex/sfu appear to not always immediately consume
273 * their src register(s):
275 if (is_tex(n
) || is_sfu(n
) || is_mem(n
)) {
276 foreach_src (reg
, n
) {
278 regmask_set(&state
->needs_ss_war
, reg
);
284 last_input_needs_ss
|= (n
->opc
== OPC_LDLV
);
291 assert(block
== list_first_entry(&block
->shader
->block_list
,
292 struct ir3_block
, node
));
293 /* special hack.. if using ldlv to bypass interpolation,
294 * we need to insert a dummy bary.f on which we can set
297 if (is_mem(last_input
) && (last_input
->opc
== OPC_LDLV
)) {
298 struct ir3_instruction
*baryf
;
300 /* (ss)bary.f (ei)r63.x, 0, r0.x */
301 baryf
= ir3_instr_create(block
, OPC_BARY_F
);
302 ir3_reg_create(baryf
, regid(63, 0), 0);
303 ir3_reg_create(baryf
, 0, IR3_REG_IMMED
)->iim_val
= 0;
304 ir3_reg_create(baryf
, regid(0, 0), 0);
306 /* insert the dummy bary.f after last_input: */
307 list_delinit(&baryf
->node
);
308 list_add(&baryf
->node
, &last_input
->node
);
312 /* by definition, we need (ss) since we are inserting
313 * the dummy bary.f immediately after the ldlv:
315 last_input_needs_ss
= true;
317 last_input
->regs
[0]->flags
|= IR3_REG_EI
;
318 if (last_input_needs_ss
)
319 last_input
->flags
|= IR3_INSTR_SS
;
320 } else if (has_tex_prefetch
) {
321 /* texture prefetch, but *no* inputs.. we need to insert a
322 * dummy bary.f at the top of the shader to unblock varying
325 struct ir3_instruction
*baryf
;
327 /* (ss)bary.f (ei)r63.x, 0, r0.x */
328 baryf
= ir3_instr_create(block
, OPC_BARY_F
);
329 ir3_reg_create(baryf
, regid(63, 0), 0)->flags
|= IR3_REG_EI
;
330 ir3_reg_create(baryf
, 0, IR3_REG_IMMED
)->iim_val
= 0;
331 ir3_reg_create(baryf
, regid(0, 0), 0);
333 /* insert the dummy bary.f at head: */
334 list_delinit(&baryf
->node
);
335 list_add(&baryf
->node
, &block
->instr_list
);
339 last_rel
->flags
|= IR3_INSTR_UL
;
343 if (memcmp(&prev_state
, state
, sizeof(*state
))) {
344 /* our output state changed, this invalidates all of our
347 for (unsigned i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
348 if (!block
->successors
[i
])
350 struct ir3_legalize_block_data
*pbd
= block
->successors
[i
]->data
;
358 /* NOTE: branch instructions are always the last instruction(s)
359 * in the block. We take advantage of this as we resolve the
360 * branches, since "if (foo) break;" constructs turn into
365 * 0029:021: mov.s32s32 r62.x, r1.y
366 * 0082:022: br !p0.x, target=block5
367 * 0083:023: br p0.x, target=block4
368 * // succs: if _[0029:021: mov.s32s32] block4; else block5;
371 * 0084:024: jump, target=block6
375 * 0085:025: jump, target=block7
379 * ie. only instruction in block4/block5 is a jump, so when
380 * resolving branches we can easily detect this by checking
381 * that the first instruction in the target block is itself
382 * a jump, and setup the br directly to the jump's target
383 * (and strip back out the now unreached jump)
385 * TODO sometimes we end up with things like:
389 * add.u r0.y, r0.y, 1
391 * If we swapped the order of the branches, we could drop one.
393 static struct ir3_block
*
394 resolve_dest_block(struct ir3_block
*block
)
396 /* special case for last block: */
397 if (!block
->successors
[0])
400 /* NOTE that we may or may not have inserted the jump
401 * in the target block yet, so conditions to resolve
402 * the dest to the dest block's successor are:
404 * (1) successor[1] == NULL &&
405 * (2) (block-is-empty || only-instr-is-jump)
407 if (block
->successors
[1] == NULL
) {
408 if (list_is_empty(&block
->instr_list
)) {
409 return block
->successors
[0];
410 } else if (list_length(&block
->instr_list
) == 1) {
411 struct ir3_instruction
*instr
= list_first_entry(
412 &block
->instr_list
, struct ir3_instruction
, node
);
413 if (instr
->opc
== OPC_JUMP
)
414 return block
->successors
[0];
421 remove_unused_block(struct ir3_block
*old_target
)
423 list_delinit(&old_target
->node
);
425 /* cleanup dangling predecessors: */
426 for (unsigned i
= 0; i
< ARRAY_SIZE(old_target
->successors
); i
++) {
427 if (old_target
->successors
[i
]) {
428 struct ir3_block
*succ
= old_target
->successors
[i
];
429 _mesa_set_remove_key(succ
->predecessors
, old_target
);
435 retarget_jump(struct ir3_instruction
*instr
, struct ir3_block
*new_target
)
437 struct ir3_block
*old_target
= instr
->cat0
.target
;
438 struct ir3_block
*cur_block
= instr
->block
;
440 /* update current blocks successors to reflect the retargetting: */
441 if (cur_block
->successors
[0] == old_target
) {
442 cur_block
->successors
[0] = new_target
;
444 debug_assert(cur_block
->successors
[1] == old_target
);
445 cur_block
->successors
[1] = new_target
;
448 /* update new target's predecessors: */
449 _mesa_set_add(new_target
->predecessors
, cur_block
);
451 /* and remove old_target's predecessor: */
452 debug_assert(_mesa_set_search(old_target
->predecessors
, cur_block
));
453 _mesa_set_remove_key(old_target
->predecessors
, cur_block
);
455 if (old_target
->predecessors
->entries
== 0)
456 remove_unused_block(old_target
);
458 instr
->cat0
.target
= new_target
;
462 resolve_jump(struct ir3_instruction
*instr
)
464 struct ir3_block
*tblock
=
465 resolve_dest_block(instr
->cat0
.target
);
466 struct ir3_instruction
*target
;
468 if (tblock
!= instr
->cat0
.target
) {
469 retarget_jump(instr
, tblock
);
473 target
= list_first_entry(&tblock
->instr_list
,
474 struct ir3_instruction
, node
);
476 /* TODO maybe a less fragile way to do this. But we are expecting
477 * a pattern from sched_block() that looks like:
479 * br !p0.x, #else-block
482 * if the first branch target is +2, or if 2nd branch target is +1
483 * then we can just drop the jump.
486 if (instr
->cat0
.inv
== true)
491 if (target
->ip
== (instr
->ip
+ next_block
)) {
492 list_delinit(&instr
->node
);
496 (int)target
->ip
- (int)instr
->ip
;
501 /* resolve jumps, removing jumps/branches to immediately following
502 * instruction which we end up with from earlier stages. Since
503 * removing an instruction can invalidate earlier instruction's
504 * branch offsets, we need to do this iteratively until no more
505 * branches are removed.
508 resolve_jumps(struct ir3
*ir
)
510 foreach_block (block
, &ir
->block_list
)
511 foreach_instr (instr
, &block
->instr_list
)
512 if (is_flow(instr
) && instr
->cat0
.target
)
513 if (resolve_jump(instr
))
519 static void mark_jp(struct ir3_block
*block
)
521 struct ir3_instruction
*target
= list_first_entry(&block
->instr_list
,
522 struct ir3_instruction
, node
);
523 target
->flags
|= IR3_INSTR_JP
;
526 /* Mark points where control flow converges or diverges.
528 * Divergence points could actually be re-convergence points where
529 * "parked" threads are recoverged with threads that took the opposite
530 * path last time around. Possibly it is easier to think of (jp) as
531 * "the execution mask might have changed".
534 mark_xvergence_points(struct ir3
*ir
)
536 foreach_block (block
, &ir
->block_list
) {
537 if (block
->predecessors
->entries
> 1) {
538 /* if a block has more than one possible predecessor, then
539 * the first instruction is a convergence point.
542 } else if (block
->predecessors
->entries
== 1) {
543 /* If a block has one predecessor, which has multiple possible
544 * successors, it is a divergence point.
546 set_foreach(block
->predecessors
, entry
) {
547 struct ir3_block
*predecessor
= (struct ir3_block
*)entry
->key
;
548 if (predecessor
->successors
[1]) {
556 /* Insert the branch/jump instructions for flow control between blocks.
557 * Initially this is done naively, without considering if the successor
558 * block immediately follows the current block (ie. so no jump required),
559 * but that is cleaned up in resolve_jumps().
561 * TODO what ensures that the last write to p0.x in a block is the
562 * branch condition? Have we been getting lucky all this time?
565 block_sched(struct ir3
*ir
)
567 foreach_block (block
, &ir
->block_list
) {
568 if (block
->successors
[1]) {
569 /* if/else, conditional branches to "then" or "else": */
570 struct ir3_instruction
*br
;
572 debug_assert(block
->condition
);
574 /* create "else" branch first (since "then" block should
575 * frequently/always end up being a fall-thru):
577 br
= ir3_BR(block
, block
->condition
, 0);
579 br
->cat0
.target
= block
->successors
[1];
582 br
= ir3_BR(block
, block
->condition
, 0);
583 br
->cat0
.target
= block
->successors
[0];
585 } else if (block
->successors
[0]) {
586 /* otherwise unconditional jump to next block: */
587 struct ir3_instruction
*jmp
;
589 jmp
= ir3_JUMP(block
);
590 jmp
->cat0
.target
= block
->successors
[0];
595 /* Insert nop's required to make this a legal/valid shader program: */
597 nop_sched(struct ir3
*ir
)
599 foreach_block (block
, &ir
->block_list
) {
600 struct ir3_instruction
*last
= NULL
;
601 struct list_head instr_list
;
603 /* remove all the instructions from the list, we'll be adding
604 * them back in as we go
606 list_replace(&block
->instr_list
, &instr_list
);
607 list_inithead(&block
->instr_list
);
609 foreach_instr_safe (instr
, &instr_list
) {
610 unsigned delay
= ir3_delay_calc(block
, instr
, false, true);
612 /* NOTE: I think the nopN encoding works for a5xx and
613 * probably a4xx, but not a3xx. So far only tested on
617 if ((delay
> 0) && (ir
->compiler
->gpu_id
>= 600) && last
&&
618 ((opc_cat(last
->opc
) == 2) || (opc_cat(last
->opc
) == 3))) {
619 /* the previous cat2/cat3 instruction can encode at most 3 nop's: */
620 unsigned transfer
= MIN2(delay
, 3 - last
->nop
);
621 last
->nop
+= transfer
;
625 if ((delay
> 0) && last
&& (last
->opc
== OPC_NOP
)) {
626 /* the previous nop can encode at most 5 repeats: */
627 unsigned transfer
= MIN2(delay
, 5 - last
->repeat
);
628 last
->repeat
+= transfer
;
633 debug_assert(delay
<= 6);
634 ir3_NOP(block
)->repeat
= delay
- 1;
637 list_addtail(&instr
->node
, &block
->instr_list
);
644 ir3_legalize(struct ir3
*ir
, struct ir3_shader_variant
*so
, int *max_bary
)
646 struct ir3_legalize_ctx
*ctx
= rzalloc(ir
, struct ir3_legalize_ctx
);
651 ctx
->compiler
= ir
->compiler
;
652 ctx
->type
= ir
->type
;
654 /* allocate per-block data: */
655 foreach_block (block
, &ir
->block_list
) {
656 block
->data
= rzalloc(ctx
, struct ir3_legalize_block_data
);
661 /* process each block: */
664 foreach_block (block
, &ir
->block_list
) {
665 progress
|= legalize_block(ctx
, block
);
669 *max_bary
= ctx
->max_bary
;
675 ir3_count_instructions(ir
);
676 } while(resolve_jumps(ir
));
678 mark_xvergence_points(ir
);