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[mesa.git] / src / freedreno / ir3 / ir3_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27
28 #include "util/debug.h"
29 #include "util/u_math.h"
30
31 #include "ir3_nir.h"
32 #include "ir3_compiler.h"
33 #include "ir3_shader.h"
34
35 static void ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir);
36
37 static const nir_shader_compiler_options options = {
38 .lower_fpow = true,
39 .lower_scmp = true,
40 .lower_flrp16 = true,
41 .lower_flrp32 = true,
42 .lower_flrp64 = true,
43 .lower_ffract = true,
44 .lower_fmod = true,
45 .lower_fdiv = true,
46 .lower_isign = true,
47 .lower_ldexp = true,
48 .lower_uadd_carry = true,
49 .lower_usub_borrow = true,
50 .lower_mul_high = true,
51 .lower_mul_2x32_64 = true,
52 .fuse_ffma = true,
53 .vertex_id_zero_based = true,
54 .lower_extract_byte = true,
55 .lower_extract_word = true,
56 .lower_all_io_to_elements = true,
57 .lower_helper_invocation = true,
58 .lower_bitfield_insert_to_shifts = true,
59 .lower_bitfield_extract_to_shifts = true,
60 .lower_pack_half_2x16 = true,
61 .lower_pack_snorm_4x8 = true,
62 .lower_pack_snorm_2x16 = true,
63 .lower_pack_unorm_4x8 = true,
64 .lower_pack_unorm_2x16 = true,
65 .lower_unpack_half_2x16 = true,
66 .lower_unpack_snorm_4x8 = true,
67 .lower_unpack_snorm_2x16 = true,
68 .lower_unpack_unorm_4x8 = true,
69 .lower_unpack_unorm_2x16 = true,
70 .lower_pack_split = true,
71 .use_interpolated_input_intrinsics = true,
72 .lower_rotate = true,
73 .lower_to_scalar = true,
74 .has_imul24 = true,
75 };
76
77 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
78 static const nir_shader_compiler_options options_a6xx = {
79 .lower_fpow = true,
80 .lower_scmp = true,
81 .lower_flrp16 = true,
82 .lower_flrp32 = true,
83 .lower_flrp64 = true,
84 .lower_ffract = true,
85 .lower_fmod = true,
86 .lower_fdiv = true,
87 .lower_isign = true,
88 .lower_ldexp = true,
89 .lower_uadd_carry = true,
90 .lower_usub_borrow = true,
91 .lower_mul_high = true,
92 .lower_mul_2x32_64 = true,
93 .fuse_ffma = true,
94 .vertex_id_zero_based = false,
95 .lower_extract_byte = true,
96 .lower_extract_word = true,
97 .lower_all_io_to_elements = true,
98 .lower_helper_invocation = true,
99 .lower_bitfield_insert_to_shifts = true,
100 .lower_bitfield_extract_to_shifts = true,
101 .lower_pack_half_2x16 = true,
102 .lower_pack_snorm_4x8 = true,
103 .lower_pack_snorm_2x16 = true,
104 .lower_pack_unorm_4x8 = true,
105 .lower_pack_unorm_2x16 = true,
106 .lower_unpack_half_2x16 = true,
107 .lower_unpack_snorm_4x8 = true,
108 .lower_unpack_snorm_2x16 = true,
109 .lower_unpack_unorm_4x8 = true,
110 .lower_unpack_unorm_2x16 = true,
111 .lower_pack_split = true,
112 .use_interpolated_input_intrinsics = true,
113 .lower_rotate = true,
114 .vectorize_io = true,
115 .lower_to_scalar = true,
116 .has_imul24 = true,
117 .max_unroll_iterations = 32,
118 };
119
120 const nir_shader_compiler_options *
121 ir3_get_compiler_options(struct ir3_compiler *compiler)
122 {
123 if (compiler->gpu_id >= 600)
124 return &options_a6xx;
125 return &options;
126 }
127
128 /* for given shader key, are any steps handled in nir? */
129 bool
130 ir3_key_lowers_nir(const struct ir3_shader_key *key)
131 {
132 return key->fsaturate_s | key->fsaturate_t | key->fsaturate_r |
133 key->vsaturate_s | key->vsaturate_t | key->vsaturate_r |
134 key->ucp_enables | key->color_two_side |
135 key->fclamp_color | key->vclamp_color |
136 key->tessellation | key->has_gs;
137 }
138
139 #define OPT(nir, pass, ...) ({ \
140 bool this_progress = false; \
141 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
142 this_progress; \
143 })
144
145 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
146
147 static void
148 ir3_optimize_loop(nir_shader *s)
149 {
150 bool progress;
151 unsigned lower_flrp =
152 (s->options->lower_flrp16 ? 16 : 0) |
153 (s->options->lower_flrp32 ? 32 : 0) |
154 (s->options->lower_flrp64 ? 64 : 0);
155
156 do {
157 progress = false;
158
159 OPT_V(s, nir_lower_vars_to_ssa);
160 progress |= OPT(s, nir_opt_copy_prop_vars);
161 progress |= OPT(s, nir_opt_dead_write_vars);
162 progress |= OPT(s, nir_lower_alu_to_scalar, NULL, NULL);
163 progress |= OPT(s, nir_lower_phis_to_scalar);
164
165 progress |= OPT(s, nir_copy_prop);
166 progress |= OPT(s, nir_opt_dce);
167 progress |= OPT(s, nir_opt_cse);
168 static int gcm = -1;
169 if (gcm == -1)
170 gcm = env_var_as_unsigned("GCM", 0);
171 if (gcm == 1)
172 progress |= OPT(s, nir_opt_gcm, true);
173 else if (gcm == 2)
174 progress |= OPT(s, nir_opt_gcm, false);
175 progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
176 progress |= OPT(s, nir_opt_intrinsics);
177 progress |= OPT(s, nir_opt_algebraic);
178 progress |= OPT(s, nir_lower_alu);
179 progress |= OPT(s, nir_opt_constant_folding);
180
181 if (lower_flrp != 0) {
182 if (OPT(s, nir_lower_flrp,
183 lower_flrp,
184 false /* always_precise */,
185 s->options->lower_ffma)) {
186 OPT(s, nir_opt_constant_folding);
187 progress = true;
188 }
189
190 /* Nothing should rematerialize any flrps, so we only
191 * need to do this lowering once.
192 */
193 lower_flrp = 0;
194 }
195
196 progress |= OPT(s, nir_opt_dead_cf);
197 if (OPT(s, nir_opt_trivial_continues)) {
198 progress |= true;
199 /* If nir_opt_trivial_continues makes progress, then we need to clean
200 * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
201 * to make progress.
202 */
203 OPT(s, nir_copy_prop);
204 OPT(s, nir_opt_dce);
205 }
206 progress |= OPT(s, nir_opt_if, false);
207 progress |= OPT(s, nir_opt_remove_phis);
208 progress |= OPT(s, nir_opt_undef);
209 } while (progress);
210 }
211
212 void
213 ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
214 const struct ir3_shader_key *key)
215 {
216 struct nir_lower_tex_options tex_options = {
217 .lower_rect = 0,
218 .lower_tg4_offsets = true,
219 };
220
221 if (key && (key->has_gs || key->tessellation)) {
222 switch (shader->type) {
223 case MESA_SHADER_VERTEX:
224 NIR_PASS_V(s, ir3_nir_lower_to_explicit_io, shader, key->tessellation);
225 break;
226 case MESA_SHADER_TESS_CTRL:
227 NIR_PASS_V(s, ir3_nir_lower_tess_ctrl, shader, key->tessellation);
228 break;
229 case MESA_SHADER_TESS_EVAL:
230 NIR_PASS_V(s, ir3_nir_lower_tess_eval, key->tessellation);
231 if (key->has_gs)
232 NIR_PASS_V(s, ir3_nir_lower_to_explicit_io, shader, key->tessellation);
233 break;
234 case MESA_SHADER_GEOMETRY:
235 NIR_PASS_V(s, ir3_nir_lower_gs, shader);
236 break;
237 default:
238 break;
239 }
240 }
241
242 if (key) {
243 switch (shader->type) {
244 case MESA_SHADER_FRAGMENT:
245 tex_options.saturate_s = key->fsaturate_s;
246 tex_options.saturate_t = key->fsaturate_t;
247 tex_options.saturate_r = key->fsaturate_r;
248 break;
249 case MESA_SHADER_VERTEX:
250 tex_options.saturate_s = key->vsaturate_s;
251 tex_options.saturate_t = key->vsaturate_t;
252 tex_options.saturate_r = key->vsaturate_r;
253 break;
254 default:
255 /* TODO */
256 break;
257 }
258 }
259
260 if (shader->compiler->gpu_id >= 400) {
261 /* a4xx seems to have *no* sam.p */
262 tex_options.lower_txp = ~0; /* lower all txp */
263 } else {
264 /* a3xx just needs to avoid sam.p for 3d tex */
265 tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
266 }
267
268 if (ir3_shader_debug & IR3_DBG_DISASM) {
269 debug_printf("----------------------\n");
270 nir_print_shader(s, stdout);
271 debug_printf("----------------------\n");
272 }
273
274 OPT_V(s, nir_lower_regs_to_ssa);
275 OPT_V(s, ir3_nir_lower_io_offsets);
276
277 if (key) {
278 if (s->info.stage == MESA_SHADER_VERTEX) {
279 OPT_V(s, nir_lower_clip_vs, key->ucp_enables, false, false, NULL);
280 if (key->vclamp_color)
281 OPT_V(s, nir_lower_clamp_color_outputs);
282 } else if (s->info.stage == MESA_SHADER_FRAGMENT) {
283 OPT_V(s, nir_lower_clip_fs, key->ucp_enables, false);
284 if (key->fclamp_color)
285 OPT_V(s, nir_lower_clamp_color_outputs);
286 }
287 if (key->color_two_side) {
288 OPT_V(s, nir_lower_two_sided_color);
289 }
290 } else {
291 /* only want to do this the first time (when key is null)
292 * and not again on any potential 2nd variant lowering pass:
293 */
294 OPT_V(s, ir3_nir_apply_trig_workarounds);
295
296 /* This wouldn't hurt to run multiple times, but there is
297 * no need to:
298 */
299 if (shader->type == MESA_SHADER_FRAGMENT)
300 OPT_V(s, nir_lower_fb_read);
301 }
302
303 OPT_V(s, nir_lower_tex, &tex_options);
304 OPT_V(s, nir_lower_load_const_to_scalar);
305 if (shader->compiler->gpu_id < 500)
306 OPT_V(s, ir3_nir_lower_tg4_to_tex);
307
308 ir3_optimize_loop(s);
309
310 /* do ubo load and idiv lowering after first opt loop to get a chance to
311 * propagate constants for divide by immed power-of-two and constant ubo
312 * block/offsets:
313 *
314 * NOTE that UBO analysis pass should only be done once, before variants
315 */
316 const bool ubo_progress = !key && OPT(s, ir3_nir_analyze_ubo_ranges, shader);
317 const bool idiv_progress = OPT(s, nir_lower_idiv, nir_lower_idiv_fast);
318 if (ubo_progress || idiv_progress)
319 ir3_optimize_loop(s);
320
321 /* Do late algebraic optimization to turn add(a, neg(b)) back into
322 * subs, then the mandatory cleanup after algebraic. Note that it may
323 * produce fnegs, and if so then we need to keep running to squash
324 * fneg(fneg(a)).
325 */
326 bool more_late_algebraic = true;
327 while (more_late_algebraic) {
328 more_late_algebraic = OPT(s, nir_opt_algebraic_late);
329 OPT_V(s, nir_opt_constant_folding);
330 OPT_V(s, nir_copy_prop);
331 OPT_V(s, nir_opt_dce);
332 OPT_V(s, nir_opt_cse);
333 }
334
335 OPT_V(s, nir_remove_dead_variables, nir_var_function_temp);
336
337 OPT_V(s, nir_opt_sink, nir_move_const_undef);
338
339 if (ir3_shader_debug & IR3_DBG_DISASM) {
340 debug_printf("----------------------\n");
341 nir_print_shader(s, stdout);
342 debug_printf("----------------------\n");
343 }
344
345 nir_sweep(s);
346
347 /* The first time thru, when not creating variant, do the one-time
348 * const_state layout setup. This should be done after ubo range
349 * analysis.
350 */
351 if (!key) {
352 ir3_setup_const_state(shader, s);
353 }
354 }
355
356 static void
357 ir3_nir_scan_driver_consts(nir_shader *shader,
358 struct ir3_const_state *layout)
359 {
360 nir_foreach_function (function, shader) {
361 if (!function->impl)
362 continue;
363
364 nir_foreach_block (block, function->impl) {
365 nir_foreach_instr (instr, block) {
366 if (instr->type != nir_instr_type_intrinsic)
367 continue;
368
369 nir_intrinsic_instr *intr =
370 nir_instr_as_intrinsic(instr);
371 unsigned idx;
372
373 switch (intr->intrinsic) {
374 case nir_intrinsic_get_buffer_size:
375 idx = nir_src_as_uint(intr->src[0]);
376 if (layout->ssbo_size.mask & (1 << idx))
377 break;
378 layout->ssbo_size.mask |= (1 << idx);
379 layout->ssbo_size.off[idx] =
380 layout->ssbo_size.count;
381 layout->ssbo_size.count += 1; /* one const per */
382 break;
383 case nir_intrinsic_image_atomic_add:
384 case nir_intrinsic_image_atomic_imin:
385 case nir_intrinsic_image_atomic_umin:
386 case nir_intrinsic_image_atomic_imax:
387 case nir_intrinsic_image_atomic_umax:
388 case nir_intrinsic_image_atomic_and:
389 case nir_intrinsic_image_atomic_or:
390 case nir_intrinsic_image_atomic_xor:
391 case nir_intrinsic_image_atomic_exchange:
392 case nir_intrinsic_image_atomic_comp_swap:
393 case nir_intrinsic_image_store:
394 case nir_intrinsic_image_size:
395 idx = nir_src_as_uint(intr->src[0]);
396 if (layout->image_dims.mask & (1 << idx))
397 break;
398 layout->image_dims.mask |= (1 << idx);
399 layout->image_dims.off[idx] =
400 layout->image_dims.count;
401 layout->image_dims.count += 3; /* three const per */
402 break;
403 case nir_intrinsic_load_ubo:
404 if (nir_src_is_const(intr->src[0])) {
405 layout->num_ubos = MAX2(layout->num_ubos,
406 nir_src_as_uint(intr->src[0]) + 1);
407 } else {
408 layout->num_ubos = shader->info.num_ubos;
409 }
410 break;
411 case nir_intrinsic_load_base_vertex:
412 case nir_intrinsic_load_first_vertex:
413 layout->num_driver_params =
414 MAX2(layout->num_driver_params, IR3_DP_VTXID_BASE + 1);
415 break;
416 case nir_intrinsic_load_base_instance:
417 layout->num_driver_params =
418 MAX2(layout->num_driver_params, IR3_DP_INSTID_BASE + 1);
419 break;
420 case nir_intrinsic_load_user_clip_plane:
421 layout->num_driver_params =
422 MAX2(layout->num_driver_params, IR3_DP_UCP7_W + 1);
423 break;
424 case nir_intrinsic_load_num_work_groups:
425 layout->num_driver_params =
426 MAX2(layout->num_driver_params, IR3_DP_NUM_WORK_GROUPS_Z + 1);
427 break;
428 case nir_intrinsic_load_local_group_size:
429 layout->num_driver_params =
430 MAX2(layout->num_driver_params, IR3_DP_LOCAL_GROUP_SIZE_Z + 1);
431 break;
432 default:
433 break;
434 }
435 }
436 }
437 }
438 }
439
440 static void
441 ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir)
442 {
443 struct ir3_compiler *compiler = shader->compiler;
444 struct ir3_const_state *const_state = &shader->const_state;
445
446 memset(&const_state->offsets, ~0, sizeof(const_state->offsets));
447
448 ir3_nir_scan_driver_consts(nir, const_state);
449
450 if ((compiler->gpu_id < 500) &&
451 (shader->stream_output.num_outputs > 0)) {
452 const_state->num_driver_params =
453 MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1);
454 }
455
456 /* num_driver_params is scalar, align to vec4: */
457 const_state->num_driver_params = align(const_state->num_driver_params, 4);
458
459 debug_assert((shader->ubo_state.size % 16) == 0);
460 unsigned constoff = align(shader->ubo_state.size / 16, 8);
461 unsigned ptrsz = ir3_pointer_size(compiler);
462
463 if (const_state->num_ubos > 0) {
464 const_state->offsets.ubo = constoff;
465 constoff += align(nir->info.num_ubos * ptrsz, 4) / 4;
466 }
467
468 if (const_state->ssbo_size.count > 0) {
469 unsigned cnt = const_state->ssbo_size.count;
470 const_state->offsets.ssbo_sizes = constoff;
471 constoff += align(cnt, 4) / 4;
472 }
473
474 if (const_state->image_dims.count > 0) {
475 unsigned cnt = const_state->image_dims.count;
476 const_state->offsets.image_dims = constoff;
477 constoff += align(cnt, 4) / 4;
478 }
479
480 if (const_state->num_driver_params > 0)
481 const_state->offsets.driver_param = constoff;
482 constoff += const_state->num_driver_params / 4;
483
484 if ((shader->type == MESA_SHADER_VERTEX) &&
485 (compiler->gpu_id < 500) &&
486 shader->stream_output.num_outputs > 0) {
487 const_state->offsets.tfbo = constoff;
488 constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
489 }
490
491 switch (shader->type) {
492 case MESA_SHADER_VERTEX:
493 const_state->offsets.primitive_param = constoff;
494 constoff += 1;
495 break;
496 case MESA_SHADER_TESS_CTRL:
497 case MESA_SHADER_TESS_EVAL:
498 constoff = align(constoff - 1, 4) + 3;
499 const_state->offsets.primitive_param = constoff;
500 const_state->offsets.primitive_map = constoff + 5;
501 constoff += 5 + DIV_ROUND_UP(nir->num_inputs, 4);
502 break;
503 case MESA_SHADER_GEOMETRY:
504 const_state->offsets.primitive_param = constoff;
505 const_state->offsets.primitive_map = constoff + 1;
506 constoff += 1 + DIV_ROUND_UP(nir->num_inputs, 4);
507 break;
508 default:
509 break;
510 }
511
512 const_state->offsets.immediate = constoff;
513 }