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[mesa.git] / src / freedreno / ir3 / ir3_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27
28 #include "util/debug.h"
29 #include "util/u_math.h"
30
31 #include "ir3_nir.h"
32 #include "ir3_compiler.h"
33 #include "ir3_shader.h"
34
35 static void ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir);
36
37 static const nir_shader_compiler_options options = {
38 .lower_fpow = true,
39 .lower_scmp = true,
40 .lower_flrp16 = true,
41 .lower_flrp32 = true,
42 .lower_flrp64 = true,
43 .lower_ffract = true,
44 .lower_fmod = true,
45 .lower_fdiv = true,
46 .lower_isign = true,
47 .lower_ldexp = true,
48 .lower_uadd_carry = true,
49 .lower_usub_borrow = true,
50 .lower_mul_high = true,
51 .lower_mul_2x32_64 = true,
52 .fuse_ffma = true,
53 .vertex_id_zero_based = true,
54 .lower_extract_byte = true,
55 .lower_extract_word = true,
56 .lower_all_io_to_elements = true,
57 .lower_helper_invocation = true,
58 .lower_bitfield_insert_to_shifts = true,
59 .lower_bitfield_extract_to_shifts = true,
60 .lower_pack_half_2x16 = true,
61 .lower_pack_half_2x16_split = true,
62 .lower_pack_snorm_4x8 = true,
63 .lower_pack_snorm_2x16 = true,
64 .lower_pack_unorm_4x8 = true,
65 .lower_pack_unorm_2x16 = true,
66 .lower_unpack_half_2x16 = true,
67 .lower_unpack_half_2x16_split = true,
68 .lower_unpack_snorm_4x8 = true,
69 .lower_unpack_snorm_2x16 = true,
70 .lower_unpack_unorm_4x8 = true,
71 .lower_unpack_unorm_2x16 = true,
72 .use_interpolated_input_intrinsics = true,
73 .lower_rotate = true,
74 .lower_to_scalar = true,
75 .has_imul24 = true,
76 };
77
78 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
79 static const nir_shader_compiler_options options_a6xx = {
80 .lower_fpow = true,
81 .lower_scmp = true,
82 .lower_flrp16 = true,
83 .lower_flrp32 = true,
84 .lower_flrp64 = true,
85 .lower_ffract = true,
86 .lower_fmod = true,
87 .lower_fdiv = true,
88 .lower_isign = true,
89 .lower_ldexp = true,
90 .lower_uadd_carry = true,
91 .lower_usub_borrow = true,
92 .lower_mul_high = true,
93 .lower_mul_2x32_64 = true,
94 .fuse_ffma = true,
95 .vertex_id_zero_based = false,
96 .lower_extract_byte = true,
97 .lower_extract_word = true,
98 .lower_all_io_to_elements = true,
99 .lower_helper_invocation = true,
100 .lower_bitfield_insert_to_shifts = true,
101 .lower_bitfield_extract_to_shifts = true,
102 .lower_pack_half_2x16 = true,
103 .lower_pack_half_2x16_split = true,
104 .lower_pack_snorm_4x8 = true,
105 .lower_pack_snorm_2x16 = true,
106 .lower_pack_unorm_4x8 = true,
107 .lower_pack_unorm_2x16 = true,
108 .lower_unpack_half_2x16 = true,
109 .lower_unpack_half_2x16_split = true,
110 .lower_unpack_snorm_4x8 = true,
111 .lower_unpack_snorm_2x16 = true,
112 .lower_unpack_unorm_4x8 = true,
113 .lower_unpack_unorm_2x16 = true,
114 .use_interpolated_input_intrinsics = true,
115 .lower_rotate = true,
116 .vectorize_io = true,
117 .lower_to_scalar = true,
118 .has_imul24 = true,
119 };
120
121 const nir_shader_compiler_options *
122 ir3_get_compiler_options(struct ir3_compiler *compiler)
123 {
124 if (compiler->gpu_id >= 600)
125 return &options_a6xx;
126 return &options;
127 }
128
129 /* for given shader key, are any steps handled in nir? */
130 bool
131 ir3_key_lowers_nir(const struct ir3_shader_key *key)
132 {
133 return key->fsaturate_s | key->fsaturate_t | key->fsaturate_r |
134 key->vsaturate_s | key->vsaturate_t | key->vsaturate_r |
135 key->ucp_enables | key->color_two_side |
136 key->fclamp_color | key->vclamp_color |
137 key->tessellation | key->has_gs;
138 }
139
140 #define OPT(nir, pass, ...) ({ \
141 bool this_progress = false; \
142 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
143 this_progress; \
144 })
145
146 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
147
148 static void
149 ir3_optimize_loop(nir_shader *s)
150 {
151 bool progress;
152 unsigned lower_flrp =
153 (s->options->lower_flrp16 ? 16 : 0) |
154 (s->options->lower_flrp32 ? 32 : 0) |
155 (s->options->lower_flrp64 ? 64 : 0);
156
157 do {
158 progress = false;
159
160 OPT_V(s, nir_lower_vars_to_ssa);
161 progress |= OPT(s, nir_opt_copy_prop_vars);
162 progress |= OPT(s, nir_opt_dead_write_vars);
163 progress |= OPT(s, nir_lower_alu_to_scalar, NULL, NULL);
164 progress |= OPT(s, nir_lower_phis_to_scalar);
165
166 progress |= OPT(s, nir_copy_prop);
167 progress |= OPT(s, nir_opt_dce);
168 progress |= OPT(s, nir_opt_cse);
169 static int gcm = -1;
170 if (gcm == -1)
171 gcm = env_var_as_unsigned("GCM", 0);
172 if (gcm == 1)
173 progress |= OPT(s, nir_opt_gcm, true);
174 else if (gcm == 2)
175 progress |= OPT(s, nir_opt_gcm, false);
176 progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
177 progress |= OPT(s, nir_opt_intrinsics);
178 progress |= OPT(s, nir_opt_algebraic);
179 progress |= OPT(s, nir_lower_alu);
180 progress |= OPT(s, nir_opt_constant_folding);
181
182 if (lower_flrp != 0) {
183 if (OPT(s, nir_lower_flrp,
184 lower_flrp,
185 false /* always_precise */,
186 s->options->lower_ffma)) {
187 OPT(s, nir_opt_constant_folding);
188 progress = true;
189 }
190
191 /* Nothing should rematerialize any flrps, so we only
192 * need to do this lowering once.
193 */
194 lower_flrp = 0;
195 }
196
197 progress |= OPT(s, nir_opt_dead_cf);
198 if (OPT(s, nir_opt_trivial_continues)) {
199 progress |= true;
200 /* If nir_opt_trivial_continues makes progress, then we need to clean
201 * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
202 * to make progress.
203 */
204 OPT(s, nir_copy_prop);
205 OPT(s, nir_opt_dce);
206 }
207 progress |= OPT(s, nir_opt_if, false);
208 progress |= OPT(s, nir_opt_remove_phis);
209 progress |= OPT(s, nir_opt_undef);
210
211 } while (progress);
212 }
213
214 void
215 ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
216 const struct ir3_shader_key *key)
217 {
218 struct nir_lower_tex_options tex_options = {
219 .lower_rect = 0,
220 .lower_tg4_offsets = true,
221 };
222
223 if (key && (key->has_gs || key->tessellation)) {
224 switch (shader->type) {
225 case MESA_SHADER_VERTEX:
226 NIR_PASS_V(s, ir3_nir_lower_to_explicit_io, shader, key->tessellation);
227 break;
228 case MESA_SHADER_TESS_CTRL:
229 NIR_PASS_V(s, ir3_nir_lower_tess_ctrl, shader, key->tessellation);
230 break;
231 case MESA_SHADER_TESS_EVAL:
232 NIR_PASS_V(s, ir3_nir_lower_tess_eval, key->tessellation);
233 if (key->has_gs)
234 NIR_PASS_V(s, ir3_nir_lower_to_explicit_io, shader, key->tessellation);
235 break;
236 case MESA_SHADER_GEOMETRY:
237 NIR_PASS_V(s, ir3_nir_lower_gs, shader);
238 break;
239 default:
240 break;
241 }
242 }
243
244 if (key) {
245 switch (shader->type) {
246 case MESA_SHADER_FRAGMENT:
247 tex_options.saturate_s = key->fsaturate_s;
248 tex_options.saturate_t = key->fsaturate_t;
249 tex_options.saturate_r = key->fsaturate_r;
250 break;
251 case MESA_SHADER_VERTEX:
252 tex_options.saturate_s = key->vsaturate_s;
253 tex_options.saturate_t = key->vsaturate_t;
254 tex_options.saturate_r = key->vsaturate_r;
255 break;
256 default:
257 /* TODO */
258 break;
259 }
260 }
261
262 if (shader->compiler->gpu_id >= 400) {
263 /* a4xx seems to have *no* sam.p */
264 tex_options.lower_txp = ~0; /* lower all txp */
265 } else {
266 /* a3xx just needs to avoid sam.p for 3d tex */
267 tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
268 }
269
270 if (ir3_shader_debug & IR3_DBG_DISASM) {
271 debug_printf("----------------------\n");
272 nir_print_shader(s, stdout);
273 debug_printf("----------------------\n");
274 }
275
276 OPT_V(s, nir_lower_regs_to_ssa);
277 OPT_V(s, ir3_nir_lower_io_offsets);
278
279 if (key) {
280 if (s->info.stage == MESA_SHADER_VERTEX) {
281 OPT_V(s, nir_lower_clip_vs, key->ucp_enables, false, false, NULL);
282 if (key->vclamp_color)
283 OPT_V(s, nir_lower_clamp_color_outputs);
284 } else if (s->info.stage == MESA_SHADER_FRAGMENT) {
285 OPT_V(s, nir_lower_clip_fs, key->ucp_enables, false);
286 if (key->fclamp_color)
287 OPT_V(s, nir_lower_clamp_color_outputs);
288 }
289 if (key->color_two_side) {
290 OPT_V(s, nir_lower_two_sided_color);
291 }
292 } else {
293 /* only want to do this the first time (when key is null)
294 * and not again on any potential 2nd variant lowering pass:
295 */
296 OPT_V(s, ir3_nir_apply_trig_workarounds);
297
298 /* This wouldn't hurt to run multiple times, but there is
299 * no need to:
300 */
301 if (shader->type == MESA_SHADER_FRAGMENT)
302 OPT_V(s, nir_lower_fb_read);
303 }
304
305 OPT_V(s, nir_lower_tex, &tex_options);
306 OPT_V(s, nir_lower_load_const_to_scalar);
307 if (shader->compiler->gpu_id < 500)
308 OPT_V(s, ir3_nir_lower_tg4_to_tex);
309
310 ir3_optimize_loop(s);
311
312 /* do ubo load and idiv lowering after first opt loop to get a chance to
313 * propagate constants for divide by immed power-of-two and constant ubo
314 * block/offsets:
315 *
316 * NOTE that UBO analysis pass should only be done once, before variants
317 */
318 const bool ubo_progress = !key && OPT(s, ir3_nir_analyze_ubo_ranges, shader);
319 const bool idiv_progress = OPT(s, nir_lower_idiv, nir_lower_idiv_fast);
320 if (ubo_progress || idiv_progress)
321 ir3_optimize_loop(s);
322
323 /* Do late algebraic optimization to turn add(a, neg(b)) back into
324 * subs, then the mandatory cleanup after algebraic. Note that it may
325 * produce fnegs, and if so then we need to keep running to squash
326 * fneg(fneg(a)).
327 */
328 bool more_late_algebraic = true;
329 while (more_late_algebraic) {
330 more_late_algebraic = OPT(s, nir_opt_algebraic_late);
331 OPT_V(s, nir_opt_constant_folding);
332 OPT_V(s, nir_copy_prop);
333 OPT_V(s, nir_opt_dce);
334 OPT_V(s, nir_opt_cse);
335 }
336
337 OPT_V(s, nir_remove_dead_variables, nir_var_function_temp);
338
339 OPT_V(s, nir_opt_sink, nir_move_const_undef);
340
341 if (ir3_shader_debug & IR3_DBG_DISASM) {
342 debug_printf("----------------------\n");
343 nir_print_shader(s, stdout);
344 debug_printf("----------------------\n");
345 }
346
347 nir_sweep(s);
348
349 /* The first time thru, when not creating variant, do the one-time
350 * const_state layout setup. This should be done after ubo range
351 * analysis.
352 */
353 if (!key) {
354 ir3_setup_const_state(shader, s);
355 }
356 }
357
358 static void
359 ir3_nir_scan_driver_consts(nir_shader *shader,
360 struct ir3_const_state *layout)
361 {
362 nir_foreach_function(function, shader) {
363 if (!function->impl)
364 continue;
365
366 nir_foreach_block(block, function->impl) {
367 nir_foreach_instr(instr, block) {
368 if (instr->type != nir_instr_type_intrinsic)
369 continue;
370
371 nir_intrinsic_instr *intr =
372 nir_instr_as_intrinsic(instr);
373 unsigned idx;
374
375 switch (intr->intrinsic) {
376 case nir_intrinsic_get_buffer_size:
377 idx = nir_src_as_uint(intr->src[0]);
378 if (layout->ssbo_size.mask & (1 << idx))
379 break;
380 layout->ssbo_size.mask |= (1 << idx);
381 layout->ssbo_size.off[idx] =
382 layout->ssbo_size.count;
383 layout->ssbo_size.count += 1; /* one const per */
384 break;
385 case nir_intrinsic_image_deref_atomic_add:
386 case nir_intrinsic_image_deref_atomic_imin:
387 case nir_intrinsic_image_deref_atomic_umin:
388 case nir_intrinsic_image_deref_atomic_imax:
389 case nir_intrinsic_image_deref_atomic_umax:
390 case nir_intrinsic_image_deref_atomic_and:
391 case nir_intrinsic_image_deref_atomic_or:
392 case nir_intrinsic_image_deref_atomic_xor:
393 case nir_intrinsic_image_deref_atomic_exchange:
394 case nir_intrinsic_image_deref_atomic_comp_swap:
395 case nir_intrinsic_image_deref_store:
396 case nir_intrinsic_image_deref_size:
397 idx = nir_intrinsic_get_var(intr, 0)->data.driver_location;
398 if (layout->image_dims.mask & (1 << idx))
399 break;
400 layout->image_dims.mask |= (1 << idx);
401 layout->image_dims.off[idx] =
402 layout->image_dims.count;
403 layout->image_dims.count += 3; /* three const per */
404 break;
405 case nir_intrinsic_load_ubo:
406 if (nir_src_is_const(intr->src[0])) {
407 layout->num_ubos = MAX2(layout->num_ubos,
408 nir_src_as_uint(intr->src[0]) + 1);
409 } else {
410 layout->num_ubos = shader->info.num_ubos;
411 }
412 break;
413 case nir_intrinsic_load_base_vertex:
414 case nir_intrinsic_load_first_vertex:
415 layout->num_driver_params =
416 MAX2(layout->num_driver_params, IR3_DP_VTXID_BASE + 1);
417 break;
418 case nir_intrinsic_load_user_clip_plane:
419 layout->num_driver_params =
420 MAX2(layout->num_driver_params, IR3_DP_UCP7_W + 1);
421 break;
422 case nir_intrinsic_load_num_work_groups:
423 layout->num_driver_params =
424 MAX2(layout->num_driver_params, IR3_DP_NUM_WORK_GROUPS_Z + 1);
425 break;
426 case nir_intrinsic_load_local_group_size:
427 layout->num_driver_params =
428 MAX2(layout->num_driver_params, IR3_DP_LOCAL_GROUP_SIZE_Z + 1);
429 break;
430 default:
431 break;
432 }
433 }
434 }
435 }
436 }
437
438 static void
439 ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir)
440 {
441 struct ir3_compiler *compiler = shader->compiler;
442 struct ir3_const_state *const_state = &shader->const_state;
443
444 memset(&const_state->offsets, ~0, sizeof(const_state->offsets));
445
446 ir3_nir_scan_driver_consts(nir, const_state);
447
448 if ((compiler->gpu_id < 500) &&
449 (shader->stream_output.num_outputs > 0)) {
450 const_state->num_driver_params =
451 MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1);
452 }
453
454 /* num_driver_params is scalar, align to vec4: */
455 const_state->num_driver_params = align(const_state->num_driver_params, 4);
456
457 debug_assert((shader->ubo_state.size % 16) == 0);
458 unsigned constoff = align(shader->ubo_state.size / 16, 8);
459 unsigned ptrsz = ir3_pointer_size(compiler);
460
461 if (const_state->num_ubos > 0) {
462 const_state->offsets.ubo = constoff;
463 constoff += align(nir->info.num_ubos * ptrsz, 4) / 4;
464 }
465
466 if (const_state->ssbo_size.count > 0) {
467 unsigned cnt = const_state->ssbo_size.count;
468 const_state->offsets.ssbo_sizes = constoff;
469 constoff += align(cnt, 4) / 4;
470 }
471
472 if (const_state->image_dims.count > 0) {
473 unsigned cnt = const_state->image_dims.count;
474 const_state->offsets.image_dims = constoff;
475 constoff += align(cnt, 4) / 4;
476 }
477
478 if (const_state->num_driver_params > 0)
479 const_state->offsets.driver_param = constoff;
480 constoff += const_state->num_driver_params / 4;
481
482 if ((shader->type == MESA_SHADER_VERTEX) &&
483 (compiler->gpu_id < 500) &&
484 shader->stream_output.num_outputs > 0) {
485 const_state->offsets.tfbo = constoff;
486 constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
487 }
488
489 switch (shader->type) {
490 case MESA_SHADER_VERTEX:
491 const_state->offsets.primitive_param = constoff;
492 constoff += 1;
493 break;
494 case MESA_SHADER_TESS_CTRL:
495 case MESA_SHADER_TESS_EVAL:
496 constoff = align(constoff - 1, 4) + 3;
497 const_state->offsets.primitive_param = constoff;
498 const_state->offsets.primitive_map = constoff + 5;
499 constoff += 5 + DIV_ROUND_UP(nir->num_inputs, 4);
500 break;
501 case MESA_SHADER_GEOMETRY:
502 const_state->offsets.primitive_param = constoff;
503 const_state->offsets.primitive_map = constoff + 1;
504 constoff += 1 + DIV_ROUND_UP(nir->num_inputs, 4);
505 break;
506 default:
507 break;
508 }
509
510 const_state->offsets.immediate = constoff;
511 }