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[mesa.git] / src / freedreno / ir3 / ir3_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27
28 #include "util/debug.h"
29 #include "util/u_math.h"
30
31 #include "ir3_nir.h"
32 #include "ir3_compiler.h"
33 #include "ir3_shader.h"
34
35 static void ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir);
36
37 static const nir_shader_compiler_options options = {
38 .lower_fpow = true,
39 .lower_scmp = true,
40 .lower_flrp32 = true,
41 .lower_flrp64 = true,
42 .lower_ffract = true,
43 .lower_fmod = true,
44 .lower_fdiv = true,
45 .lower_isign = true,
46 .lower_ldexp = true,
47 .lower_uadd_carry = true,
48 .lower_mul_high = true,
49 .fuse_ffma = true,
50 .vertex_id_zero_based = true,
51 .lower_extract_byte = true,
52 .lower_extract_word = true,
53 .lower_all_io_to_elements = true,
54 .lower_helper_invocation = true,
55 .lower_bitfield_insert_to_shifts = true,
56 .lower_bitfield_extract_to_shifts = true,
57 .use_interpolated_input_intrinsics = true,
58 .lower_rotate = true,
59 .lower_to_scalar = true,
60 .has_imul24 = true,
61 };
62
63 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
64 static const nir_shader_compiler_options options_a6xx = {
65 .lower_fpow = true,
66 .lower_scmp = true,
67 .lower_flrp32 = true,
68 .lower_flrp64 = true,
69 .lower_ffract = true,
70 .lower_fmod = true,
71 .lower_fdiv = true,
72 .lower_isign = true,
73 .lower_ldexp = true,
74 .lower_uadd_carry = true,
75 .lower_mul_high = true,
76 .fuse_ffma = true,
77 .vertex_id_zero_based = false,
78 .lower_extract_byte = true,
79 .lower_extract_word = true,
80 .lower_all_io_to_elements = true,
81 .lower_helper_invocation = true,
82 .lower_bitfield_insert_to_shifts = true,
83 .lower_bitfield_extract_to_shifts = true,
84 .use_interpolated_input_intrinsics = true,
85 .lower_rotate = true,
86 .vectorize_io = true,
87 .lower_to_scalar = true,
88 .has_imul24 = true,
89 };
90
91 const nir_shader_compiler_options *
92 ir3_get_compiler_options(struct ir3_compiler *compiler)
93 {
94 if (compiler->gpu_id >= 600)
95 return &options_a6xx;
96 return &options;
97 }
98
99 /* for given shader key, are any steps handled in nir? */
100 bool
101 ir3_key_lowers_nir(const struct ir3_shader_key *key)
102 {
103 return key->fsaturate_s | key->fsaturate_t | key->fsaturate_r |
104 key->vsaturate_s | key->vsaturate_t | key->vsaturate_r |
105 key->ucp_enables | key->color_two_side |
106 key->fclamp_color | key->vclamp_color |
107 key->has_gs;
108 }
109
110 #define OPT(nir, pass, ...) ({ \
111 bool this_progress = false; \
112 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
113 this_progress; \
114 })
115
116 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
117
118 static void
119 ir3_optimize_loop(nir_shader *s)
120 {
121 bool progress;
122 unsigned lower_flrp =
123 (s->options->lower_flrp16 ? 16 : 0) |
124 (s->options->lower_flrp32 ? 32 : 0) |
125 (s->options->lower_flrp64 ? 64 : 0);
126
127 do {
128 progress = false;
129
130 OPT_V(s, nir_lower_vars_to_ssa);
131 progress |= OPT(s, nir_opt_copy_prop_vars);
132 progress |= OPT(s, nir_opt_dead_write_vars);
133 progress |= OPT(s, nir_lower_alu_to_scalar, NULL, NULL);
134 progress |= OPT(s, nir_lower_phis_to_scalar);
135
136 progress |= OPT(s, nir_copy_prop);
137 progress |= OPT(s, nir_opt_dce);
138 progress |= OPT(s, nir_opt_cse);
139 static int gcm = -1;
140 if (gcm == -1)
141 gcm = env_var_as_unsigned("GCM", 0);
142 if (gcm == 1)
143 progress |= OPT(s, nir_opt_gcm, true);
144 else if (gcm == 2)
145 progress |= OPT(s, nir_opt_gcm, false);
146 progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
147 progress |= OPT(s, nir_opt_intrinsics);
148 progress |= OPT(s, nir_opt_algebraic);
149 progress |= OPT(s, nir_opt_constant_folding);
150
151 if (lower_flrp != 0) {
152 if (OPT(s, nir_lower_flrp,
153 lower_flrp,
154 false /* always_precise */,
155 s->options->lower_ffma)) {
156 OPT(s, nir_opt_constant_folding);
157 progress = true;
158 }
159
160 /* Nothing should rematerialize any flrps, so we only
161 * need to do this lowering once.
162 */
163 lower_flrp = 0;
164 }
165
166 progress |= OPT(s, nir_opt_dead_cf);
167 if (OPT(s, nir_opt_trivial_continues)) {
168 progress |= true;
169 /* If nir_opt_trivial_continues makes progress, then we need to clean
170 * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
171 * to make progress.
172 */
173 OPT(s, nir_copy_prop);
174 OPT(s, nir_opt_dce);
175 }
176 progress |= OPT(s, nir_opt_if, false);
177 progress |= OPT(s, nir_opt_remove_phis);
178 progress |= OPT(s, nir_opt_undef);
179
180 } while (progress);
181 }
182
183 void
184 ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
185 const struct ir3_shader_key *key)
186 {
187 struct nir_lower_tex_options tex_options = {
188 .lower_rect = 0,
189 .lower_tg4_offsets = true,
190 };
191
192 if (key && key->has_gs) {
193 switch (shader->type) {
194 case MESA_SHADER_VERTEX:
195 NIR_PASS_V(s, ir3_nir_lower_vs_to_explicit_io, shader);
196 break;
197 case MESA_SHADER_GEOMETRY:
198 NIR_PASS_V(s, ir3_nir_lower_gs, shader);
199 break;
200 default:
201 break;
202 }
203 }
204
205 if (key) {
206 switch (shader->type) {
207 case MESA_SHADER_FRAGMENT:
208 tex_options.saturate_s = key->fsaturate_s;
209 tex_options.saturate_t = key->fsaturate_t;
210 tex_options.saturate_r = key->fsaturate_r;
211 break;
212 case MESA_SHADER_VERTEX:
213 tex_options.saturate_s = key->vsaturate_s;
214 tex_options.saturate_t = key->vsaturate_t;
215 tex_options.saturate_r = key->vsaturate_r;
216 break;
217 default:
218 /* TODO */
219 break;
220 }
221 }
222
223 if (shader->compiler->gpu_id >= 400) {
224 /* a4xx seems to have *no* sam.p */
225 tex_options.lower_txp = ~0; /* lower all txp */
226 } else {
227 /* a3xx just needs to avoid sam.p for 3d tex */
228 tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
229 }
230
231 if (ir3_shader_debug & IR3_DBG_DISASM) {
232 debug_printf("----------------------\n");
233 nir_print_shader(s, stdout);
234 debug_printf("----------------------\n");
235 }
236
237 OPT_V(s, nir_lower_regs_to_ssa);
238 OPT_V(s, ir3_nir_lower_io_offsets);
239
240 if (key) {
241 if (s->info.stage == MESA_SHADER_VERTEX) {
242 OPT_V(s, nir_lower_clip_vs, key->ucp_enables, false, false, NULL);
243 if (key->vclamp_color)
244 OPT_V(s, nir_lower_clamp_color_outputs);
245 } else if (s->info.stage == MESA_SHADER_FRAGMENT) {
246 OPT_V(s, nir_lower_clip_fs, key->ucp_enables, false);
247 if (key->fclamp_color)
248 OPT_V(s, nir_lower_clamp_color_outputs);
249 }
250 if (key->color_two_side) {
251 OPT_V(s, nir_lower_two_sided_color);
252 }
253 } else {
254 /* only want to do this the first time (when key is null)
255 * and not again on any potential 2nd variant lowering pass:
256 */
257 OPT_V(s, ir3_nir_apply_trig_workarounds);
258
259 /* This wouldn't hurt to run multiple times, but there is
260 * no need to:
261 */
262 if (shader->type == MESA_SHADER_FRAGMENT)
263 OPT_V(s, nir_lower_fb_read);
264 }
265
266 OPT_V(s, nir_lower_tex, &tex_options);
267 OPT_V(s, nir_lower_load_const_to_scalar);
268 if (shader->compiler->gpu_id < 500)
269 OPT_V(s, ir3_nir_lower_tg4_to_tex);
270
271 ir3_optimize_loop(s);
272
273 /* do ubo load and idiv lowering after first opt loop to get a chance to
274 * propagate constants for divide by immed power-of-two and constant ubo
275 * block/offsets:
276 *
277 * NOTE that UBO analysis pass should only be done once, before variants
278 */
279 const bool ubo_progress = !key && OPT(s, ir3_nir_analyze_ubo_ranges, shader);
280 const bool idiv_progress = OPT(s, nir_lower_idiv);
281 if (ubo_progress || idiv_progress)
282 ir3_optimize_loop(s);
283
284 /* Do late algebraic optimization to turn add(a, neg(b)) back into
285 * subs, then the mandatory cleanup after algebraic. Note that it may
286 * produce fnegs, and if so then we need to keep running to squash
287 * fneg(fneg(a)).
288 */
289 bool more_late_algebraic = true;
290 while (more_late_algebraic) {
291 more_late_algebraic = OPT(s, nir_opt_algebraic_late);
292 OPT_V(s, nir_opt_constant_folding);
293 OPT_V(s, nir_copy_prop);
294 OPT_V(s, nir_opt_dce);
295 OPT_V(s, nir_opt_cse);
296 }
297
298 OPT_V(s, nir_remove_dead_variables, nir_var_function_temp);
299
300 OPT_V(s, nir_opt_sink, nir_move_const_undef);
301
302 if (ir3_shader_debug & IR3_DBG_DISASM) {
303 debug_printf("----------------------\n");
304 nir_print_shader(s, stdout);
305 debug_printf("----------------------\n");
306 }
307
308 nir_sweep(s);
309
310 /* The first time thru, when not creating variant, do the one-time
311 * const_state layout setup. This should be done after ubo range
312 * analysis.
313 */
314 if (!key) {
315 ir3_setup_const_state(shader, s);
316 }
317 }
318
319 static void
320 ir3_nir_scan_driver_consts(nir_shader *shader,
321 struct ir3_const_state *layout)
322 {
323 nir_foreach_function(function, shader) {
324 if (!function->impl)
325 continue;
326
327 nir_foreach_block(block, function->impl) {
328 nir_foreach_instr(instr, block) {
329 if (instr->type != nir_instr_type_intrinsic)
330 continue;
331
332 nir_intrinsic_instr *intr =
333 nir_instr_as_intrinsic(instr);
334 unsigned idx;
335
336 switch (intr->intrinsic) {
337 case nir_intrinsic_get_buffer_size:
338 idx = nir_src_as_uint(intr->src[0]);
339 if (layout->ssbo_size.mask & (1 << idx))
340 break;
341 layout->ssbo_size.mask |= (1 << idx);
342 layout->ssbo_size.off[idx] =
343 layout->ssbo_size.count;
344 layout->ssbo_size.count += 1; /* one const per */
345 break;
346 case nir_intrinsic_image_deref_atomic_add:
347 case nir_intrinsic_image_deref_atomic_imin:
348 case nir_intrinsic_image_deref_atomic_umin:
349 case nir_intrinsic_image_deref_atomic_imax:
350 case nir_intrinsic_image_deref_atomic_umax:
351 case nir_intrinsic_image_deref_atomic_and:
352 case nir_intrinsic_image_deref_atomic_or:
353 case nir_intrinsic_image_deref_atomic_xor:
354 case nir_intrinsic_image_deref_atomic_exchange:
355 case nir_intrinsic_image_deref_atomic_comp_swap:
356 case nir_intrinsic_image_deref_store:
357 case nir_intrinsic_image_deref_size:
358 idx = nir_intrinsic_get_var(intr, 0)->data.driver_location;
359 if (layout->image_dims.mask & (1 << idx))
360 break;
361 layout->image_dims.mask |= (1 << idx);
362 layout->image_dims.off[idx] =
363 layout->image_dims.count;
364 layout->image_dims.count += 3; /* three const per */
365 break;
366 case nir_intrinsic_load_ubo:
367 if (nir_src_is_const(intr->src[0])) {
368 layout->num_ubos = MAX2(layout->num_ubos,
369 nir_src_as_uint(intr->src[0]) + 1);
370 } else {
371 layout->num_ubos = shader->info.num_ubos;
372 }
373 break;
374 case nir_intrinsic_load_base_vertex:
375 case nir_intrinsic_load_first_vertex:
376 layout->num_driver_params =
377 MAX2(layout->num_driver_params, IR3_DP_VTXID_BASE + 1);
378 break;
379 case nir_intrinsic_load_user_clip_plane:
380 layout->num_driver_params =
381 MAX2(layout->num_driver_params, IR3_DP_UCP7_W + 1);
382 break;
383 case nir_intrinsic_load_num_work_groups:
384 layout->num_driver_params =
385 MAX2(layout->num_driver_params, IR3_DP_NUM_WORK_GROUPS_Z + 1);
386 break;
387 case nir_intrinsic_load_local_group_size:
388 layout->num_driver_params =
389 MAX2(layout->num_driver_params, IR3_DP_LOCAL_GROUP_SIZE_Z + 1);
390 break;
391 default:
392 break;
393 }
394 }
395 }
396 }
397 }
398
399 static void
400 ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir)
401 {
402 struct ir3_compiler *compiler = shader->compiler;
403 struct ir3_const_state *const_state = &shader->const_state;
404
405 memset(&const_state->offsets, ~0, sizeof(const_state->offsets));
406
407 ir3_nir_scan_driver_consts(nir, const_state);
408
409 if ((compiler->gpu_id < 500) &&
410 (shader->stream_output.num_outputs > 0)) {
411 const_state->num_driver_params =
412 MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1);
413 }
414
415 /* num_driver_params is scalar, align to vec4: */
416 const_state->num_driver_params = align(const_state->num_driver_params, 4);
417
418 debug_assert((shader->ubo_state.size % 16) == 0);
419 unsigned constoff = align(shader->ubo_state.size / 16, 8);
420 unsigned ptrsz = ir3_pointer_size(compiler);
421
422 if (const_state->num_ubos > 0) {
423 const_state->offsets.ubo = constoff;
424 constoff += align(nir->info.num_ubos * ptrsz, 4) / 4;
425 }
426
427 if (const_state->ssbo_size.count > 0) {
428 unsigned cnt = const_state->ssbo_size.count;
429 const_state->offsets.ssbo_sizes = constoff;
430 constoff += align(cnt, 4) / 4;
431 }
432
433 if (const_state->image_dims.count > 0) {
434 unsigned cnt = const_state->image_dims.count;
435 const_state->offsets.image_dims = constoff;
436 constoff += align(cnt, 4) / 4;
437 }
438
439 if (const_state->num_driver_params > 0)
440 const_state->offsets.driver_param = constoff;
441 constoff += const_state->num_driver_params / 4;
442
443 if ((shader->type == MESA_SHADER_VERTEX) &&
444 (compiler->gpu_id < 500) &&
445 shader->stream_output.num_outputs > 0) {
446 const_state->offsets.tfbo = constoff;
447 constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
448 }
449
450 switch (shader->type) {
451 case MESA_SHADER_VERTEX:
452 const_state->offsets.primitive_param = constoff;
453 constoff += 1;
454 break;
455 case MESA_SHADER_GEOMETRY:
456 const_state->offsets.primitive_param = constoff;
457 const_state->offsets.primitive_map = constoff + 1;
458 constoff += 1 + DIV_ROUND_UP(nir->num_inputs, 4);
459 break;
460 default:
461 break;
462 }
463
464 const_state->offsets.immediate = constoff;
465 }