2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "util/u_math.h"
28 #include "util/register_allocate.h"
29 #include "util/ralloc.h"
30 #include "util/bitset.h"
33 #include "ir3_compiler.h"
38 #define RA_DEBUG (ir3_shader_debug & IR3_DBG_RAMSGS)
42 #define d(fmt, ...) do { if (RA_DEBUG) { \
43 printf("RA: "fmt"\n", ##__VA_ARGS__); \
46 #define di(instr, fmt, ...) do { if (RA_DEBUG) { \
47 printf("RA: "fmt": ", ##__VA_ARGS__); \
48 ir3_print_instr(instr); \
52 * Register Assignment:
54 * Uses the register_allocate util, which implements graph coloring
55 * algo with interference classes. To handle the cases where we need
56 * consecutive registers (for example, texture sample instructions),
57 * we model these as larger (double/quad/etc) registers which conflict
58 * with the corresponding registers in other classes.
60 * Additionally we create additional classes for half-regs, which
61 * do not conflict with the full-reg classes. We do need at least
62 * sizes 1-4 (to deal w/ texture sample instructions output to half-
63 * reg). At the moment we don't create the higher order half-reg
64 * classes as half-reg frequently does not have enough precision
65 * for texture coords at higher resolutions.
67 * There are some additional cases that we need to handle specially,
68 * as the graph coloring algo doesn't understand "partial writes".
69 * For example, a sequence like:
72 * sam (f32)(xy)r0.x, ...
74 * sam (f32)(xyzw)r0.w, r0.x, ... ; 3d texture, so r0.xyz are coord
76 * In this scenario, we treat r0.xyz as class size 3, which is written
77 * (from a use/def perspective) at the 'add' instruction and ignore the
78 * subsequent partial writes to r0.xy. So the 'add r0.z, ...' is the
79 * defining instruction, as it is the first to partially write r0.xyz.
81 * To address the fragmentation that this can potentially cause, a
82 * two pass register allocation is used. After the first pass the
83 * assignment of scalars is discarded, but the assignment of vecN (for
84 * N > 1) is used to pre-color in the second pass, which considers
87 * Arrays of arbitrary size are handled via pre-coloring a consecutive
88 * sequence of registers. Additional scalar (single component) reg
89 * names are allocated starting at ctx->class_base[total_class_count]
90 * (see arr->base), which are pre-colored. In the use/def graph direct
91 * access is treated as a single element use/def, and indirect access
92 * is treated as use or def of all array elements. (Only the first
93 * def is tracked, in case of multiple indirect writes, etc.)
95 * TODO arrays that fit in one of the pre-defined class sizes should
96 * not need to be pre-colored, but instead could be given a normal
97 * vreg name. (Ignoring this for now since it is a good way to work
98 * out the kinks with arbitrary sized arrays.)
100 * TODO might be easier for debugging to split this into two passes,
101 * the first assigning vreg names in a way that we could ir3_print()
106 static struct ir3_instruction
* name_to_instr(struct ir3_ra_ctx
*ctx
, unsigned name
);
108 static bool name_is_array(struct ir3_ra_ctx
*ctx
, unsigned name
);
109 static struct ir3_array
* name_to_array(struct ir3_ra_ctx
*ctx
, unsigned name
);
111 /* does it conflict? */
113 intersects(unsigned a_start
, unsigned a_end
, unsigned b_start
, unsigned b_end
)
115 return !((a_start
>= b_end
) || (b_start
>= a_end
));
119 reg_size_for_array(struct ir3_array
*arr
)
122 return DIV_ROUND_UP(arr
->length
, 2);
128 instr_before(struct ir3_instruction
*a
, struct ir3_instruction
*b
)
130 if (a
->flags
& IR3_INSTR_UNUSED
)
132 return (a
->ip
< b
->ip
);
135 static struct ir3_instruction
*
136 get_definer(struct ir3_ra_ctx
*ctx
, struct ir3_instruction
*instr
,
139 struct ir3_ra_instr_data
*id
= &ctx
->instrd
[instr
->ip
];
140 struct ir3_instruction
*d
= NULL
;
142 if (ctx
->scalar_pass
) {
145 id
->sz
= 1; /* considering things as N scalar regs now */
154 if (instr
->opc
== OPC_META_COLLECT
) {
155 /* What about the case where collect is subset of array, we
156 * need to find the distance between where actual array starts
157 * and collect.. that probably doesn't happen currently.
159 struct ir3_register
*src
;
162 /* note: don't use foreach_ssa_src as this gets called once
163 * while assigning regs (which clears SSA flag)
165 foreach_src_n (src
, n
, instr
) {
166 struct ir3_instruction
*dd
;
170 dd
= get_definer(ctx
, src
->instr
, &dsz
, &doff
);
172 if ((!d
) || instr_before(dd
, d
)) {
179 } else if (instr
->cp
.right
|| instr
->cp
.left
) {
180 /* covers also the meta:fo case, which ends up w/ single
181 * scalar instructions for each component:
183 struct ir3_instruction
*f
= ir3_neighbor_first(instr
);
185 /* by definition, the entire sequence forms one linked list
186 * of single scalar register nodes (even if some of them may
187 * be splits from a texture sample (for example) instr. We
188 * just need to walk the list finding the first element of
189 * the group defined (lowest ip)
193 /* need to skip over unused in the group: */
194 while (f
&& (f
->flags
& IR3_INSTR_UNUSED
)) {
200 if ((!d
) || instr_before(f
, d
))
211 /* second case is looking directly at the instruction which
212 * produces multiple values (eg, texture sample), rather
213 * than the split nodes that point back to that instruction.
214 * This isn't quite right, because it may be part of a larger
217 * sam (f32)(xyzw)r0.x, ...
220 * sam (f32)(xyzw)r2.x, r0.w <-- (r0.w, r1.x, r1.y)
222 * need to come up with a better way to handle that case.
224 if (instr
->address
) {
225 *sz
= instr
->regs
[0]->size
;
227 *sz
= util_last_bit(instr
->regs
[0]->wrmask
);
233 if (d
->opc
== OPC_META_SPLIT
) {
234 struct ir3_instruction
*dd
;
237 dd
= get_definer(ctx
, d
->regs
[1]->instr
, &dsz
, &doff
);
239 /* by definition, should come before: */
240 debug_assert(instr_before(dd
, d
));
242 *sz
= MAX2(*sz
, dsz
);
244 if (instr
->opc
== OPC_META_SPLIT
)
245 *off
= MAX2(*off
, instr
->split
.off
);
250 debug_assert(d
->opc
!= OPC_META_SPLIT
);
260 ra_block_find_definers(struct ir3_ra_ctx
*ctx
, struct ir3_block
*block
)
262 foreach_instr (instr
, &block
->instr_list
) {
263 struct ir3_ra_instr_data
*id
= &ctx
->instrd
[instr
->ip
];
264 if (instr
->regs_count
== 0)
266 /* couple special cases: */
267 if (writes_addr0(instr
) || writes_addr1(instr
) || writes_pred(instr
)) {
269 } else if (instr
->regs
[0]->flags
& IR3_REG_ARRAY
) {
270 id
->cls
= total_class_count
;
272 /* and the normal case: */
273 id
->defn
= get_definer(ctx
, instr
, &id
->sz
, &id
->off
);
274 id
->cls
= ra_size_to_class(id
->sz
, is_half(id
->defn
), is_high(id
->defn
));
276 /* this is a bit of duct-tape.. if we have a scenario like:
278 * sam (f32)(x) out.x, ...
279 * sam (f32)(x) out.y, ...
281 * Then the fanout/split meta instructions for the two different
282 * tex instructions end up grouped as left/right neighbors. The
283 * upshot is that in when you get_definer() on one of the meta:fo's
284 * you get definer as the first sam with sz=2, but when you call
285 * get_definer() on the either of the sam's you get itself as the
288 * (We actually avoid this scenario exactly, the neighbor links
289 * prevent one of the output mov's from being eliminated, so this
290 * hack should be enough. But probably we need to rethink how we
291 * find the "defining" instruction.)
293 * TODO how do we figure out offset properly...
295 if (id
->defn
!= instr
) {
296 struct ir3_ra_instr_data
*did
= &ctx
->instrd
[id
->defn
->ip
];
297 if (did
->sz
< id
->sz
) {
306 /* give each instruction a name (and ip), and count up the # of names
310 ra_block_name_instructions(struct ir3_ra_ctx
*ctx
, struct ir3_block
*block
)
312 foreach_instr (instr
, &block
->instr_list
) {
313 struct ir3_ra_instr_data
*id
= &ctx
->instrd
[instr
->ip
];
321 if (!writes_gpr(instr
))
324 if (id
->defn
!= instr
)
327 /* In scalar pass, collect/split don't get their own names,
328 * but instead inherit them from their src(s):
330 * Possibly we don't need this because of scalar_name(), but
331 * it does make the ir3_print() dumps easier to read.
333 if (ctx
->scalar_pass
) {
334 if (instr
->opc
== OPC_META_SPLIT
) {
335 instr
->name
= instr
->regs
[1]->instr
->name
+ instr
->split
.off
;
339 if (instr
->opc
== OPC_META_COLLECT
) {
340 instr
->name
= instr
->regs
[1]->instr
->name
;
345 /* arrays which don't fit in one of the pre-defined class
346 * sizes are pre-colored:
348 if ((id
->cls
>= 0) && (id
->cls
< total_class_count
)) {
349 /* in the scalar pass, we generate a name for each
350 * scalar component, instr->name is the name of the
353 unsigned n
= ctx
->scalar_pass
? dest_regs(instr
) : 1;
354 instr
->name
= ctx
->class_alloc_count
[id
->cls
];
355 ctx
->class_alloc_count
[id
->cls
] += n
;
356 ctx
->alloc_count
+= n
;
362 * Set a value for max register target.
364 * Currently this just rounds up to a multiple of full-vec4 (ie. the
365 * granularity that we configure the hw for.. there is no point to
366 * using r3.x if you aren't going to make r3.yzw available). But
367 * in reality there seems to be multiple thresholds that affect the
368 * number of waves.. and we should round up the target to the next
369 * threshold when we round-robin registers, to give postsched more
370 * options. When we understand that better, this is where we'd
374 ra_set_register_target(struct ir3_ra_ctx
*ctx
, unsigned max_target
)
376 const unsigned hvec4
= 4;
377 const unsigned vec4
= 2 * hvec4
;
379 ctx
->max_target
= align(max_target
, vec4
);
381 d("New max_target=%u", ctx
->max_target
);
385 pick_in_range(BITSET_WORD
*regs
, unsigned min
, unsigned max
)
387 for (unsigned i
= min
; i
<= max
; i
++) {
388 if (BITSET_TEST(regs
, i
)) {
396 pick_in_range_rev(BITSET_WORD
*regs
, int min
, int max
)
398 for (int i
= max
; i
>= min
; i
--) {
399 if (BITSET_TEST(regs
, i
)) {
406 /* register selector for the a6xx+ merged register file: */
408 ra_select_reg_merged(unsigned int n
, BITSET_WORD
*regs
, void *data
)
410 struct ir3_ra_ctx
*ctx
= data
;
411 unsigned int class = ra_get_node_class(ctx
->g
, n
);
413 int sz
= ra_class_to_size(class, &half
, &high
);
417 /* dimensions within the register class: */
418 unsigned max_target
, start
;
420 /* the regs bitset will include *all* of the virtual regs, but we lay
421 * out the different classes consecutively in the virtual register
422 * space. So we just need to think about the base offset of a given
423 * class within the virtual register space, and offset the register
424 * space we search within by that base offset.
428 /* TODO I think eventually we want to round-robin in vector pass
429 * as well, but needs some more work to calculate # of live vals
430 * for this. (Maybe with some work, we could just figure out
431 * the scalar target and use that, since that is what we care
432 * about in the end.. but that would mean setting up use-def/
433 * liveranges for scalar pass before doing vector pass.)
435 * For now, in the vector class, just move assignments for scalar
436 * vals higher to hopefully prevent them from limiting where vecN
437 * values can be placed. Since the scalar values are re-assigned
438 * in the 2nd pass, we don't really care where they end up in the
441 if (!ctx
->scalar_pass
) {
442 base
= ctx
->set
->gpr_to_ra_reg
[class][0];
444 max_target
= HIGH_CLASS_REGS(class - HIGH_OFFSET
);
446 max_target
= HALF_CLASS_REGS(class - HALF_OFFSET
);
448 max_target
= CLASS_REGS(class);
451 if ((sz
== 1) && !high
) {
452 return pick_in_range_rev(regs
, base
, base
+ max_target
);
454 return pick_in_range(regs
, base
, base
+ max_target
);
460 /* NOTE: this is only used in scalar pass, so the register
461 * class will be one of the scalar classes (ie. idx==0):
463 base
= ctx
->set
->gpr_to_ra_reg
[class][0];
465 max_target
= HIGH_CLASS_REGS(0);
468 max_target
= ctx
->max_target
;
469 start
= ctx
->start_search_reg
;
471 max_target
= ctx
->max_target
/ 2;
472 start
= ctx
->start_search_reg
;
475 /* For cat4 instructions, if the src reg is already assigned, and
476 * avail to pick, use it. Because this doesn't introduce unnecessary
477 * dependencies, and it potentially avoids needing (ss) syncs to
478 * for write after read hazards:
480 struct ir3_instruction
*instr
= name_to_instr(ctx
, n
);
482 struct ir3_register
*src
= instr
->regs
[1];
485 if ((src
->flags
& IR3_REG_ARRAY
) && !(src
->flags
& IR3_REG_RELATIV
)) {
486 struct ir3_array
*arr
= ir3_lookup_array(ctx
->ir
, src
->array
.id
);
487 src_n
= arr
->base
+ src
->array
.offset
;
489 src_n
= scalar_name(ctx
, src
->instr
, 0);
492 unsigned reg
= ra_get_node_reg(ctx
->g
, src_n
);
494 /* Check if the src register has been assigned yet: */
496 if (BITSET_TEST(regs
, reg
)) {
502 int r
= pick_in_range(regs
, base
+ start
, base
+ max_target
);
505 r
= pick_in_range(regs
, base
, base
+ start
);
509 /* overflow, we need to increase max_target: */
510 ra_set_register_target(ctx
, ctx
->max_target
+ 1);
511 return ra_select_reg_merged(n
, regs
, data
);
514 if (class == ctx
->set
->half_classes
[0]) {
516 ctx
->start_search_reg
= (n
+ 1) % ctx
->max_target
;
517 } else if (class == ctx
->set
->classes
[0]) {
518 int n
= (r
- base
) * 2;
519 ctx
->start_search_reg
= (n
+ 1) % ctx
->max_target
;
526 ra_init(struct ir3_ra_ctx
*ctx
)
530 ir3_clear_mark(ctx
->ir
);
531 n
= ir3_count_instructions_ra(ctx
->ir
);
533 ctx
->instrd
= rzalloc_array(NULL
, struct ir3_ra_instr_data
, n
);
535 foreach_block (block
, &ctx
->ir
->block_list
) {
536 ra_block_find_definers(ctx
, block
);
539 foreach_block (block
, &ctx
->ir
->block_list
) {
540 ra_block_name_instructions(ctx
, block
);
543 /* figure out the base register name for each class. The
544 * actual ra name is class_base[cls] + instr->name;
546 ctx
->class_base
[0] = 0;
547 for (unsigned i
= 1; i
<= total_class_count
; i
++) {
548 ctx
->class_base
[i
] = ctx
->class_base
[i
-1] +
549 ctx
->class_alloc_count
[i
-1];
552 /* and vreg names for array elements: */
553 base
= ctx
->class_base
[total_class_count
];
554 foreach_array (arr
, &ctx
->ir
->array_list
) {
556 ctx
->class_alloc_count
[total_class_count
] += reg_size_for_array(arr
);
557 base
+= reg_size_for_array(arr
);
559 ctx
->alloc_count
+= ctx
->class_alloc_count
[total_class_count
];
561 /* Add vreg names for r0.xyz */
562 ctx
->r0_xyz_nodes
= ctx
->alloc_count
;
563 ctx
->alloc_count
+= 3;
564 ctx
->hr0_xyz_nodes
= ctx
->alloc_count
;
565 ctx
->alloc_count
+= 3;
567 ctx
->g
= ra_alloc_interference_graph(ctx
->set
->regs
, ctx
->alloc_count
);
568 ralloc_steal(ctx
->g
, ctx
->instrd
);
569 ctx
->def
= rzalloc_array(ctx
->g
, unsigned, ctx
->alloc_count
);
570 ctx
->use
= rzalloc_array(ctx
->g
, unsigned, ctx
->alloc_count
);
572 /* TODO add selector callback for split (pre-a6xx) register file: */
573 if (ctx
->ir
->compiler
->gpu_id
>= 600) {
574 ra_set_select_reg_callback(ctx
->g
, ra_select_reg_merged
, ctx
);
576 if (ctx
->scalar_pass
) {
577 ctx
->name_to_instr
= _mesa_hash_table_create(ctx
->g
,
578 _mesa_hash_int
, _mesa_key_int_equal
);
583 /* Map the name back to instruction: */
584 static struct ir3_instruction
*
585 name_to_instr(struct ir3_ra_ctx
*ctx
, unsigned name
)
587 assert(!name_is_array(ctx
, name
));
588 struct hash_entry
*entry
= _mesa_hash_table_search(ctx
->name_to_instr
, &name
);
591 unreachable("invalid instr name");
596 name_is_array(struct ir3_ra_ctx
*ctx
, unsigned name
)
598 return name
>= ctx
->class_base
[total_class_count
];
601 static struct ir3_array
*
602 name_to_array(struct ir3_ra_ctx
*ctx
, unsigned name
)
604 assert(name_is_array(ctx
, name
));
605 foreach_array (arr
, &ctx
->ir
->array_list
) {
606 unsigned sz
= reg_size_for_array(arr
);
607 if (name
< (arr
->base
+ sz
))
610 unreachable("invalid array name");
615 ra_destroy(struct ir3_ra_ctx
*ctx
)
621 __def(struct ir3_ra_ctx
*ctx
, struct ir3_ra_block_data
*bd
, unsigned name
,
622 struct ir3_instruction
*instr
)
624 debug_assert(name
< ctx
->alloc_count
);
626 /* split/collect do not actually define any real value */
627 if ((instr
->opc
== OPC_META_SPLIT
) || (instr
->opc
== OPC_META_COLLECT
))
630 /* defined on first write: */
632 ctx
->def
[name
] = instr
->ip
;
633 ctx
->use
[name
] = MAX2(ctx
->use
[name
], instr
->ip
);
634 BITSET_SET(bd
->def
, name
);
638 __use(struct ir3_ra_ctx
*ctx
, struct ir3_ra_block_data
*bd
, unsigned name
,
639 struct ir3_instruction
*instr
)
641 debug_assert(name
< ctx
->alloc_count
);
642 ctx
->use
[name
] = MAX2(ctx
->use
[name
], instr
->ip
);
643 if (!BITSET_TEST(bd
->def
, name
))
644 BITSET_SET(bd
->use
, name
);
648 ra_block_compute_live_ranges(struct ir3_ra_ctx
*ctx
, struct ir3_block
*block
)
650 struct ir3_ra_block_data
*bd
;
651 unsigned bitset_words
= BITSET_WORDS(ctx
->alloc_count
);
653 #define def(name, instr) __def(ctx, bd, name, instr)
654 #define use(name, instr) __use(ctx, bd, name, instr)
656 bd
= rzalloc(ctx
->g
, struct ir3_ra_block_data
);
658 bd
->def
= rzalloc_array(bd
, BITSET_WORD
, bitset_words
);
659 bd
->use
= rzalloc_array(bd
, BITSET_WORD
, bitset_words
);
660 bd
->livein
= rzalloc_array(bd
, BITSET_WORD
, bitset_words
);
661 bd
->liveout
= rzalloc_array(bd
, BITSET_WORD
, bitset_words
);
665 struct ir3_instruction
*first_non_input
= NULL
;
666 foreach_instr (instr
, &block
->instr_list
) {
667 if (instr
->opc
!= OPC_META_INPUT
) {
668 first_non_input
= instr
;
673 foreach_instr (instr
, &block
->instr_list
) {
674 foreach_def (name
, ctx
, instr
) {
675 if (name_is_array(ctx
, name
)) {
676 struct ir3_array
*arr
= name_to_array(ctx
, name
);
678 arr
->start_ip
= MIN2(arr
->start_ip
, instr
->ip
);
679 arr
->end_ip
= MAX2(arr
->end_ip
, instr
->ip
);
681 for (unsigned i
= 0; i
< arr
->length
; i
++) {
682 unsigned name
= arr
->base
+ i
;
684 ra_set_node_class(ctx
->g
, name
, ctx
->set
->half_classes
[0]);
686 ra_set_node_class(ctx
->g
, name
, ctx
->set
->classes
[0]);
689 struct ir3_ra_instr_data
*id
= &ctx
->instrd
[instr
->ip
];
690 if (is_high(instr
)) {
691 ra_set_node_class(ctx
->g
, name
,
692 ctx
->set
->high_classes
[id
->cls
- HIGH_OFFSET
]);
693 } else if (is_half(instr
)) {
694 ra_set_node_class(ctx
->g
, name
,
695 ctx
->set
->half_classes
[id
->cls
- HALF_OFFSET
]);
697 ra_set_node_class(ctx
->g
, name
,
698 ctx
->set
->classes
[id
->cls
]);
704 if ((instr
->opc
== OPC_META_INPUT
) && first_non_input
)
705 use(name
, first_non_input
);
707 /* Texture instructions with writemasks can be treated as smaller
708 * vectors (or just scalars!) to allocate knowing that the
709 * masked-out regs won't be written, but we need to make sure that
710 * the start of the vector doesn't come before the first register
713 if (is_tex_or_prefetch(instr
)) {
714 int writemask_skipped_regs
= ffs(instr
->regs
[0]->wrmask
) - 1;
715 int r0_xyz
= (instr
->regs
[0]->flags
& IR3_REG_HALF
) ?
716 ctx
->hr0_xyz_nodes
: ctx
->r0_xyz_nodes
;
717 for (int i
= 0; i
< writemask_skipped_regs
; i
++)
718 ra_add_node_interference(ctx
->g
, name
, r0_xyz
+ i
);
722 foreach_use (name
, ctx
, instr
) {
723 if (name_is_array(ctx
, name
)) {
724 struct ir3_array
*arr
= name_to_array(ctx
, name
);
726 arr
->start_ip
= MIN2(arr
->start_ip
, instr
->ip
);
727 arr
->end_ip
= MAX2(arr
->end_ip
, instr
->ip
);
729 /* NOTE: arrays are not SSA so unconditionally
732 BITSET_SET(bd
->use
, name
);
738 foreach_name (name
, ctx
, instr
) {
739 /* split/collect instructions have duplicate names
740 * as real instructions, so they skip the hashtable:
742 if (ctx
->name_to_instr
&& !((instr
->opc
== OPC_META_SPLIT
) ||
743 (instr
->opc
== OPC_META_COLLECT
))) {
744 /* this is slightly annoying, we can't just use an
745 * integer on the stack
747 unsigned *key
= ralloc(ctx
->name_to_instr
, unsigned);
749 debug_assert(!_mesa_hash_table_search(ctx
->name_to_instr
, key
));
750 _mesa_hash_table_insert(ctx
->name_to_instr
, key
, instr
);
757 ra_compute_livein_liveout(struct ir3_ra_ctx
*ctx
)
759 unsigned bitset_words
= BITSET_WORDS(ctx
->alloc_count
);
760 bool progress
= false;
762 foreach_block (block
, &ctx
->ir
->block_list
) {
763 struct ir3_ra_block_data
*bd
= block
->data
;
766 for (unsigned i
= 0; i
< bitset_words
; i
++) {
767 /* anything used but not def'd within a block is
768 * by definition a live value coming into the block:
770 BITSET_WORD new_livein
=
771 (bd
->use
[i
] | (bd
->liveout
[i
] & ~bd
->def
[i
]));
773 if (new_livein
& ~bd
->livein
[i
]) {
774 bd
->livein
[i
] |= new_livein
;
779 /* update liveout: */
780 for (unsigned j
= 0; j
< ARRAY_SIZE(block
->successors
); j
++) {
781 struct ir3_block
*succ
= block
->successors
[j
];
782 struct ir3_ra_block_data
*succ_bd
;
787 succ_bd
= succ
->data
;
789 for (unsigned i
= 0; i
< bitset_words
; i
++) {
790 /* add anything that is livein in a successor block
793 BITSET_WORD new_liveout
=
794 (succ_bd
->livein
[i
] & ~bd
->liveout
[i
]);
797 bd
->liveout
[i
] |= new_liveout
;
808 print_bitset(const char *name
, BITSET_WORD
*bs
, unsigned cnt
)
811 debug_printf("RA: %s:", name
);
812 for (unsigned i
= 0; i
< cnt
; i
++) {
813 if (BITSET_TEST(bs
, i
)) {
816 debug_printf(" %04u", i
);
823 /* size of one component of instruction result, ie. half vs full: */
825 live_size(struct ir3_instruction
*instr
)
827 if (is_half(instr
)) {
829 } else if (is_high(instr
)) {
830 /* doesn't count towards footprint */
838 name_size(struct ir3_ra_ctx
*ctx
, unsigned name
)
840 if (name_is_array(ctx
, name
)) {
841 struct ir3_array
*arr
= name_to_array(ctx
, name
);
842 return arr
->half
? 1 : 2;
844 struct ir3_instruction
*instr
= name_to_instr(ctx
, name
);
845 /* in scalar pass, each name represents on scalar value,
846 * half or full precision
848 return live_size(instr
);
853 ra_calc_block_live_values(struct ir3_ra_ctx
*ctx
, struct ir3_block
*block
)
855 struct ir3_ra_block_data
*bd
= block
->data
;
858 assert(ctx
->name_to_instr
);
860 /* TODO this gets a bit more complicated in non-scalar pass.. but
861 * possibly a lowball estimate is fine to start with if we do
862 * round-robin in non-scalar pass? Maybe we just want to handle
863 * that in a different fxn?
865 assert(ctx
->scalar_pass
);
868 rzalloc_array(bd
, BITSET_WORD
, BITSET_WORDS(ctx
->alloc_count
));
870 /* Add the live input values: */
872 BITSET_FOREACH_SET (name
, bd
->livein
, ctx
->alloc_count
) {
873 livein
+= name_size(ctx
, name
);
874 BITSET_SET(live
, name
);
877 d("---------------------");
878 d("block%u: LIVEIN: %u", block_id(block
), livein
);
880 unsigned max
= livein
;
883 /* Now that we know the live inputs to the block, iterate the
884 * instructions adjusting the current # of live values as we
885 * see their last use:
887 foreach_instr (instr
, &block
->instr_list
) {
889 print_bitset("LIVE", live
, ctx
->alloc_count
);
892 unsigned new_live
= 0; /* newly live values */
893 unsigned new_dead
= 0; /* newly no-longer live values */
894 unsigned next_dead
= 0; /* newly dead following this instr */
896 foreach_def (name
, ctx
, instr
) {
897 /* NOTE: checking ctx->def filters out things like split/
898 * collect which are just redefining existing live names
899 * or array writes to already live array elements:
901 if (ctx
->def
[name
] != instr
->ip
)
903 new_live
+= live_size(instr
);
904 d("NEW_LIVE: %u (new_live=%u, use=%u)", name
, new_live
, ctx
->use
[name
]);
905 BITSET_SET(live
, name
);
906 /* There can be cases where this is *also* the last use
907 * of a value, for example instructions that write multiple
908 * values, only some of which are used. These values are
909 * dead *after* (rather than during) this instruction.
911 if (ctx
->use
[name
] != instr
->ip
)
913 next_dead
+= live_size(instr
);
914 d("NEXT_DEAD: %u (next_dead=%u)", name
, next_dead
);
915 BITSET_CLEAR(live
, name
);
918 /* To be more resilient against special cases where liverange
919 * is extended (like first_non_input), rather than using the
920 * foreach_use() iterator, we iterate the current live values
923 BITSET_FOREACH_SET (name
, live
, ctx
->alloc_count
) {
924 /* Is this the last use? */
925 if (ctx
->use
[name
] != instr
->ip
)
927 new_dead
+= name_size(ctx
, name
);
928 d("NEW_DEAD: %u (new_dead=%u)", name
, new_dead
);
929 BITSET_CLEAR(live
, name
);
932 cur_live
+= new_live
;
933 cur_live
-= new_dead
;
935 assert(cur_live
>= 0);
936 d("CUR_LIVE: %u", cur_live
);
938 max
= MAX2(max
, cur_live
);
940 /* account for written values which are not used later,
941 * but after updating max (since they are for one cycle
944 cur_live
-= next_dead
;
945 assert(cur_live
>= 0);
949 BITSET_FOREACH_SET (name
, live
, ctx
->alloc_count
) {
950 cnt
+= name_size(ctx
, name
);
952 assert(cur_live
== cnt
);
956 d("block%u max=%u", block_id(block
), max
);
958 /* the remaining live should match liveout (for extra sanity testing): */
960 unsigned new_dead
= 0;
961 BITSET_FOREACH_SET (name
, live
, ctx
->alloc_count
) {
962 /* Is this the last use? */
963 if (ctx
->use
[name
] != block
->end_ip
)
965 new_dead
+= name_size(ctx
, name
);
966 d("NEW_DEAD: %u (new_dead=%u)", name
, new_dead
);
967 BITSET_CLEAR(live
, name
);
969 unsigned liveout
= 0;
970 BITSET_FOREACH_SET (name
, bd
->liveout
, ctx
->alloc_count
) {
971 liveout
+= name_size(ctx
, name
);
972 BITSET_CLEAR(live
, name
);
975 if (cur_live
!= liveout
) {
976 print_bitset("LEAKED", live
, ctx
->alloc_count
);
977 /* TODO there are a few edge cases where live-range extension
978 * tells us a value is livein. But not used by the block or
979 * liveout for the block. Possibly a bug in the liverange
980 * extension. But for now leave the assert disabled:
981 assert(cur_live == liveout);
992 ra_calc_max_live_values(struct ir3_ra_ctx
*ctx
)
996 foreach_block (block
, &ctx
->ir
->block_list
) {
997 unsigned block_live
= ra_calc_block_live_values(ctx
, block
);
998 max
= MAX2(max
, block_live
);
1005 ra_add_interference(struct ir3_ra_ctx
*ctx
)
1007 struct ir3
*ir
= ctx
->ir
;
1009 /* initialize array live ranges: */
1010 foreach_array (arr
, &ir
->array_list
) {
1016 /* set up the r0.xyz precolor regs. */
1017 for (int i
= 0; i
< 3; i
++) {
1018 ra_set_node_reg(ctx
->g
, ctx
->r0_xyz_nodes
+ i
, i
);
1019 ra_set_node_reg(ctx
->g
, ctx
->hr0_xyz_nodes
+ i
,
1020 ctx
->set
->first_half_reg
+ i
);
1023 /* compute live ranges (use/def) on a block level, also updating
1024 * block's def/use bitmasks (used below to calculate per-block
1027 foreach_block (block
, &ir
->block_list
) {
1028 ra_block_compute_live_ranges(ctx
, block
);
1031 /* update per-block livein/liveout: */
1032 while (ra_compute_livein_liveout(ctx
)) {}
1035 d("AFTER LIVEIN/OUT:");
1036 foreach_block (block
, &ir
->block_list
) {
1037 struct ir3_ra_block_data
*bd
= block
->data
;
1038 d("block%u:", block_id(block
));
1039 print_bitset(" def", bd
->def
, ctx
->alloc_count
);
1040 print_bitset(" use", bd
->use
, ctx
->alloc_count
);
1041 print_bitset(" l/i", bd
->livein
, ctx
->alloc_count
);
1042 print_bitset(" l/o", bd
->liveout
, ctx
->alloc_count
);
1044 foreach_array (arr
, &ir
->array_list
) {
1045 d("array%u:", arr
->id
);
1046 d(" length: %u", arr
->length
);
1047 d(" start_ip: %u", arr
->start_ip
);
1048 d(" end_ip: %u", arr
->end_ip
);
1050 d("INSTRUCTION VREG NAMES:");
1051 foreach_block (block
, &ctx
->ir
->block_list
) {
1052 foreach_instr (instr
, &block
->instr_list
) {
1053 if (!ctx
->instrd
[instr
->ip
].defn
)
1055 if (!writes_gpr(instr
))
1057 di(instr
, "%04u", scalar_name(ctx
, instr
, 0));
1060 d("ARRAY VREG NAMES:");
1061 foreach_array (arr
, &ctx
->ir
->array_list
) {
1062 d("%04u: arr%u", arr
->base
, arr
->id
);
1066 /* extend start/end ranges based on livein/liveout info from cfg: */
1067 foreach_block (block
, &ir
->block_list
) {
1068 struct ir3_ra_block_data
*bd
= block
->data
;
1070 for (unsigned i
= 0; i
< ctx
->alloc_count
; i
++) {
1071 if (BITSET_TEST(bd
->livein
, i
)) {
1072 ctx
->def
[i
] = MIN2(ctx
->def
[i
], block
->start_ip
);
1073 ctx
->use
[i
] = MAX2(ctx
->use
[i
], block
->start_ip
);
1076 if (BITSET_TEST(bd
->liveout
, i
)) {
1077 ctx
->def
[i
] = MIN2(ctx
->def
[i
], block
->end_ip
);
1078 ctx
->use
[i
] = MAX2(ctx
->use
[i
], block
->end_ip
);
1082 foreach_array (arr
, &ctx
->ir
->array_list
) {
1083 for (unsigned i
= 0; i
< arr
->length
; i
++) {
1084 if (BITSET_TEST(bd
->livein
, i
+ arr
->base
)) {
1085 arr
->start_ip
= MIN2(arr
->start_ip
, block
->start_ip
);
1087 if (BITSET_TEST(bd
->liveout
, i
+ arr
->base
)) {
1088 arr
->end_ip
= MAX2(arr
->end_ip
, block
->end_ip
);
1094 if (ctx
->name_to_instr
) {
1095 unsigned max
= ra_calc_max_live_values(ctx
);
1096 ra_set_register_target(ctx
, max
);
1099 for (unsigned i
= 0; i
< ctx
->alloc_count
; i
++) {
1100 for (unsigned j
= 0; j
< ctx
->alloc_count
; j
++) {
1101 if (intersects(ctx
->def
[i
], ctx
->use
[i
],
1102 ctx
->def
[j
], ctx
->use
[j
])) {
1103 ra_add_node_interference(ctx
->g
, i
, j
);
1109 /* some instructions need fix-up if dst register is half precision: */
1110 static void fixup_half_instr_dst(struct ir3_instruction
*instr
)
1112 switch (opc_cat(instr
->opc
)) {
1113 case 1: /* move instructions */
1114 instr
->cat1
.dst_type
= half_type(instr
->cat1
.dst_type
);
1117 switch (instr
->opc
) {
1119 instr
->opc
= OPC_HRSQ
;
1122 instr
->opc
= OPC_HLOG2
;
1125 instr
->opc
= OPC_HEXP2
;
1132 instr
->cat5
.type
= half_type(instr
->cat5
.type
);
1136 /* some instructions need fix-up if src register is half precision: */
1137 static void fixup_half_instr_src(struct ir3_instruction
*instr
)
1139 switch (instr
->opc
) {
1141 instr
->cat1
.src_type
= half_type(instr
->cat1
.src_type
);
1144 instr
->opc
= OPC_MAD_F16
;
1147 instr
->opc
= OPC_SEL_B16
;
1150 instr
->opc
= OPC_SEL_S16
;
1153 instr
->opc
= OPC_SEL_F16
;
1156 instr
->opc
= OPC_SAD_S16
;
1163 /* NOTE: instr could be NULL for IR3_REG_ARRAY case, for the first
1164 * array access(es) which do not have any previous access to depend
1165 * on from scheduling point of view
1168 reg_assign(struct ir3_ra_ctx
*ctx
, struct ir3_register
*reg
,
1169 struct ir3_instruction
*instr
)
1171 struct ir3_ra_instr_data
*id
;
1173 if (reg
->flags
& IR3_REG_ARRAY
) {
1174 struct ir3_array
*arr
=
1175 ir3_lookup_array(ctx
->ir
, reg
->array
.id
);
1176 unsigned name
= arr
->base
+ reg
->array
.offset
;
1177 unsigned r
= ra_get_node_reg(ctx
->g
, name
);
1178 unsigned num
= ctx
->set
->ra_reg_to_gpr
[r
];
1180 if (reg
->flags
& IR3_REG_RELATIV
) {
1181 reg
->array
.offset
= num
;
1184 reg
->flags
&= ~IR3_REG_SSA
;
1187 reg
->flags
&= ~IR3_REG_ARRAY
;
1188 } else if ((id
= &ctx
->instrd
[instr
->ip
]) && id
->defn
) {
1189 unsigned first_component
= 0;
1191 /* Special case for tex instructions, which may use the wrmask
1192 * to mask off the first component(s). In the scalar pass,
1193 * this means the masked off component(s) are not def'd/use'd,
1194 * so we get a bogus value when we ask the register_allocate
1195 * algo to get the assigned reg for the unused/untouched
1196 * component. So we need to consider the first used component:
1198 if (ctx
->scalar_pass
&& is_tex_or_prefetch(id
->defn
)) {
1199 unsigned n
= ffs(id
->defn
->regs
[0]->wrmask
);
1200 debug_assert(n
> 0);
1201 first_component
= n
- 1;
1204 unsigned name
= scalar_name(ctx
, id
->defn
, first_component
);
1205 unsigned r
= ra_get_node_reg(ctx
->g
, name
);
1206 unsigned num
= ctx
->set
->ra_reg_to_gpr
[r
] + id
->off
;
1208 debug_assert(!(reg
->flags
& IR3_REG_RELATIV
));
1210 debug_assert(num
>= first_component
);
1212 if (is_high(id
->defn
))
1213 num
+= FIRST_HIGH_REG
;
1215 reg
->num
= num
- first_component
;
1217 reg
->flags
&= ~IR3_REG_SSA
;
1219 if (is_half(id
->defn
))
1220 reg
->flags
|= IR3_REG_HALF
;
1224 /* helper to determine which regs to assign in which pass: */
1226 should_assign(struct ir3_ra_ctx
*ctx
, struct ir3_instruction
*instr
)
1228 if ((instr
->opc
== OPC_META_SPLIT
) &&
1229 (util_bitcount(instr
->regs
[1]->wrmask
) > 1))
1230 return !ctx
->scalar_pass
;
1231 if ((instr
->opc
== OPC_META_COLLECT
) &&
1232 (util_bitcount(instr
->regs
[0]->wrmask
) > 1))
1233 return !ctx
->scalar_pass
;
1234 return ctx
->scalar_pass
;
1238 ra_block_alloc(struct ir3_ra_ctx
*ctx
, struct ir3_block
*block
)
1240 foreach_instr (instr
, &block
->instr_list
) {
1241 struct ir3_register
*reg
;
1243 if (writes_gpr(instr
)) {
1244 if (should_assign(ctx
, instr
)) {
1245 reg_assign(ctx
, instr
->regs
[0], instr
);
1246 if (instr
->regs
[0]->flags
& IR3_REG_HALF
)
1247 fixup_half_instr_dst(instr
);
1251 foreach_src_n (reg
, n
, instr
) {
1252 struct ir3_instruction
*src
= reg
->instr
;
1254 if (src
&& !should_assign(ctx
, src
) && !should_assign(ctx
, instr
))
1257 if (src
&& should_assign(ctx
, instr
))
1258 reg_assign(ctx
, src
->regs
[0], src
);
1260 /* Note: reg->instr could be null for IR3_REG_ARRAY */
1261 if (src
|| (reg
->flags
& IR3_REG_ARRAY
))
1262 reg_assign(ctx
, instr
->regs
[n
+1], src
);
1264 if (instr
->regs
[n
+1]->flags
& IR3_REG_HALF
)
1265 fixup_half_instr_src(instr
);
1269 /* We need to pre-color outputs for the scalar pass in
1270 * ra_precolor_assigned(), so we need to actually assign
1271 * them in the first pass:
1273 if (!ctx
->scalar_pass
) {
1274 struct ir3_instruction
*in
, *out
;
1276 foreach_input (in
, ctx
->ir
) {
1277 reg_assign(ctx
, in
->regs
[0], in
);
1279 foreach_output (out
, ctx
->ir
) {
1280 reg_assign(ctx
, out
->regs
[0], out
);
1286 assign_arr_base(struct ir3_ra_ctx
*ctx
, struct ir3_array
*arr
,
1287 struct ir3_instruction
**precolor
, unsigned nprecolor
)
1291 /* figure out what else we conflict with which has already
1295 foreach_array (arr2
, &ctx
->ir
->array_list
) {
1298 if (arr2
->end_ip
== 0)
1300 /* if it intersects with liverange AND register range.. */
1301 if (intersects(arr
->start_ip
, arr
->end_ip
,
1302 arr2
->start_ip
, arr2
->end_ip
) &&
1303 intersects(base
, base
+ reg_size_for_array(arr
),
1304 arr2
->reg
, arr2
->reg
+ reg_size_for_array(arr2
))) {
1305 base
= MAX2(base
, arr2
->reg
+ reg_size_for_array(arr2
));
1310 /* also need to not conflict with any pre-assigned inputs: */
1311 for (unsigned i
= 0; i
< nprecolor
; i
++) {
1312 struct ir3_instruction
*instr
= precolor
[i
];
1314 if (!instr
|| (instr
->flags
& IR3_INSTR_UNUSED
))
1317 struct ir3_ra_instr_data
*id
= &ctx
->instrd
[instr
->ip
];
1319 /* only consider the first component: */
1323 unsigned name
= ra_name(ctx
, id
);
1324 unsigned regid
= instr
->regs
[0]->num
;
1326 /* Check if array intersects with liverange AND register
1327 * range of the input:
1329 if (intersects(arr
->start_ip
, arr
->end_ip
,
1330 ctx
->def
[name
], ctx
->use
[name
]) &&
1331 intersects(base
, base
+ reg_size_for_array(arr
),
1332 regid
, regid
+ class_sizes
[id
->cls
])) {
1333 base
= MAX2(base
, regid
+ class_sizes
[id
->cls
]);
1341 /* handle pre-colored registers. This includes "arrays" (which could be of
1342 * length 1, used for phi webs lowered to registers in nir), as well as
1343 * special shader input values that need to be pinned to certain registers.
1346 ra_precolor(struct ir3_ra_ctx
*ctx
, struct ir3_instruction
**precolor
, unsigned nprecolor
)
1348 for (unsigned i
= 0; i
< nprecolor
; i
++) {
1349 if (precolor
[i
] && !(precolor
[i
]->flags
& IR3_INSTR_UNUSED
)) {
1350 struct ir3_instruction
*instr
= precolor
[i
];
1352 if (instr
->regs
[0]->num
== INVALID_REG
)
1355 struct ir3_ra_instr_data
*id
= &ctx
->instrd
[instr
->ip
];
1357 debug_assert(!(instr
->regs
[0]->flags
& (IR3_REG_HALF
| IR3_REG_HIGH
)));
1359 /* only consider the first component: */
1363 if (ctx
->scalar_pass
&& !should_assign(ctx
, instr
))
1366 /* 'base' is in scalar (class 0) but we need to map that
1367 * the conflicting register of the appropriate class (ie.
1368 * input could be vec2/vec3/etc)
1370 * Note that the higher class (larger than scalar) regs
1371 * are setup to conflict with others in the same class,
1372 * so for example, R1 (scalar) is also the first component
1373 * of D1 (vec2/double):
1375 * Single (base) | Double
1376 * --------------+---------------
1383 unsigned regid
= instr
->regs
[0]->num
;
1384 unsigned reg
= ctx
->set
->gpr_to_ra_reg
[id
->cls
][regid
];
1385 unsigned name
= ra_name(ctx
, id
);
1386 ra_set_node_reg(ctx
->g
, name
, reg
);
1390 /* pre-assign array elements:
1392 * TODO this is going to need some work for half-precision.. possibly
1393 * this is easier on a6xx, where we can just divide array size by two?
1394 * But on a5xx and earlier it will need to track two bases.
1396 foreach_array (arr
, &ctx
->ir
->array_list
) {
1398 if (arr
->end_ip
== 0)
1401 if (!ctx
->scalar_pass
)
1402 assign_arr_base(ctx
, arr
, precolor
, nprecolor
);
1404 unsigned base
= arr
->reg
;
1406 for (unsigned i
= 0; i
< arr
->length
; i
++) {
1410 /* Doesn't need to do this on older generations than a6xx,
1411 * since there's no conflict between full regs and half regs
1414 * TODO Presumably "base" could start from 0 respectively
1415 * for half regs of arrays on older generations.
1417 unsigned base_half
= base
* 2 + i
;
1418 reg
= ctx
->set
->gpr_to_ra_reg
[0+HALF_OFFSET
][base_half
];
1419 base
= base_half
/ 2 + 1;
1421 reg
= ctx
->set
->gpr_to_ra_reg
[0][base
++];
1424 name
= arr
->base
+ i
;
1425 ra_set_node_reg(ctx
->g
, name
, reg
);
1429 if (ir3_shader_debug
& IR3_DBG_OPTMSGS
) {
1430 foreach_array (arr
, &ctx
->ir
->array_list
) {
1431 unsigned first
= arr
->reg
;
1432 unsigned last
= arr
->reg
+ arr
->length
- 1;
1433 debug_printf("arr[%d] at r%d.%c->r%d.%c\n", arr
->id
,
1434 (first
>> 2), "xyzw"[first
& 0x3],
1435 (last
>> 2), "xyzw"[last
& 0x3]);
1441 precolor(struct ir3_ra_ctx
*ctx
, struct ir3_instruction
*instr
)
1443 struct ir3_ra_instr_data
*id
= &ctx
->instrd
[instr
->ip
];
1444 unsigned n
= dest_regs(instr
);
1445 for (unsigned i
= 0; i
< n
; i
++) {
1446 /* tex instructions actually have a wrmask, and
1447 * don't touch masked out components. So we
1448 * shouldn't precolor them::
1450 if (is_tex_or_prefetch(instr
) &&
1451 !(instr
->regs
[0]->wrmask
& (1 << i
)))
1454 unsigned name
= scalar_name(ctx
, instr
, i
);
1455 unsigned regid
= instr
->regs
[0]->num
+ i
;
1457 if (instr
->regs
[0]->flags
& IR3_REG_HIGH
)
1458 regid
-= FIRST_HIGH_REG
;
1460 unsigned vreg
= ctx
->set
->gpr_to_ra_reg
[id
->cls
][regid
];
1461 ra_set_node_reg(ctx
->g
, name
, vreg
);
1465 /* pre-color non-scalar registers based on the registers assigned in previous
1466 * pass. Do this by looking actually at the fanout instructions.
1469 ra_precolor_assigned(struct ir3_ra_ctx
*ctx
)
1471 debug_assert(ctx
->scalar_pass
);
1473 foreach_block (block
, &ctx
->ir
->block_list
) {
1474 foreach_instr (instr
, &block
->instr_list
) {
1476 if (!writes_gpr(instr
))
1479 if (should_assign(ctx
, instr
))
1482 precolor(ctx
, instr
);
1484 struct ir3_register
*src
;
1485 foreach_src (src
, instr
) {
1488 precolor(ctx
, src
->instr
);
1495 ra_alloc(struct ir3_ra_ctx
*ctx
)
1497 if (!ra_allocate(ctx
->g
))
1500 foreach_block (block
, &ctx
->ir
->block_list
) {
1501 ra_block_alloc(ctx
, block
);
1507 /* if we end up with split/collect instructions with non-matching src
1508 * and dest regs, that means something has gone wrong. Which makes it
1509 * a pretty good sanity check.
1512 ra_sanity_check(struct ir3
*ir
)
1514 foreach_block (block
, &ir
->block_list
) {
1515 foreach_instr (instr
, &block
->instr_list
) {
1516 if (instr
->opc
== OPC_META_SPLIT
) {
1517 struct ir3_register
*dst
= instr
->regs
[0];
1518 struct ir3_register
*src
= instr
->regs
[1];
1519 debug_assert(dst
->num
== (src
->num
+ instr
->split
.off
));
1520 } else if (instr
->opc
== OPC_META_COLLECT
) {
1521 struct ir3_register
*dst
= instr
->regs
[0];
1522 struct ir3_register
*src
;
1524 foreach_src_n (src
, n
, instr
) {
1525 debug_assert(dst
->num
== (src
->num
- n
));
1533 ir3_ra_pass(struct ir3_shader_variant
*v
, struct ir3_instruction
**precolor
,
1534 unsigned nprecolor
, bool scalar_pass
)
1536 struct ir3_ra_ctx ctx
= {
1539 .set
= v
->ir
->compiler
->set
,
1540 .scalar_pass
= scalar_pass
,
1545 ra_add_interference(&ctx
);
1546 ra_precolor(&ctx
, precolor
, nprecolor
);
1548 ra_precolor_assigned(&ctx
);
1549 ret
= ra_alloc(&ctx
);
1556 ir3_ra(struct ir3_shader_variant
*v
, struct ir3_instruction
**precolor
,
1561 /* First pass, assign the vecN (non-scalar) registers: */
1562 ret
= ir3_ra_pass(v
, precolor
, nprecolor
, false);
1566 ir3_debug_print(v
->ir
, "AFTER: ir3_ra (1st pass)");
1568 /* Second pass, assign the scalar registers: */
1569 ret
= ir3_ra_pass(v
, precolor
, nprecolor
, true);
1573 ir3_debug_print(v
->ir
, "AFTER: ir3_ra (2st pass)");
1576 # define SANITY_CHECK DEBUG
1578 # define SANITY_CHECK 0
1581 ra_sanity_check(v
->ir
);