src/freedreno/ir3/ir3_ra.h

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #ifndef IR3_RA_H_
  28 #define IR3_RA_H_
  29
  30 #include "util/bitset.h"
  31
  32
  33 static const unsigned class_sizes[] = {
  34         1, 2, 3, 4,
  35         4 + 4, /* txd + 1d/2d */
  36         4 + 6, /* txd + 3d */
  37 };
  38 #define class_count ARRAY_SIZE(class_sizes)
  39
  40 static const unsigned half_class_sizes[] = {
  41         1, 2, 3, 4,
  42 };
  43 #define half_class_count  ARRAY_SIZE(half_class_sizes)
  44
  45 /* seems to just be used for compute shaders?  Seems like vec1 and vec3
  46  * are sufficient (for now?)
  47  */
  48 static const unsigned high_class_sizes[] = {
  49         1, 3,
  50 };
  51 #define high_class_count ARRAY_SIZE(high_class_sizes)
  52
  53 #define total_class_count (class_count + half_class_count + high_class_count)
  54
  55 /* Below a0.x are normal regs.  RA doesn't need to assign a0.x/p0.x. */
  56 #define NUM_REGS             (4 * 48)  /* r0 to r47 */
  57 #define NUM_HIGH_REGS        (4 * 8)   /* r48 to r55 */
  58 #define FIRST_HIGH_REG       (4 * 48)
  59 /* Number of virtual regs in a given class: */
  60
  61 static inline unsigned CLASS_REGS(unsigned i)
  62 {
  63         assert(i < class_count);
  64
  65         return (NUM_REGS - (class_sizes[i] - 1));
  66 }
  67
  68 static inline unsigned HALF_CLASS_REGS(unsigned i)
  69 {
  70         assert(i < half_class_count);
  71
  72         return (NUM_REGS - (half_class_sizes[i] - 1));
  73 }
  74
  75 static inline unsigned HIGH_CLASS_REGS(unsigned i)
  76 {
  77         assert(i < high_class_count);
  78
  79         return (NUM_HIGH_REGS - (high_class_sizes[i] - 1));
  80 }
  81
  82 #define HALF_OFFSET          (class_count)
  83 #define HIGH_OFFSET          (class_count + half_class_count)
  84
  85 /* register-set, created one time, used for all shaders: */
  86 struct ir3_ra_reg_set {
  87         struct ra_regs *regs;
  88         unsigned int classes[class_count];
  89         unsigned int half_classes[half_class_count];
  90         unsigned int high_classes[high_class_count];
  91
  92         /* The virtual register space flattens out all the classes,
  93          * starting with full, followed by half and then high, ie:
  94          *
  95          *   scalar full  (starting at zero)
  96          *   vec2 full
  97          *   vec3 full
  98          *   ...
  99          *   vecN full
 100          *   scalar half  (starting at first_half_reg)
 101          *   vec2 half
 102          *   ...
 103          *   vecN half
 104          *   scalar high  (starting at first_high_reg)
 105          *   ...
 106          *   vecN high
 107          *
 108          */
 109         unsigned first_half_reg, first_high_reg;
 110
 111         /* maps flat virtual register space to base gpr: */
 112         uint16_t *ra_reg_to_gpr;
 113         /* maps cls,gpr to flat virtual register space: */
 114         uint16_t **gpr_to_ra_reg;
 115 };
 116
 117 /* additional block-data (per-block) */
 118 struct ir3_ra_block_data {
 119         BITSET_WORD *def;        /* variables defined before used in block */
 120         BITSET_WORD *use;        /* variables used before defined in block */
 121         BITSET_WORD *livein;     /* which defs reach entry point of block */
 122         BITSET_WORD *liveout;    /* which defs reach exit point of block */
 123 };
 124
 125 /* additional instruction-data (per-instruction) */
 126 struct ir3_ra_instr_data {
 127         /* cached instruction 'definer' info: */
 128         struct ir3_instruction *defn;
 129         int off, sz, cls;
 130 };
 131
 132 /* register-assign context, per-shader */
 133 struct ir3_ra_ctx {
 134         struct ir3_shader_variant *v;
 135         struct ir3 *ir;
 136
 137         struct ir3_ra_reg_set *set;
 138         struct ra_graph *g;
 139
 140         /* Are we in the scalar assignment pass?  In this pass, all larger-
 141          * than-vec1 vales have already been assigned and pre-colored, so
 142          * we only consider scalar values.
 143          */
 144         bool scalar_pass;
 145
 146         unsigned alloc_count;
 147         unsigned r0_xyz_nodes; /* ra node numbers for r0.[xyz] precolors */
 148         unsigned hr0_xyz_nodes; /* ra node numbers for hr0.[xyz] precolors pre-a6xx */
 149         /* one per class, plus one slot for arrays: */
 150         unsigned class_alloc_count[total_class_count + 1];
 151         unsigned class_base[total_class_count + 1];
 152         unsigned instr_cnt;
 153         unsigned *def, *use;     /* def/use table */
 154         struct ir3_ra_instr_data *instrd;
 155
 156         /* Mapping vreg name back to instruction, used select reg callback: */
 157         struct hash_table *name_to_instr;
 158
 159         /* Tracking for select_reg callback */
 160         unsigned start_search_reg;
 161         unsigned max_target;
 162
 163         /* Temporary buffer for def/use iterators
 164          *
 165          * The worst case should probably be an array w/ relative access (ie.
 166          * all elements are def'd or use'd), and that can't be larger than
 167          * the number of registers.
 168          *
 169          * NOTE we could declare this on the stack if needed, but I don't
 170          * think there is a need for nested iterators.
 171          */
 172         unsigned namebuf[NUM_REGS];
 173         unsigned namecnt, nameidx;
 174 };
 175
 176 static inline int
 177 ra_name(struct ir3_ra_ctx *ctx, struct ir3_ra_instr_data *id)
 178 {
 179         unsigned name;
 180         debug_assert(id->cls >= 0);
 181         debug_assert(id->cls < total_class_count);  /* we shouldn't get arrays here.. */
 182         name = ctx->class_base[id->cls] + id->defn->name;
 183         debug_assert(name < ctx->alloc_count);
 184         return name;
 185 }
 186
 187 /* Get the scalar name of the n'th component of an instruction dst: */
 188 static inline int
 189 scalar_name(struct ir3_ra_ctx *ctx, struct ir3_instruction *instr, unsigned n)
 190 {
 191         if (ctx->scalar_pass) {
 192                 if (instr->opc == OPC_META_SPLIT) {
 193                         debug_assert(n == 0);     /* split results in a scalar */
 194                         struct ir3_instruction *src = instr->regs[1]->instr;
 195                         return scalar_name(ctx, src, instr->split.off);
 196                 } else if (instr->opc == OPC_META_COLLECT) {
 197                         debug_assert(n < (instr->regs_count + 1));
 198                         struct ir3_instruction *src = instr->regs[n + 1]->instr;
 199                         return scalar_name(ctx, src, 0);
 200                 }
 201         } else {
 202                 debug_assert(n == 0);
 203         }
 204
 205         return ra_name(ctx, &ctx->instrd[instr->ip]) + n;
 206 }
 207
 208 #define NO_NAME ~0
 209
 210 /*
 211  * Iterators to iterate the vreg names of an instructions def's and use's
 212  */
 213
 214 static inline unsigned
 215 __ra_name_cnt(struct ir3_ra_ctx *ctx, struct ir3_instruction *instr)
 216 {
 217         if (!instr)
 218                 return 0;
 219
 220         /* Filter special cases, ie. writes to a0.x or p0.x, or non-ssa: */
 221         if (!writes_gpr(instr) || (instr->regs[0]->flags & IR3_REG_ARRAY))
 222                 return 0;
 223
 224         /* in scalar pass, we aren't considering virtual register classes, ie.
 225          * if an instruction writes a vec2, then it defines two different scalar
 226          * register names.
 227          */
 228         if (ctx->scalar_pass)
 229                 return dest_regs(instr);
 230
 231         return 1;
 232 }
 233
 234 #define foreach_name_n(__name, __n, __ctx, __instr) \
 235         for (unsigned __cnt = __ra_name_cnt(__ctx, __instr), __n = 0, __name; \
 236              (__n < __cnt) && ({__name = scalar_name(__ctx, __instr, __n); 1;}); __n++)
 237
 238 #define foreach_name(__name, __ctx, __instr) \
 239         foreach_name_n(__name, __n, __ctx, __instr)
 240
 241 static inline unsigned
 242 __ra_itr_pop(struct ir3_ra_ctx *ctx)
 243 {
 244         if (ctx->nameidx < ctx->namecnt)
 245                 return ctx->namebuf[ctx->nameidx++];
 246         return NO_NAME;
 247 }
 248
 249 static inline void
 250 __ra_itr_push(struct ir3_ra_ctx *ctx, unsigned name)
 251 {
 252         assert(ctx->namecnt < ARRAY_SIZE(ctx->namebuf));
 253         ctx->namebuf[ctx->namecnt++] = name;
 254 }
 255
 256 static inline unsigned
 257 __ra_init_def_itr(struct ir3_ra_ctx *ctx, struct ir3_instruction *instr)
 258 {
 259         /* nested use is not supported: */
 260         assert(ctx->namecnt == ctx->nameidx);
 261
 262         ctx->namecnt = ctx->nameidx = 0;
 263
 264         if (!writes_gpr(instr))
 265                 return NO_NAME;
 266
 267         struct ir3_ra_instr_data *id = &ctx->instrd[instr->ip];
 268         struct ir3_register *dst = instr->regs[0];
 269
 270         if (dst->flags & IR3_REG_ARRAY) {
 271                 struct ir3_array *arr = ir3_lookup_array(ctx->ir, dst->array.id);
 272
 273                 /* indirect write is treated like a write to all array
 274                  * elements, since we don't know which one is actually
 275                  * written:
 276                  */
 277                 if (dst->flags & IR3_REG_RELATIV) {
 278                         for (unsigned i = 0; i < arr->length; i++) {
 279                                 __ra_itr_push(ctx, arr->base + i);
 280                         }
 281                 } else {
 282                         __ra_itr_push(ctx, arr->base + dst->array.offset);
 283                         debug_assert(dst->array.offset < arr->length);
 284                 }
 285         } else if (id->defn == instr) {
 286                 foreach_name_n (name, i, ctx, instr) {
 287                         /* tex instructions actually have a wrmask, and
 288                          * don't touch masked out components.  We can't do
 289                          * anything useful about that in the first pass,
 290                          * but in the scalar pass we can realize these
 291                          * registers are available:
 292                          */
 293                         if (ctx->scalar_pass && is_tex_or_prefetch(instr) &&
 294                                         !(instr->regs[0]->wrmask & (1 << i)))
 295                                 continue;
 296                         __ra_itr_push(ctx, name);
 297                 }
 298         }
 299
 300         return __ra_itr_pop(ctx);
 301 }
 302
 303 static inline unsigned
 304 __ra_init_use_itr(struct ir3_ra_ctx *ctx, struct ir3_instruction *instr)
 305 {
 306         /* nested use is not supported: */
 307         assert(ctx->namecnt == ctx->nameidx);
 308
 309         ctx->namecnt = ctx->nameidx = 0;
 310
 311         foreach_src (reg, instr) {
 312                 if (reg->flags & IR3_REG_ARRAY) {
 313                         struct ir3_array *arr =
 314                                 ir3_lookup_array(ctx->ir, reg->array.id);
 315
 316                         /* indirect read is treated like a read from all array
 317                          * elements, since we don't know which one is actually
 318                          * read:
 319                          */
 320                         if (reg->flags & IR3_REG_RELATIV) {
 321                                 for (unsigned i = 0; i < arr->length; i++) {
 322                                         __ra_itr_push(ctx, arr->base + i);
 323                                 }
 324                         } else {
 325                                 __ra_itr_push(ctx, arr->base + reg->array.offset);
 326                                 debug_assert(reg->array.offset < arr->length);
 327                         }
 328                 } else {
 329                         foreach_name_n (name, i, ctx, reg->instr) {
 330                                 /* split takes a src w/ wrmask potentially greater
 331                                  * than 0x1, but it really only cares about a single
 332                                  * component.  This shows up in splits coming out of
 333                                  * a tex instruction w/ wrmask=.z, for example.
 334                                  */
 335                                 if (ctx->scalar_pass && (instr->opc == OPC_META_SPLIT) &&
 336                                                 !(i == instr->split.off))
 337                                         continue;
 338                                 __ra_itr_push(ctx, name);
 339                         }
 340                 }
 341         }
 342
 343         return __ra_itr_pop(ctx);
 344 }
 345
 346 #define foreach_def(__name, __ctx, __instr) \
 347         for (unsigned __name = __ra_init_def_itr(__ctx, __instr); \
 348              __name != NO_NAME; __name = __ra_itr_pop(__ctx))
 349
 350 #define foreach_use(__name, __ctx, __instr) \
 351         for (unsigned __name = __ra_init_use_itr(__ctx, __instr); \
 352              __name != NO_NAME; __name = __ra_itr_pop(__ctx))
 353
 354 int ra_size_to_class(unsigned sz, bool half, bool high);
 355 int ra_class_to_size(unsigned class, bool *half, bool *high);
 356
 357 #endif  /* IR3_RA_H_ */