src/freedreno/ir3/ir3_shader.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "util/u_atomic.h"
  28 #include "util/u_string.h"
  29 #include "util/u_math.h"
  30 #include "util/u_memory.h"
  31 #include "util/format/u_format.h"
  32
  33 #include "drm/freedreno_drmif.h"
  34
  35 #include "ir3_shader.h"
  36 #include "ir3_compiler.h"
  37 #include "ir3_nir.h"
  38
  39 int
  40 ir3_glsl_type_size(const struct glsl_type *type, bool bindless)
  41 {
  42         return glsl_count_attribute_slots(type, false);
  43 }
  44
  45 /* for vertex shader, the inputs are loaded into registers before the shader
  46  * is executed, so max_regs from the shader instructions might not properly
  47  * reflect the # of registers actually used, especially in case passthrough
  48  * varyings.
  49  *
  50  * Likewise, for fragment shader, we can have some regs which are passed
  51  * input values but never touched by the resulting shader (ie. as result
  52  * of dead code elimination or simply because we don't know how to turn
  53  * the reg off.
  54  */
  55 static void
  56 fixup_regfootprint(struct ir3_shader_variant *v)
  57 {
  58         unsigned i;
  59
  60         for (i = 0; i < v->inputs_count; i++) {
  61                 /* skip frag inputs fetch via bary.f since their reg's are
  62                  * not written by gpu before shader starts (and in fact the
  63                  * regid's might not even be valid)
  64                  */
  65                 if (v->inputs[i].bary)
  66                         continue;
  67
  68                 /* ignore high regs that are global to all threads in a warp
  69                  * (they exist by default) (a5xx+)
  70                  */
  71                 if (v->inputs[i].regid >= regid(48,0))
  72                         continue;
  73
  74                 if (v->inputs[i].compmask) {
  75                         unsigned n = util_last_bit(v->inputs[i].compmask) - 1;
  76                         int32_t regid = v->inputs[i].regid + n;
  77                         if (v->inputs[i].half) {
  78                                 if (!v->mergedregs) {
  79                                         v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
  80                                 } else {
  81                                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
  82                                 }
  83                         } else {
  84                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
  85                         }
  86                 }
  87         }
  88
  89         for (i = 0; i < v->outputs_count; i++) {
  90                 /* for ex, VS shaders with tess don't have normal varying outs: */
  91                 if (!VALIDREG(v->outputs[i].regid))
  92                         continue;
  93                 int32_t regid = v->outputs[i].regid + 3;
  94                 if (v->outputs[i].half) {
  95                         if (!v->mergedregs) {
  96                                 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
  97                         } else {
  98                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
  99                         }
 100                 } else {
 101                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
 102                 }
 103         }
 104
 105         for (i = 0; i < v->num_sampler_prefetch; i++) {
 106                 unsigned n = util_last_bit(v->sampler_prefetch[i].wrmask) - 1;
 107                 int32_t regid = v->sampler_prefetch[i].dst + n;
 108                 if (v->sampler_prefetch[i].half_precision) {
 109                         if (!v->mergedregs) {
 110                                 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
 111                         } else {
 112                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
 113                         }
 114                 } else {
 115                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
 116                 }
 117         }
 118 }
 119
 120 /* wrapper for ir3_assemble() which does some info fixup based on
 121  * shader state.  Non-static since used by ir3_cmdline too.
 122  */
 123 void * ir3_shader_assemble(struct ir3_shader_variant *v)
 124 {
 125         unsigned gpu_id = v->shader->compiler->gpu_id;
 126         void *bin;
 127
 128         bin = ir3_assemble(v);
 129         if (!bin)
 130                 return NULL;
 131
 132         if (gpu_id >= 400) {
 133                 v->instrlen = v->info.sizedwords / (2 * 16);
 134         } else {
 135                 v->instrlen = v->info.sizedwords / (2 * 4);
 136         }
 137
 138         /* NOTE: if relative addressing is used, we set constlen in
 139          * the compiler (to worst-case value) since we don't know in
 140          * the assembler what the max addr reg value can be:
 141          */
 142         v->constlen = MAX2(v->constlen, v->info.max_const + 1);
 143
 144         /* On a4xx and newer, constlen must be a multiple of 16 dwords even though
 145          * uploads are in units of 4 dwords. Round it up here to make calculations
 146          * regarding the shared constlen simpler.
 147          */
 148         if (gpu_id >= 400)
 149                 v->constlen = align(v->constlen, 4);
 150
 151         fixup_regfootprint(v);
 152
 153         return bin;
 154 }
 155
 156 static void
 157 assemble_variant(struct ir3_shader_variant *v)
 158 {
 159         v->bin = ir3_shader_assemble(v);
 160
 161         if (shader_debug_enabled(v->shader->type)) {
 162                 fprintf(stdout, "Native code for unnamed %s shader %s:\n",
 163                         ir3_shader_stage(v), v->shader->nir->info.name);
 164                 if (v->shader->type == MESA_SHADER_FRAGMENT)
 165                         fprintf(stdout, "SIMD0\n");
 166                 ir3_shader_disasm(v, v->bin, stdout);
 167         }
 168
 169         /* no need to keep the ir around beyond this point: */
 170         ir3_destroy(v->ir);
 171         v->ir = NULL;
 172 }
 173
 174 static bool
 175 compile_variant(struct ir3_shader_variant *v)
 176 {
 177         int ret = ir3_compile_shader_nir(v->shader->compiler, v);
 178         if (ret) {
 179                 debug_error("compile failed!");
 180                 return false;
 181         }
 182
 183         assemble_variant(v);
 184         if (!v->bin) {
 185                 debug_error("assemble failed!");
 186                 return false;
 187         }
 188
 189         return true;
 190 }
 191
 192 /*
 193  * For creating normal shader variants, 'nonbinning' is NULL.  For
 194  * creating binning pass shader, it is link to corresponding normal
 195  * (non-binning) variant.
 196  */
 197 static struct ir3_shader_variant *
 198 alloc_variant(struct ir3_shader *shader, const struct ir3_shader_key *key,
 199                 struct ir3_shader_variant *nonbinning)
 200 {
 201         void *mem_ctx = shader;
 202         /* hang the binning variant off it's non-binning counterpart instead
 203          * of the shader, to simplify the error cleanup paths
 204          */
 205         if (nonbinning)
 206                 mem_ctx = nonbinning;
 207         struct ir3_shader_variant *v = rzalloc_size(mem_ctx, sizeof(*v));
 208
 209         if (!v)
 210                 return NULL;
 211
 212         v->id = ++shader->variant_count;
 213         v->shader = shader;
 214         v->binning_pass = !!nonbinning;
 215         v->nonbinning = nonbinning;
 216         v->key = *key;
 217         v->type = shader->type;
 218         v->mergedregs = shader->compiler->gpu_id >= 600;
 219
 220         if (!v->binning_pass)
 221                 v->const_state = rzalloc_size(v, sizeof(*v->const_state));
 222
 223         return v;
 224 }
 225
 226 static bool
 227 needs_binning_variant(struct ir3_shader_variant *v)
 228 {
 229         if ((v->type == MESA_SHADER_VERTEX) && ir3_has_binning_vs(&v->key))
 230                 return true;
 231         return false;
 232 }
 233
 234 static struct ir3_shader_variant *
 235 create_variant(struct ir3_shader *shader, const struct ir3_shader_key *key)
 236 {
 237         struct ir3_shader_variant *v = alloc_variant(shader, key, NULL);
 238
 239         if (!v)
 240                 goto fail;
 241
 242         if (needs_binning_variant(v)) {
 243                 v->binning = alloc_variant(shader, key, v);
 244                 if (!v->binning)
 245                         goto fail;
 246         }
 247
 248         if (ir3_disk_cache_retrieve(shader->compiler, v))
 249                 return v;
 250
 251         if (!shader->nir_finalized) {
 252                 ir3_nir_post_finalize(shader->compiler, shader->nir);
 253
 254                 if (ir3_shader_debug & IR3_DBG_DISASM) {
 255                         printf("dump nir%d: type=%d", shader->id, shader->type);
 256                         nir_print_shader(shader->nir, stdout);
 257                 }
 258
 259                 shader->nir_finalized = true;
 260         }
 261
 262         if (!compile_variant(v))
 263                 goto fail;
 264
 265         if (needs_binning_variant(v) && !compile_variant(v->binning))
 266                 goto fail;
 267
 268         ir3_disk_cache_store(shader->compiler, v);
 269
 270         return v;
 271
 272 fail:
 273         ralloc_free(v);
 274         return NULL;
 275 }
 276
 277 static inline struct ir3_shader_variant *
 278 shader_variant(struct ir3_shader *shader, const struct ir3_shader_key *key)
 279 {
 280         struct ir3_shader_variant *v;
 281
 282         for (v = shader->variants; v; v = v->next)
 283                 if (ir3_shader_key_equal(key, &v->key))
 284                         return v;
 285
 286         return NULL;
 287 }
 288
 289 struct ir3_shader_variant *
 290 ir3_shader_get_variant(struct ir3_shader *shader, const struct ir3_shader_key *key,
 291                 bool binning_pass, bool *created)
 292 {
 293         mtx_lock(&shader->variants_lock);
 294         struct ir3_shader_variant *v = shader_variant(shader, key);
 295
 296         if (!v) {
 297                 /* compile new variant if it doesn't exist already: */
 298                 v = create_variant(shader, key);
 299                 if (v) {
 300                         v->next = shader->variants;
 301                         shader->variants = v;
 302                         *created = true;
 303                 }
 304         }
 305
 306         if (v && binning_pass) {
 307                 v = v->binning;
 308                 assert(v);
 309         }
 310
 311         mtx_unlock(&shader->variants_lock);
 312
 313         return v;
 314 }
 315
 316 void
 317 ir3_shader_destroy(struct ir3_shader *shader)
 318 {
 319         ralloc_free(shader->nir);
 320         mtx_destroy(&shader->variants_lock);
 321         ralloc_free(shader);
 322 }
 323
 324 /**
 325  * Creates a bitmask of the used bits of the shader key by this particular
 326  * shader.  Used by the gallium driver to skip state-dependent recompiles when
 327  * possible.
 328  */
 329 static void
 330 ir3_setup_used_key(struct ir3_shader *shader)
 331 {
 332         nir_shader *nir = shader->nir;
 333         struct shader_info *info = &nir->info;
 334         struct ir3_shader_key *key = &shader->key_mask;
 335
 336         /* This key flag is just used to make for a cheaper ir3_shader_key_equal
 337          * check in the common case.
 338          */
 339         key->has_per_samp = true;
 340
 341         key->safe_constlen = true;
 342
 343         if (info->stage == MESA_SHADER_FRAGMENT) {
 344                 key->fsaturate_s = ~0;
 345                 key->fsaturate_t = ~0;
 346                 key->fsaturate_r = ~0;
 347                 key->fastc_srgb = ~0;
 348                 key->fsamples = ~0;
 349
 350                 if (info->inputs_read & VARYING_BITS_COLOR) {
 351                         key->rasterflat = true;
 352                         key->color_two_side = true;
 353                 }
 354
 355                 if ((info->outputs_written & ~(FRAG_RESULT_DEPTH |
 356                                                                 FRAG_RESULT_STENCIL |
 357                                                                 FRAG_RESULT_SAMPLE_MASK)) != 0) {
 358                         key->fclamp_color = true;
 359                 }
 360
 361                 /* Only used for deciding on behavior of
 362                  * nir_intrinsic_load_barycentric_sample
 363                  */
 364                 key->msaa = info->fs.uses_sample_qualifier;
 365         } else {
 366                 key->tessellation = ~0;
 367                 key->has_gs = true;
 368
 369                 if (info->outputs_written & VARYING_BITS_COLOR)
 370                         key->vclamp_color = true;
 371
 372                 if (info->stage == MESA_SHADER_VERTEX) {
 373                         key->vsaturate_s = ~0;
 374                         key->vsaturate_t = ~0;
 375                         key->vsaturate_r = ~0;
 376                         key->vastc_srgb = ~0;
 377                         key->vsamples = ~0;
 378                 }
 379         }
 380 }
 381
 382
 383 /* Given an array of constlen's, decrease some of them so that the sum stays
 384  * within "combined_limit" while trying to fairly share the reduction. Returns
 385  * a bitfield of which stages should be trimmed.
 386  */
 387 static uint32_t
 388 trim_constlens(unsigned *constlens,
 389                            unsigned first_stage, unsigned last_stage,
 390                            unsigned combined_limit, unsigned safe_limit)
 391 {
 392    unsigned cur_total = 0;
 393    for (unsigned i = first_stage; i <= last_stage; i++) {
 394       cur_total += constlens[i];
 395    }
 396
 397    unsigned max_stage;
 398    unsigned max_const = 0;
 399    uint32_t trimmed = 0;
 400
 401    while (cur_total > combined_limit) {
 402            for (unsigned i = first_stage; i <= last_stage; i++) {
 403                    if (constlens[i] >= max_const) {
 404                            max_stage = i;
 405                            max_const = constlens[i];
 406                    }
 407            }
 408
 409            assert(max_const > safe_limit);
 410            trimmed |= 1 << max_stage;
 411            cur_total = cur_total - max_const + safe_limit;
 412            constlens[max_stage] = safe_limit;
 413    }
 414
 415    return trimmed;
 416 }
 417
 418 /* Figures out which stages in the pipeline to use the "safe" constlen for, in
 419  * order to satisfy all shared constlen limits.
 420  */
 421 uint32_t
 422 ir3_trim_constlen(struct ir3_shader_variant **variants,
 423                                   const struct ir3_compiler *compiler)
 424 {
 425         unsigned constlens[MESA_SHADER_STAGES] = {};
 426
 427         for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
 428                 if (variants[i])
 429                         constlens[i] = variants[i]->constlen;
 430         }
 431
 432         uint32_t trimmed = 0;
 433         STATIC_ASSERT(MESA_SHADER_STAGES <= 8 * sizeof(trimmed));
 434
 435         /* There are two shared limits to take into account, the geometry limit on
 436          * a6xx and the total limit. The frag limit on a6xx only matters for a
 437          * single stage, so it's always satisfied with the first variant.
 438          */
 439         if (compiler->gpu_id >= 600) {
 440                 trimmed |=
 441                         trim_constlens(constlens, MESA_SHADER_VERTEX, MESA_SHADER_GEOMETRY,
 442                                                    compiler->max_const_geom, compiler->max_const_safe);
 443         }
 444         trimmed |=
 445                 trim_constlens(constlens, MESA_SHADER_VERTEX, MESA_SHADER_FRAGMENT,
 446                                            compiler->max_const_pipeline, compiler->max_const_safe);
 447
 448         return trimmed;
 449 }
 450
 451 struct ir3_shader *
 452 ir3_shader_from_nir(struct ir3_compiler *compiler, nir_shader *nir,
 453                 unsigned reserved_user_consts, struct ir3_stream_output_info *stream_output)
 454 {
 455         struct ir3_shader *shader = rzalloc_size(NULL, sizeof(*shader));
 456
 457         mtx_init(&shader->variants_lock, mtx_plain);
 458         shader->compiler = compiler;
 459         shader->id = p_atomic_inc_return(&shader->compiler->shader_count);
 460         shader->type = nir->info.stage;
 461         if (stream_output)
 462                 memcpy(&shader->stream_output, stream_output, sizeof(shader->stream_output));
 463         shader->num_reserved_user_consts = reserved_user_consts;
 464         shader->nir = nir;
 465
 466         ir3_disk_cache_init_shader_key(compiler, shader);
 467
 468         ir3_setup_used_key(shader);
 469
 470         return shader;
 471 }
 472
 473 static void dump_reg(FILE *out, const char *name, uint32_t r)
 474 {
 475         if (r != regid(63,0)) {
 476                 const char *reg_type = (r & HALF_REG_ID) ? "hr" : "r";
 477                 fprintf(out, "; %s: %s%d.%c\n", name, reg_type,
 478                                 (r & ~HALF_REG_ID) >> 2, "xyzw"[r & 0x3]);
 479         }
 480 }
 481
 482 static void dump_output(FILE *out, struct ir3_shader_variant *so,
 483                 unsigned slot, const char *name)
 484 {
 485         uint32_t regid;
 486         regid = ir3_find_output_regid(so, slot);
 487         dump_reg(out, name, regid);
 488 }
 489
 490 static const char *
 491 input_name(struct ir3_shader_variant *so, int i)
 492 {
 493         if (so->inputs[i].sysval) {
 494                 return gl_system_value_name(so->inputs[i].slot);
 495         } else if (so->type == MESA_SHADER_VERTEX) {
 496                 return gl_vert_attrib_name(so->inputs[i].slot);
 497         } else {
 498                 return gl_varying_slot_name(so->inputs[i].slot);
 499         }
 500 }
 501
 502 static const char *
 503 output_name(struct ir3_shader_variant *so, int i)
 504 {
 505         if (so->type == MESA_SHADER_FRAGMENT) {
 506                 return gl_frag_result_name(so->outputs[i].slot);
 507         } else {
 508                 switch (so->outputs[i].slot) {
 509                 case VARYING_SLOT_GS_HEADER_IR3:
 510                         return "GS_HEADER";
 511                 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
 512                         return "GS_VERTEX_FLAGS";
 513                 case VARYING_SLOT_TCS_HEADER_IR3:
 514                         return "TCS_HEADER";
 515                 default:
 516                         return gl_varying_slot_name(so->outputs[i].slot);
 517                 }
 518         }
 519 }
 520
 521 void
 522 ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
 523 {
 524         struct ir3 *ir = so->ir;
 525         struct ir3_register *reg;
 526         const char *type = ir3_shader_stage(so);
 527         uint8_t regid;
 528         unsigned i;
 529
 530         foreach_input_n (instr, i, ir) {
 531                 reg = instr->regs[0];
 532                 regid = reg->num;
 533                 fprintf(out, "@in(%sr%d.%c)\tin%d",
 534                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 535                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 536
 537                 if (reg->wrmask > 0x1)
 538                         fprintf(out, " (wrmask=0x%x)", reg->wrmask);
 539                 fprintf(out, "\n");
 540         }
 541
 542         /* print pre-dispatch texture fetches: */
 543         for (i = 0; i < so->num_sampler_prefetch; i++) {
 544                 const struct ir3_sampler_prefetch *fetch = &so->sampler_prefetch[i];
 545                 fprintf(out, "@tex(%sr%d.%c)\tsrc=%u, samp=%u, tex=%u, wrmask=0x%x, cmd=%u\n",
 546                                 fetch->half_precision ? "h" : "",
 547                                 fetch->dst >> 2, "xyzw"[fetch->dst & 0x3],
 548                                 fetch->src, fetch->samp_id, fetch->tex_id,
 549                                 fetch->wrmask, fetch->cmd);
 550         }
 551
 552         foreach_output_n (instr, i, ir) {
 553                 reg = instr->regs[0];
 554                 regid = reg->num;
 555                 fprintf(out, "@out(%sr%d.%c)\tout%d",
 556                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 557                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 558                 if (reg->wrmask > 0x1)
 559                         fprintf(out, " (wrmask=0x%x)", reg->wrmask);
 560                 fprintf(out, "\n");
 561         }
 562
 563         const struct ir3_const_state *const_state = ir3_const_state(so);
 564         for (i = 0; i < const_state->immediates_count; i++) {
 565                 fprintf(out, "@const(c%d.x)\t", const_state->offsets.immediate + i);
 566                 fprintf(out, "0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
 567                                 const_state->immediates[i].val[0],
 568                                 const_state->immediates[i].val[1],
 569                                 const_state->immediates[i].val[2],
 570                                 const_state->immediates[i].val[3]);
 571         }
 572
 573         disasm_a3xx(bin, so->info.sizedwords, 0, out, ir->compiler->gpu_id);
 574
 575         fprintf(out, "; %s: outputs:", type);
 576         for (i = 0; i < so->outputs_count; i++) {
 577                 uint8_t regid = so->outputs[i].regid;
 578                 const char *reg_type = so->outputs[i].half ? "hr" : "r";
 579                 fprintf(out, " %s%d.%c (%s)",
 580                                 reg_type, (regid >> 2), "xyzw"[regid & 0x3],
 581                                 output_name(so, i));
 582         }
 583         fprintf(out, "\n");
 584
 585         fprintf(out, "; %s: inputs:", type);
 586         for (i = 0; i < so->inputs_count; i++) {
 587                 uint8_t regid = so->inputs[i].regid;
 588                 fprintf(out, " r%d.%c (%s slot=%d cm=%x,il=%u,b=%u)",
 589                                 (regid >> 2), "xyzw"[regid & 0x3],
 590                                 input_name(so, i),
 591                                 so->inputs[i].slot,
 592                                 so->inputs[i].compmask,
 593                                 so->inputs[i].inloc,
 594                                 so->inputs[i].bary);
 595         }
 596         fprintf(out, "\n");
 597
 598         /* print generic shader info: */
 599         fprintf(out, "; %s prog %d/%d: %u instr, %u nops, %u non-nops, %u mov, %u cov, %u dwords\n",
 600                         type, so->shader->id, so->id,
 601                         so->info.instrs_count,
 602                         so->info.nops_count,
 603                         so->info.instrs_count - so->info.nops_count,
 604                         so->info.mov_count, so->info.cov_count,
 605                         so->info.sizedwords);
 606
 607         fprintf(out, "; %s prog %d/%d: %u last-baryf, %d half, %d full, %u constlen\n",
 608                         type, so->shader->id, so->id,
 609                         so->info.last_baryf,
 610                         so->info.max_half_reg + 1,
 611                         so->info.max_reg + 1,
 612                         so->constlen);
 613
 614         fprintf(out, "; %s prog %d/%d: %u sstall, %u (ss), %u (sy), %d max_sun, %d loops\n",
 615                         type, so->shader->id, so->id,
 616                         so->info.sstall,
 617                         so->info.ss,
 618                         so->info.sy,
 619                         so->max_sun,
 620                         so->loops);
 621
 622         /* print shader type specific info: */
 623         switch (so->type) {
 624         case MESA_SHADER_VERTEX:
 625                 dump_output(out, so, VARYING_SLOT_POS, "pos");
 626                 dump_output(out, so, VARYING_SLOT_PSIZ, "psize");
 627                 break;
 628         case MESA_SHADER_FRAGMENT:
 629                 dump_reg(out, "pos (ij_pixel)",
 630                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL));
 631                 dump_reg(out, "pos (ij_centroid)",
 632                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID));
 633                 dump_reg(out, "pos (ij_size)",
 634                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE));
 635                 dump_output(out, so, FRAG_RESULT_DEPTH, "posz");
 636                 if (so->color0_mrt) {
 637                         dump_output(out, so, FRAG_RESULT_COLOR, "color");
 638                 } else {
 639                         dump_output(out, so, FRAG_RESULT_DATA0, "data0");
 640                         dump_output(out, so, FRAG_RESULT_DATA1, "data1");
 641                         dump_output(out, so, FRAG_RESULT_DATA2, "data2");
 642                         dump_output(out, so, FRAG_RESULT_DATA3, "data3");
 643                         dump_output(out, so, FRAG_RESULT_DATA4, "data4");
 644                         dump_output(out, so, FRAG_RESULT_DATA5, "data5");
 645                         dump_output(out, so, FRAG_RESULT_DATA6, "data6");
 646                         dump_output(out, so, FRAG_RESULT_DATA7, "data7");
 647                 }
 648                 dump_reg(out, "fragcoord",
 649                         ir3_find_sysval_regid(so, SYSTEM_VALUE_FRAG_COORD));
 650                 dump_reg(out, "fragface",
 651                         ir3_find_sysval_regid(so, SYSTEM_VALUE_FRONT_FACE));
 652                 break;
 653         default:
 654                 /* TODO */
 655                 break;
 656         }
 657
 658         fprintf(out, "\n");
 659 }
 660
 661 uint64_t
 662 ir3_shader_outputs(const struct ir3_shader *so)
 663 {
 664         return so->nir->info.outputs_written;
 665 }