src/freedreno/ir3/ir3_shader.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "util/u_string.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_format.h"
  30
  31 #include "drm/freedreno_drmif.h"
  32
  33 #include "ir3_shader.h"
  34 #include "ir3_compiler.h"
  35 #include "ir3_nir.h"
  36
  37 int
  38 ir3_glsl_type_size(const struct glsl_type *type, bool bindless)
  39 {
  40         return glsl_count_attribute_slots(type, false);
  41 }
  42
  43 static void
  44 delete_variant(struct ir3_shader_variant *v)
  45 {
  46         if (v->ir)
  47                 ir3_destroy(v->ir);
  48         if (v->bo)
  49                 fd_bo_del(v->bo);
  50         free(v);
  51 }
  52
  53 /* for vertex shader, the inputs are loaded into registers before the shader
  54  * is executed, so max_regs from the shader instructions might not properly
  55  * reflect the # of registers actually used, especially in case passthrough
  56  * varyings.
  57  *
  58  * Likewise, for fragment shader, we can have some regs which are passed
  59  * input values but never touched by the resulting shader (ie. as result
  60  * of dead code elimination or simply because we don't know how to turn
  61  * the reg off.
  62  */
  63 static void
  64 fixup_regfootprint(struct ir3_shader_variant *v, uint32_t gpu_id)
  65 {
  66         unsigned i;
  67
  68         for (i = 0; i < v->inputs_count; i++) {
  69                 /* skip frag inputs fetch via bary.f since their reg's are
  70                  * not written by gpu before shader starts (and in fact the
  71                  * regid's might not even be valid)
  72                  */
  73                 if (v->inputs[i].bary)
  74                         continue;
  75
  76                 /* ignore high regs that are global to all threads in a warp
  77                  * (they exist by default) (a5xx+)
  78                  */
  79                 if (v->inputs[i].regid >= regid(48,0))
  80                         continue;
  81
  82                 if (v->inputs[i].compmask) {
  83                         unsigned n = util_last_bit(v->inputs[i].compmask) - 1;
  84                         int32_t regid = v->inputs[i].regid + n;
  85                         if (v->inputs[i].half) {
  86                                 if (gpu_id < 500) {
  87                                         v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
  88                                 } else {
  89                                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
  90                                 }
  91                         } else {
  92                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
  93                         }
  94                 }
  95         }
  96
  97         for (i = 0; i < v->outputs_count; i++) {
  98                 int32_t regid = v->outputs[i].regid + 3;
  99                 if (v->outputs[i].half) {
 100                         if (gpu_id < 500) {
 101                                 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
 102                         } else {
 103                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
 104                         }
 105                 } else {
 106                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
 107                 }
 108         }
 109 }
 110
 111 /* wrapper for ir3_assemble() which does some info fixup based on
 112  * shader state.  Non-static since used by ir3_cmdline too.
 113  */
 114 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id)
 115 {
 116         void *bin;
 117
 118         bin = ir3_assemble(v->ir, &v->info, gpu_id);
 119         if (!bin)
 120                 return NULL;
 121
 122         if (gpu_id >= 400) {
 123                 v->instrlen = v->info.sizedwords / (2 * 16);
 124         } else {
 125                 v->instrlen = v->info.sizedwords / (2 * 4);
 126         }
 127
 128         /* NOTE: if relative addressing is used, we set constlen in
 129          * the compiler (to worst-case value) since we don't know in
 130          * the assembler what the max addr reg value can be:
 131          */
 132         v->constlen = MAX2(v->constlen, v->info.max_const + 1);
 133
 134         fixup_regfootprint(v, gpu_id);
 135
 136         return bin;
 137 }
 138
 139 static void
 140 assemble_variant(struct ir3_shader_variant *v)
 141 {
 142         struct ir3_compiler *compiler = v->shader->compiler;
 143         struct shader_info *info = &v->shader->nir->info;
 144         uint32_t gpu_id = compiler->gpu_id;
 145         uint32_t sz, *bin;
 146
 147         bin = ir3_shader_assemble(v, gpu_id);
 148         sz = v->info.sizedwords * 4;
 149
 150         v->bo = fd_bo_new(compiler->dev, sz,
 151                         DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
 152                         DRM_FREEDRENO_GEM_TYPE_KMEM,
 153                         "%s:%s", ir3_shader_stage(v->shader), info->name);
 154
 155         memcpy(fd_bo_map(v->bo), bin, sz);
 156
 157         if (ir3_shader_debug & IR3_DBG_DISASM) {
 158                 struct ir3_shader_key key = v->key;
 159                 printf("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}\n", v->type,
 160                         v->binning_pass, key.color_two_side, key.half_precision);
 161                 ir3_shader_disasm(v, bin, stdout);
 162         }
 163
 164         if (shader_debug_enabled(v->shader->type)) {
 165                 fprintf(stderr, "Native code for unnamed %s shader %s:\n",
 166                         _mesa_shader_stage_to_string(v->shader->type),
 167                         v->shader->nir->info.name);
 168                 if (v->shader->type == MESA_SHADER_FRAGMENT)
 169                         fprintf(stderr, "SIMD0\n");
 170                 ir3_shader_disasm(v, bin, stderr);
 171         }
 172
 173         free(bin);
 174
 175         /* no need to keep the ir around beyond this point: */
 176         ir3_destroy(v->ir);
 177         v->ir = NULL;
 178 }
 179
 180 static struct ir3_shader_variant *
 181 create_variant(struct ir3_shader *shader, struct ir3_shader_key *key,
 182                 bool binning_pass)
 183 {
 184         struct ir3_shader_variant *v = CALLOC_STRUCT(ir3_shader_variant);
 185         int ret;
 186
 187         if (!v)
 188                 return NULL;
 189
 190         v->id = ++shader->variant_count;
 191         v->shader = shader;
 192         v->binning_pass = binning_pass;
 193         v->key = *key;
 194         v->type = shader->type;
 195
 196         ret = ir3_compile_shader_nir(shader->compiler, v);
 197         if (ret) {
 198                 debug_error("compile failed!");
 199                 goto fail;
 200         }
 201
 202         assemble_variant(v);
 203         if (!v->bo) {
 204                 debug_error("assemble failed!");
 205                 goto fail;
 206         }
 207
 208         return v;
 209
 210 fail:
 211         delete_variant(v);
 212         return NULL;
 213 }
 214
 215 static inline struct ir3_shader_variant *
 216 shader_variant(struct ir3_shader *shader, struct ir3_shader_key *key,
 217                 bool *created)
 218 {
 219         struct ir3_shader_variant *v;
 220
 221         *created = false;
 222
 223         for (v = shader->variants; v; v = v->next)
 224                 if (ir3_shader_key_equal(key, &v->key))
 225                         return v;
 226
 227         /* compile new variant if it doesn't exist already: */
 228         v = create_variant(shader, key, false);
 229         if (v) {
 230                 v->next = shader->variants;
 231                 shader->variants = v;
 232                 *created = true;
 233         }
 234
 235         return v;
 236 }
 237
 238 struct ir3_shader_variant *
 239 ir3_shader_get_variant(struct ir3_shader *shader, struct ir3_shader_key *key,
 240                 bool binning_pass, bool *created)
 241 {
 242         struct ir3_shader_variant *v =
 243                         shader_variant(shader, key, created);
 244
 245         if (v && binning_pass) {
 246                 if (!v->binning)
 247                         v->binning = create_variant(shader, key, true);
 248                 return v->binning;
 249         }
 250
 251         return v;
 252 }
 253
 254 void
 255 ir3_shader_destroy(struct ir3_shader *shader)
 256 {
 257         struct ir3_shader_variant *v, *t;
 258         for (v = shader->variants; v; ) {
 259                 t = v;
 260                 v = v->next;
 261                 delete_variant(t);
 262         }
 263         free(shader->const_state.immediates);
 264         ralloc_free(shader->nir);
 265         free(shader);
 266 }
 267
 268 struct ir3_shader *
 269 ir3_shader_from_nir(struct ir3_compiler *compiler, nir_shader *nir)
 270 {
 271         struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
 272
 273         shader->compiler = compiler;
 274         shader->id = ++shader->compiler->shader_count;
 275         shader->type = nir->info.stage;
 276
 277         NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size,
 278                            (nir_lower_io_options)0);
 279
 280         if (nir->info.stage == MESA_SHADER_FRAGMENT) {
 281                 /* NOTE: lower load_barycentric_at_sample first, since it
 282                  * produces load_barycentric_at_offset:
 283                  */
 284                 NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_sample);
 285                 NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_offset);
 286
 287                 NIR_PASS_V(nir, ir3_nir_move_varying_inputs);
 288         }
 289
 290         NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
 291
 292         /* do first pass optimization, ignoring the key: */
 293         shader->nir = ir3_optimize_nir(shader, nir, NULL);
 294         if (ir3_shader_debug & IR3_DBG_DISASM) {
 295                 printf("dump nir%d: type=%d", shader->id, shader->type);
 296                 nir_print_shader(shader->nir, stdout);
 297         }
 298
 299         return shader;
 300 }
 301
 302 static void dump_reg(FILE *out, const char *name, uint32_t r)
 303 {
 304         if (r != regid(63,0)) {
 305                 const char *reg_type = (r & HALF_REG_ID) ? "hr" : "r";
 306                 fprintf(out, "; %s: %s%d.%c\n", name, reg_type,
 307                                 (r & ~HALF_REG_ID) >> 2, "xyzw"[r & 0x3]);
 308         }
 309 }
 310
 311 static void dump_output(FILE *out, struct ir3_shader_variant *so,
 312                 unsigned slot, const char *name)
 313 {
 314         uint32_t regid;
 315         regid = ir3_find_output_regid(so, slot);
 316         dump_reg(out, name, regid);
 317 }
 318
 319 void
 320 ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
 321 {
 322         struct ir3 *ir = so->ir;
 323         struct ir3_register *reg;
 324         const char *type = ir3_shader_stage(so->shader);
 325         uint8_t regid;
 326         unsigned i;
 327
 328         for (i = 0; i < ir->ninputs; i++) {
 329                 if (!ir->inputs[i]) {
 330                         fprintf(out, "; in%d unused\n", i);
 331                         continue;
 332                 }
 333                 reg = ir->inputs[i]->regs[0];
 334                 regid = reg->num;
 335                 fprintf(out, "@in(%sr%d.%c)\tin%d\n",
 336                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 337                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 338         }
 339
 340         for (i = 0; i < ir->noutputs; i++) {
 341                 if (!ir->outputs[i]) {
 342                         fprintf(out, "; out%d unused\n", i);
 343                         continue;
 344                 }
 345                 /* kill shows up as a virtual output.. skip it! */
 346                 if (is_kill(ir->outputs[i]))
 347                         continue;
 348                 reg = ir->outputs[i]->regs[0];
 349                 regid = reg->num;
 350                 fprintf(out, "@out(%sr%d.%c)\tout%d\n",
 351                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 352                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 353         }
 354
 355         struct ir3_const_state *const_state = &so->shader->const_state;
 356         for (i = 0; i < const_state->immediates_count; i++) {
 357                 fprintf(out, "@const(c%d.x)\t", const_state->offsets.immediate + i);
 358                 fprintf(out, "0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
 359                                 const_state->immediates[i].val[0],
 360                                 const_state->immediates[i].val[1],
 361                                 const_state->immediates[i].val[2],
 362                                 const_state->immediates[i].val[3]);
 363         }
 364
 365         disasm_a3xx(bin, so->info.sizedwords, 0, out, ir->compiler->gpu_id);
 366
 367         switch (so->type) {
 368         case MESA_SHADER_VERTEX:
 369                 fprintf(out, "; %s: outputs:", type);
 370                 for (i = 0; i < so->outputs_count; i++) {
 371                         uint8_t regid = so->outputs[i].regid;
 372                         fprintf(out, " r%d.%c (%s)",
 373                                         (regid >> 2), "xyzw"[regid & 0x3],
 374                                         gl_varying_slot_name(so->outputs[i].slot));
 375                 }
 376                 fprintf(out, "\n");
 377                 fprintf(out, "; %s: inputs:", type);
 378                 for (i = 0; i < so->inputs_count; i++) {
 379                         uint8_t regid = so->inputs[i].regid;
 380                         fprintf(out, " r%d.%c (cm=%x,il=%u,b=%u)",
 381                                         (regid >> 2), "xyzw"[regid & 0x3],
 382                                         so->inputs[i].compmask,
 383                                         so->inputs[i].inloc,
 384                                         so->inputs[i].bary);
 385                 }
 386                 fprintf(out, "\n");
 387                 break;
 388         case MESA_SHADER_FRAGMENT:
 389                 fprintf(out, "; %s: outputs:", type);
 390                 for (i = 0; i < so->outputs_count; i++) {
 391                         uint8_t regid = so->outputs[i].regid;
 392                         const char *reg_type = so->outputs[i].half ? "hr" : "r";
 393                         fprintf(out, " %s%d.%c (%s)",
 394                                         reg_type, (regid >> 2), "xyzw"[regid & 0x3],
 395                                         gl_frag_result_name(so->outputs[i].slot));
 396                 }
 397                 fprintf(out, "\n");
 398                 fprintf(out, "; %s: inputs:", type);
 399                 for (i = 0; i < so->inputs_count; i++) {
 400                         uint8_t regid = so->inputs[i].regid;
 401                         fprintf(out, " r%d.%c (%s,cm=%x,il=%u,b=%u)",
 402                                         (regid >> 2), "xyzw"[regid & 0x3],
 403                                         gl_varying_slot_name(so->inputs[i].slot),
 404                                         so->inputs[i].compmask,
 405                                         so->inputs[i].inloc,
 406                                         so->inputs[i].bary);
 407                 }
 408                 fprintf(out, "\n");
 409                 break;
 410         default:
 411                 /* TODO */
 412                 break;
 413         }
 414
 415         /* print generic shader info: */
 416         fprintf(out, "; %s prog %d/%d: %u instructions, %d half, %d full\n",
 417                         type, so->shader->id, so->id,
 418                         so->info.instrs_count,
 419                         so->info.max_half_reg + 1,
 420                         so->info.max_reg + 1);
 421
 422         fprintf(out, "; %d const, %u constlen\n",
 423                         so->info.max_const + 1,
 424                         so->constlen);
 425
 426         fprintf(out, "; %u (ss), %u (sy)\n", so->info.ss, so->info.sy);
 427
 428         fprintf(out, "; max_sun=%u\n", ir->max_sun);
 429
 430         /* print shader type specific info: */
 431         switch (so->type) {
 432         case MESA_SHADER_VERTEX:
 433                 dump_output(out, so, VARYING_SLOT_POS, "pos");
 434                 dump_output(out, so, VARYING_SLOT_PSIZ, "psize");
 435                 break;
 436         case MESA_SHADER_FRAGMENT:
 437                 dump_reg(out, "pos (ij_pixel)",
 438                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PIXEL));
 439                 dump_reg(out, "pos (ij_centroid)",
 440                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_CENTROID));
 441                 dump_reg(out, "pos (ij_size)",
 442                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_SIZE));
 443                 dump_output(out, so, FRAG_RESULT_DEPTH, "posz");
 444                 if (so->color0_mrt) {
 445                         dump_output(out, so, FRAG_RESULT_COLOR, "color");
 446                 } else {
 447                         dump_output(out, so, FRAG_RESULT_DATA0, "data0");
 448                         dump_output(out, so, FRAG_RESULT_DATA1, "data1");
 449                         dump_output(out, so, FRAG_RESULT_DATA2, "data2");
 450                         dump_output(out, so, FRAG_RESULT_DATA3, "data3");
 451                         dump_output(out, so, FRAG_RESULT_DATA4, "data4");
 452                         dump_output(out, so, FRAG_RESULT_DATA5, "data5");
 453                         dump_output(out, so, FRAG_RESULT_DATA6, "data6");
 454                         dump_output(out, so, FRAG_RESULT_DATA7, "data7");
 455                 }
 456                 /* these two are hard-coded since we don't know how to
 457                  * program them to anything but all 0's...
 458                  */
 459                 if (so->frag_coord)
 460                         fprintf(out, "; fragcoord: r0.x\n");
 461                 if (so->frag_face)
 462                         fprintf(out, "; fragface: hr0.x\n");
 463                 break;
 464         default:
 465                 /* TODO */
 466                 break;
 467         }
 468
 469         fprintf(out, "\n");
 470 }
 471
 472 uint64_t
 473 ir3_shader_outputs(const struct ir3_shader *so)
 474 {
 475         return so->nir->info.outputs_written;
 476 }