src/freedreno/ir3/ir3_shader.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "util/u_atomic.h"
  28 #include "util/u_string.h"
  29 #include "util/u_memory.h"
  30 #include "util/format/u_format.h"
  31
  32 #include "drm/freedreno_drmif.h"
  33
  34 #include "ir3_shader.h"
  35 #include "ir3_compiler.h"
  36 #include "ir3_nir.h"
  37
  38 int
  39 ir3_glsl_type_size(const struct glsl_type *type, bool bindless)
  40 {
  41         return glsl_count_attribute_slots(type, false);
  42 }
  43
  44 static void
  45 delete_variant(struct ir3_shader_variant *v)
  46 {
  47         if (v->ir)
  48                 ir3_destroy(v->ir);
  49         if (v->bo)
  50                 fd_bo_del(v->bo);
  51         if (v->binning)
  52                 delete_variant(v->binning);
  53         free(v);
  54 }
  55
  56 /* for vertex shader, the inputs are loaded into registers before the shader
  57  * is executed, so max_regs from the shader instructions might not properly
  58  * reflect the # of registers actually used, especially in case passthrough
  59  * varyings.
  60  *
  61  * Likewise, for fragment shader, we can have some regs which are passed
  62  * input values but never touched by the resulting shader (ie. as result
  63  * of dead code elimination or simply because we don't know how to turn
  64  * the reg off.
  65  */
  66 static void
  67 fixup_regfootprint(struct ir3_shader_variant *v, uint32_t gpu_id)
  68 {
  69         unsigned i;
  70
  71         for (i = 0; i < v->inputs_count; i++) {
  72                 /* skip frag inputs fetch via bary.f since their reg's are
  73                  * not written by gpu before shader starts (and in fact the
  74                  * regid's might not even be valid)
  75                  */
  76                 if (v->inputs[i].bary)
  77                         continue;
  78
  79                 /* ignore high regs that are global to all threads in a warp
  80                  * (they exist by default) (a5xx+)
  81                  */
  82                 if (v->inputs[i].regid >= regid(48,0))
  83                         continue;
  84
  85                 if (v->inputs[i].compmask) {
  86                         unsigned n = util_last_bit(v->inputs[i].compmask) - 1;
  87                         int32_t regid = v->inputs[i].regid + n;
  88                         if (v->inputs[i].half) {
  89                                 if (gpu_id < 500) {
  90                                         v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
  91                                 } else {
  92                                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
  93                                 }
  94                         } else {
  95                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
  96                         }
  97                 }
  98         }
  99
 100         for (i = 0; i < v->outputs_count; i++) {
 101                 /* for ex, VS shaders with tess don't have normal varying outs: */
 102                 if (!VALIDREG(v->outputs[i].regid))
 103                         continue;
 104                 int32_t regid = v->outputs[i].regid + 3;
 105                 if (v->outputs[i].half) {
 106                         if (gpu_id < 500) {
 107                                 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
 108                         } else {
 109                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
 110                         }
 111                 } else {
 112                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
 113                 }
 114         }
 115
 116         for (i = 0; i < v->num_sampler_prefetch; i++) {
 117                 unsigned n = util_last_bit(v->sampler_prefetch[i].wrmask) - 1;
 118                 int32_t regid = v->sampler_prefetch[i].dst + n;
 119                 if (v->sampler_prefetch[i].half_precision) {
 120                         if (gpu_id < 500) {
 121                                 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
 122                         } else {
 123                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
 124                         }
 125                 } else {
 126                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
 127                 }
 128         }
 129 }
 130
 131 /* wrapper for ir3_assemble() which does some info fixup based on
 132  * shader state.  Non-static since used by ir3_cmdline too.
 133  */
 134 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id)
 135 {
 136         void *bin;
 137
 138         bin = ir3_assemble(v->ir, &v->info, gpu_id);
 139         if (!bin)
 140                 return NULL;
 141
 142         if (gpu_id >= 400) {
 143                 v->instrlen = v->info.sizedwords / (2 * 16);
 144         } else {
 145                 v->instrlen = v->info.sizedwords / (2 * 4);
 146         }
 147
 148         /* NOTE: if relative addressing is used, we set constlen in
 149          * the compiler (to worst-case value) since we don't know in
 150          * the assembler what the max addr reg value can be:
 151          */
 152         v->constlen = MAX2(v->constlen, v->info.max_const + 1);
 153
 154         fixup_regfootprint(v, gpu_id);
 155
 156         return bin;
 157 }
 158
 159 static void
 160 assemble_variant(struct ir3_shader_variant *v)
 161 {
 162         struct ir3_compiler *compiler = v->shader->compiler;
 163         struct shader_info *info = &v->shader->nir->info;
 164         uint32_t gpu_id = compiler->gpu_id;
 165         uint32_t sz, *bin;
 166
 167         bin = ir3_shader_assemble(v, gpu_id);
 168         sz = v->info.sizedwords * 4;
 169
 170         v->bo = fd_bo_new(compiler->dev, sz,
 171                         DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
 172                         DRM_FREEDRENO_GEM_TYPE_KMEM,
 173                         "%s:%s", ir3_shader_stage(v), info->name);
 174
 175         memcpy(fd_bo_map(v->bo), bin, sz);
 176
 177         if (shader_debug_enabled(v->shader->type)) {
 178                 fprintf(stdout, "Native code for unnamed %s shader %s:\n",
 179                         ir3_shader_stage(v), v->shader->nir->info.name);
 180                 if (v->shader->type == MESA_SHADER_FRAGMENT)
 181                         fprintf(stdout, "SIMD0\n");
 182                 ir3_shader_disasm(v, bin, stdout);
 183         }
 184
 185         free(bin);
 186
 187         /* no need to keep the ir around beyond this point: */
 188         ir3_destroy(v->ir);
 189         v->ir = NULL;
 190 }
 191
 192 /*
 193  * For creating normal shader variants, 'nonbinning' is NULL.  For
 194  * creating binning pass shader, it is link to corresponding normal
 195  * (non-binning) variant.
 196  */
 197 static struct ir3_shader_variant *
 198 create_variant(struct ir3_shader *shader, struct ir3_shader_key *key,
 199                 struct ir3_shader_variant *nonbinning)
 200 {
 201         struct ir3_shader_variant *v = CALLOC_STRUCT(ir3_shader_variant);
 202         int ret;
 203
 204         if (!v)
 205                 return NULL;
 206
 207         v->id = ++shader->variant_count;
 208         v->shader = shader;
 209         v->binning_pass = !!nonbinning;
 210         v->nonbinning = nonbinning;
 211         v->key = *key;
 212         v->type = shader->type;
 213
 214         ret = ir3_compile_shader_nir(shader->compiler, v);
 215         if (ret) {
 216                 debug_error("compile failed!");
 217                 goto fail;
 218         }
 219
 220         assemble_variant(v);
 221         if (!v->bo) {
 222                 debug_error("assemble failed!");
 223                 goto fail;
 224         }
 225
 226         return v;
 227
 228 fail:
 229         delete_variant(v);
 230         return NULL;
 231 }
 232
 233 static inline struct ir3_shader_variant *
 234 shader_variant(struct ir3_shader *shader, struct ir3_shader_key *key,
 235                 bool *created)
 236 {
 237         struct ir3_shader_variant *v;
 238
 239         *created = false;
 240
 241         for (v = shader->variants; v; v = v->next)
 242                 if (ir3_shader_key_equal(key, &v->key))
 243                         return v;
 244
 245         /* compile new variant if it doesn't exist already: */
 246         v = create_variant(shader, key, NULL);
 247         if (v) {
 248                 v->next = shader->variants;
 249                 shader->variants = v;
 250                 *created = true;
 251         }
 252
 253         return v;
 254 }
 255
 256 struct ir3_shader_variant *
 257 ir3_shader_get_variant(struct ir3_shader *shader, struct ir3_shader_key *key,
 258                 bool binning_pass, bool *created)
 259 {
 260         mtx_lock(&shader->variants_lock);
 261         struct ir3_shader_variant *v =
 262                         shader_variant(shader, key, created);
 263
 264         if (v && binning_pass) {
 265                 if (!v->binning) {
 266                         v->binning = create_variant(shader, key, v);
 267                         *created = true;
 268                 }
 269                 mtx_unlock(&shader->variants_lock);
 270                 return v->binning;
 271         }
 272         mtx_unlock(&shader->variants_lock);
 273
 274         return v;
 275 }
 276
 277 void
 278 ir3_shader_destroy(struct ir3_shader *shader)
 279 {
 280         struct ir3_shader_variant *v, *t;
 281         for (v = shader->variants; v; ) {
 282                 t = v;
 283                 v = v->next;
 284                 delete_variant(t);
 285         }
 286         free(shader->const_state.immediates);
 287         ralloc_free(shader->nir);
 288         mtx_destroy(&shader->variants_lock);
 289         free(shader);
 290 }
 291
 292 struct ir3_shader *
 293 ir3_shader_from_nir(struct ir3_compiler *compiler, nir_shader *nir,
 294                 struct ir3_stream_output_info *stream_output)
 295 {
 296         struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
 297
 298         mtx_init(&shader->variants_lock, mtx_plain);
 299         shader->compiler = compiler;
 300         shader->id = p_atomic_inc_return(&shader->compiler->shader_count);
 301         shader->type = nir->info.stage;
 302         if (stream_output)
 303                 memcpy(&shader->stream_output, stream_output, sizeof(shader->stream_output));
 304
 305         NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size,
 306                            (nir_lower_io_options)0);
 307
 308         if (compiler->gpu_id >= 600 &&
 309                         nir->info.stage == MESA_SHADER_FRAGMENT &&
 310                         !(ir3_shader_debug & IR3_DBG_NOFP16))
 311                 NIR_PASS_V(nir, nir_lower_mediump_outputs);
 312
 313         if (nir->info.stage == MESA_SHADER_FRAGMENT) {
 314                 /* NOTE: lower load_barycentric_at_sample first, since it
 315                  * produces load_barycentric_at_offset:
 316                  */
 317                 NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_sample);
 318                 NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_offset);
 319
 320                 NIR_PASS_V(nir, ir3_nir_move_varying_inputs);
 321         }
 322
 323         NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
 324
 325         NIR_PASS_V(nir, nir_lower_amul, ir3_glsl_type_size);
 326
 327         /* do first pass optimization, ignoring the key: */
 328         ir3_optimize_nir(shader, nir, NULL);
 329
 330         shader->nir = nir;
 331         if (ir3_shader_debug & IR3_DBG_DISASM) {
 332                 printf("dump nir%d: type=%d", shader->id, shader->type);
 333                 nir_print_shader(shader->nir, stdout);
 334         }
 335
 336         return shader;
 337 }
 338
 339 static void dump_reg(FILE *out, const char *name, uint32_t r)
 340 {
 341         if (r != regid(63,0)) {
 342                 const char *reg_type = (r & HALF_REG_ID) ? "hr" : "r";
 343                 fprintf(out, "; %s: %s%d.%c\n", name, reg_type,
 344                                 (r & ~HALF_REG_ID) >> 2, "xyzw"[r & 0x3]);
 345         }
 346 }
 347
 348 static void dump_output(FILE *out, struct ir3_shader_variant *so,
 349                 unsigned slot, const char *name)
 350 {
 351         uint32_t regid;
 352         regid = ir3_find_output_regid(so, slot);
 353         dump_reg(out, name, regid);
 354 }
 355
 356 static const char *
 357 input_name(struct ir3_shader_variant *so, int i)
 358 {
 359         if (so->inputs[i].sysval) {
 360                 return gl_system_value_name(so->inputs[i].slot);
 361         } else if (so->type == MESA_SHADER_VERTEX) {
 362                 return gl_vert_attrib_name(so->inputs[i].slot);
 363         } else {
 364                 return gl_varying_slot_name(so->inputs[i].slot);
 365         }
 366 }
 367
 368 static const char *
 369 output_name(struct ir3_shader_variant *so, int i)
 370 {
 371         if (so->type == MESA_SHADER_FRAGMENT) {
 372                 return gl_frag_result_name(so->outputs[i].slot);
 373         } else {
 374                 switch (so->outputs[i].slot) {
 375                 case VARYING_SLOT_GS_HEADER_IR3:
 376                         return "GS_HEADER";
 377                 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
 378                         return "GS_VERTEX_FLAGS";
 379                 case VARYING_SLOT_TCS_HEADER_IR3:
 380                         return "TCS_HEADER";
 381                 default:
 382                         return gl_varying_slot_name(so->outputs[i].slot);
 383                 }
 384         }
 385 }
 386
 387 void
 388 ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
 389 {
 390         struct ir3 *ir = so->ir;
 391         struct ir3_register *reg;
 392         const char *type = ir3_shader_stage(so);
 393         uint8_t regid;
 394         unsigned i;
 395
 396         struct ir3_instruction *instr;
 397         foreach_input_n (instr, i, ir) {
 398                 reg = instr->regs[0];
 399                 regid = reg->num;
 400                 fprintf(out, "@in(%sr%d.%c)\tin%d",
 401                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 402                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 403
 404                 if (reg->wrmask > 0x1)
 405                         fprintf(out, " (wrmask=0x%x)", reg->wrmask);
 406                 fprintf(out, "\n");
 407         }
 408
 409         /* print pre-dispatch texture fetches: */
 410         for (i = 0; i < so->num_sampler_prefetch; i++) {
 411                 const struct ir3_sampler_prefetch *fetch = &so->sampler_prefetch[i];
 412                 fprintf(out, "@tex(%sr%d.%c)\tsrc=%u, samp=%u, tex=%u, wrmask=0x%x, cmd=%u\n",
 413                                 fetch->half_precision ? "h" : "",
 414                                 fetch->dst >> 2, "xyzw"[fetch->dst & 0x3],
 415                                 fetch->src, fetch->samp_id, fetch->tex_id,
 416                                 fetch->wrmask, fetch->cmd);
 417         }
 418
 419         foreach_output_n (instr, i, ir) {
 420                 reg = instr->regs[0];
 421                 regid = reg->num;
 422                 fprintf(out, "@out(%sr%d.%c)\tout%d",
 423                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 424                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 425                 if (reg->wrmask > 0x1)
 426                         fprintf(out, " (wrmask=0x%x)", reg->wrmask);
 427                 fprintf(out, "\n");
 428         }
 429
 430         struct ir3_const_state *const_state = &so->shader->const_state;
 431         for (i = 0; i < const_state->immediates_count; i++) {
 432                 fprintf(out, "@const(c%d.x)\t", const_state->offsets.immediate + i);
 433                 fprintf(out, "0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
 434                                 const_state->immediates[i].val[0],
 435                                 const_state->immediates[i].val[1],
 436                                 const_state->immediates[i].val[2],
 437                                 const_state->immediates[i].val[3]);
 438         }
 439
 440         disasm_a3xx(bin, so->info.sizedwords, 0, out, ir->compiler->gpu_id);
 441
 442         fprintf(out, "; %s: outputs:", type);
 443         for (i = 0; i < so->outputs_count; i++) {
 444                 uint8_t regid = so->outputs[i].regid;
 445                 const char *reg_type = so->outputs[i].half ? "hr" : "r";
 446                 fprintf(out, " %s%d.%c (%s)",
 447                                 reg_type, (regid >> 2), "xyzw"[regid & 0x3],
 448                                 output_name(so, i));
 449         }
 450         fprintf(out, "\n");
 451
 452         fprintf(out, "; %s: inputs:", type);
 453         for (i = 0; i < so->inputs_count; i++) {
 454                 uint8_t regid = so->inputs[i].regid;
 455                 fprintf(out, " r%d.%c (%s slot=%d cm=%x,il=%u,b=%u)",
 456                                 (regid >> 2), "xyzw"[regid & 0x3],
 457                                 input_name(so, i),
 458                                 so->inputs[i].slot,
 459                                 so->inputs[i].compmask,
 460                                 so->inputs[i].inloc,
 461                                 so->inputs[i].bary);
 462         }
 463         fprintf(out, "\n");
 464
 465         /* print generic shader info: */
 466         fprintf(out, "; %s prog %d/%d: %u instr, %u nops, %u non-nops, %u mov, %u cov, %u dwords\n",
 467                         type, so->shader->id, so->id,
 468                         so->info.instrs_count,
 469                         so->info.nops_count,
 470                         so->info.instrs_count - so->info.nops_count,
 471                         so->info.mov_count, so->info.cov_count,
 472                         so->info.sizedwords);
 473
 474         fprintf(out, "; %s prog %d/%d: %u last-baryf, %d half, %d full, %u constlen\n",
 475                         type, so->shader->id, so->id,
 476                         so->info.last_baryf,
 477                         so->info.max_half_reg + 1,
 478                         so->info.max_reg + 1,
 479                         so->constlen);
 480
 481         fprintf(out, "; %s prog %d/%d: %u sstall, %u (ss), %u (sy), %d max_sun, %d loops\n",
 482                         type, so->shader->id, so->id,
 483                         so->info.sstall,
 484                         so->info.ss,
 485                         so->info.sy,
 486                         so->max_sun,
 487                         so->loops);
 488
 489         /* print shader type specific info: */
 490         switch (so->type) {
 491         case MESA_SHADER_VERTEX:
 492                 dump_output(out, so, VARYING_SLOT_POS, "pos");
 493                 dump_output(out, so, VARYING_SLOT_PSIZ, "psize");
 494                 break;
 495         case MESA_SHADER_FRAGMENT:
 496                 dump_reg(out, "pos (ij_pixel)",
 497                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL));
 498                 dump_reg(out, "pos (ij_centroid)",
 499                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID));
 500                 dump_reg(out, "pos (ij_size)",
 501                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE));
 502                 dump_output(out, so, FRAG_RESULT_DEPTH, "posz");
 503                 if (so->color0_mrt) {
 504                         dump_output(out, so, FRAG_RESULT_COLOR, "color");
 505                 } else {
 506                         dump_output(out, so, FRAG_RESULT_DATA0, "data0");
 507                         dump_output(out, so, FRAG_RESULT_DATA1, "data1");
 508                         dump_output(out, so, FRAG_RESULT_DATA2, "data2");
 509                         dump_output(out, so, FRAG_RESULT_DATA3, "data3");
 510                         dump_output(out, so, FRAG_RESULT_DATA4, "data4");
 511                         dump_output(out, so, FRAG_RESULT_DATA5, "data5");
 512                         dump_output(out, so, FRAG_RESULT_DATA6, "data6");
 513                         dump_output(out, so, FRAG_RESULT_DATA7, "data7");
 514                 }
 515                 dump_reg(out, "fragcoord",
 516                         ir3_find_sysval_regid(so, SYSTEM_VALUE_FRAG_COORD));
 517                 dump_reg(out, "fragface",
 518                         ir3_find_sysval_regid(so, SYSTEM_VALUE_FRONT_FACE));
 519                 break;
 520         default:
 521                 /* TODO */
 522                 break;
 523         }
 524
 525         fprintf(out, "\n");
 526 }
 527
 528 uint64_t
 529 ir3_shader_outputs(const struct ir3_shader *so)
 530 {
 531         return so->nir->info.outputs_written;
 532 }