2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "util/u_atomic.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_format.h"
32 #include "drm/freedreno_drmif.h"
34 #include "ir3_shader.h"
35 #include "ir3_compiler.h"
39 ir3_glsl_type_size(const struct glsl_type
*type
, bool bindless
)
41 return glsl_count_attribute_slots(type
, false);
45 delete_variant(struct ir3_shader_variant
*v
)
54 /* for vertex shader, the inputs are loaded into registers before the shader
55 * is executed, so max_regs from the shader instructions might not properly
56 * reflect the # of registers actually used, especially in case passthrough
59 * Likewise, for fragment shader, we can have some regs which are passed
60 * input values but never touched by the resulting shader (ie. as result
61 * of dead code elimination or simply because we don't know how to turn
65 fixup_regfootprint(struct ir3_shader_variant
*v
, uint32_t gpu_id
)
69 for (i
= 0; i
< v
->inputs_count
; i
++) {
70 /* skip frag inputs fetch via bary.f since their reg's are
71 * not written by gpu before shader starts (and in fact the
72 * regid's might not even be valid)
74 if (v
->inputs
[i
].bary
)
77 /* ignore high regs that are global to all threads in a warp
78 * (they exist by default) (a5xx+)
80 if (v
->inputs
[i
].regid
>= regid(48,0))
83 if (v
->inputs
[i
].compmask
) {
84 unsigned n
= util_last_bit(v
->inputs
[i
].compmask
) - 1;
85 int32_t regid
= v
->inputs
[i
].regid
+ n
;
86 if (v
->inputs
[i
].half
) {
88 v
->info
.max_half_reg
= MAX2(v
->info
.max_half_reg
, regid
>> 2);
90 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 3);
93 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 2);
98 for (i
= 0; i
< v
->outputs_count
; i
++) {
99 int32_t regid
= v
->outputs
[i
].regid
+ 3;
100 if (v
->outputs
[i
].half
) {
102 v
->info
.max_half_reg
= MAX2(v
->info
.max_half_reg
, regid
>> 2);
104 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 3);
107 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 2);
111 for (i
= 0; i
< v
->num_sampler_prefetch
; i
++) {
112 unsigned n
= util_last_bit(v
->sampler_prefetch
[i
].wrmask
) - 1;
113 int32_t regid
= v
->sampler_prefetch
[i
].dst
+ n
;
114 if (v
->sampler_prefetch
[i
].half_precision
) {
116 v
->info
.max_half_reg
= MAX2(v
->info
.max_half_reg
, regid
>> 2);
118 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 3);
121 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 2);
126 /* wrapper for ir3_assemble() which does some info fixup based on
127 * shader state. Non-static since used by ir3_cmdline too.
129 void * ir3_shader_assemble(struct ir3_shader_variant
*v
, uint32_t gpu_id
)
133 bin
= ir3_assemble(v
->ir
, &v
->info
, gpu_id
);
138 v
->instrlen
= v
->info
.sizedwords
/ (2 * 16);
140 v
->instrlen
= v
->info
.sizedwords
/ (2 * 4);
143 /* NOTE: if relative addressing is used, we set constlen in
144 * the compiler (to worst-case value) since we don't know in
145 * the assembler what the max addr reg value can be:
147 v
->constlen
= MAX2(v
->constlen
, v
->info
.max_const
+ 1);
149 fixup_regfootprint(v
, gpu_id
);
155 assemble_variant(struct ir3_shader_variant
*v
)
157 struct ir3_compiler
*compiler
= v
->shader
->compiler
;
158 struct shader_info
*info
= &v
->shader
->nir
->info
;
159 uint32_t gpu_id
= compiler
->gpu_id
;
162 bin
= ir3_shader_assemble(v
, gpu_id
);
163 sz
= v
->info
.sizedwords
* 4;
165 v
->bo
= fd_bo_new(compiler
->dev
, sz
,
166 DRM_FREEDRENO_GEM_CACHE_WCOMBINE
|
167 DRM_FREEDRENO_GEM_TYPE_KMEM
,
168 "%s:%s", ir3_shader_stage(v
), info
->name
);
170 memcpy(fd_bo_map(v
->bo
), bin
, sz
);
172 if (shader_debug_enabled(v
->shader
->type
)) {
173 fprintf(stdout
, "Native code for unnamed %s shader %s:\n",
174 ir3_shader_stage(v
), v
->shader
->nir
->info
.name
);
175 if (v
->shader
->type
== MESA_SHADER_FRAGMENT
)
176 fprintf(stdout
, "SIMD0\n");
177 ir3_shader_disasm(v
, bin
, stdout
);
182 /* no need to keep the ir around beyond this point: */
188 * For creating normal shader variants, 'nonbinning' is NULL. For
189 * creating binning pass shader, it is link to corresponding normal
190 * (non-binning) variant.
192 static struct ir3_shader_variant
*
193 create_variant(struct ir3_shader
*shader
, struct ir3_shader_key
*key
,
194 struct ir3_shader_variant
*nonbinning
)
196 struct ir3_shader_variant
*v
= CALLOC_STRUCT(ir3_shader_variant
);
202 v
->id
= ++shader
->variant_count
;
204 v
->binning_pass
= !!nonbinning
;
205 v
->nonbinning
= nonbinning
;
207 v
->type
= shader
->type
;
209 ret
= ir3_compile_shader_nir(shader
->compiler
, v
);
211 debug_error("compile failed!");
217 debug_error("assemble failed!");
228 static inline struct ir3_shader_variant
*
229 shader_variant(struct ir3_shader
*shader
, struct ir3_shader_key
*key
,
232 struct ir3_shader_variant
*v
;
236 for (v
= shader
->variants
; v
; v
= v
->next
)
237 if (ir3_shader_key_equal(key
, &v
->key
))
240 /* compile new variant if it doesn't exist already: */
241 v
= create_variant(shader
, key
, NULL
);
243 v
->next
= shader
->variants
;
244 shader
->variants
= v
;
251 struct ir3_shader_variant
*
252 ir3_shader_get_variant(struct ir3_shader
*shader
, struct ir3_shader_key
*key
,
253 bool binning_pass
, bool *created
)
255 mtx_lock(&shader
->variants_lock
);
256 struct ir3_shader_variant
*v
=
257 shader_variant(shader
, key
, created
);
259 if (v
&& binning_pass
) {
261 v
->binning
= create_variant(shader
, key
, v
);
264 mtx_unlock(&shader
->variants_lock
);
267 mtx_unlock(&shader
->variants_lock
);
273 ir3_shader_destroy(struct ir3_shader
*shader
)
275 struct ir3_shader_variant
*v
, *t
;
276 for (v
= shader
->variants
; v
; ) {
281 free(shader
->const_state
.immediates
);
282 ralloc_free(shader
->nir
);
283 mtx_destroy(&shader
->variants_lock
);
288 ir3_shader_from_nir(struct ir3_compiler
*compiler
, nir_shader
*nir
)
290 struct ir3_shader
*shader
= CALLOC_STRUCT(ir3_shader
);
292 mtx_init(&shader
->variants_lock
, mtx_plain
);
293 shader
->compiler
= compiler
;
294 shader
->id
= p_atomic_inc_return(&shader
->compiler
->shader_count
);
295 shader
->type
= nir
->info
.stage
;
297 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, ir3_glsl_type_size
,
298 (nir_lower_io_options
)0);
300 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
301 /* NOTE: lower load_barycentric_at_sample first, since it
302 * produces load_barycentric_at_offset:
304 NIR_PASS_V(nir
, ir3_nir_lower_load_barycentric_at_sample
);
305 NIR_PASS_V(nir
, ir3_nir_lower_load_barycentric_at_offset
);
307 NIR_PASS_V(nir
, ir3_nir_move_varying_inputs
);
310 NIR_PASS_V(nir
, nir_lower_io_arrays_to_elements_no_indirects
, false);
312 NIR_PASS_V(nir
, nir_lower_amul
, ir3_glsl_type_size
);
314 /* do first pass optimization, ignoring the key: */
315 ir3_optimize_nir(shader
, nir
, NULL
);
318 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
319 printf("dump nir%d: type=%d", shader
->id
, shader
->type
);
320 nir_print_shader(shader
->nir
, stdout
);
326 static void dump_reg(FILE *out
, const char *name
, uint32_t r
)
328 if (r
!= regid(63,0)) {
329 const char *reg_type
= (r
& HALF_REG_ID
) ? "hr" : "r";
330 fprintf(out
, "; %s: %s%d.%c\n", name
, reg_type
,
331 (r
& ~HALF_REG_ID
) >> 2, "xyzw"[r
& 0x3]);
335 static void dump_output(FILE *out
, struct ir3_shader_variant
*so
,
336 unsigned slot
, const char *name
)
339 regid
= ir3_find_output_regid(so
, slot
);
340 dump_reg(out
, name
, regid
);
344 input_name(struct ir3_shader_variant
*so
, int i
)
346 if (so
->inputs
[i
].sysval
) {
347 return gl_system_value_name(so
->inputs
[i
].slot
);
348 } else if (so
->type
== MESA_SHADER_VERTEX
) {
349 return gl_vert_attrib_name(so
->inputs
[i
].slot
);
351 return gl_varying_slot_name(so
->inputs
[i
].slot
);
356 output_name(struct ir3_shader_variant
*so
, int i
)
358 if (so
->type
== MESA_SHADER_FRAGMENT
) {
359 return gl_frag_result_name(so
->outputs
[i
].slot
);
361 switch (so
->outputs
[i
].slot
) {
362 case VARYING_SLOT_GS_HEADER_IR3
:
364 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3
:
365 return "GS_VERTEX_FLAGS";
366 case VARYING_SLOT_TCS_HEADER_IR3
:
369 return gl_varying_slot_name(so
->outputs
[i
].slot
);
375 ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
, FILE *out
)
377 struct ir3
*ir
= so
->ir
;
378 struct ir3_register
*reg
;
379 const char *type
= ir3_shader_stage(so
);
383 for (i
= 0; i
< ir
->ninputs
; i
++) {
384 if (!ir
->inputs
[i
]) {
385 fprintf(out
, "; in%d unused\n", i
);
388 reg
= ir
->inputs
[i
]->regs
[0];
390 fprintf(out
, "@in(%sr%d.%c)\tin%d\n",
391 (reg
->flags
& IR3_REG_HALF
) ? "h" : "",
392 (regid
>> 2), "xyzw"[regid
& 0x3], i
);
395 /* print pre-dispatch texture fetches: */
396 for (i
= 0; i
< so
->num_sampler_prefetch
; i
++) {
397 const struct ir3_sampler_prefetch
*fetch
= &so
->sampler_prefetch
[i
];
398 fprintf(out
, "@tex(%sr%d.%c)\tsrc=%u, samp=%u, tex=%u, wrmask=%x, cmd=%u\n",
399 fetch
->half_precision
? "h" : "",
400 fetch
->dst
>> 2, "xyzw"[fetch
->dst
& 0x3],
401 fetch
->src
, fetch
->samp_id
, fetch
->tex_id
,
402 fetch
->wrmask
, fetch
->cmd
);
405 for (i
= 0; i
< ir
->noutputs
; i
++) {
406 if (!ir
->outputs
[i
]) {
407 fprintf(out
, "; out%d unused\n", i
);
410 /* kill shows up as a virtual output.. skip it! */
411 if (is_kill(ir
->outputs
[i
]))
413 reg
= ir
->outputs
[i
]->regs
[0];
415 fprintf(out
, "@out(%sr%d.%c)\tout%d\n",
416 (reg
->flags
& IR3_REG_HALF
) ? "h" : "",
417 (regid
>> 2), "xyzw"[regid
& 0x3], i
);
420 struct ir3_const_state
*const_state
= &so
->shader
->const_state
;
421 for (i
= 0; i
< const_state
->immediates_count
; i
++) {
422 fprintf(out
, "@const(c%d.x)\t", const_state
->offsets
.immediate
+ i
);
423 fprintf(out
, "0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
424 const_state
->immediates
[i
].val
[0],
425 const_state
->immediates
[i
].val
[1],
426 const_state
->immediates
[i
].val
[2],
427 const_state
->immediates
[i
].val
[3]);
430 disasm_a3xx(bin
, so
->info
.sizedwords
, 0, out
, ir
->compiler
->gpu_id
);
432 fprintf(out
, "; %s: outputs:", type
);
433 for (i
= 0; i
< so
->outputs_count
; i
++) {
434 uint8_t regid
= so
->outputs
[i
].regid
;
435 fprintf(out
, " r%d.%c (%s)",
436 (regid
>> 2), "xyzw"[regid
& 0x3],
441 fprintf(out
, "; %s: inputs:", type
);
442 for (i
= 0; i
< so
->inputs_count
; i
++) {
443 uint8_t regid
= so
->inputs
[i
].regid
;
444 fprintf(out
, " r%d.%c (%s slot=%d cm=%x,il=%u,b=%u)",
445 (regid
>> 2), "xyzw"[regid
& 0x3],
448 so
->inputs
[i
].compmask
,
454 /* print generic shader info: */
455 fprintf(out
, "; %s prog %d/%d: %u instructions, %d half, %d full\n",
456 type
, so
->shader
->id
, so
->id
,
457 so
->info
.instrs_count
,
458 so
->info
.max_half_reg
+ 1,
459 so
->info
.max_reg
+ 1);
461 fprintf(out
, "; %u constlen\n", so
->constlen
);
463 fprintf(out
, "; %u (ss), %u (sy)\n", so
->info
.ss
, so
->info
.sy
);
465 fprintf(out
, "; max_sun=%u\n", ir
->max_sun
);
467 /* print shader type specific info: */
469 case MESA_SHADER_VERTEX
:
470 dump_output(out
, so
, VARYING_SLOT_POS
, "pos");
471 dump_output(out
, so
, VARYING_SLOT_PSIZ
, "psize");
473 case MESA_SHADER_FRAGMENT
:
474 dump_reg(out
, "pos (ij_pixel)",
475 ir3_find_sysval_regid(so
, SYSTEM_VALUE_BARYCENTRIC_PIXEL
));
476 dump_reg(out
, "pos (ij_centroid)",
477 ir3_find_sysval_regid(so
, SYSTEM_VALUE_BARYCENTRIC_CENTROID
));
478 dump_reg(out
, "pos (ij_size)",
479 ir3_find_sysval_regid(so
, SYSTEM_VALUE_BARYCENTRIC_SIZE
));
480 dump_output(out
, so
, FRAG_RESULT_DEPTH
, "posz");
481 if (so
->color0_mrt
) {
482 dump_output(out
, so
, FRAG_RESULT_COLOR
, "color");
484 dump_output(out
, so
, FRAG_RESULT_DATA0
, "data0");
485 dump_output(out
, so
, FRAG_RESULT_DATA1
, "data1");
486 dump_output(out
, so
, FRAG_RESULT_DATA2
, "data2");
487 dump_output(out
, so
, FRAG_RESULT_DATA3
, "data3");
488 dump_output(out
, so
, FRAG_RESULT_DATA4
, "data4");
489 dump_output(out
, so
, FRAG_RESULT_DATA5
, "data5");
490 dump_output(out
, so
, FRAG_RESULT_DATA6
, "data6");
491 dump_output(out
, so
, FRAG_RESULT_DATA7
, "data7");
493 /* these two are hard-coded since we don't know how to
494 * program them to anything but all 0's...
497 fprintf(out
, "; fragcoord: r0.x\n");
499 fprintf(out
, "; fragface: hr0.x\n");
510 ir3_shader_outputs(const struct ir3_shader
*so
)
512 return so
->nir
->info
.outputs_written
;