src/freedreno/ir3/ir3_shader.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "util/u_string.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_format.h"
  30
  31 #include "drm/freedreno_drmif.h"
  32
  33 #include "ir3_shader.h"
  34 #include "ir3_compiler.h"
  35 #include "ir3_nir.h"
  36
  37 int
  38 ir3_glsl_type_size(const struct glsl_type *type)
  39 {
  40         return glsl_count_attribute_slots(type, false);
  41 }
  42
  43 static void
  44 delete_variant(struct ir3_shader_variant *v)
  45 {
  46         if (v->ir)
  47                 ir3_destroy(v->ir);
  48         if (v->bo)
  49                 fd_bo_del(v->bo);
  50         if (v->immediates)
  51                 free(v->immediates);
  52         free(v);
  53 }
  54
  55 /* for vertex shader, the inputs are loaded into registers before the shader
  56  * is executed, so max_regs from the shader instructions might not properly
  57  * reflect the # of registers actually used, especially in case passthrough
  58  * varyings.
  59  *
  60  * Likewise, for fragment shader, we can have some regs which are passed
  61  * input values but never touched by the resulting shader (ie. as result
  62  * of dead code elimination or simply because we don't know how to turn
  63  * the reg off.
  64  */
  65 static void
  66 fixup_regfootprint(struct ir3_shader_variant *v)
  67 {
  68         unsigned i;
  69
  70         for (i = 0; i < v->inputs_count; i++) {
  71                 /* skip frag inputs fetch via bary.f since their reg's are
  72                  * not written by gpu before shader starts (and in fact the
  73                  * regid's might not even be valid)
  74                  */
  75                 if (v->inputs[i].bary)
  76                         continue;
  77
  78                 /* ignore high regs that are global to all threads in a warp
  79                  * (they exist by default) (a5xx+)
  80                  */
  81                 if (v->inputs[i].regid >= regid(48,0))
  82                         continue;
  83
  84                 if (v->inputs[i].compmask) {
  85                         unsigned n = util_last_bit(v->inputs[i].compmask) - 1;
  86                         int32_t regid = (v->inputs[i].regid + n) >> 2;
  87                         v->info.max_reg = MAX2(v->info.max_reg, regid);
  88                 }
  89         }
  90
  91         for (i = 0; i < v->outputs_count; i++) {
  92                 int32_t regid = (v->outputs[i].regid + 3) >> 2;
  93                 v->info.max_reg = MAX2(v->info.max_reg, regid);
  94         }
  95 }
  96
  97 /* wrapper for ir3_assemble() which does some info fixup based on
  98  * shader state.  Non-static since used by ir3_cmdline too.
  99  */
 100 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id)
 101 {
 102         void *bin;
 103
 104         bin = ir3_assemble(v->ir, &v->info, gpu_id);
 105         if (!bin)
 106                 return NULL;
 107
 108         if (gpu_id >= 400) {
 109                 v->instrlen = v->info.sizedwords / (2 * 16);
 110         } else {
 111                 v->instrlen = v->info.sizedwords / (2 * 4);
 112         }
 113
 114         /* NOTE: if relative addressing is used, we set constlen in
 115          * the compiler (to worst-case value) since we don't know in
 116          * the assembler what the max addr reg value can be:
 117          */
 118         v->constlen = MIN2(255, MAX2(v->constlen, v->info.max_const + 1));
 119
 120         fixup_regfootprint(v);
 121
 122         return bin;
 123 }
 124
 125 static void
 126 assemble_variant(struct ir3_shader_variant *v)
 127 {
 128         struct ir3_compiler *compiler = v->shader->compiler;
 129         uint32_t gpu_id = compiler->gpu_id;
 130         uint32_t sz, *bin;
 131
 132         bin = ir3_shader_assemble(v, gpu_id);
 133         sz = v->info.sizedwords * 4;
 134
 135         v->bo = fd_bo_new(compiler->dev, sz,
 136                         DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
 137                         DRM_FREEDRENO_GEM_TYPE_KMEM);
 138
 139         memcpy(fd_bo_map(v->bo), bin, sz);
 140
 141         if (ir3_shader_debug & IR3_DBG_DISASM) {
 142                 struct ir3_shader_key key = v->key;
 143                 printf("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}", v->type,
 144                         v->binning_pass, key.color_two_side, key.half_precision);
 145                 ir3_shader_disasm(v, bin, stdout);
 146         }
 147
 148         if (shader_debug_enabled(v->shader->type)) {
 149                 fprintf(stderr, "Native code for unnamed %s shader %s:\n",
 150                         _mesa_shader_stage_to_string(v->shader->type),
 151                         v->shader->nir->info.name);
 152                 if (v->shader->type == MESA_SHADER_FRAGMENT)
 153                         fprintf(stderr, "SIMD0\n");
 154                 ir3_shader_disasm(v, bin, stderr);
 155         }
 156
 157         free(bin);
 158
 159         /* no need to keep the ir around beyond this point: */
 160         ir3_destroy(v->ir);
 161         v->ir = NULL;
 162 }
 163
 164 static struct ir3_shader_variant *
 165 create_variant(struct ir3_shader *shader, struct ir3_shader_key *key,
 166                 bool binning_pass)
 167 {
 168         struct ir3_shader_variant *v = CALLOC_STRUCT(ir3_shader_variant);
 169         int ret;
 170
 171         if (!v)
 172                 return NULL;
 173
 174         v->id = ++shader->variant_count;
 175         v->shader = shader;
 176         v->binning_pass = binning_pass;
 177         v->key = *key;
 178         v->type = shader->type;
 179
 180         ret = ir3_compile_shader_nir(shader->compiler, v);
 181         if (ret) {
 182                 debug_error("compile failed!");
 183                 goto fail;
 184         }
 185
 186         assemble_variant(v);
 187         if (!v->bo) {
 188                 debug_error("assemble failed!");
 189                 goto fail;
 190         }
 191
 192         return v;
 193
 194 fail:
 195         delete_variant(v);
 196         return NULL;
 197 }
 198
 199 static inline struct ir3_shader_variant *
 200 shader_variant(struct ir3_shader *shader, struct ir3_shader_key *key,
 201                 bool *created)
 202 {
 203         struct ir3_shader_variant *v;
 204
 205         *created = false;
 206
 207         for (v = shader->variants; v; v = v->next)
 208                 if (ir3_shader_key_equal(key, &v->key))
 209                         return v;
 210
 211         /* compile new variant if it doesn't exist already: */
 212         v = create_variant(shader, key, false);
 213         if (v) {
 214                 v->next = shader->variants;
 215                 shader->variants = v;
 216                 *created = true;
 217         }
 218
 219         return v;
 220 }
 221
 222 struct ir3_shader_variant *
 223 ir3_shader_get_variant(struct ir3_shader *shader, struct ir3_shader_key *key,
 224                 bool binning_pass, bool *created)
 225 {
 226         struct ir3_shader_variant *v =
 227                         shader_variant(shader, key, created);
 228
 229         if (binning_pass) {
 230                 if (!v->binning)
 231                         v->binning = create_variant(shader, key, true);
 232                 return v->binning;
 233         }
 234
 235         return v;
 236 }
 237
 238 void
 239 ir3_shader_destroy(struct ir3_shader *shader)
 240 {
 241         struct ir3_shader_variant *v, *t;
 242         for (v = shader->variants; v; ) {
 243                 t = v;
 244                 v = v->next;
 245                 delete_variant(t);
 246         }
 247         ralloc_free(shader->nir);
 248         free(shader);
 249 }
 250
 251 struct ir3_shader *
 252 ir3_shader_from_nir(struct ir3_compiler *compiler, nir_shader *nir)
 253 {
 254         struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
 255
 256         shader->compiler = compiler;
 257         shader->id = ++shader->compiler->shader_count;
 258         shader->type = nir->info.stage;
 259
 260         NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size,
 261                            (nir_lower_io_options)0);
 262
 263         /* do first pass optimization, ignoring the key: */
 264         shader->nir = ir3_optimize_nir(shader, nir, NULL);
 265         if (ir3_shader_debug & IR3_DBG_DISASM) {
 266                 printf("dump nir%d: type=%d", shader->id, shader->type);
 267                 nir_print_shader(shader->nir, stdout);
 268         }
 269
 270         return shader;
 271 }
 272
 273 static void dump_reg(FILE *out, const char *name, uint32_t r)
 274 {
 275         if (r != regid(63,0))
 276                 fprintf(out, "; %s: r%d.%c\n", name, r >> 2, "xyzw"[r & 0x3]);
 277 }
 278
 279 static void dump_output(FILE *out, struct ir3_shader_variant *so,
 280                 unsigned slot, const char *name)
 281 {
 282         uint32_t regid;
 283         regid = ir3_find_output_regid(so, slot);
 284         dump_reg(out, name, regid);
 285 }
 286
 287 void
 288 ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
 289 {
 290         struct ir3 *ir = so->ir;
 291         struct ir3_register *reg;
 292         const char *type = ir3_shader_stage(so->shader);
 293         uint8_t regid;
 294         unsigned i;
 295
 296         for (i = 0; i < ir->ninputs; i++) {
 297                 if (!ir->inputs[i]) {
 298                         fprintf(out, "; in%d unused\n", i);
 299                         continue;
 300                 }
 301                 reg = ir->inputs[i]->regs[0];
 302                 regid = reg->num;
 303                 fprintf(out, "@in(%sr%d.%c)\tin%d\n",
 304                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 305                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 306         }
 307
 308         for (i = 0; i < ir->noutputs; i++) {
 309                 if (!ir->outputs[i]) {
 310                         fprintf(out, "; out%d unused\n", i);
 311                         continue;
 312                 }
 313                 /* kill shows up as a virtual output.. skip it! */
 314                 if (is_kill(ir->outputs[i]))
 315                         continue;
 316                 reg = ir->outputs[i]->regs[0];
 317                 regid = reg->num;
 318                 fprintf(out, "@out(%sr%d.%c)\tout%d\n",
 319                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 320                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 321         }
 322
 323         for (i = 0; i < so->immediates_count; i++) {
 324                 fprintf(out, "@const(c%d.x)\t", so->constbase.immediate + i);
 325                 fprintf(out, "0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
 326                                 so->immediates[i].val[0],
 327                                 so->immediates[i].val[1],
 328                                 so->immediates[i].val[2],
 329                                 so->immediates[i].val[3]);
 330         }
 331
 332         disasm_a3xx(bin, so->info.sizedwords, 0, out, ir->compiler->gpu_id);
 333
 334         switch (so->type) {
 335         case MESA_SHADER_VERTEX:
 336                 fprintf(out, "; %s: outputs:", type);
 337                 for (i = 0; i < so->outputs_count; i++) {
 338                         uint8_t regid = so->outputs[i].regid;
 339                         fprintf(out, " r%d.%c (%s)",
 340                                         (regid >> 2), "xyzw"[regid & 0x3],
 341                                         gl_varying_slot_name(so->outputs[i].slot));
 342                 }
 343                 fprintf(out, "\n");
 344                 fprintf(out, "; %s: inputs:", type);
 345                 for (i = 0; i < so->inputs_count; i++) {
 346                         uint8_t regid = so->inputs[i].regid;
 347                         fprintf(out, " r%d.%c (cm=%x,il=%u,b=%u)",
 348                                         (regid >> 2), "xyzw"[regid & 0x3],
 349                                         so->inputs[i].compmask,
 350                                         so->inputs[i].inloc,
 351                                         so->inputs[i].bary);
 352                 }
 353                 fprintf(out, "\n");
 354                 break;
 355         case MESA_SHADER_FRAGMENT:
 356                 fprintf(out, "; %s: outputs:", type);
 357                 for (i = 0; i < so->outputs_count; i++) {
 358                         uint8_t regid = so->outputs[i].regid;
 359                         fprintf(out, " r%d.%c (%s)",
 360                                         (regid >> 2), "xyzw"[regid & 0x3],
 361                                         gl_frag_result_name(so->outputs[i].slot));
 362                 }
 363                 fprintf(out, "\n");
 364                 fprintf(out, "; %s: inputs:", type);
 365                 for (i = 0; i < so->inputs_count; i++) {
 366                         uint8_t regid = so->inputs[i].regid;
 367                         fprintf(out, " r%d.%c (%s,cm=%x,il=%u,b=%u)",
 368                                         (regid >> 2), "xyzw"[regid & 0x3],
 369                                         gl_varying_slot_name(so->inputs[i].slot),
 370                                         so->inputs[i].compmask,
 371                                         so->inputs[i].inloc,
 372                                         so->inputs[i].bary);
 373                 }
 374                 fprintf(out, "\n");
 375                 break;
 376         default:
 377                 /* TODO */
 378                 break;
 379         }
 380
 381         /* print generic shader info: */
 382         fprintf(out, "; %s prog %d/%d: %u instructions, %d half, %d full\n",
 383                         type, so->shader->id, so->id,
 384                         so->info.instrs_count,
 385                         so->info.max_half_reg + 1,
 386                         so->info.max_reg + 1);
 387
 388         fprintf(out, "; %d const, %u constlen\n",
 389                         so->info.max_const + 1,
 390                         so->constlen);
 391
 392         fprintf(out, "; %u (ss), %u (sy)\n", so->info.ss, so->info.sy);
 393
 394         /* print shader type specific info: */
 395         switch (so->type) {
 396         case MESA_SHADER_VERTEX:
 397                 dump_output(out, so, VARYING_SLOT_POS, "pos");
 398                 dump_output(out, so, VARYING_SLOT_PSIZ, "psize");
 399                 break;
 400         case MESA_SHADER_FRAGMENT:
 401                 dump_reg(out, "pos (bary)",
 402                         ir3_find_sysval_regid(so, SYSTEM_VALUE_VARYING_COORD));
 403                 dump_output(out, so, FRAG_RESULT_DEPTH, "posz");
 404                 if (so->color0_mrt) {
 405                         dump_output(out, so, FRAG_RESULT_COLOR, "color");
 406                 } else {
 407                         dump_output(out, so, FRAG_RESULT_DATA0, "data0");
 408                         dump_output(out, so, FRAG_RESULT_DATA1, "data1");
 409                         dump_output(out, so, FRAG_RESULT_DATA2, "data2");
 410                         dump_output(out, so, FRAG_RESULT_DATA3, "data3");
 411                         dump_output(out, so, FRAG_RESULT_DATA4, "data4");
 412                         dump_output(out, so, FRAG_RESULT_DATA5, "data5");
 413                         dump_output(out, so, FRAG_RESULT_DATA6, "data6");
 414                         dump_output(out, so, FRAG_RESULT_DATA7, "data7");
 415                 }
 416                 /* these two are hard-coded since we don't know how to
 417                  * program them to anything but all 0's...
 418                  */
 419                 if (so->frag_coord)
 420                         fprintf(out, "; fragcoord: r0.x\n");
 421                 if (so->frag_face)
 422                         fprintf(out, "; fragface: hr0.x\n");
 423                 break;
 424         default:
 425                 /* TODO */
 426                 break;
 427         }
 428
 429         fprintf(out, "\n");
 430 }
 431
 432 uint64_t
 433 ir3_shader_outputs(const struct ir3_shader *so)
 434 {
 435         return so->nir->info.outputs_written;
 436 }