src/freedreno/ir3/ir3_shader.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "util/u_atomic.h"
  28 #include "util/u_string.h"
  29 #include "util/u_math.h"
  30 #include "util/u_memory.h"
  31 #include "util/format/u_format.h"
  32
  33 #include "drm/freedreno_drmif.h"
  34
  35 #include "ir3_shader.h"
  36 #include "ir3_compiler.h"
  37 #include "ir3_nir.h"
  38
  39 int
  40 ir3_glsl_type_size(const struct glsl_type *type, bool bindless)
  41 {
  42         return glsl_count_attribute_slots(type, false);
  43 }
  44
  45 /* for vertex shader, the inputs are loaded into registers before the shader
  46  * is executed, so max_regs from the shader instructions might not properly
  47  * reflect the # of registers actually used, especially in case passthrough
  48  * varyings.
  49  *
  50  * Likewise, for fragment shader, we can have some regs which are passed
  51  * input values but never touched by the resulting shader (ie. as result
  52  * of dead code elimination or simply because we don't know how to turn
  53  * the reg off.
  54  */
  55 static void
  56 fixup_regfootprint(struct ir3_shader_variant *v)
  57 {
  58         unsigned i;
  59
  60         for (i = 0; i < v->inputs_count; i++) {
  61                 /* skip frag inputs fetch via bary.f since their reg's are
  62                  * not written by gpu before shader starts (and in fact the
  63                  * regid's might not even be valid)
  64                  */
  65                 if (v->inputs[i].bary)
  66                         continue;
  67
  68                 /* ignore high regs that are global to all threads in a warp
  69                  * (they exist by default) (a5xx+)
  70                  */
  71                 if (v->inputs[i].regid >= regid(48,0))
  72                         continue;
  73
  74                 if (v->inputs[i].compmask) {
  75                         unsigned n = util_last_bit(v->inputs[i].compmask) - 1;
  76                         int32_t regid = v->inputs[i].regid + n;
  77                         if (v->inputs[i].half) {
  78                                 if (!v->mergedregs) {
  79                                         v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
  80                                 } else {
  81                                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
  82                                 }
  83                         } else {
  84                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
  85                         }
  86                 }
  87         }
  88
  89         for (i = 0; i < v->outputs_count; i++) {
  90                 /* for ex, VS shaders with tess don't have normal varying outs: */
  91                 if (!VALIDREG(v->outputs[i].regid))
  92                         continue;
  93                 int32_t regid = v->outputs[i].regid + 3;
  94                 if (v->outputs[i].half) {
  95                         if (!v->mergedregs) {
  96                                 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
  97                         } else {
  98                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
  99                         }
 100                 } else {
 101                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
 102                 }
 103         }
 104
 105         for (i = 0; i < v->num_sampler_prefetch; i++) {
 106                 unsigned n = util_last_bit(v->sampler_prefetch[i].wrmask) - 1;
 107                 int32_t regid = v->sampler_prefetch[i].dst + n;
 108                 if (v->sampler_prefetch[i].half_precision) {
 109                         if (!v->mergedregs) {
 110                                 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
 111                         } else {
 112                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
 113                         }
 114                 } else {
 115                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
 116                 }
 117         }
 118 }
 119
 120 /* wrapper for ir3_assemble() which does some info fixup based on
 121  * shader state.  Non-static since used by ir3_cmdline too.
 122  */
 123 void * ir3_shader_assemble(struct ir3_shader_variant *v)
 124 {
 125         unsigned gpu_id = v->shader->compiler->gpu_id;
 126         void *bin;
 127
 128         bin = ir3_assemble(v);
 129         if (!bin)
 130                 return NULL;
 131
 132         if (gpu_id >= 400) {
 133                 v->instrlen = v->info.sizedwords / (2 * 16);
 134         } else {
 135                 v->instrlen = v->info.sizedwords / (2 * 4);
 136         }
 137
 138         /* NOTE: if relative addressing is used, we set constlen in
 139          * the compiler (to worst-case value) since we don't know in
 140          * the assembler what the max addr reg value can be:
 141          */
 142         v->constlen = MAX2(v->constlen, v->info.max_const + 1);
 143
 144         /* On a4xx and newer, constlen must be a multiple of 16 dwords even though
 145          * uploads are in units of 4 dwords. Round it up here to make calculations
 146          * regarding the shared constlen simpler.
 147          */
 148         if (gpu_id >= 400)
 149                 v->constlen = align(v->constlen, 4);
 150
 151         fixup_regfootprint(v);
 152
 153         return bin;
 154 }
 155
 156 static void
 157 assemble_variant(struct ir3_shader_variant *v)
 158 {
 159         v->bin = ir3_shader_assemble(v);
 160
 161         if (shader_debug_enabled(v->shader->type)) {
 162                 fprintf(stdout, "Native code for unnamed %s shader %s:\n",
 163                         ir3_shader_stage(v), v->shader->nir->info.name);
 164                 if (v->shader->type == MESA_SHADER_FRAGMENT)
 165                         fprintf(stdout, "SIMD0\n");
 166                 ir3_shader_disasm(v, v->bin, stdout);
 167         }
 168
 169         /* no need to keep the ir around beyond this point: */
 170         ir3_destroy(v->ir);
 171         v->ir = NULL;
 172 }
 173
 174 /*
 175  * For creating normal shader variants, 'nonbinning' is NULL.  For
 176  * creating binning pass shader, it is link to corresponding normal
 177  * (non-binning) variant.
 178  */
 179 static struct ir3_shader_variant *
 180 create_variant(struct ir3_shader *shader, const struct ir3_shader_key *key,
 181                 struct ir3_shader_variant *nonbinning)
 182 {
 183         struct ir3_shader_variant *v = rzalloc_size(shader, sizeof(*v));
 184         int ret;
 185
 186         if (!v)
 187                 return NULL;
 188
 189         v->id = ++shader->variant_count;
 190         v->shader = shader;
 191         v->binning_pass = !!nonbinning;
 192         v->nonbinning = nonbinning;
 193         v->key = *key;
 194         v->type = shader->type;
 195         v->mergedregs = shader->compiler->gpu_id >= 600;
 196
 197         if (!v->binning_pass)
 198                 v->const_state = rzalloc_size(v, sizeof(*v->const_state));
 199
 200         ret = ir3_compile_shader_nir(shader->compiler, v);
 201         if (ret) {
 202                 debug_error("compile failed!");
 203                 goto fail;
 204         }
 205
 206         assemble_variant(v);
 207         if (!v->bin) {
 208                 debug_error("assemble failed!");
 209                 goto fail;
 210         }
 211
 212         return v;
 213
 214 fail:
 215         ralloc_free(v);
 216         return NULL;
 217 }
 218
 219 static inline struct ir3_shader_variant *
 220 shader_variant(struct ir3_shader *shader, const struct ir3_shader_key *key,
 221                 bool *created)
 222 {
 223         struct ir3_shader_variant *v;
 224
 225         *created = false;
 226
 227         for (v = shader->variants; v; v = v->next)
 228                 if (ir3_shader_key_equal(key, &v->key))
 229                         return v;
 230
 231         /* compile new variant if it doesn't exist already: */
 232         v = create_variant(shader, key, NULL);
 233         if (v) {
 234                 v->next = shader->variants;
 235                 shader->variants = v;
 236                 *created = true;
 237         }
 238
 239         return v;
 240 }
 241
 242 struct ir3_shader_variant *
 243 ir3_shader_get_variant(struct ir3_shader *shader, const struct ir3_shader_key *key,
 244                 bool binning_pass, bool *created)
 245 {
 246         mtx_lock(&shader->variants_lock);
 247         struct ir3_shader_variant *v =
 248                         shader_variant(shader, key, created);
 249
 250         if (v && binning_pass) {
 251                 if (!v->binning) {
 252                         v->binning = create_variant(shader, key, v);
 253                         *created = true;
 254                 }
 255                 mtx_unlock(&shader->variants_lock);
 256                 return v->binning;
 257         }
 258         mtx_unlock(&shader->variants_lock);
 259
 260         return v;
 261 }
 262
 263 void
 264 ir3_shader_destroy(struct ir3_shader *shader)
 265 {
 266         ralloc_free(shader->nir);
 267         mtx_destroy(&shader->variants_lock);
 268         ralloc_free(shader);
 269 }
 270
 271 /**
 272  * Creates a bitmask of the used bits of the shader key by this particular
 273  * shader.  Used by the gallium driver to skip state-dependent recompiles when
 274  * possible.
 275  */
 276 static void
 277 ir3_setup_used_key(struct ir3_shader *shader)
 278 {
 279         nir_shader *nir = shader->nir;
 280         struct shader_info *info = &nir->info;
 281         struct ir3_shader_key *key = &shader->key_mask;
 282
 283         /* This key flag is just used to make for a cheaper ir3_shader_key_equal
 284          * check in the common case.
 285          */
 286         key->has_per_samp = true;
 287
 288         key->safe_constlen = true;
 289
 290         if (info->stage == MESA_SHADER_FRAGMENT) {
 291                 key->fsaturate_s = ~0;
 292                 key->fsaturate_t = ~0;
 293                 key->fsaturate_r = ~0;
 294                 key->fastc_srgb = ~0;
 295                 key->fsamples = ~0;
 296
 297                 if (info->inputs_read & VARYING_BITS_COLOR) {
 298                         key->rasterflat = true;
 299                         key->color_two_side = true;
 300                 }
 301
 302                 if ((info->outputs_written & ~(FRAG_RESULT_DEPTH |
 303                                                                 FRAG_RESULT_STENCIL |
 304                                                                 FRAG_RESULT_SAMPLE_MASK)) != 0) {
 305                         key->fclamp_color = true;
 306                 }
 307
 308                 /* Only used for deciding on behavior of
 309                  * nir_intrinsic_load_barycentric_sample
 310                  */
 311                 key->msaa = info->fs.uses_sample_qualifier;
 312         } else {
 313                 key->tessellation = ~0;
 314                 key->has_gs = true;
 315
 316                 if (info->outputs_written & VARYING_BITS_COLOR)
 317                         key->vclamp_color = true;
 318
 319                 if (info->stage == MESA_SHADER_VERTEX) {
 320                         key->vsaturate_s = ~0;
 321                         key->vsaturate_t = ~0;
 322                         key->vsaturate_r = ~0;
 323                         key->vastc_srgb = ~0;
 324                         key->vsamples = ~0;
 325                 }
 326         }
 327 }
 328
 329
 330 /* Given an array of constlen's, decrease some of them so that the sum stays
 331  * within "combined_limit" while trying to fairly share the reduction. Returns
 332  * a bitfield of which stages should be trimmed.
 333  */
 334 static uint32_t
 335 trim_constlens(unsigned *constlens,
 336                            unsigned first_stage, unsigned last_stage,
 337                            unsigned combined_limit, unsigned safe_limit)
 338 {
 339    unsigned cur_total = 0;
 340    for (unsigned i = first_stage; i <= last_stage; i++) {
 341       cur_total += constlens[i];
 342    }
 343
 344    unsigned max_stage;
 345    unsigned max_const = 0;
 346    uint32_t trimmed = 0;
 347
 348    while (cur_total > combined_limit) {
 349            for (unsigned i = first_stage; i <= last_stage; i++) {
 350                    if (constlens[i] >= max_const) {
 351                            max_stage = i;
 352                            max_const = constlens[i];
 353                    }
 354            }
 355
 356            assert(max_const > safe_limit);
 357            trimmed |= 1 << max_stage;
 358            cur_total = cur_total - max_const + safe_limit;
 359            constlens[max_stage] = safe_limit;
 360    }
 361
 362    return trimmed;
 363 }
 364
 365 /* Figures out which stages in the pipeline to use the "safe" constlen for, in
 366  * order to satisfy all shared constlen limits.
 367  */
 368 uint32_t
 369 ir3_trim_constlen(struct ir3_shader_variant **variants,
 370                                   const struct ir3_compiler *compiler)
 371 {
 372         unsigned constlens[MESA_SHADER_STAGES] = {};
 373
 374         for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
 375                 if (variants[i])
 376                         constlens[i] = variants[i]->constlen;
 377         }
 378
 379         uint32_t trimmed = 0;
 380         STATIC_ASSERT(MESA_SHADER_STAGES <= 8 * sizeof(trimmed));
 381
 382         /* There are two shared limits to take into account, the geometry limit on
 383          * a6xx and the total limit. The frag limit on a6xx only matters for a
 384          * single stage, so it's always satisfied with the first variant.
 385          */
 386         if (compiler->gpu_id >= 600) {
 387                 trimmed |=
 388                         trim_constlens(constlens, MESA_SHADER_VERTEX, MESA_SHADER_GEOMETRY,
 389                                                    compiler->max_const_geom, compiler->max_const_safe);
 390         }
 391         trimmed |=
 392                 trim_constlens(constlens, MESA_SHADER_VERTEX, MESA_SHADER_FRAGMENT,
 393                                            compiler->max_const_pipeline, compiler->max_const_safe);
 394
 395         return trimmed;
 396 }
 397
 398 struct ir3_shader *
 399 ir3_shader_from_nir(struct ir3_compiler *compiler, nir_shader *nir,
 400                 unsigned reserved_user_consts, struct ir3_stream_output_info *stream_output)
 401 {
 402         struct ir3_shader *shader = rzalloc_size(NULL, sizeof(*shader));
 403
 404         mtx_init(&shader->variants_lock, mtx_plain);
 405         shader->compiler = compiler;
 406         shader->id = p_atomic_inc_return(&shader->compiler->shader_count);
 407         shader->type = nir->info.stage;
 408         if (stream_output)
 409                 memcpy(&shader->stream_output, stream_output, sizeof(shader->stream_output));
 410         shader->num_reserved_user_consts = reserved_user_consts;
 411
 412         ir3_nir_post_finalize(compiler, nir);
 413
 414         shader->nir = nir;
 415
 416         if (ir3_shader_debug & IR3_DBG_DISASM) {
 417                 printf("dump nir%d: type=%d", shader->id, shader->type);
 418                 nir_print_shader(shader->nir, stdout);
 419         }
 420
 421         ir3_setup_used_key(shader);
 422
 423         return shader;
 424 }
 425
 426 static void dump_reg(FILE *out, const char *name, uint32_t r)
 427 {
 428         if (r != regid(63,0)) {
 429                 const char *reg_type = (r & HALF_REG_ID) ? "hr" : "r";
 430                 fprintf(out, "; %s: %s%d.%c\n", name, reg_type,
 431                                 (r & ~HALF_REG_ID) >> 2, "xyzw"[r & 0x3]);
 432         }
 433 }
 434
 435 static void dump_output(FILE *out, struct ir3_shader_variant *so,
 436                 unsigned slot, const char *name)
 437 {
 438         uint32_t regid;
 439         regid = ir3_find_output_regid(so, slot);
 440         dump_reg(out, name, regid);
 441 }
 442
 443 static const char *
 444 input_name(struct ir3_shader_variant *so, int i)
 445 {
 446         if (so->inputs[i].sysval) {
 447                 return gl_system_value_name(so->inputs[i].slot);
 448         } else if (so->type == MESA_SHADER_VERTEX) {
 449                 return gl_vert_attrib_name(so->inputs[i].slot);
 450         } else {
 451                 return gl_varying_slot_name(so->inputs[i].slot);
 452         }
 453 }
 454
 455 static const char *
 456 output_name(struct ir3_shader_variant *so, int i)
 457 {
 458         if (so->type == MESA_SHADER_FRAGMENT) {
 459                 return gl_frag_result_name(so->outputs[i].slot);
 460         } else {
 461                 switch (so->outputs[i].slot) {
 462                 case VARYING_SLOT_GS_HEADER_IR3:
 463                         return "GS_HEADER";
 464                 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
 465                         return "GS_VERTEX_FLAGS";
 466                 case VARYING_SLOT_TCS_HEADER_IR3:
 467                         return "TCS_HEADER";
 468                 default:
 469                         return gl_varying_slot_name(so->outputs[i].slot);
 470                 }
 471         }
 472 }
 473
 474 void
 475 ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
 476 {
 477         struct ir3 *ir = so->ir;
 478         struct ir3_register *reg;
 479         const char *type = ir3_shader_stage(so);
 480         uint8_t regid;
 481         unsigned i;
 482
 483         foreach_input_n (instr, i, ir) {
 484                 reg = instr->regs[0];
 485                 regid = reg->num;
 486                 fprintf(out, "@in(%sr%d.%c)\tin%d",
 487                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 488                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 489
 490                 if (reg->wrmask > 0x1)
 491                         fprintf(out, " (wrmask=0x%x)", reg->wrmask);
 492                 fprintf(out, "\n");
 493         }
 494
 495         /* print pre-dispatch texture fetches: */
 496         for (i = 0; i < so->num_sampler_prefetch; i++) {
 497                 const struct ir3_sampler_prefetch *fetch = &so->sampler_prefetch[i];
 498                 fprintf(out, "@tex(%sr%d.%c)\tsrc=%u, samp=%u, tex=%u, wrmask=0x%x, cmd=%u\n",
 499                                 fetch->half_precision ? "h" : "",
 500                                 fetch->dst >> 2, "xyzw"[fetch->dst & 0x3],
 501                                 fetch->src, fetch->samp_id, fetch->tex_id,
 502                                 fetch->wrmask, fetch->cmd);
 503         }
 504
 505         foreach_output_n (instr, i, ir) {
 506                 reg = instr->regs[0];
 507                 regid = reg->num;
 508                 fprintf(out, "@out(%sr%d.%c)\tout%d",
 509                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 510                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 511                 if (reg->wrmask > 0x1)
 512                         fprintf(out, " (wrmask=0x%x)", reg->wrmask);
 513                 fprintf(out, "\n");
 514         }
 515
 516         const struct ir3_const_state *const_state = ir3_const_state(so);
 517         for (i = 0; i < const_state->immediates_count; i++) {
 518                 fprintf(out, "@const(c%d.x)\t", const_state->offsets.immediate + i);
 519                 fprintf(out, "0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
 520                                 const_state->immediates[i].val[0],
 521                                 const_state->immediates[i].val[1],
 522                                 const_state->immediates[i].val[2],
 523                                 const_state->immediates[i].val[3]);
 524         }
 525
 526         disasm_a3xx(bin, so->info.sizedwords, 0, out, ir->compiler->gpu_id);
 527
 528         fprintf(out, "; %s: outputs:", type);
 529         for (i = 0; i < so->outputs_count; i++) {
 530                 uint8_t regid = so->outputs[i].regid;
 531                 const char *reg_type = so->outputs[i].half ? "hr" : "r";
 532                 fprintf(out, " %s%d.%c (%s)",
 533                                 reg_type, (regid >> 2), "xyzw"[regid & 0x3],
 534                                 output_name(so, i));
 535         }
 536         fprintf(out, "\n");
 537
 538         fprintf(out, "; %s: inputs:", type);
 539         for (i = 0; i < so->inputs_count; i++) {
 540                 uint8_t regid = so->inputs[i].regid;
 541                 fprintf(out, " r%d.%c (%s slot=%d cm=%x,il=%u,b=%u)",
 542                                 (regid >> 2), "xyzw"[regid & 0x3],
 543                                 input_name(so, i),
 544                                 so->inputs[i].slot,
 545                                 so->inputs[i].compmask,
 546                                 so->inputs[i].inloc,
 547                                 so->inputs[i].bary);
 548         }
 549         fprintf(out, "\n");
 550
 551         /* print generic shader info: */
 552         fprintf(out, "; %s prog %d/%d: %u instr, %u nops, %u non-nops, %u mov, %u cov, %u dwords\n",
 553                         type, so->shader->id, so->id,
 554                         so->info.instrs_count,
 555                         so->info.nops_count,
 556                         so->info.instrs_count - so->info.nops_count,
 557                         so->info.mov_count, so->info.cov_count,
 558                         so->info.sizedwords);
 559
 560         fprintf(out, "; %s prog %d/%d: %u last-baryf, %d half, %d full, %u constlen\n",
 561                         type, so->shader->id, so->id,
 562                         so->info.last_baryf,
 563                         so->info.max_half_reg + 1,
 564                         so->info.max_reg + 1,
 565                         so->constlen);
 566
 567         fprintf(out, "; %s prog %d/%d: %u sstall, %u (ss), %u (sy), %d max_sun, %d loops\n",
 568                         type, so->shader->id, so->id,
 569                         so->info.sstall,
 570                         so->info.ss,
 571                         so->info.sy,
 572                         so->max_sun,
 573                         so->loops);
 574
 575         /* print shader type specific info: */
 576         switch (so->type) {
 577         case MESA_SHADER_VERTEX:
 578                 dump_output(out, so, VARYING_SLOT_POS, "pos");
 579                 dump_output(out, so, VARYING_SLOT_PSIZ, "psize");
 580                 break;
 581         case MESA_SHADER_FRAGMENT:
 582                 dump_reg(out, "pos (ij_pixel)",
 583                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL));
 584                 dump_reg(out, "pos (ij_centroid)",
 585                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID));
 586                 dump_reg(out, "pos (ij_size)",
 587                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE));
 588                 dump_output(out, so, FRAG_RESULT_DEPTH, "posz");
 589                 if (so->color0_mrt) {
 590                         dump_output(out, so, FRAG_RESULT_COLOR, "color");
 591                 } else {
 592                         dump_output(out, so, FRAG_RESULT_DATA0, "data0");
 593                         dump_output(out, so, FRAG_RESULT_DATA1, "data1");
 594                         dump_output(out, so, FRAG_RESULT_DATA2, "data2");
 595                         dump_output(out, so, FRAG_RESULT_DATA3, "data3");
 596                         dump_output(out, so, FRAG_RESULT_DATA4, "data4");
 597                         dump_output(out, so, FRAG_RESULT_DATA5, "data5");
 598                         dump_output(out, so, FRAG_RESULT_DATA6, "data6");
 599                         dump_output(out, so, FRAG_RESULT_DATA7, "data7");
 600                 }
 601                 dump_reg(out, "fragcoord",
 602                         ir3_find_sysval_regid(so, SYSTEM_VALUE_FRAG_COORD));
 603                 dump_reg(out, "fragface",
 604                         ir3_find_sysval_regid(so, SYSTEM_VALUE_FRONT_FACE));
 605                 break;
 606         default:
 607                 /* TODO */
 608                 break;
 609         }
 610
 611         fprintf(out, "\n");
 612 }
 613
 614 uint64_t
 615 ir3_shader_outputs(const struct ir3_shader *so)
 616 {
 617         return so->nir->info.outputs_written;
 618 }