2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "util/u_string.h"
28 #include "util/u_memory.h"
29 #include "util/u_format.h"
31 #include "drm/freedreno_drmif.h"
33 #include "ir3_shader.h"
34 #include "ir3_compiler.h"
38 ir3_glsl_type_size(const struct glsl_type
*type
)
40 return glsl_count_attribute_slots(type
, false);
44 delete_variant(struct ir3_shader_variant
*v
)
55 /* for vertex shader, the inputs are loaded into registers before the shader
56 * is executed, so max_regs from the shader instructions might not properly
57 * reflect the # of registers actually used, especially in case passthrough
60 * Likewise, for fragment shader, we can have some regs which are passed
61 * input values but never touched by the resulting shader (ie. as result
62 * of dead code elimination or simply because we don't know how to turn
66 fixup_regfootprint(struct ir3_shader_variant
*v
)
70 for (i
= 0; i
< v
->inputs_count
; i
++) {
71 /* skip frag inputs fetch via bary.f since their reg's are
72 * not written by gpu before shader starts (and in fact the
73 * regid's might not even be valid)
75 if (v
->inputs
[i
].bary
)
78 /* ignore high regs that are global to all threads in a warp
79 * (they exist by default) (a5xx+)
81 if (v
->inputs
[i
].regid
>= regid(48,0))
84 if (v
->inputs
[i
].compmask
) {
85 unsigned n
= util_last_bit(v
->inputs
[i
].compmask
) - 1;
86 int32_t regid
= (v
->inputs
[i
].regid
+ n
) >> 2;
87 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
);
91 for (i
= 0; i
< v
->outputs_count
; i
++) {
92 int32_t regid
= (v
->outputs
[i
].regid
+ 3) >> 2;
93 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
);
97 /* wrapper for ir3_assemble() which does some info fixup based on
98 * shader state. Non-static since used by ir3_cmdline too.
100 void * ir3_shader_assemble(struct ir3_shader_variant
*v
, uint32_t gpu_id
)
104 bin
= ir3_assemble(v
->ir
, &v
->info
, gpu_id
);
109 v
->instrlen
= v
->info
.sizedwords
/ (2 * 16);
111 v
->instrlen
= v
->info
.sizedwords
/ (2 * 4);
114 /* NOTE: if relative addressing is used, we set constlen in
115 * the compiler (to worst-case value) since we don't know in
116 * the assembler what the max addr reg value can be:
118 v
->constlen
= MIN2(255, MAX2(v
->constlen
, v
->info
.max_const
+ 1));
120 fixup_regfootprint(v
);
126 assemble_variant(struct ir3_shader_variant
*v
)
128 struct ir3_compiler
*compiler
= v
->shader
->compiler
;
129 struct shader_info
*info
= &v
->shader
->nir
->info
;
130 uint32_t gpu_id
= compiler
->gpu_id
;
133 bin
= ir3_shader_assemble(v
, gpu_id
);
134 sz
= v
->info
.sizedwords
* 4;
136 v
->bo
= fd_bo_new(compiler
->dev
, sz
,
137 DRM_FREEDRENO_GEM_CACHE_WCOMBINE
|
138 DRM_FREEDRENO_GEM_TYPE_KMEM
,
139 "%s:%s", ir3_shader_stage(v
->shader
), info
->name
);
141 memcpy(fd_bo_map(v
->bo
), bin
, sz
);
143 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
144 struct ir3_shader_key key
= v
->key
;
145 printf("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}", v
->type
,
146 v
->binning_pass
, key
.color_two_side
, key
.half_precision
);
147 ir3_shader_disasm(v
, bin
, stdout
);
150 if (shader_debug_enabled(v
->shader
->type
)) {
151 fprintf(stderr
, "Native code for unnamed %s shader %s:\n",
152 _mesa_shader_stage_to_string(v
->shader
->type
),
153 v
->shader
->nir
->info
.name
);
154 if (v
->shader
->type
== MESA_SHADER_FRAGMENT
)
155 fprintf(stderr
, "SIMD0\n");
156 ir3_shader_disasm(v
, bin
, stderr
);
161 /* no need to keep the ir around beyond this point: */
166 static struct ir3_shader_variant
*
167 create_variant(struct ir3_shader
*shader
, struct ir3_shader_key
*key
,
170 struct ir3_shader_variant
*v
= CALLOC_STRUCT(ir3_shader_variant
);
176 v
->id
= ++shader
->variant_count
;
178 v
->binning_pass
= binning_pass
;
180 v
->type
= shader
->type
;
182 ret
= ir3_compile_shader_nir(shader
->compiler
, v
);
184 debug_error("compile failed!");
190 debug_error("assemble failed!");
201 static inline struct ir3_shader_variant
*
202 shader_variant(struct ir3_shader
*shader
, struct ir3_shader_key
*key
,
205 struct ir3_shader_variant
*v
;
209 for (v
= shader
->variants
; v
; v
= v
->next
)
210 if (ir3_shader_key_equal(key
, &v
->key
))
213 /* compile new variant if it doesn't exist already: */
214 v
= create_variant(shader
, key
, false);
216 v
->next
= shader
->variants
;
217 shader
->variants
= v
;
224 struct ir3_shader_variant
*
225 ir3_shader_get_variant(struct ir3_shader
*shader
, struct ir3_shader_key
*key
,
226 bool binning_pass
, bool *created
)
228 struct ir3_shader_variant
*v
=
229 shader_variant(shader
, key
, created
);
231 if (v
&& binning_pass
) {
233 v
->binning
= create_variant(shader
, key
, true);
241 ir3_shader_destroy(struct ir3_shader
*shader
)
243 struct ir3_shader_variant
*v
, *t
;
244 for (v
= shader
->variants
; v
; ) {
249 ralloc_free(shader
->nir
);
254 ir3_shader_from_nir(struct ir3_compiler
*compiler
, nir_shader
*nir
)
256 struct ir3_shader
*shader
= CALLOC_STRUCT(ir3_shader
);
258 shader
->compiler
= compiler
;
259 shader
->id
= ++shader
->compiler
->shader_count
;
260 shader
->type
= nir
->info
.stage
;
262 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, ir3_glsl_type_size
,
263 (nir_lower_io_options
)0);
265 /* do first pass optimization, ignoring the key: */
266 shader
->nir
= ir3_optimize_nir(shader
, nir
, NULL
);
267 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
268 printf("dump nir%d: type=%d", shader
->id
, shader
->type
);
269 nir_print_shader(shader
->nir
, stdout
);
275 static void dump_reg(FILE *out
, const char *name
, uint32_t r
)
277 if (r
!= regid(63,0))
278 fprintf(out
, "; %s: r%d.%c\n", name
, r
>> 2, "xyzw"[r
& 0x3]);
281 static void dump_output(FILE *out
, struct ir3_shader_variant
*so
,
282 unsigned slot
, const char *name
)
285 regid
= ir3_find_output_regid(so
, slot
);
286 dump_reg(out
, name
, regid
);
290 ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
, FILE *out
)
292 struct ir3
*ir
= so
->ir
;
293 struct ir3_register
*reg
;
294 const char *type
= ir3_shader_stage(so
->shader
);
298 for (i
= 0; i
< ir
->ninputs
; i
++) {
299 if (!ir
->inputs
[i
]) {
300 fprintf(out
, "; in%d unused\n", i
);
303 reg
= ir
->inputs
[i
]->regs
[0];
305 fprintf(out
, "@in(%sr%d.%c)\tin%d\n",
306 (reg
->flags
& IR3_REG_HALF
) ? "h" : "",
307 (regid
>> 2), "xyzw"[regid
& 0x3], i
);
310 for (i
= 0; i
< ir
->noutputs
; i
++) {
311 if (!ir
->outputs
[i
]) {
312 fprintf(out
, "; out%d unused\n", i
);
315 /* kill shows up as a virtual output.. skip it! */
316 if (is_kill(ir
->outputs
[i
]))
318 reg
= ir
->outputs
[i
]->regs
[0];
320 fprintf(out
, "@out(%sr%d.%c)\tout%d\n",
321 (reg
->flags
& IR3_REG_HALF
) ? "h" : "",
322 (regid
>> 2), "xyzw"[regid
& 0x3], i
);
325 for (i
= 0; i
< so
->immediates_count
; i
++) {
326 fprintf(out
, "@const(c%d.x)\t", so
->constbase
.immediate
+ i
);
327 fprintf(out
, "0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
328 so
->immediates
[i
].val
[0],
329 so
->immediates
[i
].val
[1],
330 so
->immediates
[i
].val
[2],
331 so
->immediates
[i
].val
[3]);
334 disasm_a3xx(bin
, so
->info
.sizedwords
, 0, out
, ir
->compiler
->gpu_id
);
337 case MESA_SHADER_VERTEX
:
338 fprintf(out
, "; %s: outputs:", type
);
339 for (i
= 0; i
< so
->outputs_count
; i
++) {
340 uint8_t regid
= so
->outputs
[i
].regid
;
341 fprintf(out
, " r%d.%c (%s)",
342 (regid
>> 2), "xyzw"[regid
& 0x3],
343 gl_varying_slot_name(so
->outputs
[i
].slot
));
346 fprintf(out
, "; %s: inputs:", type
);
347 for (i
= 0; i
< so
->inputs_count
; i
++) {
348 uint8_t regid
= so
->inputs
[i
].regid
;
349 fprintf(out
, " r%d.%c (cm=%x,il=%u,b=%u)",
350 (regid
>> 2), "xyzw"[regid
& 0x3],
351 so
->inputs
[i
].compmask
,
357 case MESA_SHADER_FRAGMENT
:
358 fprintf(out
, "; %s: outputs:", type
);
359 for (i
= 0; i
< so
->outputs_count
; i
++) {
360 uint8_t regid
= so
->outputs
[i
].regid
;
361 fprintf(out
, " r%d.%c (%s)",
362 (regid
>> 2), "xyzw"[regid
& 0x3],
363 gl_frag_result_name(so
->outputs
[i
].slot
));
366 fprintf(out
, "; %s: inputs:", type
);
367 for (i
= 0; i
< so
->inputs_count
; i
++) {
368 uint8_t regid
= so
->inputs
[i
].regid
;
369 fprintf(out
, " r%d.%c (%s,cm=%x,il=%u,b=%u)",
370 (regid
>> 2), "xyzw"[regid
& 0x3],
371 gl_varying_slot_name(so
->inputs
[i
].slot
),
372 so
->inputs
[i
].compmask
,
383 /* print generic shader info: */
384 fprintf(out
, "; %s prog %d/%d: %u instructions, %d half, %d full\n",
385 type
, so
->shader
->id
, so
->id
,
386 so
->info
.instrs_count
,
387 so
->info
.max_half_reg
+ 1,
388 so
->info
.max_reg
+ 1);
390 fprintf(out
, "; %d const, %u constlen\n",
391 so
->info
.max_const
+ 1,
394 fprintf(out
, "; %u (ss), %u (sy)\n", so
->info
.ss
, so
->info
.sy
);
396 fprintf(out
, "; max_sun=%u\n", ir
->max_sun
);
398 /* print shader type specific info: */
400 case MESA_SHADER_VERTEX
:
401 dump_output(out
, so
, VARYING_SLOT_POS
, "pos");
402 dump_output(out
, so
, VARYING_SLOT_PSIZ
, "psize");
404 case MESA_SHADER_FRAGMENT
:
405 dump_reg(out
, "pos (bary)",
406 ir3_find_sysval_regid(so
, SYSTEM_VALUE_VARYING_COORD
));
407 dump_output(out
, so
, FRAG_RESULT_DEPTH
, "posz");
408 if (so
->color0_mrt
) {
409 dump_output(out
, so
, FRAG_RESULT_COLOR
, "color");
411 dump_output(out
, so
, FRAG_RESULT_DATA0
, "data0");
412 dump_output(out
, so
, FRAG_RESULT_DATA1
, "data1");
413 dump_output(out
, so
, FRAG_RESULT_DATA2
, "data2");
414 dump_output(out
, so
, FRAG_RESULT_DATA3
, "data3");
415 dump_output(out
, so
, FRAG_RESULT_DATA4
, "data4");
416 dump_output(out
, so
, FRAG_RESULT_DATA5
, "data5");
417 dump_output(out
, so
, FRAG_RESULT_DATA6
, "data6");
418 dump_output(out
, so
, FRAG_RESULT_DATA7
, "data7");
420 /* these two are hard-coded since we don't know how to
421 * program them to anything but all 0's...
424 fprintf(out
, "; fragcoord: r0.x\n");
426 fprintf(out
, "; fragface: hr0.x\n");
437 ir3_shader_outputs(const struct ir3_shader
*so
)
439 return so
->nir
->info
.outputs_written
;