2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "util/u_atomic.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/format/u_format.h"
32 #include "drm/freedreno_drmif.h"
34 #include "ir3_shader.h"
35 #include "ir3_compiler.h"
39 ir3_glsl_type_size(const struct glsl_type
*type
, bool bindless
)
41 return glsl_count_attribute_slots(type
, false);
45 delete_variant(struct ir3_shader_variant
*v
)
54 /* for vertex shader, the inputs are loaded into registers before the shader
55 * is executed, so max_regs from the shader instructions might not properly
56 * reflect the # of registers actually used, especially in case passthrough
59 * Likewise, for fragment shader, we can have some regs which are passed
60 * input values but never touched by the resulting shader (ie. as result
61 * of dead code elimination or simply because we don't know how to turn
65 fixup_regfootprint(struct ir3_shader_variant
*v
, uint32_t gpu_id
)
69 for (i
= 0; i
< v
->inputs_count
; i
++) {
70 /* skip frag inputs fetch via bary.f since their reg's are
71 * not written by gpu before shader starts (and in fact the
72 * regid's might not even be valid)
74 if (v
->inputs
[i
].bary
)
77 /* ignore high regs that are global to all threads in a warp
78 * (they exist by default) (a5xx+)
80 if (v
->inputs
[i
].regid
>= regid(48,0))
83 if (v
->inputs
[i
].compmask
) {
84 unsigned n
= util_last_bit(v
->inputs
[i
].compmask
) - 1;
85 int32_t regid
= v
->inputs
[i
].regid
+ n
;
86 if (v
->inputs
[i
].half
) {
88 v
->info
.max_half_reg
= MAX2(v
->info
.max_half_reg
, regid
>> 2);
90 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 3);
93 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 2);
98 for (i
= 0; i
< v
->outputs_count
; i
++) {
99 /* for ex, VS shaders with tess don't have normal varying outs: */
100 if (!VALIDREG(v
->outputs
[i
].regid
))
102 int32_t regid
= v
->outputs
[i
].regid
+ 3;
103 if (v
->outputs
[i
].half
) {
105 v
->info
.max_half_reg
= MAX2(v
->info
.max_half_reg
, regid
>> 2);
107 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 3);
110 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 2);
114 for (i
= 0; i
< v
->num_sampler_prefetch
; i
++) {
115 unsigned n
= util_last_bit(v
->sampler_prefetch
[i
].wrmask
) - 1;
116 int32_t regid
= v
->sampler_prefetch
[i
].dst
+ n
;
117 if (v
->sampler_prefetch
[i
].half_precision
) {
119 v
->info
.max_half_reg
= MAX2(v
->info
.max_half_reg
, regid
>> 2);
121 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 3);
124 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 2);
129 /* wrapper for ir3_assemble() which does some info fixup based on
130 * shader state. Non-static since used by ir3_cmdline too.
132 void * ir3_shader_assemble(struct ir3_shader_variant
*v
, uint32_t gpu_id
)
136 bin
= ir3_assemble(v
->ir
, &v
->info
, gpu_id
);
141 v
->instrlen
= v
->info
.sizedwords
/ (2 * 16);
143 v
->instrlen
= v
->info
.sizedwords
/ (2 * 4);
146 /* NOTE: if relative addressing is used, we set constlen in
147 * the compiler (to worst-case value) since we don't know in
148 * the assembler what the max addr reg value can be:
150 v
->constlen
= MAX2(v
->constlen
, v
->info
.max_const
+ 1);
152 fixup_regfootprint(v
, gpu_id
);
158 assemble_variant(struct ir3_shader_variant
*v
)
160 struct ir3_compiler
*compiler
= v
->shader
->compiler
;
161 struct shader_info
*info
= &v
->shader
->nir
->info
;
162 uint32_t gpu_id
= compiler
->gpu_id
;
165 bin
= ir3_shader_assemble(v
, gpu_id
);
166 sz
= v
->info
.sizedwords
* 4;
168 v
->bo
= fd_bo_new(compiler
->dev
, sz
,
169 DRM_FREEDRENO_GEM_CACHE_WCOMBINE
|
170 DRM_FREEDRENO_GEM_TYPE_KMEM
,
171 "%s:%s", ir3_shader_stage(v
), info
->name
);
173 memcpy(fd_bo_map(v
->bo
), bin
, sz
);
175 if (shader_debug_enabled(v
->shader
->type
)) {
176 fprintf(stdout
, "Native code for unnamed %s shader %s:\n",
177 ir3_shader_stage(v
), v
->shader
->nir
->info
.name
);
178 if (v
->shader
->type
== MESA_SHADER_FRAGMENT
)
179 fprintf(stdout
, "SIMD0\n");
180 ir3_shader_disasm(v
, bin
, stdout
);
185 /* no need to keep the ir around beyond this point: */
191 * For creating normal shader variants, 'nonbinning' is NULL. For
192 * creating binning pass shader, it is link to corresponding normal
193 * (non-binning) variant.
195 static struct ir3_shader_variant
*
196 create_variant(struct ir3_shader
*shader
, struct ir3_shader_key
*key
,
197 struct ir3_shader_variant
*nonbinning
)
199 struct ir3_shader_variant
*v
= CALLOC_STRUCT(ir3_shader_variant
);
205 v
->id
= ++shader
->variant_count
;
207 v
->binning_pass
= !!nonbinning
;
208 v
->nonbinning
= nonbinning
;
210 v
->type
= shader
->type
;
212 ret
= ir3_compile_shader_nir(shader
->compiler
, v
);
214 debug_error("compile failed!");
220 debug_error("assemble failed!");
231 static inline struct ir3_shader_variant
*
232 shader_variant(struct ir3_shader
*shader
, struct ir3_shader_key
*key
,
235 struct ir3_shader_variant
*v
;
239 for (v
= shader
->variants
; v
; v
= v
->next
)
240 if (ir3_shader_key_equal(key
, &v
->key
))
243 /* compile new variant if it doesn't exist already: */
244 v
= create_variant(shader
, key
, NULL
);
246 v
->next
= shader
->variants
;
247 shader
->variants
= v
;
254 struct ir3_shader_variant
*
255 ir3_shader_get_variant(struct ir3_shader
*shader
, struct ir3_shader_key
*key
,
256 bool binning_pass
, bool *created
)
258 mtx_lock(&shader
->variants_lock
);
259 struct ir3_shader_variant
*v
=
260 shader_variant(shader
, key
, created
);
262 if (v
&& binning_pass
) {
264 v
->binning
= create_variant(shader
, key
, v
);
267 mtx_unlock(&shader
->variants_lock
);
270 mtx_unlock(&shader
->variants_lock
);
276 ir3_shader_destroy(struct ir3_shader
*shader
)
278 struct ir3_shader_variant
*v
, *t
;
279 for (v
= shader
->variants
; v
; ) {
284 free(shader
->const_state
.immediates
);
285 ralloc_free(shader
->nir
);
286 mtx_destroy(&shader
->variants_lock
);
291 lower_output_var(nir_shader
*nir
, int location
)
293 nir_foreach_variable (var
, &nir
->outputs
) {
294 if (var
->data
.driver_location
== location
&&
295 ((var
->data
.precision
== GLSL_PRECISION_MEDIUM
) ||
296 (var
->data
.precision
== GLSL_PRECISION_LOW
))) {
297 if (glsl_get_base_type(var
->type
) == GLSL_TYPE_FLOAT
)
298 var
->type
= glsl_float16_type(var
->type
);
300 return glsl_get_base_type(var
->type
) == GLSL_TYPE_FLOAT16
;
308 lower_mediump_outputs(nir_shader
*nir
)
310 nir_function_impl
*impl
= nir_shader_get_entrypoint(nir
);
313 /* Get rid of old derefs before we change the types of the variables */
317 nir_builder_init(&b
, impl
);
319 nir_foreach_block_safe (block
, impl
) {
320 nir_foreach_instr_safe (instr
, block
) {
321 if (instr
->type
!= nir_instr_type_intrinsic
)
324 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
325 if (intr
->intrinsic
!= nir_intrinsic_store_output
)
328 if (!lower_output_var(nir
, nir_intrinsic_base(intr
)))
331 b
.cursor
= nir_before_instr(&intr
->instr
);
332 nir_instr_rewrite_src(&intr
->instr
, &intr
->src
[0],
333 nir_src_for_ssa(nir_f2f16(&b
, intr
->src
[0].ssa
)));
339 ir3_shader_from_nir(struct ir3_compiler
*compiler
, nir_shader
*nir
)
341 struct ir3_shader
*shader
= CALLOC_STRUCT(ir3_shader
);
343 mtx_init(&shader
->variants_lock
, mtx_plain
);
344 shader
->compiler
= compiler
;
345 shader
->id
= p_atomic_inc_return(&shader
->compiler
->shader_count
);
346 shader
->type
= nir
->info
.stage
;
348 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, ir3_glsl_type_size
,
349 (nir_lower_io_options
)0);
351 if (compiler
->gpu_id
>= 600 &&
352 nir
->info
.stage
== MESA_SHADER_FRAGMENT
&&
353 !(ir3_shader_debug
& IR3_DBG_NOFP16
))
354 lower_mediump_outputs(nir
);
356 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
357 /* NOTE: lower load_barycentric_at_sample first, since it
358 * produces load_barycentric_at_offset:
360 NIR_PASS_V(nir
, ir3_nir_lower_load_barycentric_at_sample
);
361 NIR_PASS_V(nir
, ir3_nir_lower_load_barycentric_at_offset
);
363 NIR_PASS_V(nir
, ir3_nir_move_varying_inputs
);
366 NIR_PASS_V(nir
, nir_lower_io_arrays_to_elements_no_indirects
, false);
368 NIR_PASS_V(nir
, nir_lower_amul
, ir3_glsl_type_size
);
370 /* do first pass optimization, ignoring the key: */
371 ir3_optimize_nir(shader
, nir
, NULL
);
374 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
375 printf("dump nir%d: type=%d", shader
->id
, shader
->type
);
376 nir_print_shader(shader
->nir
, stdout
);
382 static void dump_reg(FILE *out
, const char *name
, uint32_t r
)
384 if (r
!= regid(63,0)) {
385 const char *reg_type
= (r
& HALF_REG_ID
) ? "hr" : "r";
386 fprintf(out
, "; %s: %s%d.%c\n", name
, reg_type
,
387 (r
& ~HALF_REG_ID
) >> 2, "xyzw"[r
& 0x3]);
391 static void dump_output(FILE *out
, struct ir3_shader_variant
*so
,
392 unsigned slot
, const char *name
)
395 regid
= ir3_find_output_regid(so
, slot
);
396 dump_reg(out
, name
, regid
);
400 input_name(struct ir3_shader_variant
*so
, int i
)
402 if (so
->inputs
[i
].sysval
) {
403 return gl_system_value_name(so
->inputs
[i
].slot
);
404 } else if (so
->type
== MESA_SHADER_VERTEX
) {
405 return gl_vert_attrib_name(so
->inputs
[i
].slot
);
407 return gl_varying_slot_name(so
->inputs
[i
].slot
);
412 output_name(struct ir3_shader_variant
*so
, int i
)
414 if (so
->type
== MESA_SHADER_FRAGMENT
) {
415 return gl_frag_result_name(so
->outputs
[i
].slot
);
417 switch (so
->outputs
[i
].slot
) {
418 case VARYING_SLOT_GS_HEADER_IR3
:
420 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3
:
421 return "GS_VERTEX_FLAGS";
422 case VARYING_SLOT_TCS_HEADER_IR3
:
425 return gl_varying_slot_name(so
->outputs
[i
].slot
);
431 ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
, FILE *out
)
433 struct ir3
*ir
= so
->ir
;
434 struct ir3_register
*reg
;
435 const char *type
= ir3_shader_stage(so
);
439 struct ir3_instruction
*instr
;
440 foreach_input_n (instr
, i
, ir
) {
441 reg
= instr
->regs
[0];
443 fprintf(out
, "@in(%sr%d.%c)\tin%d",
444 (reg
->flags
& IR3_REG_HALF
) ? "h" : "",
445 (regid
>> 2), "xyzw"[regid
& 0x3], i
);
447 if (reg
->wrmask
> 0x1)
448 fprintf(out
, " (wrmask=0x%x)", reg
->wrmask
);
452 /* print pre-dispatch texture fetches: */
453 for (i
= 0; i
< so
->num_sampler_prefetch
; i
++) {
454 const struct ir3_sampler_prefetch
*fetch
= &so
->sampler_prefetch
[i
];
455 fprintf(out
, "@tex(%sr%d.%c)\tsrc=%u, samp=%u, tex=%u, wrmask=%x, cmd=%u\n",
456 fetch
->half_precision
? "h" : "",
457 fetch
->dst
>> 2, "xyzw"[fetch
->dst
& 0x3],
458 fetch
->src
, fetch
->samp_id
, fetch
->tex_id
,
459 fetch
->wrmask
, fetch
->cmd
);
462 foreach_output_n (instr
, i
, ir
) {
463 reg
= instr
->regs
[0];
465 fprintf(out
, "@out(%sr%d.%c)\tout%d",
466 (reg
->flags
& IR3_REG_HALF
) ? "h" : "",
467 (regid
>> 2), "xyzw"[regid
& 0x3], i
);
468 if (reg
->wrmask
> 0x1)
469 fprintf(out
, " (wrmask=0x%x)", reg
->wrmask
);
473 struct ir3_const_state
*const_state
= &so
->shader
->const_state
;
474 for (i
= 0; i
< const_state
->immediates_count
; i
++) {
475 fprintf(out
, "@const(c%d.x)\t", const_state
->offsets
.immediate
+ i
);
476 fprintf(out
, "0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
477 const_state
->immediates
[i
].val
[0],
478 const_state
->immediates
[i
].val
[1],
479 const_state
->immediates
[i
].val
[2],
480 const_state
->immediates
[i
].val
[3]);
483 disasm_a3xx(bin
, so
->info
.sizedwords
, 0, out
, ir
->compiler
->gpu_id
);
485 fprintf(out
, "; %s: outputs:", type
);
486 for (i
= 0; i
< so
->outputs_count
; i
++) {
487 uint8_t regid
= so
->outputs
[i
].regid
;
488 const char *reg_type
= so
->outputs
[i
].half
? "hr" : "r";
489 fprintf(out
, " %s%d.%c (%s)",
490 reg_type
, (regid
>> 2), "xyzw"[regid
& 0x3],
495 fprintf(out
, "; %s: inputs:", type
);
496 for (i
= 0; i
< so
->inputs_count
; i
++) {
497 uint8_t regid
= so
->inputs
[i
].regid
;
498 fprintf(out
, " r%d.%c (%s slot=%d cm=%x,il=%u,b=%u)",
499 (regid
>> 2), "xyzw"[regid
& 0x3],
502 so
->inputs
[i
].compmask
,
508 /* print generic shader info: */
509 fprintf(out
, "; %s prog %d/%d: %u instr, %u nops, %u non-nops, %u dwords\n",
510 type
, so
->shader
->id
, so
->id
,
511 so
->info
.instrs_count
,
513 so
->info
.instrs_count
- so
->info
.nops_count
,
514 so
->info
.sizedwords
);
516 fprintf(out
, "; %s prog %d/%d: %u last-baryf, %d half, %d full, %u constlen\n",
517 type
, so
->shader
->id
, so
->id
,
519 so
->info
.max_half_reg
+ 1,
520 so
->info
.max_reg
+ 1,
523 fprintf(out
, "; %s prog %d/%d: %u sstall, %u (ss), %u (sy), %d max_sun, %d loops\n",
524 type
, so
->shader
->id
, so
->id
,
531 /* print shader type specific info: */
533 case MESA_SHADER_VERTEX
:
534 dump_output(out
, so
, VARYING_SLOT_POS
, "pos");
535 dump_output(out
, so
, VARYING_SLOT_PSIZ
, "psize");
537 case MESA_SHADER_FRAGMENT
:
538 dump_reg(out
, "pos (ij_pixel)",
539 ir3_find_sysval_regid(so
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
));
540 dump_reg(out
, "pos (ij_centroid)",
541 ir3_find_sysval_regid(so
, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
));
542 dump_reg(out
, "pos (ij_size)",
543 ir3_find_sysval_regid(so
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE
));
544 dump_output(out
, so
, FRAG_RESULT_DEPTH
, "posz");
545 if (so
->color0_mrt
) {
546 dump_output(out
, so
, FRAG_RESULT_COLOR
, "color");
548 dump_output(out
, so
, FRAG_RESULT_DATA0
, "data0");
549 dump_output(out
, so
, FRAG_RESULT_DATA1
, "data1");
550 dump_output(out
, so
, FRAG_RESULT_DATA2
, "data2");
551 dump_output(out
, so
, FRAG_RESULT_DATA3
, "data3");
552 dump_output(out
, so
, FRAG_RESULT_DATA4
, "data4");
553 dump_output(out
, so
, FRAG_RESULT_DATA5
, "data5");
554 dump_output(out
, so
, FRAG_RESULT_DATA6
, "data6");
555 dump_output(out
, so
, FRAG_RESULT_DATA7
, "data7");
557 dump_reg(out
, "fragcoord",
558 ir3_find_sysval_regid(so
, SYSTEM_VALUE_FRAG_COORD
));
559 dump_reg(out
, "fragface",
560 ir3_find_sysval_regid(so
, SYSTEM_VALUE_FRONT_FACE
));
571 ir3_shader_outputs(const struct ir3_shader
*so
)
573 return so
->nir
->info
.outputs_written
;