src/freedreno/ir3/ir3_shader.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "util/u_atomic.h"
  28 #include "util/u_string.h"
  29 #include "util/u_memory.h"
  30 #include "util/u_format.h"
  31
  32 #include "drm/freedreno_drmif.h"
  33
  34 #include "ir3_shader.h"
  35 #include "ir3_compiler.h"
  36 #include "ir3_nir.h"
  37
  38 int
  39 ir3_glsl_type_size(const struct glsl_type *type, bool bindless)
  40 {
  41         return glsl_count_attribute_slots(type, false);
  42 }
  43
  44 static void
  45 delete_variant(struct ir3_shader_variant *v)
  46 {
  47         if (v->ir)
  48                 ir3_destroy(v->ir);
  49         if (v->bo)
  50                 fd_bo_del(v->bo);
  51         free(v);
  52 }
  53
  54 /* for vertex shader, the inputs are loaded into registers before the shader
  55  * is executed, so max_regs from the shader instructions might not properly
  56  * reflect the # of registers actually used, especially in case passthrough
  57  * varyings.
  58  *
  59  * Likewise, for fragment shader, we can have some regs which are passed
  60  * input values but never touched by the resulting shader (ie. as result
  61  * of dead code elimination or simply because we don't know how to turn
  62  * the reg off.
  63  */
  64 static void
  65 fixup_regfootprint(struct ir3_shader_variant *v, uint32_t gpu_id)
  66 {
  67         unsigned i;
  68
  69         for (i = 0; i < v->inputs_count; i++) {
  70                 /* skip frag inputs fetch via bary.f since their reg's are
  71                  * not written by gpu before shader starts (and in fact the
  72                  * regid's might not even be valid)
  73                  */
  74                 if (v->inputs[i].bary)
  75                         continue;
  76
  77                 /* ignore high regs that are global to all threads in a warp
  78                  * (they exist by default) (a5xx+)
  79                  */
  80                 if (v->inputs[i].regid >= regid(48,0))
  81                         continue;
  82
  83                 if (v->inputs[i].compmask) {
  84                         unsigned n = util_last_bit(v->inputs[i].compmask) - 1;
  85                         int32_t regid = v->inputs[i].regid + n;
  86                         if (v->inputs[i].half) {
  87                                 if (gpu_id < 500) {
  88                                         v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
  89                                 } else {
  90                                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
  91                                 }
  92                         } else {
  93                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
  94                         }
  95                 }
  96         }
  97
  98         for (i = 0; i < v->outputs_count; i++) {
  99                 int32_t regid = v->outputs[i].regid + 3;
 100                 if (v->outputs[i].half) {
 101                         if (gpu_id < 500) {
 102                                 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
 103                         } else {
 104                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
 105                         }
 106                 } else {
 107                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
 108                 }
 109         }
 110 }
 111
 112 /* wrapper for ir3_assemble() which does some info fixup based on
 113  * shader state.  Non-static since used by ir3_cmdline too.
 114  */
 115 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id)
 116 {
 117         void *bin;
 118
 119         bin = ir3_assemble(v->ir, &v->info, gpu_id);
 120         if (!bin)
 121                 return NULL;
 122
 123         if (gpu_id >= 400) {
 124                 v->instrlen = v->info.sizedwords / (2 * 16);
 125         } else {
 126                 v->instrlen = v->info.sizedwords / (2 * 4);
 127         }
 128
 129         /* NOTE: if relative addressing is used, we set constlen in
 130          * the compiler (to worst-case value) since we don't know in
 131          * the assembler what the max addr reg value can be:
 132          */
 133         v->constlen = MAX2(v->constlen, v->info.max_const + 1);
 134
 135         fixup_regfootprint(v, gpu_id);
 136
 137         return bin;
 138 }
 139
 140 static void
 141 assemble_variant(struct ir3_shader_variant *v)
 142 {
 143         struct ir3_compiler *compiler = v->shader->compiler;
 144         struct shader_info *info = &v->shader->nir->info;
 145         uint32_t gpu_id = compiler->gpu_id;
 146         uint32_t sz, *bin;
 147
 148         bin = ir3_shader_assemble(v, gpu_id);
 149         sz = v->info.sizedwords * 4;
 150
 151         v->bo = fd_bo_new(compiler->dev, sz,
 152                         DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
 153                         DRM_FREEDRENO_GEM_TYPE_KMEM,
 154                         "%s:%s", ir3_shader_stage(v->shader), info->name);
 155
 156         memcpy(fd_bo_map(v->bo), bin, sz);
 157
 158         if (ir3_shader_debug & IR3_DBG_DISASM) {
 159                 struct ir3_shader_key key = v->key;
 160                 printf("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}\n", v->type,
 161                         v->binning_pass, key.color_two_side, key.half_precision);
 162                 ir3_shader_disasm(v, bin, stdout);
 163         }
 164
 165         if (shader_debug_enabled(v->shader->type)) {
 166                 fprintf(stderr, "Native code for unnamed %s shader %s:\n",
 167                         _mesa_shader_stage_to_string(v->shader->type),
 168                         v->shader->nir->info.name);
 169                 if (v->shader->type == MESA_SHADER_FRAGMENT)
 170                         fprintf(stderr, "SIMD0\n");
 171                 ir3_shader_disasm(v, bin, stderr);
 172         }
 173
 174         free(bin);
 175
 176         /* no need to keep the ir around beyond this point: */
 177         ir3_destroy(v->ir);
 178         v->ir = NULL;
 179 }
 180
 181 /*
 182  * For creating normal shader variants, 'nonbinning' is NULL.  For
 183  * creating binning pass shader, it is link to corresponding normal
 184  * (non-binning) variant.
 185  */
 186 static struct ir3_shader_variant *
 187 create_variant(struct ir3_shader *shader, struct ir3_shader_key *key,
 188                 struct ir3_shader_variant *nonbinning)
 189 {
 190         struct ir3_shader_variant *v = CALLOC_STRUCT(ir3_shader_variant);
 191         int ret;
 192
 193         if (!v)
 194                 return NULL;
 195
 196         v->id = ++shader->variant_count;
 197         v->shader = shader;
 198         v->binning_pass = !!nonbinning;
 199         v->nonbinning = nonbinning;
 200         v->key = *key;
 201         v->type = shader->type;
 202
 203         ret = ir3_compile_shader_nir(shader->compiler, v);
 204         if (ret) {
 205                 debug_error("compile failed!");
 206                 goto fail;
 207         }
 208
 209         assemble_variant(v);
 210         if (!v->bo) {
 211                 debug_error("assemble failed!");
 212                 goto fail;
 213         }
 214
 215         return v;
 216
 217 fail:
 218         delete_variant(v);
 219         return NULL;
 220 }
 221
 222 static inline struct ir3_shader_variant *
 223 shader_variant(struct ir3_shader *shader, struct ir3_shader_key *key,
 224                 bool *created)
 225 {
 226         struct ir3_shader_variant *v;
 227
 228         *created = false;
 229
 230         for (v = shader->variants; v; v = v->next)
 231                 if (ir3_shader_key_equal(key, &v->key))
 232                         return v;
 233
 234         /* compile new variant if it doesn't exist already: */
 235         v = create_variant(shader, key, NULL);
 236         if (v) {
 237                 v->next = shader->variants;
 238                 shader->variants = v;
 239                 *created = true;
 240         }
 241
 242         return v;
 243 }
 244
 245 struct ir3_shader_variant *
 246 ir3_shader_get_variant(struct ir3_shader *shader, struct ir3_shader_key *key,
 247                 bool binning_pass, bool *created)
 248 {
 249         mtx_lock(&shader->variants_lock);
 250         struct ir3_shader_variant *v =
 251                         shader_variant(shader, key, created);
 252
 253         if (v && binning_pass) {
 254                 if (!v->binning) {
 255                         v->binning = create_variant(shader, key, v);
 256                         *created = true;
 257                 }
 258                 mtx_unlock(&shader->variants_lock);
 259                 return v->binning;
 260         }
 261         mtx_unlock(&shader->variants_lock);
 262
 263         return v;
 264 }
 265
 266 void
 267 ir3_shader_destroy(struct ir3_shader *shader)
 268 {
 269         struct ir3_shader_variant *v, *t;
 270         for (v = shader->variants; v; ) {
 271                 t = v;
 272                 v = v->next;
 273                 delete_variant(t);
 274         }
 275         free(shader->const_state.immediates);
 276         ralloc_free(shader->nir);
 277         mtx_destroy(&shader->variants_lock);
 278         free(shader);
 279 }
 280
 281 struct ir3_shader *
 282 ir3_shader_from_nir(struct ir3_compiler *compiler, nir_shader *nir)
 283 {
 284         struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
 285
 286         mtx_init(&shader->variants_lock, mtx_plain);
 287         shader->compiler = compiler;
 288         shader->id = p_atomic_inc_return(&shader->compiler->shader_count);
 289         shader->type = nir->info.stage;
 290
 291         NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size,
 292                            (nir_lower_io_options)0);
 293
 294         if (nir->info.stage == MESA_SHADER_FRAGMENT) {
 295                 /* NOTE: lower load_barycentric_at_sample first, since it
 296                  * produces load_barycentric_at_offset:
 297                  */
 298                 NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_sample);
 299                 NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_offset);
 300
 301                 NIR_PASS_V(nir, ir3_nir_move_varying_inputs);
 302         }
 303
 304         NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
 305
 306         /* do first pass optimization, ignoring the key: */
 307         ir3_optimize_nir(shader, nir, NULL);
 308
 309         shader->nir = nir;
 310         if (ir3_shader_debug & IR3_DBG_DISASM) {
 311                 printf("dump nir%d: type=%d", shader->id, shader->type);
 312                 nir_print_shader(shader->nir, stdout);
 313         }
 314
 315         return shader;
 316 }
 317
 318 static void dump_reg(FILE *out, const char *name, uint32_t r)
 319 {
 320         if (r != regid(63,0)) {
 321                 const char *reg_type = (r & HALF_REG_ID) ? "hr" : "r";
 322                 fprintf(out, "; %s: %s%d.%c\n", name, reg_type,
 323                                 (r & ~HALF_REG_ID) >> 2, "xyzw"[r & 0x3]);
 324         }
 325 }
 326
 327 static void dump_output(FILE *out, struct ir3_shader_variant *so,
 328                 unsigned slot, const char *name)
 329 {
 330         uint32_t regid;
 331         regid = ir3_find_output_regid(so, slot);
 332         dump_reg(out, name, regid);
 333 }
 334
 335 static const char *
 336 input_name(struct ir3_shader_variant *so, int i)
 337 {
 338         if (so->inputs[i].sysval) {
 339                 return gl_system_value_name(so->inputs[i].slot);
 340         } else if (so->type == MESA_SHADER_VERTEX) {
 341                 return gl_vert_attrib_name(so->inputs[i].slot);
 342         } else {
 343                 return gl_varying_slot_name(so->inputs[i].slot);
 344         }
 345 }
 346
 347 static const char *
 348 output_name(struct ir3_shader_variant *so, int i)
 349 {
 350         if (so->type == MESA_SHADER_FRAGMENT) {
 351                 return gl_frag_result_name(so->outputs[i].slot);
 352         } else {
 353                 switch (so->outputs[i].slot) {
 354                 case VARYING_SLOT_GS_HEADER_IR3:
 355                         return "GS_HEADER";
 356                 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
 357                         return "GS_VERTEX_FLAGS";
 358                 default:
 359                         return gl_varying_slot_name(so->outputs[i].slot);
 360                 }
 361         }
 362 }
 363
 364 void
 365 ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
 366 {
 367         struct ir3 *ir = so->ir;
 368         struct ir3_register *reg;
 369         const char *type = ir3_shader_stage(so->shader);
 370         uint8_t regid;
 371         unsigned i;
 372
 373         for (i = 0; i < ir->ninputs; i++) {
 374                 if (!ir->inputs[i]) {
 375                         fprintf(out, "; in%d unused\n", i);
 376                         continue;
 377                 }
 378                 reg = ir->inputs[i]->regs[0];
 379                 regid = reg->num;
 380                 fprintf(out, "@in(%sr%d.%c)\tin%d\n",
 381                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 382                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 383         }
 384
 385         for (i = 0; i < ir->noutputs; i++) {
 386                 if (!ir->outputs[i]) {
 387                         fprintf(out, "; out%d unused\n", i);
 388                         continue;
 389                 }
 390                 /* kill shows up as a virtual output.. skip it! */
 391                 if (is_kill(ir->outputs[i]))
 392                         continue;
 393                 reg = ir->outputs[i]->regs[0];
 394                 regid = reg->num;
 395                 fprintf(out, "@out(%sr%d.%c)\tout%d\n",
 396                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 397                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 398         }
 399
 400         struct ir3_const_state *const_state = &so->shader->const_state;
 401         for (i = 0; i < const_state->immediates_count; i++) {
 402                 fprintf(out, "@const(c%d.x)\t", const_state->offsets.immediate + i);
 403                 fprintf(out, "0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
 404                                 const_state->immediates[i].val[0],
 405                                 const_state->immediates[i].val[1],
 406                                 const_state->immediates[i].val[2],
 407                                 const_state->immediates[i].val[3]);
 408         }
 409
 410         disasm_a3xx(bin, so->info.sizedwords, 0, out, ir->compiler->gpu_id);
 411
 412         fprintf(out, "; %s: outputs:", type);
 413         for (i = 0; i < so->outputs_count; i++) {
 414                 uint8_t regid = so->outputs[i].regid;
 415                 fprintf(out, " r%d.%c (%s)",
 416                                 (regid >> 2), "xyzw"[regid & 0x3],
 417                                 output_name(so, i));
 418         }
 419         fprintf(out, "\n");
 420
 421         fprintf(out, "; %s: inputs:", type);
 422         for (i = 0; i < so->inputs_count; i++) {
 423                 uint8_t regid = so->inputs[i].regid;
 424                 fprintf(out, " r%d.%c (%s slot=%d cm=%x,il=%u,b=%u)",
 425                                 (regid >> 2), "xyzw"[regid & 0x3],
 426                                 input_name(so, i),
 427                                 so->inputs[i].slot,
 428                                 so->inputs[i].compmask,
 429                                 so->inputs[i].inloc,
 430                                 so->inputs[i].bary);
 431         }
 432         fprintf(out, "\n");
 433
 434         /* print generic shader info: */
 435         fprintf(out, "; %s prog %d/%d: %u instructions, %d half, %d full\n",
 436                         type, so->shader->id, so->id,
 437                         so->info.instrs_count,
 438                         so->info.max_half_reg + 1,
 439                         so->info.max_reg + 1);
 440
 441         fprintf(out, "; %u constlen\n", so->constlen);
 442
 443         fprintf(out, "; %u (ss), %u (sy)\n", so->info.ss, so->info.sy);
 444
 445         fprintf(out, "; max_sun=%u\n", ir->max_sun);
 446
 447         /* print shader type specific info: */
 448         switch (so->type) {
 449         case MESA_SHADER_VERTEX:
 450                 dump_output(out, so, VARYING_SLOT_POS, "pos");
 451                 dump_output(out, so, VARYING_SLOT_PSIZ, "psize");
 452                 break;
 453         case MESA_SHADER_FRAGMENT:
 454                 dump_reg(out, "pos (ij_pixel)",
 455                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PIXEL));
 456                 dump_reg(out, "pos (ij_centroid)",
 457                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_CENTROID));
 458                 dump_reg(out, "pos (ij_size)",
 459                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_SIZE));
 460                 dump_output(out, so, FRAG_RESULT_DEPTH, "posz");
 461                 if (so->color0_mrt) {
 462                         dump_output(out, so, FRAG_RESULT_COLOR, "color");
 463                 } else {
 464                         dump_output(out, so, FRAG_RESULT_DATA0, "data0");
 465                         dump_output(out, so, FRAG_RESULT_DATA1, "data1");
 466                         dump_output(out, so, FRAG_RESULT_DATA2, "data2");
 467                         dump_output(out, so, FRAG_RESULT_DATA3, "data3");
 468                         dump_output(out, so, FRAG_RESULT_DATA4, "data4");
 469                         dump_output(out, so, FRAG_RESULT_DATA5, "data5");
 470                         dump_output(out, so, FRAG_RESULT_DATA6, "data6");
 471                         dump_output(out, so, FRAG_RESULT_DATA7, "data7");
 472                 }
 473                 /* these two are hard-coded since we don't know how to
 474                  * program them to anything but all 0's...
 475                  */
 476                 if (so->frag_coord)
 477                         fprintf(out, "; fragcoord: r0.x\n");
 478                 if (so->frag_face)
 479                         fprintf(out, "; fragface: hr0.x\n");
 480                 break;
 481         default:
 482                 /* TODO */
 483                 break;
 484         }
 485
 486         fprintf(out, "\n");
 487 }
 488
 489 uint64_t
 490 ir3_shader_outputs(const struct ir3_shader *so)
 491 {
 492         return so->nir->info.outputs_written;
 493 }