2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "util/u_string.h"
28 #include "util/u_memory.h"
29 #include "util/u_format.h"
31 #include "drm/freedreno_drmif.h"
33 #include "ir3_shader.h"
34 #include "ir3_compiler.h"
38 ir3_glsl_type_size(const struct glsl_type
*type
, bool bindless
)
40 return glsl_count_attribute_slots(type
, false);
44 delete_variant(struct ir3_shader_variant
*v
)
55 /* for vertex shader, the inputs are loaded into registers before the shader
56 * is executed, so max_regs from the shader instructions might not properly
57 * reflect the # of registers actually used, especially in case passthrough
60 * Likewise, for fragment shader, we can have some regs which are passed
61 * input values but never touched by the resulting shader (ie. as result
62 * of dead code elimination or simply because we don't know how to turn
66 fixup_regfootprint(struct ir3_shader_variant
*v
, uint32_t gpu_id
)
70 for (i
= 0; i
< v
->inputs_count
; i
++) {
71 /* skip frag inputs fetch via bary.f since their reg's are
72 * not written by gpu before shader starts (and in fact the
73 * regid's might not even be valid)
75 if (v
->inputs
[i
].bary
)
78 /* ignore high regs that are global to all threads in a warp
79 * (they exist by default) (a5xx+)
81 if (v
->inputs
[i
].regid
>= regid(48,0))
84 if (v
->inputs
[i
].compmask
) {
85 unsigned n
= util_last_bit(v
->inputs
[i
].compmask
) - 1;
86 int32_t regid
= v
->inputs
[i
].regid
+ n
;
87 if (v
->inputs
[i
].half
) {
89 v
->info
.max_half_reg
= MAX2(v
->info
.max_half_reg
, regid
>> 2);
91 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 3);
94 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 2);
99 for (i
= 0; i
< v
->outputs_count
; i
++) {
100 int32_t regid
= v
->outputs
[i
].regid
+ 3;
101 if (v
->outputs
[i
].half
) {
103 v
->info
.max_half_reg
= MAX2(v
->info
.max_half_reg
, regid
>> 2);
105 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 3);
108 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 2);
113 /* wrapper for ir3_assemble() which does some info fixup based on
114 * shader state. Non-static since used by ir3_cmdline too.
116 void * ir3_shader_assemble(struct ir3_shader_variant
*v
, uint32_t gpu_id
)
120 bin
= ir3_assemble(v
->ir
, &v
->info
, gpu_id
);
125 v
->instrlen
= v
->info
.sizedwords
/ (2 * 16);
127 v
->instrlen
= v
->info
.sizedwords
/ (2 * 4);
130 /* NOTE: if relative addressing is used, we set constlen in
131 * the compiler (to worst-case value) since we don't know in
132 * the assembler what the max addr reg value can be:
134 v
->constlen
= MAX2(v
->constlen
, v
->info
.max_const
+ 1);
135 debug_assert(v
->constlen
< 256);
137 fixup_regfootprint(v
, gpu_id
);
143 assemble_variant(struct ir3_shader_variant
*v
)
145 struct ir3_compiler
*compiler
= v
->shader
->compiler
;
146 struct shader_info
*info
= &v
->shader
->nir
->info
;
147 uint32_t gpu_id
= compiler
->gpu_id
;
150 bin
= ir3_shader_assemble(v
, gpu_id
);
151 sz
= v
->info
.sizedwords
* 4;
153 v
->bo
= fd_bo_new(compiler
->dev
, sz
,
154 DRM_FREEDRENO_GEM_CACHE_WCOMBINE
|
155 DRM_FREEDRENO_GEM_TYPE_KMEM
,
156 "%s:%s", ir3_shader_stage(v
->shader
), info
->name
);
158 memcpy(fd_bo_map(v
->bo
), bin
, sz
);
160 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
161 struct ir3_shader_key key
= v
->key
;
162 printf("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}", v
->type
,
163 v
->binning_pass
, key
.color_two_side
, key
.half_precision
);
164 ir3_shader_disasm(v
, bin
, stdout
);
167 if (shader_debug_enabled(v
->shader
->type
)) {
168 fprintf(stderr
, "Native code for unnamed %s shader %s:\n",
169 _mesa_shader_stage_to_string(v
->shader
->type
),
170 v
->shader
->nir
->info
.name
);
171 if (v
->shader
->type
== MESA_SHADER_FRAGMENT
)
172 fprintf(stderr
, "SIMD0\n");
173 ir3_shader_disasm(v
, bin
, stderr
);
178 /* no need to keep the ir around beyond this point: */
183 static struct ir3_shader_variant
*
184 create_variant(struct ir3_shader
*shader
, struct ir3_shader_key
*key
,
187 struct ir3_shader_variant
*v
= CALLOC_STRUCT(ir3_shader_variant
);
193 v
->id
= ++shader
->variant_count
;
195 v
->binning_pass
= binning_pass
;
197 v
->type
= shader
->type
;
199 ret
= ir3_compile_shader_nir(shader
->compiler
, v
);
201 debug_error("compile failed!");
207 debug_error("assemble failed!");
218 static inline struct ir3_shader_variant
*
219 shader_variant(struct ir3_shader
*shader
, struct ir3_shader_key
*key
,
222 struct ir3_shader_variant
*v
;
226 for (v
= shader
->variants
; v
; v
= v
->next
)
227 if (ir3_shader_key_equal(key
, &v
->key
))
230 /* compile new variant if it doesn't exist already: */
231 v
= create_variant(shader
, key
, false);
233 v
->next
= shader
->variants
;
234 shader
->variants
= v
;
241 struct ir3_shader_variant
*
242 ir3_shader_get_variant(struct ir3_shader
*shader
, struct ir3_shader_key
*key
,
243 bool binning_pass
, bool *created
)
245 struct ir3_shader_variant
*v
=
246 shader_variant(shader
, key
, created
);
248 if (v
&& binning_pass
) {
250 v
->binning
= create_variant(shader
, key
, true);
258 ir3_shader_destroy(struct ir3_shader
*shader
)
260 struct ir3_shader_variant
*v
, *t
;
261 for (v
= shader
->variants
; v
; ) {
266 ralloc_free(shader
->nir
);
271 ir3_shader_from_nir(struct ir3_compiler
*compiler
, nir_shader
*nir
)
273 struct ir3_shader
*shader
= CALLOC_STRUCT(ir3_shader
);
275 shader
->compiler
= compiler
;
276 shader
->id
= ++shader
->compiler
->shader_count
;
277 shader
->type
= nir
->info
.stage
;
279 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, ir3_glsl_type_size
,
280 (nir_lower_io_options
)0);
282 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
283 /* NOTE: lower load_barycentric_at_sample first, since it
284 * produces load_barycentric_at_offset:
286 NIR_PASS_V(nir
, ir3_nir_lower_load_barycentric_at_sample
);
287 NIR_PASS_V(nir
, ir3_nir_lower_load_barycentric_at_offset
);
289 NIR_PASS_V(nir
, ir3_nir_move_varying_inputs
);
292 NIR_PASS_V(nir
, nir_lower_io_arrays_to_elements_no_indirects
, false);
294 /* do first pass optimization, ignoring the key: */
295 shader
->nir
= ir3_optimize_nir(shader
, nir
, NULL
);
296 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
297 printf("dump nir%d: type=%d", shader
->id
, shader
->type
);
298 nir_print_shader(shader
->nir
, stdout
);
304 static void dump_reg(FILE *out
, const char *name
, uint32_t r
)
306 if (r
!= regid(63,0))
307 fprintf(out
, "; %s: r%d.%c\n", name
, r
>> 2, "xyzw"[r
& 0x3]);
310 static void dump_output(FILE *out
, struct ir3_shader_variant
*so
,
311 unsigned slot
, const char *name
)
314 regid
= ir3_find_output_regid(so
, slot
);
315 dump_reg(out
, name
, regid
);
319 ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
, FILE *out
)
321 struct ir3
*ir
= so
->ir
;
322 struct ir3_register
*reg
;
323 const char *type
= ir3_shader_stage(so
->shader
);
327 for (i
= 0; i
< ir
->ninputs
; i
++) {
328 if (!ir
->inputs
[i
]) {
329 fprintf(out
, "; in%d unused\n", i
);
332 reg
= ir
->inputs
[i
]->regs
[0];
334 fprintf(out
, "@in(%sr%d.%c)\tin%d\n",
335 (reg
->flags
& IR3_REG_HALF
) ? "h" : "",
336 (regid
>> 2), "xyzw"[regid
& 0x3], i
);
339 for (i
= 0; i
< ir
->noutputs
; i
++) {
340 if (!ir
->outputs
[i
]) {
341 fprintf(out
, "; out%d unused\n", i
);
344 /* kill shows up as a virtual output.. skip it! */
345 if (is_kill(ir
->outputs
[i
]))
347 reg
= ir
->outputs
[i
]->regs
[0];
349 fprintf(out
, "@out(%sr%d.%c)\tout%d\n",
350 (reg
->flags
& IR3_REG_HALF
) ? "h" : "",
351 (regid
>> 2), "xyzw"[regid
& 0x3], i
);
354 for (i
= 0; i
< so
->immediates_count
; i
++) {
355 fprintf(out
, "@const(c%d.x)\t", so
->constbase
.immediate
+ i
);
356 fprintf(out
, "0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
357 so
->immediates
[i
].val
[0],
358 so
->immediates
[i
].val
[1],
359 so
->immediates
[i
].val
[2],
360 so
->immediates
[i
].val
[3]);
363 disasm_a3xx(bin
, so
->info
.sizedwords
, 0, out
, ir
->compiler
->gpu_id
);
366 case MESA_SHADER_VERTEX
:
367 fprintf(out
, "; %s: outputs:", type
);
368 for (i
= 0; i
< so
->outputs_count
; i
++) {
369 uint8_t regid
= so
->outputs
[i
].regid
;
370 fprintf(out
, " r%d.%c (%s)",
371 (regid
>> 2), "xyzw"[regid
& 0x3],
372 gl_varying_slot_name(so
->outputs
[i
].slot
));
375 fprintf(out
, "; %s: inputs:", type
);
376 for (i
= 0; i
< so
->inputs_count
; i
++) {
377 uint8_t regid
= so
->inputs
[i
].regid
;
378 fprintf(out
, " r%d.%c (cm=%x,il=%u,b=%u)",
379 (regid
>> 2), "xyzw"[regid
& 0x3],
380 so
->inputs
[i
].compmask
,
386 case MESA_SHADER_FRAGMENT
:
387 fprintf(out
, "; %s: outputs:", type
);
388 for (i
= 0; i
< so
->outputs_count
; i
++) {
389 uint8_t regid
= so
->outputs
[i
].regid
;
390 fprintf(out
, " r%d.%c (%s)",
391 (regid
>> 2), "xyzw"[regid
& 0x3],
392 gl_frag_result_name(so
->outputs
[i
].slot
));
395 fprintf(out
, "; %s: inputs:", type
);
396 for (i
= 0; i
< so
->inputs_count
; i
++) {
397 uint8_t regid
= so
->inputs
[i
].regid
;
398 fprintf(out
, " r%d.%c (%s,cm=%x,il=%u,b=%u)",
399 (regid
>> 2), "xyzw"[regid
& 0x3],
400 gl_varying_slot_name(so
->inputs
[i
].slot
),
401 so
->inputs
[i
].compmask
,
412 /* print generic shader info: */
413 fprintf(out
, "; %s prog %d/%d: %u instructions, %d half, %d full\n",
414 type
, so
->shader
->id
, so
->id
,
415 so
->info
.instrs_count
,
416 so
->info
.max_half_reg
+ 1,
417 so
->info
.max_reg
+ 1);
419 fprintf(out
, "; %d const, %u constlen\n",
420 so
->info
.max_const
+ 1,
423 fprintf(out
, "; %u (ss), %u (sy)\n", so
->info
.ss
, so
->info
.sy
);
425 fprintf(out
, "; max_sun=%u\n", ir
->max_sun
);
427 /* print shader type specific info: */
429 case MESA_SHADER_VERTEX
:
430 dump_output(out
, so
, VARYING_SLOT_POS
, "pos");
431 dump_output(out
, so
, VARYING_SLOT_PSIZ
, "psize");
433 case MESA_SHADER_FRAGMENT
:
434 dump_reg(out
, "pos (ij_pixel)",
435 ir3_find_sysval_regid(so
, SYSTEM_VALUE_BARYCENTRIC_PIXEL
));
436 dump_reg(out
, "pos (ij_centroid)",
437 ir3_find_sysval_regid(so
, SYSTEM_VALUE_BARYCENTRIC_CENTROID
));
438 dump_reg(out
, "pos (ij_size)",
439 ir3_find_sysval_regid(so
, SYSTEM_VALUE_BARYCENTRIC_SIZE
));
440 dump_output(out
, so
, FRAG_RESULT_DEPTH
, "posz");
441 if (so
->color0_mrt
) {
442 dump_output(out
, so
, FRAG_RESULT_COLOR
, "color");
444 dump_output(out
, so
, FRAG_RESULT_DATA0
, "data0");
445 dump_output(out
, so
, FRAG_RESULT_DATA1
, "data1");
446 dump_output(out
, so
, FRAG_RESULT_DATA2
, "data2");
447 dump_output(out
, so
, FRAG_RESULT_DATA3
, "data3");
448 dump_output(out
, so
, FRAG_RESULT_DATA4
, "data4");
449 dump_output(out
, so
, FRAG_RESULT_DATA5
, "data5");
450 dump_output(out
, so
, FRAG_RESULT_DATA6
, "data6");
451 dump_output(out
, so
, FRAG_RESULT_DATA7
, "data7");
453 /* these two are hard-coded since we don't know how to
454 * program them to anything but all 0's...
457 fprintf(out
, "; fragcoord: r0.x\n");
459 fprintf(out
, "; fragface: hr0.x\n");
470 ir3_shader_outputs(const struct ir3_shader
*so
)
472 return so
->nir
->info
.outputs_written
;